JP2012083532A - Driving method for plasma display panel and plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of times of forced initialization operations of a plasma display panel to suppress black luminance and to perform a stable writing operation.SOLUTION: In a driving method for a plasma display panel, a field includes: a first kind of subfield in which a scanning electrode applying falling inclined waveform voltage after applying rising inclined waveform voltage rising up to prescribed voltage generating discharge, regardless of the history of discharge, and a scanning electrode applying falling inclined waveform voltage after applying rising inclined waveform voltage rising up to voltage lower than prescribed voltage exist; and a second kind of subfield applying falling inclined waveform voltage to the scanning electrodes. In an initialization period of the first kind of subfield, falling inclined waveform voltage is applied to the scanning electrodes and first voltage is applied to a data electrode. In an initialization period of the second kind of subfield, falling inclined waveform voltage is applied to the scanning electrodes, and second voltage higher than the first voltage is applied to the data electrode.

Description

  The present invention relates to an AC surface discharge type plasma display panel driving method and a plasma display apparatus.

  A plasma display panel (hereinafter abbreviated as “panel”) includes a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and is red with ultraviolet rays generated by gas discharge in the discharge cell. Color display is performed by exciting and emitting phosphors of green and blue colors.

  As a method for driving the panel, a subfield method, that is, a method in which a single field is formed using a plurality of subfields having an initialization period, an address period, and a sustain period, and gradation display is performed by combining subfields that emit light. Is common. An initialization operation is performed during the initialization period of each subfield, a write operation is performed during the write period, and a maintenance operation is performed during the sustain period. The initialization operation is an operation that generates initialization discharge and forms wall charges necessary for the subsequent address operation. The initializing operation includes a forced initializing operation that generates an initializing discharge regardless of the operation of the immediately preceding subfield, and a selective initializing operation that generates an initializing discharge in a discharge cell that has performed an address discharge in the immediately preceding subfield. There is. The address operation is an operation in which an address discharge is selectively generated in the discharge cells in accordance with an image to be displayed to form wall charges, and the sustain operation is to generate a sustain discharge by alternately applying a sustain pulse to the display electrode pair, This is an operation of causing the phosphor layer of the corresponding discharge cell to emit light.

  There is a driving method that improves the contrast by lowering the luminance (hereinafter abbreviated as “black luminance”) when displaying black, which is the lowest gradation among the subfield methods, and reducing light emission not related to gradation display as much as possible. It is being considered. For example, Patent Document 1 discloses a driving method in which the forced initialization operation is performed once per field and the forced initialization operation is performed using a slowly changing ramp waveform voltage.

  Further, in Patent Document 2, the display electrode pair is divided into n, the number of times of forced initialization operation is set to once per n fields, light emission not related to gradation display is further reduced, black luminance is further reduced, and contrast is further increased. An improved driving method is disclosed.

JP 2000-242224 A JP 2006-091295 A

  However, the forced initializing operation has a function of accumulating wall charges necessary for generating the address discharge in the subsequent address period, and in addition, priming for reliably generating the address discharge by shortening the discharge delay time. It also has the function of generating. Therefore, if the number of forced initialization operations is simply reduced, address discharge will not occur, or the discharge delay time of address discharge will become too long and the address operation will become unstable, and normal image display may not be possible. was there.

  The present invention has been made in view of these problems, and by reducing the number of forced initialization operations to suppress black luminance and performing a stable writing operation, image display with high contrast and high image display quality is possible. An object is to provide a panel driving method and a plasma display device.

  To achieve the above object, according to the present invention, a discharge cell having a scan electrode, a sustain electrode, and a data electrode is formed by using a plurality of subfields having an initialization period, an address period, and a sustain period. A panel driving method for driving a plurality of panels, wherein a field is discharged again after applying an upward ramp waveform voltage that rises to a predetermined voltage at which discharge occurs regardless of discharge history during the initialization period. A scan electrode that applies a downward ramp waveform voltage that drops to a generated voltage, and a scan electrode that applies a downward ramp waveform voltage after applying an up ramp waveform voltage that rises to a voltage lower than a predetermined voltage exists. In the initializing period, the voltage drops to a voltage at which discharge occurs only in the discharge cells that have generated address discharge in the immediately preceding subfield. A second type subfield for applying a ramp waveform voltage to the scan electrode, and applying a down ramp waveform voltage to the scan electrode and applying a first voltage to the data electrode in the initialization period of the first type subfield, A down-gradient waveform voltage is applied to the scan electrode and a second voltage higher than the first voltage is applied to the data electrode in the initialization period of the second type subfield. By this method, it is possible to provide a panel driving method capable of displaying an image with high contrast and high image display quality by reducing the number of forced initialization operations to suppress black luminance and performing a stable writing operation. it can.

  In the panel driving method of the present invention, the arrival voltage of the falling ramp waveform voltage applied to the scan electrode in the initialization period of the second type subfield is applied to the scan electrode in the initialization period of the first type subfield. It is desirable that it is higher than the ultimate voltage of the ramp waveform voltage.

  In addition, the present invention constitutes one field using a panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, and a plurality of subfields having an initialization period, an address period, and a sustain period. And a driving circuit for generating a driving voltage waveform and applying the driving voltage waveform to each electrode of the panel, wherein the driving circuit has a predetermined voltage at which discharge occurs in the initialization period regardless of the discharge history. A scan electrode that applies a descending ramp waveform voltage that falls again to a voltage at which discharge occurs again after applying an ascending ramp waveform voltage, and a descending ramp waveform after applying an ascending ramp waveform voltage that rises to a voltage lower than a predetermined voltage The first type subfield in which a scan electrode to which a voltage is applied exists and the address discharge in the immediately preceding subfield in the initialization period. A field is formed by the second type subfield that applies a falling ramp waveform voltage that drops to a voltage at which discharge occurs only in the discharge cell to the scan electrode, and the scan electrode has a downward ramp in the initializing period of the first type subfield. A waveform voltage is applied, a first voltage is applied to the data electrode, a falling ramp waveform voltage is applied to the scan electrode in the initialization period of the second type subfield, and a second higher voltage than the first voltage is applied to the data electrode. The plasma display panel is driven by applying the above voltage. With this configuration, it is possible to provide a plasma display device capable of displaying an image with high contrast and high image display quality by reducing the number of forced initialization operations to suppress black luminance and performing a stable writing operation. .

  According to the present invention, a panel driving method and a plasma display capable of displaying an image with high contrast and high image display quality by reducing the number of forced initialization operations to suppress black luminance and performing a stable writing operation. An apparatus can be provided.

It is a disassembled perspective view of the panel used for the plasma display apparatus in Embodiment 1 of this invention. It is an electrode array figure of the panel used for the plasma display apparatus. It is a drive voltage waveform figure applied to each electrode of the plasma display apparatus. It is a figure which shows the relationship between the scanning electrode and field which perform forced initialization operation | movement in Embodiment 1 of this invention. It is a circuit block diagram of the plasma display apparatus in Embodiment 1 of the present invention. It is a circuit diagram of the scan electrode drive circuit of the plasma display device. It is a circuit diagram of the sustain electrode drive circuit of the plasma display device. It is a circuit diagram of the data electrode drive circuit of the plasma display device. 4 is a timing chart for explaining the operation of the drive circuit of the plasma display device. It is a drive voltage waveform figure applied to each electrode of the plasma display apparatus in Embodiment 2 of this invention.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the display electrode pair 24, and a protective layer 26 is formed on the dielectric layer 25. The protective layer 26 is formed using magnesium oxide, which is a material having high electron emission performance, in order to easily generate discharge. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is sealed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed.

  Next, a driving voltage waveform for driving panel 10 and its operation will be described. The plasma display apparatus displays an image by subfield method, that is, by dividing one field into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, an initializing discharge is generated, and an initializing operation for forming wall charges necessary for the subsequent address discharge on each electrode is performed. The initializing operation at this time includes only a forced initializing operation that forcibly generates an initializing discharge in a discharge cell regardless of whether or not there is a previous discharge, and only a discharge cell that has undergone a sustain discharge in the immediately preceding subfield. There is a selective initializing operation for generating an initializing discharge. In the address period, an address operation is performed in which address discharge is selectively generated in the discharge cells to emit light to form wall charges. In the sustain period, a sustain pulse of the number corresponding to the luminance weight determined in advance for each subfield is alternately applied to the display electrode pair, and the sustain discharge is generated in the discharge cell in which the address discharge is generated. Perform the action.

  As a subfield configuration, for example, one field is divided into 10 subfields (SF1, SF2,..., SF10), and each subfield is (1, 2, 3, 6, 11, 18, 30). , 44, 60, 80).

  In the present embodiment, subfield SF1 is a first-type subfield in which there are discharge cells that perform forced initialization operation and discharge cells that do not perform forced initialization operation. Further, the subfields SF2 to SF10 are second type subfields in which the selective initialization operation is performed in all the discharge cells. An example of the driving voltage waveform will be described first as details of a specific scan electrode that performs the forced initializing operation in the first type subfield will be described later.

  FIG. 3 is a drive voltage waveform diagram applied to each electrode of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 3 shows drive voltage waveforms applied to scan electrode SC1, scan electrode SC2, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm for subfields SF1 to SF3. In FIG. 3, it is assumed that the forced initialization operation is performed in the discharge cell having scan electrode SC1, and the forced initialization operation is not performed in the discharge cell having scan electrode SC2.

  In the first half of the initialization period of the first type subfield SF1, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the voltage 0 (V) is also applied to the sustain electrodes SU1 to SUn. Scan electrode SC1 that performs the forced initializing operation gradually decreases from voltage Vi1 at which no discharge occurs to a predetermined voltage Vi2 at which discharge occurs regardless of the discharge history (hereinafter simply referred to as “voltage Vi2”). Ascending ramp waveform voltage is applied. Then, weak initializing discharge occurs between scan electrode SC1 and sustain electrode SU1, and between scan electrode SC1 and data electrodes D1 to Dm, and negative wall voltage is accumulated on scan electrode SC1. A positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrode SU1. In addition, priming that shortens the discharge delay time of the address discharge also occurs. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  On the other hand, an upward ramp waveform voltage that gradually rises from voltage 0 (V) to voltage Vi5 lower than the predetermined voltage Vi2 is applied to scan electrode SC2 that does not perform the forced initialization operation. In this case, however, no discharge occurs.

  Thus, in the first half of the initializing period of the subfield SF1, the scan electrode that performs the forced initializing operation gradually rises toward the voltage Vi2 at which the discharge occurs regardless of the presence or absence of the previous discharge. Apply voltage. Further, an upward ramp waveform voltage that gently rises toward the voltage Vi5 lower than the voltage Vi2 is applied to the scan electrode that does not perform the forced initialization operation.

  In the subsequent second half of the initializing period of the first type subfield SF1, the voltage 0 (V) is applied as the first voltage to the data electrodes D1 to Dm, and the voltage Ve is applied to the sustain electrodes SU1 to SUn. Then, a downward ramp waveform voltage that gently falls from voltage Vi3 to voltage Vi4 is applied to scan electrodes SC1 to SCn. Then, a discharge is generated in the discharge cell in which the weak initializing discharge is generated in the first half of the initializing period of the subfield SF1 and the subfield SF10 of the previous field which is the immediately preceding subfield, and excessive wall charges are accumulated. A weak initializing discharge is generated in the discharge cell. Then, the wall voltage on the scan electrode and the sustain electrode of the corresponding discharge cell is weakened, and an excessive portion of the wall voltage of the data electrodes D1 to Dm is discharged and adjusted to a wall voltage suitable for the address operation. In addition, priming that shortens the discharge delay time of the address discharge also occurs. On the other hand, in the discharge cells in which no discharge is generated in the immediately preceding subfield and no initializing discharge is generated in the first half of the initializing period of subfield SF1, initializing discharge does not occur, and the previous wall voltage is maintained.

  Thus, in the present embodiment, subfield SF1 is a first-type subfield in which discharge cells that perform forced initializing operation and discharge cells that perform selective initializing operation coexist in the initializing period. Then, in the initialization period, a scan electrode that applies a downward ramp waveform voltage that decreases to a voltage Vi4 at which discharge occurs again after applying an upward ramp waveform voltage that increases to a predetermined voltage Vi2 at which discharge occurs regardless of the discharge history. And a scan electrode that applies a falling ramp waveform voltage that rises to a voltage Vi5 lower than a predetermined voltage Vi2 and then applies a falling ramp waveform voltage that falls to a voltage Vi4. A downward ramp waveform voltage is applied to scan electrodes SC1 to SCn, and a first voltage 0 (V) is applied to data electrodes D1 to Dm.

  In the subsequent address period of subfield SF1, voltage 0 (V) is continuously applied to data electrodes D1 to Dm, voltage Ve is continuously applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn. Next, a scan pulse of voltage Va is applied to scan electrode SC1 in the first row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, the voltage difference at the intersection between data electrode Dk and scan electrode SC1 exceeds the discharge start voltage, discharge occurs between data electrode Dk and scan electrode SC1, and further, scan electrode SC1 and sustain electrode SU1 In the meantime, the discharge expands and an address discharge occurs. A positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection between the data electrode to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur.

  Next, a scan pulse is applied to scan electrode SC2 in the second row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, address discharge occurs between data electrode Dk and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1, positive wall voltage is accumulated on scan electrode SC2, and negative wall voltage is applied on sustain electrode SU2. And a negative wall voltage is also accumulated on the data electrode Dk. In this manner, an address operation is performed in which an address discharge is caused in the discharge cell to be lit in the second row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection between the data electrode to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur.

  Thereafter, the same addressing operation is performed until reaching the n-th scan electrode SCn, and wall charges necessary for the subsequent sustain discharge are formed.

  In the subsequent sustain period of subfield SF1, voltage 0 (V) is applied to data electrodes D1 to Dm. Then, voltage 0 (V) is applied to sustain electrodes SU1 to SUn, and a sustain pulse of voltage Vs is applied to scan electrodes SC1 to SCn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the voltage Vs plus the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. The discharge start voltage is exceeded. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. On the other hand, the sustain discharge does not occur in the discharge cells in which the address discharge has not occurred, and the wall voltage at the end of the initialization operation is maintained.

  Subsequently, voltage 0 (V) is applied to scan electrodes SC1 to SCn, and a sustain pulse of voltage Vs is applied to sustain electrodes SU1 to SUn. Then, the sustain discharge occurs again in the discharge cell in which the sustain discharge has occurred, and the phosphor layer 35 emits light. Then, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, sustain pulses of the number corresponding to the luminance weight are alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and sustain discharge is continuously generated in the discharge cells in which the address discharge has occurred.

  Thereafter, an upward ramp waveform voltage that gently rises toward voltage Vr is applied to scan electrodes SC1 to SCn. Then, an erasing discharge is generated in the discharge cell in which the sustain discharge has been performed, and the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. Thus, the maintenance operation is finished.

  In the initialization period of the second type subfield SF2, a positive voltage Vg is applied to the data electrodes D1 to Dm as a second voltage higher than the first voltage 0 (V). Further, voltage Vh higher than voltage Ve is applied to sustain electrodes SU1 to SUn. Then, a downward ramp waveform voltage that gently falls toward voltage Vi6 is applied to scan electrodes SC1 to SCn. Here, the arrival voltage Vi6 of the downward ramp waveform voltage applied to the scan electrodes SC1 to SCn in the initialization period of the second type subfield SF1 is applied to the scan electrodes SC1 to SCn in the initialization period of the first type subfield SF1. The voltage is set to be higher than the ultimate voltage Vi4 of the descending ramp waveform voltage, and is set to a voltage approximately equal to the sum of the voltage Vi4 and the voltage Vg. Then, a weak initializing discharge is generated in the discharge cell that has generated the sustain discharge in the immediately preceding subfield SF1, and the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. In addition, an excessive portion of the wall voltage on the data electrode Dk is discharged and adjusted to a wall voltage suitable for the address operation. In this way, the selective initialization operation is completed.

  As described above, in the present embodiment, the subfield SF2 is the second type subfield in which the selective initialization operation is performed in all the discharge cells. In the initialization period, a downward ramp waveform voltage that drops to a voltage at which discharge occurs only in the discharge cells that have generated address discharge in the immediately preceding subfield is applied to scan electrodes SC1 to SCn. In addition, a downward ramp waveform voltage is applied to scan electrodes SC1 to SCn, and a second voltage Vg higher than the first voltage 0 (V) is applied to data electrodes D1 to Dm.

  The drive voltage waveform in the subsequent writing period of the subfield SF2 is the same as that in the writing period of the subfield SF1. That is, the voltage 0 (V) is applied to the data electrodes D1 to Dm, the voltage Ve is applied to the sustain electrodes SU1 to SUn, the scan pulse of the voltage Va is sequentially applied to the scan electrodes SC1 to SCn, and the discharge cells to emit light are applied. An address operation is performed by applying an address pulse of voltage Vd to the corresponding data electrode Dk.

  The driving voltage waveform in the sustain period of the subsequent subfield SF2 is the same as the sustain period of the subfield SF1 except for the number of sustain pulses. That is, sustain pulses of the number corresponding to the luminance weight are alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and sustain discharge is continuously generated in the discharge cells in which the address discharge has occurred. Thereafter, an upward ramp waveform voltage that gradually rises toward the voltage Vr is applied to the scan electrodes SC1 to SCn, leaving the positive wall voltage on the data electrode Dk, and on the scan electrode SCi and the sustain electrode SUi. Decrease the upper wall voltage.

  The drive voltage waveforms in the subsequent second type subfields SF3 to SF10 are the same as those of the second type subfield SF2 except for the number of sustain pulses.

  In this embodiment, the voltage Vi1 is 150 (V), the voltage Vi2 is 350 (V), the voltage Vi3 is 200 (V), the voltage Vi4 is −170 (V), the voltage Vi5 is 200 (V), The voltage Vi6 is −110 (V), the voltage Vc is −50 (V), the voltage Va is −200 (V), the voltage Vs is 200 (V), the voltage Vr is 200 (V), and the voltage Ve is 170 (V). The voltage Vd is 60 (V), the voltage Vg is 60 (V), and the voltage Vh is 200 (V). The slope of the rising ramp waveform voltage applied to scan electrodes SC1 to SCn is 10 (V / μs), and the slope of the falling ramp waveform voltage is −1.5 (V / μs). However, these voltage values are not limited to the values described above, and are desirably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.

Next, the relationship between a specific scan electrode that performs a forced initialization operation and a field will be described. In the present embodiment, a specific scan electrode for performing a forced initialization operation is set for each field based on the following rules. When a forced initialization operation is performed only once in one field among N consecutive fields (N is a natural number) for one scan electrode, the N fields that are temporally continuous are defined as one field group. N scan electrodes arranged in series are defined as one scan electrode group. Moreover,
(Rule 1) The field where the forced initialization operation is performed by one scan electrode is one in each field group.

  (Rule 2) There is one scan electrode in each scan electrode group that performs the forced initialization operation in one field.

Furthermore, if N ≧ 5,
(Rule 3) In the scan electrode adjacent to the scan electrode that performs the forced initialization operation in a certain field, the forced initialization operation is not performed in at least the field and the next field.

  FIG. 4 is a diagram showing the relationship between the scan electrode that performs the forced initializing operation and the field in the first embodiment of the present invention. In the case of N = 5 where five consecutive fields are one field group. An example is shown. The horizontal axis represents the field, and the vertical axis represents the scan electrode. The fields Fj to Fj + 4 constitute one field group, and the scan electrodes SCi to SCi + 4 constitute one scan electrode group. Further, “◯” indicates that the forced initialization operation is performed, and “X” indicates that the forced initialization operation is not performed.

  As is apparent from FIG. 4, each scan electrode SCi performs a forced initialization operation in one field in each field group. The same applies to the other scan electrodes (Rule 1). As a result, the number of forced initialization operations is reduced by a factor of 5 compared to the case where the forced initialization operation is performed every time in all the discharge cells for each field, so the black luminance of the display image is also 5 minutes. It can be reduced to 1. For each field Fj, a forced initialization operation is performed with one scan electrode in the scan electrode group. The same applies to the other fields (Rule 2). As a result, the scan electrodes that perform the forced initialization operation can be dispersed in each field, and flicker can be reduced. Scan electrode SCi performs a forced initialization operation in field Fj, and scan electrode SCi-1 and scan electrode SCi + 1 adjacent to scan electrode SCi do not perform a forced initialization operation in field Fj and the next field Fj + 1. The same applies to the other scan electrodes (Rule 3). As a result, the temporal and spatial continuity of the scan electrodes that perform the forced initialization operation can be reduced, so that light emission due to the forced initialization operation is hardly recognized.

  As described above, in the present embodiment, each of the discharge cells is forcibly initialized to forcibly generate an initializing discharge in the initializing period of one subfield belonging to one of a plurality of consecutive fields. Perform the action. As a result, the forced initialization operation is performed once per n fields, light emission not related to gradation display is further reduced to reduce black luminance, and image display with high contrast is performed.

  However, as described above, if the number of forced initialization operations is simply reduced, address discharge does not occur, or the discharge delay time of address discharge becomes too long and the address operation becomes unstable, and normal image display cannot be performed. There is.

  However, in the present embodiment, the second voltage Vg higher than the first voltage 0 (V) is applied to the data electrodes D1 to Dm in the initialization period of the second type subfields SF2 to SF10 in which the selective initialization operation is performed. Is applied. Further, the falling voltage Vi6 of the falling ramp waveform voltage applied to scan electrodes SC1 to SCn is set higher than the reaching voltage Vi4 of the falling ramp waveform voltage applied to scan electrodes SC1 to SCn in the initialization period of first type subfield SF1. Has been. As a result, the writing operation is stabilized, and an image with high contrast and high image display quality is displayed. The reason will be described below.

  In the present embodiment, since the number of times of performing the forced initialization operation is reduced, there is a possibility that the variation in the wall voltage of each discharge cell becomes large. However, in the present embodiment, the positive voltage Vg is applied to the data electrodes D1 to Dm in the initialization period of the second type subfields SF2 to SF10 in which the selective initialization operation is performed. Therefore, the voltage difference between scan electrodes SC1 to SCn and data electrodes D1 to Dm increases, and discharge can be reliably generated between data electrode Dk and scan electrode SCi of the discharge cell performing the selective initialization operation. In addition, the wall voltage on the data electrode Dk can be accurately adjusted. In order to compensate for the wall voltage reduced by this discharge and to generate the address discharge reliably, the low-voltage side voltage Va of the scan pulse applied to the scan electrode in the address period is obtained by subtracting the positive voltage Vg from the voltage Vi6. It is set to the same level. In other words, in the initialization period in which the selective initial operation is performed, the downward ramp waveform voltage that decreases toward the voltage Vi6 that is the same as the voltage obtained by superimposing the positive voltage Vg on the low-voltage side voltage Va of the scan pulse Applied to SCn. In the present embodiment, the voltage Vi6 is set to a voltage slightly higher than the sum of the voltage Vi4 and the voltage Vg.

  On the other hand, the positive voltage Vg is not applied to the data electrodes D1 to Dm in the initialization period of the first type subfield SF1. The reason will be described below.

  In the initializing period of the first type subfield SF1, there are discharge cells that perform a forced initializing operation. That is, in the first half of the initialization period, there is a discharge cell that forcibly generates an initialization discharge by applying an upward ramp waveform voltage that rises toward the voltage Vi2 at which the discharge occurs regardless of the presence or absence of the previous discharge. . A wall voltage with high positive polarity is accumulated on the data electrode of such a discharge cell. Assuming that a positive voltage is applied to the data electrode of such a discharge cell, the voltage difference between the scan electrode and the data electrode becomes too large in the second half of the initialization period, causing a strong false discharge. The probability of doing is increased. Therefore, in the present embodiment, a positive voltage is not applied to the data electrode in the initialization period of the first type subfield SF1 in which the discharge cell performing the forced initialization operation exists.

  Thus, by accurately adjusting the wall voltage on the data electrode Dk, the address discharge can be stably generated even if the number of forced initialization operations is reduced.

  Next, a driving circuit for driving the panel 10 and its operation will be described. FIG. 5 is a circuit block diagram of plasma display device 40 in accordance with the first exemplary embodiment of the present invention. The plasma display device 40 includes the panel 10 and its drive circuit. The drive circuit includes an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and each of them. A power supply circuit (not shown) for supplying necessary power to the circuit block is provided.

  The image signal processing circuit 41 converts the input image signal into image data indicating light emission / non-light emission for each subfield. The data electrode driving circuit 42 converts the image data for each subfield into address pulses corresponding to the data electrodes D1 to Dm, and applies them to the data electrodes D1 to Dm. The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block on the basis of the vertical and horizontal synchronization signals, and supplies them to the respective circuit blocks. Scan electrode drive circuit 43 generates the drive voltage waveform described above based on the timing signal and applies it to each of scan electrodes SC1 to SCn. Sustain electrode drive circuit 44 generates the drive voltage waveform described above based on the timing signal and applies it to sustain electrodes SU1 to SUn.

  FIG. 6 is a circuit diagram of scan electrode drive circuit 43 of plasma display device 40 in accordance with the first exemplary embodiment of the present invention. Scan electrode drive circuit 43 includes sustain pulse generation circuit 50, ramp waveform voltage generation circuit 60, and scan pulse generation circuit 70.

  Sustain pulse generation circuit 50 includes power recovery circuit 51, switching element Q55, switching element Q56, and switching element Q59, and generates sustain pulses to be applied to scan electrodes SC1 to SCn. The power recovery circuit 51 recovers and reuses power when driving the scan electrodes SC1 to SCn. Switching element Q55 clamps scan electrodes SC1 to SCn to voltage Vs, and switching element Q56 clamps scan electrodes SC1 to SCn to voltage 0 (V). The switching element Q59 is a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43.

  Scan pulse generating circuit 70 includes switching elements Q71H1 to Q71Hn, Q71L1 to Q71Ln, switching element Q72, and power source E71 of voltage Vp superimposed on the reference potential (potential of node A shown in FIG. 6) of scan pulse generating circuit 70. Have. Then, a scan pulse is generated based on the power source of voltage Va and power source E71, and the scan pulse is sequentially applied to each of scan electrodes SC1 to SCn at the timing shown in FIG. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 50 as it is during the sustain operation. That is, the voltage at node A is output to scan electrodes SC1 to SCn.

  The ramp waveform voltage generation circuit 60 includes Miller integration circuits 61 to 63, and generates the ramp waveform voltage shown in FIG. Miller integrating circuit 61 includes transistor Q61, capacitor C61, and resistor R61, and applies a constant voltage to input terminal IN61 to generate an upward ramp waveform voltage that gradually rises toward voltage Vt. Miller integrating circuit 62 includes transistor Q62, capacitor C62, resistor R62, and diode D62 for preventing backflow, and by applying a constant voltage to input terminal IN62, it rises gently toward voltage Vr. Generate waveform voltage. Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63, and applies a constant voltage to input terminal IN63 to generate a downward ramp waveform voltage that gradually decreases toward voltage Vi4. The switching element Q69 is also a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode drive circuit 43.

  In addition, these switching elements and transistors can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the switching elements and transistors generated by the timing generation circuit 45.

  FIG. 7 is a circuit diagram of sustain electrode drive circuit 44 of plasma display device 40 in accordance with the first exemplary embodiment of the present invention. Sustain electrode drive circuit 44 includes sustain pulse generation circuit 80 and constant voltage generation circuit 85.

  Sustain pulse generation circuit 80 includes power recovery circuit 81, switching element Q83, and switching element Q84, and generates sustain pulses to be applied to sustain electrodes SU1 to SUn. The power recovery circuit 81 recovers and reuses power when driving the sustain electrodes SU1 to SUn. Switching element Q83 clamps sustain electrodes SU1 to SUn to voltage Vs, and switching element Q84 clamps sustain electrodes SU1 to SUn to voltage 0 (V).

  Constant voltage generation circuit 85 has switching elements Q86 and Q87, and applies voltage Ve to sustain electrodes SU1 to SUn.

  Note that these switching elements can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements are controlled by timing signals corresponding to the respective switching elements generated by the timing generation circuit 45.

  FIG. 8 is a circuit diagram of data electrode drive circuit 42 of plasma display device 40 in accordance with the first exemplary embodiment of the present invention. Data electrode drive circuit 42 includes switching elements Q91H1 to Q91Hm and switching elements Q91L1 to Q91Lm. The voltage 0 (V) is applied to the data electrode Dj by turning on the switching element Q91Lj, and the voltage Vd is applied to the data electrode Dj by turning on the switching element Q91Hj.

  Next, the operation of the drive circuit, in particular, the operation of the scan electrode drive circuit 43, the sustain electrode drive circuit 44, and the data electrode drive circuit 42 from the first type subfield SF1 to the second type subfield SF2 will be described. In the present embodiment, the voltage Vi1 shown in FIG. 3 is equal to the voltage Vp, the voltage Vi2 is equal to the voltage (Vt + Vp), the voltage Vi3 is equal to the voltage Vs, the voltage Vi5 is equal to the voltage Vt, and the voltage Vc is equal to the voltage Vc. In the following description, it is assumed that the voltage Vg is equal to the voltage Vd and the voltage Vh is equal to the voltage Vs. However, these voltages are not limited to the above, and can be appropriately set according to the circuit configuration.

  FIG. 9 is a timing chart for explaining the operation of the drive circuit of plasma display device 40 in the first exemplary embodiment of the present invention. In FIG. 9, among the scan electrodes SC1 to SCn, the scan electrode that performs the forced initialization operation is indicated by the scan electrode SCx, and the scan electrode that does not perform the forced initialization operation is indicated by the scan electrode SCy. Of the switching elements Q71H1 to Q71Hn, a switching element corresponding to the scan electrode SCx is indicated by a switching element Q71Hx, and a switching element corresponding to the scan electrode SCy is indicated by a switching element Q71Hy. Similarly, among switching elements Q71L1 to Q71Ln, a switching element corresponding to scan electrode SCx is indicated by switching element Q71Lx, and a switching element corresponding to scan electrode SCy is indicated by switching element Q71Ly.

  In the first half of the initialization period of subfield SF1, first, switching element Q56 of scan electrode drive circuit 43 is turned on to apply voltage 0 (V) to scan electrodes SCx and SCy. Next, switching element Q56 is turned off, and switching element Q71Lx is turned off and switching element Q71Hx is turned on to apply voltage Vp to scan electrode SCx that performs the forced initialization operation. On the other hand, voltage 0 (V) is still applied to scan electrode SCy that does not perform the forced initialization operation.

  Next, a constant voltage is applied to the input terminal IN61 of the Miller integrating circuit 61, and the voltage at the node A is gradually increased to the voltage Vt. Then, an upward ramp waveform voltage that gently rises from the voltage Vp to the voltage (Vt + Vp) is applied to the scan electrode SCx that performs the forced initialization operation. On the other hand, an upward ramp waveform voltage that gently rises from voltage 0 (V) to voltage Vt is applied to scan electrode SCy that does not perform the forced initialization operation.

  In the second half of the initializing period of the subsequent subfield SF1, the switching element Q84 of the sustain electrode driving circuit 44 is turned off, the switching elements Q86 and Q87 are turned on, and the voltage Ve is applied to the sustain electrodes SU1 to SUn. Then, the switching element Q71Hx of the scan electrode driving circuit 43 is turned off, the switching element Q71Lx is turned back on, and the switching elements Q55 and Q59 are turned on. First, the voltage Vs is applied to the scan electrodes SCx and SCy. After that, the switching element Q69 is turned off and a constant voltage is applied to the input terminal IN63 of the Miller integrating circuit 63 to operate the Miller integrating circuit 63, so that the downward slope gradually falls to the voltage Vi4 on the scan electrodes SCx and SCy. Apply waveform voltage.

  In the subsequent writing period of the subfield SF1, the transistor Q63 of the Miller integrating circuit 63 of the scan electrode driving circuit 43 is turned off, the switching element Q72 is turned on, and the voltage at the node A is set to the voltage Va. Then, switching elements Q71Lx and Q71Ly are turned off, switching elements Q71Hx and Q71Hy are turned on, and voltage (Va + Vp) is applied to each of scan electrodes SCx and SCy.

  Next, switching element Q71H1 is turned off, switching element Q71L1 is turned on, and switching element Q91Lj and switching element Q91Hj of data electrode drive circuit 42 are controlled in accordance with the image data. After a certain time, switching element Q71L1 is turned off and switching element Q71H1 is turned back on. In this way, the scan pulse is applied to the scan electrode SC1, and the write pulse is applied to the data electrode. Similarly, the scan pulse and the address pulse are sequentially applied to the scan electrode SCn.

  Thereafter, switching element Q72, switching elements Q71Hx, Q71Hy are turned off, switching element Q56, switching element Q69, switching elements Q71Lx, Q71Ly are turned on, and voltage 0 (V) is applied to scan electrodes SCx, SCy.

  In the subsequent sustain period of subfield SF1, scan electrode SCx and SCy and sustain electrodes SU1 to SUn are applied to sustain electrode generating circuit 50 of sustain electrode driving circuit 43 and sustain pulse generating circuit 80 of sustain electrode driving circuit 44. A sustain pulse corresponding to the luminance weight is applied. After that, the switching element Q56 of the scan electrode driving circuit 43 is turned off, and a constant voltage is applied to the input terminal IN62 of the Miller integrating circuit 62 to operate the Miller integrating circuit 62. The voltage is applied to the scan electrodes SCx and SCy. An upward ramp waveform voltage that gradually rises to Vr is applied.

  In the subsequent initializing period of subfield SF2, switching elements Q91L1 to Q91Lm of data electrode driving circuit 42 are turned off and switching elements Q91H1 to Q91Hm are turned on to apply positive voltage Vd to data electrodes D1 to Dm. Further, switching element Q84 of sustain electrode drive circuit 44 is turned off and switching element Q83 is turned on to apply voltage Vs to sustain electrodes SU1 to SUn. Then, the switching elements Q71Lx and Q71Ly of the scan electrode driving circuit 43 are turned on, and a constant voltage is applied to the input terminal IN63 of the Miller integrating circuit 63 to operate the Miller integrating circuit 63. Then, when the voltage having the downward ramp waveform applied to the scan electrodes SCx and SCy reaches the voltage Vi6, the voltage applied to the input terminal IN63 is stopped. In this way, a downward ramp waveform voltage that gently falls to voltage Vi6 is applied to scan electrodes SCx and SCy.

  The operations in the subsequent writing period and sustaining period of subfield SF2 are the same as in the writing period and sustaining period of subfield SF1.

  In this manner, in the present embodiment, the drive voltage waveforms shown in FIG. 3 are converted to the data electrodes D1 to Dm and the scan electrode SC1 using the data electrode drive circuit 42, the scan electrode drive circuit 43, and the sustain electrode drive circuit 44. To SCn and sustain electrodes SU1 to SUn.

  Then, a downward ramp waveform voltage is applied to the scan electrode in the initialization period of the first type subfield and a first voltage 0 (V) is applied to the data electrode, and the scan electrode is applied in the initialization period of the second type subfield. By applying a downward ramp waveform voltage to the data electrode and applying a second voltage Vg higher than the first voltage to the data electrode, the number of forced initializing operations is reduced, black luminance is suppressed, and stable writing operation is performed. It can be carried out.

In the present embodiment, whether or not the forced initialization operation is performed for each scan electrode and each field is set based on the above (Rule 1) and (Rule 2). When N ≧ 5, the setting was made based on (Rule 3) in addition to (Rule 1) and (Rule 2). However, the present invention is not limited to this, and can be applied to driving with relaxed conditions. For example, instead of (Rule 2)
(Rule 2 ′) The number of scan electrodes that perform the forced initialization operation in one field is one or zero in each scan electrode group.
May be applied.

  Further, the present invention is not limited to the drive voltage waveform shown in FIG. 3, and can be applied to other drive voltage waveforms in which the number of forced initialization operations is suppressed. An example of another driving voltage waveform will be described below.

(Embodiment 2)
FIG. 10 is a drive voltage waveform diagram applied to each electrode of the plasma display device in accordance with the second exemplary embodiment of the present invention. FIG. 10 shows drive voltage waveforms applied to scan electrode SC1, scan electrode SC2, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm for subfields SF1 to SF3. In FIG. 10, it is assumed that the forced initialization operation is performed in the discharge cell having the scan electrode SC1, and the forced initialization operation is not performed in the discharge cell having the scan electrode SC2.

  The first half and the second half of the initialization period of the first type subfield SF1 are the same as those in the first embodiment. That is, in the first half, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the voltage 0 (V) is also applied to the sustain electrodes SU1 to SUn. Then, a weak initializing discharge is generated by applying an upward ramp waveform voltage that gradually increases from the voltage Vi1 to the voltage Vi2 to the scan electrode SC1 that performs the forced initializing operation. On the other hand, an upward ramp waveform voltage that gently rises from voltage 0 (V) toward voltage Vi5 is applied to scan electrode SC2 that does not perform the forced initialization operation. In the latter half of the initialization period, voltage 0 (V) is applied to data electrodes D1 to Dm, and voltage Ve is applied to sustain electrodes SU1 to SUn. Then, a downward ramp waveform voltage that gently falls from voltage Vi3 to voltage Vi4 is applied to scan electrodes SC1 to SCn.

  In the second embodiment, an abnormal charge erasing unit is further provided thereafter. In the abnormal charge erasing unit, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, and an upward ramp waveform voltage that gradually rises to voltage Vr is applied to scan electrode SC1 through scan electrode SCn. Then, a weak erasing discharge is generated in a discharge cell having an abnormal charge that may cause an erroneous discharge. Thereafter, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and a downward ramp waveform voltage that gently decreases from voltage 0 (V) toward voltage Vi4 is applied to scan electrode SC1 through scan electrode SCn. Then, a weak discharge occurs again in the discharge cell having an abnormal charge, and the wall voltage is adjusted to be suitable for the address operation. Note that no discharge occurs in a discharge cell having no abnormal charge.

  By providing the abnormal charge erasing portion in this way, the wall voltage can be adjusted with higher accuracy, and thus more stable address discharge can be generated.

  The subsequent writing period of the subfield SF1 is the same as that of the first embodiment, and thus the description thereof is omitted.

  In the sustain period of the subsequent subfield SF1, as in the first embodiment, the number of sustain pulses corresponding to the luminance weight is alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and address discharge is caused. Sustain discharge is continuously generated in the discharge cell.

  In the second embodiment, after that, while voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, scan electrode SC1 through scan electrode SCn are gradually applied from voltage 0 (V) to voltage Vi4. A falling ramp waveform voltage is applied. Then, a weak discharge is generated in the discharge cell that has generated the sustain discharge.

  Thereafter, an upward ramp waveform voltage that gently rises toward voltage Vr is applied to scan electrodes SC1 to SCn. Then, an erasing discharge is generated in the discharge cell in which the sustain discharge has been performed, and the wall voltage on scan electrode SCi and sustain electrode SUi is weakened.

  The initialization period of the second type subfield SF2 is the same as that in the first embodiment. That is, a positive voltage Vg is applied to the data electrodes D1 to Dm. Further, voltage Vh higher than voltage Ve is applied to sustain electrodes SU1 to SUn. Then, a downward ramp waveform voltage that gently falls toward voltage Vi6 is applied to scan electrodes SC1 to SCn. Here again, the voltage Vi6 is set to a voltage approximately equal to the sum of the voltage Vi4 and the voltage Vg. Then, a weak initializing discharge is generated in the discharge cell that has generated the sustain discharge in the immediately preceding subfield, and the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. In addition, an excessive portion of the wall voltage on the data electrode Dk is discharged and adjusted to a wall voltage suitable for the address operation. In this way, the selective initialization operation is completed.

  The drive voltage waveform in the subsequent writing period of the subfield SF2 is the same as that in the writing period of the subfield SF1. The driving voltage waveform in the sustain period of the subsequent subfield SF2 is the same as the sustain period of the subfield SF1 except for the number of sustain pulses. The drive voltage waveforms in the second type subfields SF3 to SF10 are the same as those in the subfield SF2 except for the number of sustain pulses.

  As described above, also in the second embodiment, the down slope waveform voltage is applied to the scan electrode and the first voltage 0 (V) is applied to the data electrode in the initializing period of the first type subfield, and the second type subfield is applied. By applying a downward ramp waveform voltage to the scan electrode and applying a second voltage Vg higher than the first voltage to the data electrode in the field initialization period, the number of forced initialization operations is reduced and black luminance is applied. And a stable write operation can be performed.

  The specific numerical values shown in the first and second embodiments are merely examples, and the present invention is not limited to these numerical values. The panel characteristics and the specifications of the plasma display device are not limited to these numerical values. It is desirable to set optimally according to the above.

  The present invention reduces the number of forced initialization operations to suppress black luminance and performs a stable writing operation, and can display an image with high contrast and high image display quality. It is useful as a plasma display device used.

DESCRIPTION OF SYMBOLS 10 Panel 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 32 Data electrode 35 Phosphor layer 40 Plasma display apparatus 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 50,80 Sustain pulse generation circuit 51, 81 Power recovery circuit 60 Ramp waveform voltage generation circuit 61, 62, 63 Miller integration circuit 70 Scanning pulse generation circuit 85 Constant voltage generation circuit

Claims (3)

A plasma display for driving a plasma display panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, with a plurality of subfields having an initialization period, an address period, and a sustain period. A panel driving method,
In the initializing period, the field applies a ramp waveform voltage that drops to a voltage at which discharge occurs again after applying a ramp waveform voltage that rises to a predetermined voltage at which discharge occurs regardless of the discharge history. A first-type subfield in which a scan electrode, a scan electrode to which a ramp-down waveform voltage is applied after application of a ramp-up waveform voltage that rises to a voltage lower than the predetermined voltage, and immediately before the initialization period, A second type subfield that applies a downward ramp waveform voltage that drops to a voltage at which a discharge occurs only in the discharge cells that have generated an address discharge in the subfield of
A downward ramp waveform voltage is applied to the scan electrode in the initialization period of the first type subfield, a first voltage is applied to the data electrode, and the scan electrode is applied to the scan electrode in the initialization period of the second type subfield. A method of driving a plasma display panel, wherein a downward ramp waveform voltage is applied and a second voltage higher than the first voltage is applied to the data electrode. The arrival voltage of the falling ramp waveform voltage applied to the scan electrode in the initialization period of the second type subfield is the arrival voltage of the down ramp waveform voltage applied to the scan electrode in the initialization period of the first type subfield. The method for driving a plasma display panel according to claim 1, wherein the driving method is higher. A plasma display panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, and a plurality of subfields having an initialization period, an address period, and a sustain period are used to form one field and drive voltage waveform A plasma display device comprising a drive circuit that generates and applies to each electrode of the plasma display panel,
The drive circuit is
In the initialization period, a scan electrode that applies a downward ramp waveform voltage that decreases to a voltage at which discharge occurs again after applying an upward ramp waveform voltage that increases to a predetermined voltage at which discharge occurs regardless of the history of discharge; A first type subfield in which there is a scan electrode to which a falling ramp waveform voltage is applied after applying an rising ramp waveform voltage that rises to a voltage lower than the predetermined voltage, and the immediately preceding subfield in the initialization period; The field is constituted by a second type subfield that applies a downward ramp waveform voltage that drops to a voltage at which discharge occurs only in the discharge cell that has generated address discharge, to the scan electrode,
A downward ramp waveform voltage is applied to the scan electrode in the initialization period of the first type subfield, a first voltage is applied to the data electrode, and the scan electrode is applied to the scan electrode in the initialization period of the second type subfield. A plasma display device driving a plasma display panel by applying a downward ramp waveform voltage and applying a second voltage higher than the first voltage to the data electrode.

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