JP2007108487A - Method of driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of driving a panel which suppresses wrong illumination and has good image display quality even when the panel has high luminance and high definition. <P>SOLUTION: The method includes a plurality of discharge cells each having a display electrode pair comprising a scanning electrode and a sustain electrode. A sustain pulse generation part is provided which divides a one-field period into a plurality of sub-fields each having a write period and a sustain period and applies a sustain pulse to a display electrode pair in a sustain period to generate the sustain discharge of a discharge cell. The sustain pulse generation part applies a voltage lower than a voltage generating a starting sustain discharge in the sustain period to the display electrode pair before applying the voltage generating the starting sustain discharge to the display electrode pair. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for driving a plasma display panel.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing xenon is sealed in the internal discharge space. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet light is generated by gas discharge in each discharge cell, and phosphors of RGB colors are excited and emitted by the ultraviolet light to perform color display.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields. Each subfield has an initialization period, an address period, and a sustain period. In the initialization period, an initialization discharge is generated, and wall charges necessary for the subsequent address operation are formed on each electrode. In the address period, address discharge is selectively generated in the discharge cells to be displayed to form wall charges. In the sustain period, a sustain pulse is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell in which the address discharge is generated, and the phosphor layer of the corresponding discharge cell is caused to emit light. The image is displayed.

Even in the subfield method, light emission that is not related to gradation display is achieved by performing initializing discharge using a slowly changing voltage waveform and selectively performing initializing discharge on discharge cells that have undergone sustain discharge. Patent Document 1 discloses a novel driving method in which the contrast ratio is improved as much as possible.
JP 2000-242224 A

  However, if the discharge cells are miniaturized as the panel becomes higher in definition, or if the xenon partial pressure is increased to increase the brightness of the panel, a sustain discharge occurs in the discharge cells that should not be sustained discharge (hereinafter referred to as light emission). , Abbreviated as “wrong lighting”). In particular, erroneous lighting occurring in a discharge cell in a region displaying a dark image is easily noticeable and greatly reduces the image display quality.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a panel driving method that suppresses erroneous lighting and has high image display quality even for a high-luminance and high-definition panel.

  The present invention relates to a method for driving a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, and sustaining the discharge cell by applying a sustain pulse to the display electrode pair during the sustain period. The sustain pulse generator includes a voltage lower than a voltage for generating the first sustain discharge before applying a voltage for generating the first sustain discharge in the sustain period to the display electrode pair. It is characterized by applying to. This method can provide a panel driving method that suppresses erroneous lighting and has high image display quality even for a high-brightness and high-definition panel.

  The sustain pulse generator of the present invention is connected to a power recovery unit that applies a voltage to the display electrode pair by resonance between the capacitance between the electrodes of the display electrode pair and the power recovery inductor, and is connected to a predetermined power source or ground potential. And a clamp unit for applying a voltage to the display electrode pair, and the power recovery unit is applied to a voltage lower than a voltage for generating the first sustain discharge over a period longer than ½ of the resonance period of the power recovery unit. And may be applied to the display electrode pair. By this method, erroneous lighting can be suppressed while collecting power.

  In the panel driving method of the present invention, the period longer than ½ of the resonance period of the power recovery unit is preferably 600 μs to 700 μs.

  According to the present invention, it is possible to provide a panel driving method that suppresses erroneous lighting and has high image display quality even for a high-luminance and high-definition panel.

  Hereinafter, a panel driving method according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing a main part of a panel used in the embodiment of the present invention. The panel 10 is configured such that a glass front substrate 21 and a rear substrate 31 are arranged to face each other and a discharge space is formed therebetween. On the front substrate 21, a plurality of scanning electrodes 22 and sustaining electrodes 23 constituting a display electrode pair are formed in parallel with each other. A dielectric layer 24 is formed so as to cover the scan electrodes 22 and the sustain electrodes 23, and a protective layer 25 is formed on the dielectric layer 24. A plurality of data electrodes 32 covered with an insulating layer 33 are provided on the back substrate 31, and a grid-like partition wall 34 is provided on the insulating layer 33. A phosphor layer 35 is provided on the surface of the insulator layer 33 and the side surfaces of the partition walls 34. The front substrate 21 and the rear substrate 31 are arranged to face each other so that the scan electrode 22 and the sustain electrode 23 and the data electrode 32 intersect each other, and in the discharge space formed therebetween, for example, neon And a mixed gas of xenon. Note that the structure of the panel is not limited to the above-described structure, and for example, a structure having a stripe-shaped partition may be used.

  FIG. 2 is an electrode array diagram of the panel used in the embodiment of the present invention. N scan electrodes SC1 to SCn (scan electrode 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 23 in FIG. 1) are arranged in the row direction, and m data electrodes D1 to D1 are arranged in the column direction. Dm (data electrode 32 in FIG. 1) is arranged. A discharge cell is formed at a portion where a pair of scan electrode SCi and sustain electrode SUi (i = 1 to n) and one data electrode Dj (j = 1 to m) intersect, and the discharge cell is in the discharge space. M × n are formed.

  FIG. 3 is a circuit block diagram of the plasma display device according to the embodiment of the present invention. The plasma display device includes a panel 10, an image signal processing circuit 51, a data electrode drive circuit 52, a scan electrode drive circuit 53, a sustain electrode drive circuit 54, a timing generation circuit 55, and a power supply circuit (not shown).

  The image signal processing circuit 51 converts the image signal sig into image data for each subfield. The data electrode driving circuit 52 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm. The timing generation circuit 55 generates various timing signals based on the horizontal synchronization signal H and the vertical synchronization signal V and supplies them to each circuit block. Scan electrode drive circuit 53 supplies drive voltage waveforms to scan electrodes SC1 to SCn based on timing signals, and sustain electrode drive circuit 54 supplies drive voltage waveforms to sustain electrodes SU1 to SUn based on timing signals. Here, scan electrode driving circuit 53 includes sustain pulse generating unit 100 for generating a sustain pulse to be described later, and sustain electrode driving circuit 54 includes sustain pulse generating unit 200 in the same manner.

  Next, a driving voltage waveform for driving the panel and its operation will be described. In the embodiment of the present invention, one field is divided into a plurality of subfields, and each subfield has an initialization period, an address period, and a sustain period. FIG. 4 is a diagram showing drive voltage waveforms applied to the respective electrodes of the panel according to the embodiment of the present invention.

  In the initializing period of the first subfield, first, in the first half, the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn are held at 0 V, and from the voltage Vi1 that is lower than the discharge start voltage with respect to the scan electrodes SC1 to SCn. A ramp voltage that gradually increases toward the voltage Vi2 that exceeds the discharge start voltage is applied. Then, a weak initializing discharge is caused in all discharge cells, negative wall voltages are accumulated on scan electrodes SC1 to SCn, and positive wall voltages are accumulated on sustain electrodes SU1 to SUn and data electrodes D1 to Dm. The Here, the wall voltage on the electrode refers to a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the phosphor layer, or the like.

  Subsequently, in the second half of the initialization period, sustain electrodes SU1 to SUn are maintained at positive voltage Ve1, and a ramp voltage that gradually decreases from voltage Vi3 to voltage Vi4 is applied to scan electrodes SC1 to SCn. Then, a weak initializing discharge occurs again in all the discharge cells, the wall voltage between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn is weakened, and the positive wall voltage on data electrodes D1 to Dm is reduced. Is adjusted to a value suitable for the write operation.

  As described above, the initializing operation in the first subfield is an all-cell initializing operation in which initializing discharge is performed on all discharge cells.

  In the subsequent address period, sustain electrodes SU1 to SUn are held at voltage Ve2, and scan electrodes SC1 to SCn are held at Vc. Next, a negative scan pulse voltage Va is applied to scan electrode SC1 in the first row, and data electrode Dk (k = 1 to m) of the discharge cell to be displayed in the first row among data electrodes D1 to Dm. A positive address pulse voltage Vd is applied. At this time, the voltage at the intersection of the data electrode Dk and the scan electrode SC1 is obtained by adding the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 to the externally applied voltage (Vd−Va). The starting voltage is exceeded. Then, an address discharge occurs between data electrode Dk and scan electrode SC1 and between sustain electrode SU1 and scan electrode SC1, and a positive wall voltage is accumulated on scan electrode SC1 of this discharge cell, and on sustain electrode SU1. And a negative wall voltage is also accumulated on the data electrode Dk. In this manner, an address operation is performed in which address discharge is caused in the discharge cells to be displayed in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse voltage Vd is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, driving is performed using a power recovery circuit in order to reduce power consumption. The details of the drive voltage waveform will be described later, and here, the outline of the sustain operation in the sustain period will be described. First, positive sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn, and a ground potential, that is, 0 V is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage between scan electrode SCi and sustain electrode SUi is the sum of sustain pulse voltage Vs and the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeding the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 V is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, since the voltage between sustain electrode SUi and scan electrode SCi exceeds the discharge start voltage, a sustain discharge occurs again between sustain electrode SUi and scan electrode SCi, and the sustain cell is maintained. Negative wall voltage is accumulated on electrode SUi, and positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, by applying sustain pulses of the number corresponding to the luminance weight alternately to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, the sustain discharge continues in the discharge cells that have caused the address discharge in the address period. Done.

  Note that at the end of the sustain period, a potential difference in the form of a narrow pulse is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and the positive wall charges on data electrode Dk are left while scanning. The wall voltage on the electrode SCi and the sustain electrode SUi is erased. Thus, the maintenance operation in the maintenance period is completed.

  Here, the rise time of the first sustain pulse in the sustain period is set to be longer than the rise time of the subsequent sustain pulse. In the present embodiment, the rise time of the first sustain pulse is 650 ns. The subsequent sustain pulse rise time is set to 100 ns longer than 550 ns. Although details will be described later, this makes it possible to significantly suppress erroneous lighting. In this embodiment, the pulse width of the first sustain pulse in the sustain period is 20 μs, and thereafter The sustain pulse is set longer than the pulse width of 1.8 μs. This is due to the following reason. The discharge cells written at the beginning of the address period have a considerable time elapsed until the sustain discharge is generated, and the discharge delay of the sustain discharge tends to increase. Therefore, in order to reliably generate a sustain discharge even in a discharge cell having a large discharge delay, the pulse width of the first sustain pulse is set to be long.

  In the initializing period of the second subfield, sustain electrodes SU1 to SUn are held at voltage Ve1, and data electrodes D1 to Dm are held at 0 V, respectively, and scan electrodes SC1 to SCn gradually drop from voltage Vi3 ′ to voltage Vi4. Apply the ramp voltage. Then, a weak initializing discharge is generated in the discharge cell in which the sustain discharge has been performed in the sustain period of the previous subfield, and the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. For data electrode Dk, since the positive wall voltage is sufficiently accumulated on data electrode Dk in the immediately preceding sustain period, an excessive portion of this wall voltage is discharged, and the wall voltage suitable for the write operation is obtained. Adjusted to On the other hand, discharge cells that have not undergone sustain discharge in the previous subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained.

  As described above, the initializing operation of the second subfield is a selective initializing operation in which initializing discharge is selectively performed on the discharge cells that have undergone the sustain operation in the sustain period of the immediately preceding subfield.

  Since the operation in the writing period of the second subfield is the same as that of the first subfield, description thereof is omitted. The operation in the subsequent sustain period is the same as that in the first subfield except for the number of sustain pulses. In the subsequent subfields after the third subfield, substantially the same operation as in the second subfield is performed.

  In the present embodiment, it has been described that the all-cell initialization operation is performed in the initialization period of the first subfield and the selective initialization operation is performed in the initialization period of the second subfield. The invention is not limited to this, and all cell initialization and selective initialization operations may be arbitrarily performed in each subfield.

  Next, details of the operation in the sustain period will be described. First, details of sustain pulse generators 100 and 200, which are drive circuits for applying a sustain pulse to display electrode pairs to sustain discharge the discharge cells, will be described. FIG. 5 is a circuit diagram of sustain pulse generators 100 and 200 of the plasma display device in accordance with the exemplary embodiment of the present invention. Sustain pulse generation unit 100 includes power recovery unit 110 and clamp unit 120. The power recovery unit 110 includes a power recovery capacitor C10, switching elements Q11 and Q12, backflow prevention diodes D11 and D12, and a power recovery inductor L10. The clamp unit 120 includes a power source VS having a voltage value Vs, and switching elements Q13 and Q14. The power recovery unit 110 and the clamp unit 120 are connected to the scan electrode 22 which is one end of the interelectrode capacitance Cp of the panel 10 via a scan pulse generation circuit. In FIG. 5, the scan pulse generating circuit is not shown. Capacitor C10 has a sufficiently large capacity compared to interelectrode capacity Cp, is charged to a voltage value of approximately Vs / 2, and functions as a power source for power recovery unit 110.

  Sustain pulse generator 200 has the same circuit configuration as sustain pulse generator 100, and includes power recovery capacitor C20, switching elements Q21 and Q22, backflow prevention diodes D21 and D22, and power recovery inductor L20. A recovery unit 210 and a clamp unit 220 having a power source VS and switching elements Q23 and Q24 are provided, and the output of the sustain pulse generator 200 is connected to the sustain electrode 23 which is the other end of the interelectrode capacitance Cp of the panel 10.

  Next, details of the drive voltage waveform will be described. FIG. 6 is a timing chart for explaining a panel driving method according to the embodiment of the present invention. The first sustain pulse in the sustain period is indicated by T1 to T4, and then one sustain pulse period applied to the sustain electrode and the scan electrode is divided into six periods indicated by periods T4 to T9. explain.

(Period T1)
At time t1, switching element Q22 is turned on. Then, a current starts to flow from the sustain electrode 23 to the power recovery capacitor C20 through the inductor L20, the diode D22, and the switching element Q22, and the voltage of the sustain electrode 23 starts to decrease.

(Period T2)
Since the inductor L20 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the sustain electrode 23 decreases to around 0 V at time t2 after the time ½ of the resonance period has elapsed, but the resistance component of the resonance circuit Therefore, the voltage of the scan electrode 23 does not drop to 0V. At time t2, switching element Q24 is turned on. Then, since sustain electrode 23 is directly grounded through switching element Q24, the voltage of sustain electrode 23 is forcibly reduced to 0V.

  Further, the switching element Q11 is turned ON at time t2. Then, current begins to flow from the power recovery capacitor C10 through the switching element Q11, the diode D11, and the inductor L10, and the voltage of the scan electrode 22 begins to rise.

(Period T3)
Since the inductor L10 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the scan electrode 22 rises to near Vs at the time after ½ of the resonance period has elapsed, but it depends on the resistance component of the resonance circuit. Due to power loss, the voltage of the scan electrode 22 does not rise to Vs. And then it begins to fall again. In the present embodiment, the above-described resonance period is set to about 1100 ns, and the time until the voltage of the scan electrode 22 rises to a voltage slightly lower than Vs is about 550 ns after the time t2. In the present embodiment, the switching element Q13 is turned ON at time t3 after 100 ns. Then, since the scan electrode 22 is directly connected to the power supply VS through the switching element Q13, the voltage of the scan electrode 22 is forcibly increased to Vs. Then, in the discharge cell in which the address discharge has occurred, the voltage between scan electrode 22 and sustain electrode 23 exceeds the discharge start voltage, and the first sustain discharge in the sustain period is generated.

  Here, as described above, the pulse width of the first sustain pulse in the present embodiment is 20 μs, and is set longer than the pulse width of 1.8 μs after that.

  Switching element Q11 may be turned off after time t3 and before time t4, and switching element Q22 may be turned off after time t2 and before time t5. In order to lower the output impedance of sustain pulse generating units 100 and 200, switching element Q13 is preferably turned off immediately before time t4 and switching element Q24 is turned off immediately before time t5.

(Period T4)
At time t4, switching element Q12 is turned on. Then, the charge on the scan electrode 22 side starts to flow to the capacitor C10 through the inductor L10, the diode D12, and the switching element Q12, and the voltage of the scan electrode 22 starts to decrease.

(Period T5)
At time t5 after the half of the resonance period has elapsed, the voltage of scan electrode 22 decreases to near 0V. However, due to power loss due to the resistance component of the resonance circuit, the voltage of the scan electrode 22 cannot be reduced to 0V. At time t5, switching element Q14 is turned on. Then, since scan electrode 22 is directly grounded through switching element Q14, the voltage of scan electrode 22 is forcibly lowered to 0V.

  Further, the switching element Q21 is turned ON at time t5. Then, current starts to flow from the power recovery capacitor C20 through the switching element Q21, the diode D21, and the inductor L20, and the voltage of the sustain electrode 23 starts to rise.

(Period T6)
At time t6 after lapse of half the resonance period, the voltage of sustain electrode 23 rises to near Vs, but the voltage of sustain electrode 23 does not rise to Vs due to power loss due to the resistance component of the resonance circuit. Absent. At time t6, the switching element Q23 is turned on. Then, since sustain electrode 23 is directly connected to power supply VS through switching element Q23, the voltage of sustain electrode 23 is forcibly increased to Vs. Then, in the discharge cell in which the address discharge has occurred, the voltage between the scan electrode 22 and the sustain electrode 23 exceeds the discharge start voltage, and a sustain discharge occurs.

  Switching element Q12 may be turned off after time t5 and before time t8, and switching element Q21 may be turned off after time t6 and before time t7. In order to lower the output impedance of sustain pulse generating units 100 and 200, switching element Q14 is preferably turned off immediately before time t8, and switching element Q23 is preferably turned off immediately before time t7.

(Period T7-T9)
Since the sustain pulse applied to scan electrode 22 and the sustain pulse applied to sustain electrode 23 have the same waveform, the operation from period T7 to period T9 is the same as operation from period T4 to period T6. Since this is equivalent to the operation of replacing the electrode 23, the description thereof is omitted.

  The operations in the above periods T4 to T9 are repeated according to the required number of pulses.

  Next, the reason why the erroneous lighting can be significantly suppressed by applying the first sustain pulse of the sustain period to the scan electrode 22 using the power recovery unit over a period longer than ½ of the resonance period will be described. .

  First, a mechanism of erroneous lighting will be described. Various hypotheses have been considered for the occurrence of erroneous lighting, but the hypothesis that it is due to residual gas such as air existing inside the panel is promising. There are discharge cells (hereinafter abbreviated as “non-lighting cells”) that do not generate a sustain discharge over several fields or more in the discharge cells in the region displaying a dark image. In these non-lighting cells, residual gas or ions thereof blown out by discharge from a discharge cell (hereinafter abbreviated as “lighting cell”) that has generated a sustain discharge fly and adsorb. The adsorbed residual gas lowers the discharge start voltage of the non-lighting cell and forms non-uniform wall charges, generating a non-uniform electric field inside the non-lighting cell. If wall charges generate a local strong electric field inside the non-lighted cell, and a sustain pulse is applied to further strengthen this electric field, the discharge start voltage is also applied to the non-lighted cell that does not generate an address discharge. There is a high possibility that the sustain discharge will occur. As described in this embodiment, when the pulse width of the first sustain pulse in the sustain period is set to be long, the sum of the local wall voltage and the sustain pulse voltage only slightly exceeds the discharge start voltage, and the discharge delay Even if is large, the probability of reaching a sustain discharge is further increased.

  However, in the embodiment of the present invention, the rising time of the first sustain pulse in the sustain period is set long. As a result, the time spent as dark current before the wall charge that generates a strong local electric field inside the non-lighting cell develops into a sustain discharge is lengthened, and the local electric field is weakened and erroneous lighting is suppressed. Can be considered. Although the above is only one of the hypotheses, it has been experimentally confirmed that the effect of suppressing erroneous lighting is set by setting a long rise time of the first sustain pulse in the sustain period. FIG. 7 shows experimental data showing the relationship between the rise time of the first sustain pulse in the sustain period and the erroneous lighting. The horizontal axis indicates the rise time of the first sustain pulse in the sustain period, that is, the length of time T2, and the vertical axis The axis indicates the sustain pulse voltage at which erroneous lighting starts to occur. Here, the sustain pulse voltage at which erroneous lighting starts to occur is an index of the difficulty of erroneous lighting, and the higher the sustain pulse voltage at which erroneous lighting starts to occur, the less likely that erroneous lighting occurs. As shown in FIG. 7, when the rise time of the first sustain pulse is lengthened, it becomes difficult to generate an erroneous discharge until 650 ns, and it is experimentally demonstrated that the erroneous discharge can be suppressed most when set to 600 ns to 700 ns. I was able to confirm.

  Thus, in the present embodiment, the occurrence of erroneous discharge is suppressed by making the rise of the sustain pulse longer than ½ of the resonance period while keeping the pulse width of the first sustain pulse wide. As described above, the reason why the pulse width of the first sustain pulse is increased is to ensure that the sustain discharge of the discharge cell having a large discharge delay is generated, but erroneous lighting is likely to occur in the first sustain pulse. ing. Even if the pulse width of the first sustain pulse is narrowed, the probability of erroneous discharge can be reduced, but at the same time, the sustain discharge of the discharge cell having a large discharge delay becomes unstable. However, it has been found that by increasing the rising edge of the first sustain pulse, erroneous discharge can be suppressed without significantly adversely affecting the sustain discharge.

  In the present embodiment, the rising period of the first sustain pulse is extended longer than ½ of the resonance period using the power recovery unit, but the present invention is not limited to this. If a voltage lower than the voltage that generates the first sustain discharge is applied to the display electrode pair before the voltage that generates the first sustain discharge in the sustain period is applied to the display electrode pair, a strong local electric field is generated. The wall charges are consumed as dark current before developing into a sustain discharge, and erroneous discharge can be suppressed. FIG. 8 is a diagram showing drive voltage waveforms in another embodiment of the present invention. FIG. 8A shows a driving method in which, after a voltage Vs ′ lower than the sustain pulse voltage Vs is applied to the scan electrode 22 for a certain period T2, the sustain pulse voltage Vs is applied to the scan electrode 22 at time t3. . FIG. 8B shows a driving method in which a ramp voltage rising toward the sustain pulse voltage Vs is applied to the scan electrode 22 in the period T2, and then the sustain pulse voltage Vs is applied to the scan electrode 22 at time t3. It is. Even with other drive voltage waveforms, it is possible to suppress erroneous discharge if the wall charges that generate a strong local electric field can be reduced before the start of the sustain discharge.

  The panel driving method of the present invention is useful as an image display device or the like using a panel because it can suppress erroneous lighting and drive with high image display quality even for a high-luminance and high-definition panel.

The disassembled perspective view which shows the principal part of the panel used for embodiment of this invention. Electrode arrangement of the panel Circuit block diagram of plasma display device using the panel The figure which shows the drive voltage waveform impressed to each electrode of the panel Circuit diagram of sustain pulse generator of plasma display device using the panel Timing chart for explaining a panel driving method according to an embodiment of the present invention The figure which showed the experimental data which shows the relationship between the drive timing and the erroneous lighting at that time The figure which shows the drive voltage waveform in other embodiment of this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Panel 22 Scan electrode 23 Sustain electrode 32 Data electrode 51 Image signal processing circuit 52 Data electrode drive circuit 53 Scan electrode drive circuit 54 Sustain electrode drive circuit 55 Timing generation circuit 100,200 Sustain pulse generation part 110,210 Power recovery part 120, 220 Clamp part

Claims (3)

A method of driving a plasma display panel comprising a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode,
A sustain pulse generator for sustaining and discharging the discharge cells by applying a sustain pulse to the display electrode pair in the sustain period;
The sustain pulse generator applies a voltage to the display electrode pair that is lower than a voltage that generates the first sustain discharge before applying a voltage that generates the first sustain discharge in the sustain period to the display electrode pair. A method of driving a plasma display panel. The sustain pulse generator is connected to a power recovery unit that applies a voltage to the display electrode pair by resonance between a capacitance between the electrodes of the display electrode pair and a power recovery inductor, and a predetermined power source or ground potential. And a clamp part for applying a voltage to the display electrode pair,
A voltage lower than a voltage for generating the first sustain discharge is applied to the display electrode pair using the power recovery unit over a period longer than ½ of a resonance period of the power recovery unit. The method for driving a plasma display panel according to claim 1. 3. The method of driving a plasma display panel according to claim 1, wherein a period longer than ½ of a resonance period of the power recovery unit is 600 μs to 700 μs. 4.

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