JP2012037589A - Driving method of plasma display panel, and plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate an emission independent of gradation display by omitting forced initialization operation while stably generating writing operation.SOLUTION: When a voltage obtained by subtracting a data electrode voltage from a low voltage side voltage of a sustaining pulse is a first voltage, and a voltage obtained by subtracting a low voltage side voltage of a data pulse from a low voltage side voltage of a scanning pulse is a third voltage, a voltage obtained by subtracting the third voltage from the first voltage is a discharge start voltage or more where the data electrode is an anode and a scanning electrode is a cathode. In an erasure period, erasure discharge is selectively generated only in a discharge cell with a write discharge generated in a last write period, and in the erasure period, a fourth voltage of positive polarity is applied to the data electrode. In a write period, a downward inclined waveform voltage descending toward a fifth voltage higher than a voltage obtained by superimposing the fourth voltage to a low voltage side voltage of the scanning pulse applied to the scanning electrode is applied to the scanning electrode, and the erasure discharge is selectively generated only in the discharge cell with the write discharge generated in the last write period.

Description

  The present invention relates to an AC surface discharge type plasma display panel driving method and a plasma display apparatus.

  A plasma display panel (hereinafter abbreviated as “panel”) includes a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode. Red, green, and blue light are generated by ultraviolet rays generated by gas discharge in the discharge cell. Color display is performed by exciting and emitting phosphors of each color.

  As a method for driving the panel, a subfield method, that is, a method in which a single field is formed using a plurality of subfields having an initialization period, an address period, and a sustain period, and gradation display is performed by combining subfields that emit light. Is common. An initialization operation is performed during the initialization period of each subfield, a write operation is performed during the write period, and a maintenance operation is performed during the sustain period. The initialization operation is an operation that generates initialization discharge and forms wall charges necessary for the subsequent address operation. The initializing operation includes a forced initializing operation that generates an initializing discharge regardless of the operation of the immediately preceding subfield, and a selective initializing operation that generates an initializing discharge in a discharge cell that has performed an address discharge in the immediately preceding subfield. There is. The address operation is an operation in which an address discharge is selectively generated in the discharge cells in accordance with an image to be displayed to form wall charges, and the sustain operation is to generate a sustain discharge by alternately applying a sustain pulse to the display electrode pair, This is an operation of causing the phosphor layer of the corresponding discharge cell to emit light. The light emission of the phosphor layer due to the sustain discharge is light emission related to gradation display, and the other light emission is light emission not related to gradation display.

  There is a driving method that improves the contrast by lowering the luminance (hereinafter abbreviated as “black luminance”) when displaying black, which is the lowest gradation among the subfield methods, and reducing light emission not related to gradation display as much as possible. It is being considered. For example, Patent Document 1 discloses a driving method in which the forced initialization operation is performed once per field and the forced initialization operation is performed using a slowly changing ramp waveform voltage.

  Further, in Patent Document 2, the display electrode pair is divided into n, the number of times of forced initialization operation is set to once per n fields, light emission not related to gradation display is further reduced, black luminance is further reduced, and contrast is further increased. An improved driving method is disclosed.

JP 2000-242224 A JP 2006-091295 A

  However, even with the driving methods described in Patent Document 1 and Patent Document 2, since the forced initialization operation is performed, light emission not related to gradation display occurs. This means that even a discharge cell displaying black emits light, and thus there is a limit to improving the contrast. In addition, the forced initialization operation has a function of accumulating wall charges necessary for generating an address discharge in the subsequent address period, and in addition, a priming for surely generating an address discharge by shortening the discharge delay time. It also has the function of generating. Therefore, if the forced initializing operation is simply omitted, there is a problem that the address discharge does not occur, or the address delay becomes too long for the address discharge to become unstable, and normal image display cannot be performed.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a panel driving method and a plasma display device that perform stable writing operation and improve contrast without using forced initialization operation.

  In order to achieve the above object, the present invention forms a single field using a plurality of subfields each having an address period, a sustain period, and an erase period, and includes a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode. A panel driving method for driving a provided panel, wherein a voltage obtained by subtracting a voltage applied to a data electrode from a low-voltage side voltage of a sustain pulse applied to a scan electrode during a sustain period is defined as a first voltage, and scanning is performed during the sustain period. The voltage obtained by subtracting the voltage applied to the data electrode from the high-voltage side voltage of the sustain pulse applied to the electrode is used as the second voltage, and the data pulse applied to the data electrode from the low-voltage side voltage of the scan pulse applied to the scan electrode in the address period When the voltage obtained by subtracting the low-voltage side voltage is the third voltage, the voltage obtained by subtracting the third voltage from the first voltage uses the data electrode as the anode and the scan electrode. A voltage obtained by subtracting the third voltage from the second voltage, which is equal to or higher than the discharge start voltage for the cathode, is the discharge start voltage with the data electrode as the anode and the scan electrode as the cathode, and the data electrode as the cathode and the scan electrode as the anode. The positive fourth voltage is applied to the data electrode during the erasing period, and the low voltage of the scan pulse applied to the scan electrode during the address period is 4 is applied to the scan electrode with a falling ramp waveform voltage falling toward the fifth voltage higher than the voltage superposed with the voltage of 4, and the erasing discharge is selectively performed only in the discharge cells that have generated the address discharge in the immediately preceding address period. Is generated. By this method, it is possible to provide a panel driving method in which the forced initialization operation is omitted while the writing operation is stably generated, the light emission not related to the gradation display is eliminated, and the contrast is greatly improved.

  In the panel driving method of the present invention, the rising ramp waveform voltage is applied to the scan electrode during the erasing period, and then the fourth voltage is applied to the data electrode and the falling ramp descends toward the fifth voltage. A waveform voltage is applied to the scan electrode, then a positive rectangular voltage is applied to the scan electrode, and then a fourth voltage is applied to the data electrode and a downward ramp waveform voltage that decreases toward the fifth voltage is applied. An erasing discharge may be generated by applying the scanning electrode.

  The present invention also comprises a panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, and a plurality of subfields each having an address period, a sustain period, and an erase period. And a driving circuit that generates a voltage waveform and applies it to each electrode of the panel, wherein the driving circuit applies to the data electrode from the low-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period The voltage obtained by subtracting the voltage is set as the first voltage, the voltage obtained by subtracting the voltage applied to the data electrode from the high-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period is set as the second voltage, and the scan electrode is applied in the write period. When the voltage obtained by subtracting the low-voltage side voltage of the data pulse applied to the data electrode from the low-voltage side voltage of the applied scan pulse is the third voltage, The voltage obtained by subtracting the third voltage from the voltage is equal to or higher than the discharge start voltage using the data electrode as the anode and the scan electrode as the cathode, and the voltage obtained by subtracting the third voltage from the second voltage as the anode is used for scanning. The voltage is set so as not to exceed the sum of the discharge start voltage with the electrode as the cathode and the discharge start voltage with the data electrode as the cathode and the scan electrode as the anode, and the positive fourth voltage is applied to the data electrode during the erasing period. And applying a downward ramp waveform voltage that falls toward the fifth voltage higher than the voltage obtained by superimposing the fourth voltage on the low-voltage side voltage of the scan pulse applied to the scan electrode in the address period, to the scan electrode. The erasing discharge is selectively generated only in the discharge cells that have generated the address discharge in the immediately preceding address period. With this configuration, it is possible to provide a plasma display device that performs stable writing operation and improves contrast without using forced initialization operation.

  According to the present invention, it is possible to provide a panel driving method and a plasma display apparatus that perform stable writing operation and improve contrast without using forced initialization operation.

It is a disassembled perspective view of the panel used for the plasma display apparatus in Embodiment 1 of this invention. It is an electrode array figure of the panel used for the plasma display apparatus. It is a drive voltage waveform figure applied to each electrode of the plasma display apparatus. It is a figure for demonstrating the definition of a 1st voltage, a 2nd voltage, and a 3rd voltage. It is a figure which shows an example of the method of measuring a discharge start voltage. It is a circuit block diagram of the plasma display apparatus in Embodiment 1 of the present invention. It is a circuit diagram of the scan electrode drive circuit of the plasma display device. It is a circuit diagram of the sustain electrode drive circuit of the plasma display device. It is a circuit diagram of the data electrode drive circuit of the plasma display device. It is a drive voltage waveform figure in the 1st field applied to each electrode of the plasma display apparatus in Embodiment 2 of this invention. It is a drive voltage waveform figure in the 2nd field applied to each electrode of the plasma display apparatus.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the display electrode pair 24, and a protective layer 26 is formed on the dielectric layer 25. The protective layer 26 is formed using magnesium oxide, which is a material having high electron emission performance, in order to easily generate discharge. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33. For example, (Y, Gd) BO3: Eu is used as a red phosphor, Zn2SiO4: Mn is used as a green phosphor, and BaMgAl10O17: Eu is used as a blue phosphor. Is used.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is sealed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) that are long in the row direction. M data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed.

  Next, a driving voltage waveform for driving panel 10 and its operation will be described. The plasma display apparatus displays an image by subfield method, that is, by dividing one field into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield.

  In the present embodiment, each subfield has an address period, a sustain period, and an erase period. In the present embodiment, the forced initializing operation for forcibly generating the initializing discharge is not performed regardless of the presence or absence of the previous discharge.

  In the address period, an address operation is performed in which address discharge is selectively generated in the discharge cells to emit light to form wall charges. In the sustain period, a sustain operation is performed in which a sustain pulse of the number corresponding to the luminance weight determined in advance for each subfield is alternately applied to the display electrode pair to generate a sustain discharge in the discharge cell that generated the address discharge. I do. Note that the maintenance period may be omitted in order to keep the emission luminance low. In the erasing period, an erasing discharge is selectively generated only in the discharge cells that generated the address discharge in the immediately preceding address period, and the history of wall charges formed by the address discharge or the subsequent sustain discharge is erased, and the subsequent address discharge is performed. An erasing operation is performed to form necessary wall charges on each electrode.

  As a subfield configuration, for example, one field is divided into 10 subfields (SF1, SF2,..., SF10), and each subfield is (1, 2, 3, 6, 11, 18, 30). , 44, 60, 80). However, the present invention is not limited to the subfield configuration such as the number of subfields and the luminance weight.

  FIG. 3 is a drive voltage waveform diagram applied to each electrode of the plasma display device in accordance with the first exemplary embodiment of the present invention.

  In the address period of SF1, voltage 0 (V) is applied to data electrode D1 through data electrode Dm, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and voltage Vc is applied to scan electrode SC1 through scan electrode SCn. Next, a scan pulse of voltage Va is applied to scan electrode SC1 in the first row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light.

  Then, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is because the positive wall voltage on the data electrode Dk is added to the difference (Vd−Va) of the externally applied voltage, and exceeds the discharge start voltage VFds. Discharge occurs between data electrode Dk and scan electrode SC1. Then, the discharge generated between data electrode Dk and scan electrode SC1 extends between scan electrode SC1 and sustain electrode SU1, and an address discharge occurs. A positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrode Dh to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage VFds, so the address discharge does not occur.

  Next, a scan pulse is applied to scan electrode SC2 in the second row, and an address pulse is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, an address discharge occurs between data electrode Dk and scan electrode SC2 and between sustain electrode SU2 and scan electrode SC2, a positive wall voltage is accumulated on scan electrode SC2, and a negative wall voltage is applied on sustain electrode SU2. And a negative wall voltage is also accumulated on the data electrode Dk. In this manner, an address operation is performed in which an address discharge is caused in the discharge cell to be lit in the second row and wall voltage is accumulated on each electrode. On the other hand, since the voltage at the intersection between the data electrode Dh and the scan electrode SC2 to which no address pulse is applied does not exceed the discharge start voltage VFds, no address discharge occurs.

  Thereafter, the same address operation is performed until the scan electrode SCn in the n-th row, and wall charges necessary for the subsequent sustain discharge are formed.

  Here, for the following description, the first voltage V1, the second voltage V2, and the third voltage V3 are defined as shown in FIG. A voltage obtained by subtracting the voltage applied to the data electrode Dj from the low-voltage side voltage of the sustain pulse applied to the scan electrode SCi in the sustain period to be described later is defined as a first voltage V1, and the high voltage of the sustain pulse applied to the scan electrode SCi in the sustain period. The voltage obtained by subtracting the voltage applied to the data electrode Dj from the side voltage is the second voltage V2, and the low voltage side voltage of the data pulse applied to the data electrode Dj from the low voltage side voltage of the scan pulse applied to the scan electrode SCi in the address period The voltage obtained by subtracting is set as the third voltage V3.

  Further, a discharge start voltage with the data electrode Dj as an anode and the scan electrode SCi as a cathode is a discharge start voltage VFds, and a discharge start voltage with the data electrode Dj as a cathode and the scan electrode SCi as an anode is a discharge start voltage VFsd. The discharge with the data electrode Dj as the anode and the scan electrode SCi as the cathode is a discharge in which the electric field in the discharge cell when the discharge occurs is a high potential side on the data electrode Dj side and a low potential side on the scan electrode SCi side. It is. The discharge with the data electrode Dj as the cathode and the scan electrode SCi as the anode is a discharge in which the electric field in the discharge cell when the discharge occurs is a low potential side on the data electrode Dj side and a high potential side on the scan electrode SCi side. is there. Since the protective layer 26 of magnesium oxide having high electron emission performance is formed on the scan electrode SCi side, the discharge start voltage VFds is lower than the discharge start voltage VFsd.

  At this time, the voltage Va of the scan pulse applied to the scan electrode SCi is set so as to satisfy the following two conditions (condition 1) and (condition 2).

(Condition 1) For all discharge cells, the voltage obtained by subtracting the third voltage V3 from the first voltage V1 is equal to or higher than the discharge start voltage VFds with the data electrode Dj as the anode and the scan electrode SCi as the cathode,
(V1-V3) ≧ VFds is satisfied.

(Condition 2) For all the discharge cells, a voltage obtained by subtracting the third voltage V3 from the second voltage V2 is a discharge start voltage VFds and a data electrode Dj with the data electrode Dj as an anode and the scan electrode SCi as a cathode. And the discharge start voltage VFsd with the scan electrode SCi as the anode and not exceeding, that is,
(V2−V3) ≦ (VFds + VFsd) is satisfied.

  In the sustain period of SF1 following the address period, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, and a sustain pulse of voltage Vs is applied to scan electrode SC1 through scan electrode SCn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the voltage Vs plus the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. It exceeds the discharge start voltage VFss between scan electrode SCi and sustain electrode SUi. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. On the other hand, the sustain discharge does not occur in the discharge cells in which the address discharge has not occurred, and the wall voltage at the end of the initialization operation is maintained.

  Subsequently, voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn, and a sustain pulse of voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. Then, the sustain discharge occurs again in the discharge cell in which the sustain discharge has occurred, and the phosphor layer 35 emits light. Then, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, sustain pulses of the number corresponding to the luminance weight are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and the sustain discharge is continued in the discharge cells that have caused the address discharge. generate.

  In the subsequent erasing period of SF1, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, and an upward ramp waveform voltage that gradually rises to voltage Vr is applied to scan electrode SC1 through scan electrode SCn. In the present embodiment, the voltage Vr is set to the same voltage as the voltage Vs. Then, in a discharge cell that has undergone a sustain discharge (a discharge cell that has undergone an address discharge when the sustain period is omitted), a first weak erase discharge is generated with scan electrode SCi as an anode and sustain electrode SUi as a cathode. . Then, the wall voltage on scan electrode SCi and sustain electrode SUi is weakened.

  Next, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn. The positive fourth voltage is applied to the data electrodes D1 to Dm, and the fourth voltage is superimposed on the low-voltage side voltage Va of the scan pulse applied to the scan electrodes SC1 to SCn in the address period. A downward ramp waveform voltage that gradually falls toward higher fifth voltage Vi is applied to scan electrode SC1 through scan electrode SCn. In the present embodiment, the fourth voltage is set to the same voltage as the voltage Vd. Then, a weak discharge is generated again in the discharge cell that has generated the first weak erase discharge. The discharge at this time is a discharge using the scan electrode SCi as a cathode and the data electrode Dk as an anode.

  Due to this weak discharge, excessive portions of the wall voltage on scan electrode SCi, sustain electrode SUi, and data electrode Dk are discharged and adjusted to a wall voltage suitable for the address operation. In this manner, the erasing operation for selectively generating the erasing discharge is completed only in the discharge cells that have generated the address discharge in the immediately preceding address period.

  The subsequent operations in SF2 to SF10 are the same as those in SF1 except for the number of sustain pulses.

  As described above, in the present embodiment, in the erase period of all subfields, the erase discharge is generated only in the discharge cells in which the address discharge is generated in the immediately preceding address period. In addition, no discharge occurs in the discharge cells that did not generate the address discharge. Therefore, no light emission occurs in the discharge cell displaying black.

  In this embodiment, the voltage Vi is −260 (V), the voltage Vc is −145 (V), the voltage Va is −280 (V), the voltage Vs is 200 (V), the voltage Vr is 200 (V), The voltage Ve is 20 (V), and the voltage Vd is 60 (V). However, these voltage values are not limited to the values described above, and are desirably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.

  Note that the discharge start voltage VFds and the discharge start voltage VFsd of the panel 10 used in the present embodiment are measured by the methods described later, and their values are as follows. The discharge start voltage varies depending on the phosphor, and the discharge start voltage VFds between the “data electrode-scan electrode” for the discharge cell coated with the red phosphor is 200 ± 10 (V), and the discharge start voltage VFsd is 320 ± 10 ( V), the discharge start voltage VFds between the “data electrode and the scan electrode” for the discharge cell coated with the green phosphor is 220 ± 10 (V), the discharge start voltage VFsd is 350 ± 10 (V), and the blue fluorescence The discharge start voltage VFds between the “data electrode and the scan electrode” for the discharge cell coated with the body was 200 ± 10 (V), and the discharge start voltage VFsd was 330 ± 10 (V). The discharge start voltage VFss between the “scan electrode and sustain electrode” is 250 ± 10 (V) for the discharge cells coated with red and blue phosphors, and for the discharge cells coated with green phosphors, It was 280 ± 10 (V).

  In the present embodiment, the voltage on the low voltage side of the sustain pulse is voltage 0 (V), and the voltage applied to the data electrode in the sustain period is voltage 0 (V), so the first voltage V1 is voltage 0 (V ). Further, since the low-voltage side of the scan pulse is the voltage Va and the low-voltage side voltage of the data pulse is the voltage 0 (V), the third voltage V3 is the voltage Va. Further, the maximum value of the discharge start voltage VFds is a voltage 230 (V) in consideration of variations. Therefore, (first voltage V1−third voltage V3) = − Va> (maximum value of VFds), that is, 280 (V)> 230 (V), and (condition 1) is satisfied in all discharge cells. You can see that

  Further, since the high voltage side of the sustain pulse is the voltage Vs and the voltage applied to the data electrode in the sustain period is the voltage 0 (V), the second voltage V2 is the voltage Vs. The minimum value of the sum of the discharge start voltage VFsd and the discharge start voltage VFds is a voltage 500 (V). Therefore, the minimum value of (second voltage V2−third voltage V3) = Vs−Va <(VFds + VFsd), that is, 480 (V) <500 (V), and (condition 2) also applies to all discharge cells. You can see that you are satisfied.

  Further, as apparent from the above voltage, a voltage lower than the low voltage side voltage Va of the scan pulse is applied to the scan electrode by applying a voltage not lower than the low voltage side voltage Va of the scan pulse and not higher than the high voltage side voltage Vs of the sustain pulse. A voltage exceeding the high voltage Vs of the sustain pulse is not applied. Therefore, a discharge cell that has not performed address discharge does not emit light.

  As apparent from the above voltage, when the voltage Va is set low so as to satisfy (Condition 1), the absolute value | Va | of the low-voltage side voltage Va of the scan pulse is the absolute value of the high-voltage side voltage Vs of the sustain pulse. It becomes larger than the value | Vs |.

  Thus, in the present embodiment, the drive voltage waveform applied to each electrode, in particular, the voltage Va of the scan pulse is set to satisfy (Condition 1) and (Condition 2). That is, in the erasing period, the erasing discharge is selectively generated only in the discharge cells that have generated the address discharge in the immediately preceding address period, and the data electrode Dj is applied from the low-voltage side voltage of the sustain pulse applied to the scan electrode SCi in the sustain period. The voltage obtained by subtracting the voltage applied to the first electrode V1 is defined as the first voltage V1, and the voltage obtained by subtracting the voltage applied to the data electrode Dj from the high voltage on the sustain pulse applied to the scan electrode SCi in the sustain period is defined as the second voltage V2. When the voltage obtained by subtracting the low-voltage side voltage of the data pulse applied to the data electrode Dj from the low-voltage side voltage of the scan pulse applied to the scan electrode SCi in the address period is the third voltage V3, the first voltage V1 to the first voltage 3 is equal to or higher than the discharge start voltage VFds having the data electrode Dj as the anode and the scan electrode SCi as the cathode, and the voltage V3 is reduced from the second voltage V2. 3 is less than the sum of the discharge start voltage VFds with the data electrode Dj as the anode and the scan electrode SCi as the cathode and the discharge start voltage VFsd with the data electrode Dj as the cathode and the scan electrode SCi as the anode. Absent. By setting in this way, the write operation can be stably generated without using the forced initialization operation. The reason is considered as follows.

  First, (Condition 1) will be described. In order to generate the address discharge, it is necessary to start the discharge between the data electrode Dj and the scan electrode SCi. In order to start a discharge by applying a relatively low voltage Vda to the data electrode Dj, a voltage substantially equal to the discharge start voltage VFds is applied between the data electrode Dj and the scan electrode SCi when a scan pulse is applied to the scan electrode SCi. A sufficient positive wall voltage must be stored on the data electrode Dj to be applied in between. As described above, in this embodiment, the forced initialization operation is not performed, and no discharge is generated in the discharge cells displaying black. Therefore, the wall voltage cannot be actively controlled, and the wall voltage of the discharge cell displaying black is indefinite. However, even in such a discharge cell, if there are a few charged particles in the discharge space, they move to each electrode so as to relax the electric field inside the discharge space and adhere to the wall of the discharge cell. Accumulate wall voltage.

  First, the wall voltage accumulated in this way will be described. During the sustain period, a large amount of charged particles are generated in the discharge cell that generates the sustain discharge, and when these particles diffuse, a small amount of charged particles are supplied to the space inside the discharge cell that displays black without causing the sustain discharge. It is thought that. In the discharge cell displaying black, wall voltages are slowly accumulated so as to alleviate the potential difference between the electrodes by the voltages applied to scan electrode SCi, sustain electrode SUi, and data electrode Dj. If the voltage at which the wall voltage gradually approaches (finally settles) is defined as the neglected wall voltage, the neglected wall voltage when the sustain pulse is continuously applied alternately to the scan electrode SCi and the sustain electrode SUi is the high voltage of the sustain pulse. The voltage is between the side voltage and the low voltage. Actually, since a drive voltage waveform other than the sustain pulse is also applied, it can be considered that the neglected wall voltage of each discharge cell is substantially close to the low-voltage side voltage of the sustain pulse.

  The neglected wall voltage is greatly affected by the charging characteristics of the phosphor applied inside the discharge cell. In this embodiment, the charging characteristics of the phosphor are +20 (μC / g) for the red phosphor, −30 (μC / g) for the green phosphor, and +10 (μC / g) for the blue phosphor, respectively. Since only the green phosphor is charged to a negative potential, the neglected wall voltage is lower than that of the red and blue phosphors.

  Next, the voltage inside the discharge cell in the address period will be described. On the data electrode Dh of the discharge cell displaying black, a wall voltage is gradually accumulated toward the low voltage on the low side of the sustain pulse or a neglected wall voltage higher than that. On the other hand, the voltage Va of the scan pulse in the present embodiment is a voltage that satisfies (Condition 1). Therefore, a positive wall voltage sufficient to generate the address discharge is accumulated on the data electrode Dh, and the address discharge can be generated without performing any forced initialization operation.

  In addition, the wall voltage of the discharge cell displaying black slowly approaches the left wall voltage, and when the voltage obtained by adding the wall voltage to the voltage between the “data electrode-scan electrode” approaches the discharge start voltage during the erasing period, the dark current is generated. The wall voltage on the data electrode Dh is decreased. And since the dark current flowing at this time plays a role of priming to assist the address discharge, it is considered that a stable address discharge can be generated without causing a large discharge delay even in a discharge cell displaying black. be able to.

  In this way, by setting the drive voltage applied to each electrode to satisfy (Condition 1), in particular, by setting the scan pulse voltage Va low so as to satisfy (Condition 1), the forced initialization operation is not performed. The wall voltage necessary for addressing can be accumulated, and priming for stabilizing the address discharge can also be generated.

  Next, (Condition 2) will be described. If the voltage Va of the scan pulse is too low, a discharge occurs regardless of whether or not an address operation is performed when the sustain pulse voltage Vs is applied to the scan electrode in the sustain period, and an image cannot be displayed. In order to suppress this erroneous discharge, it is necessary to set the voltage between the “data electrode-scanning electrode” to be equal to or lower than the discharge start voltage VFsd when the sustain pulse voltage Vs is applied. This condition is (Condition 2).

  Thus, in the present embodiment, the drive voltage waveform is set so as to satisfy (Condition 1) and (Condition 2) in all the discharge cells. Therefore, it is possible to display an image without light emission not related to gradation display by omitting the forced initialization operation while stably generating the writing operation.

  In the present embodiment, in the erasing period, the rising ramp waveform voltage that rises gently is applied to scan electrode SC1 through scan electrode SCn, and then voltage Vd is applied to data electrode D1 through data electrode Dm as the fourth voltage. At the same time, a downward ramp waveform voltage that gently falls toward the fifth voltage Vi was applied to scan electrode SC1 through scan electrode SCn. The reason why such driving is performed will be described below.

  In the present embodiment, since the forced initialization operation is omitted, the influence of the neglected wall voltage is great, and the wall voltage variation of each discharge cell tends to increase. Therefore, in the present embodiment, when a downward ramp waveform voltage that gently falls toward voltage Vi that is the fifth voltage is applied to scan electrode SC1 through scan electrode SCn, voltage Vd that is the fourth voltage is applied. The data electrodes D1 to Dm are applied. By doing so, it is possible to positively generate a discharge between the data electrode Dk and the scan electrode SCi, and it is possible to accurately adjust the wall voltage on the data electrode Dk. In order to compensate for the wall voltage which is insufficient due to this discharge and to generate the address discharge, the low voltage side voltage Va of the scan pulse is set lower than the voltage obtained by subtracting the fourth voltage Vd from the fifth voltage Vi. . That is, in the erasing period, a downward slope that decreases toward the fifth voltage Vi higher than the voltage obtained by superimposing the fourth voltage Vd on the low-voltage side voltage Va of the scan pulse applied to the scan electrodes SC1 to SCn in the write period. Waveform voltage is applied to scan electrode SC1 through scan electrode SCn.

  In order to prevent malfunction due to abnormal charges, the following drive voltage waveform may be applied to each electrode during the erasing period.

  At the beginning of the erasing period, an upward ramp waveform voltage rising toward the voltage Vr is applied to scan electrode SC1 through scan electrode SCn, and then a fourth voltage is applied to data electrode D1 through data electrode Dm and a fifth voltage is applied. A downward ramp waveform voltage that decreases toward voltage Vi is applied to scan electrode SC1 through scan electrode SCn, then a rectangular voltage of positive voltage Vr is applied to scan electrode SC1 through scan electrode SCn, and then a fourth voltage is applied. An erase discharge may be generated by applying a voltage to the data electrode D1 to the data electrode Dm and applying a downward ramp waveform voltage that decreases toward the fifth voltage Vi to the scan electrode SC1 to the scan electrode SCn. Here, the slope of the upward ramp waveform voltage applied to scan electrode SC1 to scan electrode SCn is 10 (V / μs), and the slope of the downward ramp waveform voltage applied to scan electrode SC1 to scan electrode SCn is −1.5. (V / μs). However, these values are merely examples, and the present invention is not limited to the above values.

  Even if the forced initializing operation is omitted in this way, it is possible to accumulate a sufficient wall voltage on each electrode by repeatedly generating a weak discharge several times during the erasing period, and to stabilize the subsequent address discharge. Can be generated.

  Note that the discharge start voltage VFsd, the discharge start voltage VFds, and the wall voltage are, for example, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-24, NO. 7, JULY, 1977 "Measurement of a Plasma in the AC Plasma Display panel Using RF Capacitance and Microwave Techniques". Or you may measure simply as follows. An example of a method for simply measuring the discharge start voltage will be described with reference to FIG.

  First, an operation for erasing wall charges is performed. Specifically, as shown in the wall charge erasing period of FIG. 5, a pulsed voltage Vers sufficiently higher than the expected discharge start voltage is alternately applied between the electrodes to be measured, for example, the data electrode and the scan electrode. To do. Next, the discharge start is observed. Specifically, as shown in the measurement period of FIG. 5, a pulsed voltage Vmsr lower than the expected discharge start voltage is applied to one electrode, for example, the data electrode, and the light emission associated with the discharge at that time is photogenerated. Detection is performed using a light detection sensor such as Maru. When no discharge is observed, after performing an operation of erasing wall charges during the wall charge erasing period, light emission is observed by applying a pulsed voltage Vmsr with a slightly increased absolute value of voltage during the measurement period.

  This operation is repeated, and the voltage Vmsr having the minimum absolute value at which light emission is observed in the measurement period is the discharge start voltage. At this time, if the voltage Vmsr applied in the measurement period is a positive voltage, the discharge start voltage VFds with the data electrode as the anode and the scan electrode as the cathode can be measured. If the voltage Vmsr applied during the measurement period is a negative voltage, the discharge start voltage VFsd with the data electrode as the cathode and the scan electrode as the anode can be measured.

  If the discharge start voltage is known, the voltage at which discharge starts is measured for the discharge cell in which the wall voltage is accumulated, and the wall voltage can be known as the difference between the voltage value and the discharge start voltage measured in advance. .

  Next, a drive circuit for driving the panel 10 will be described. FIG. 6 is a circuit block diagram of plasma display device 40 in accordance with the exemplary embodiment of the present invention. The plasma display device 40 includes the panel 10 and its drive circuit. The drive circuit includes an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and each of them. A power supply circuit (not shown) for supplying necessary power to the circuit block is provided.

  The image signal processing circuit 41 converts the input image signal into image data indicating light emission / non-light emission for each subfield. The data electrode driving circuit 42 converts the image data for each subfield into address pulses corresponding to the data electrodes D1 to Dm and applies them to the data electrodes D1 to Dm. The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block on the basis of the vertical and horizontal synchronization signals, and supplies them to the respective circuit blocks. Scan electrode drive circuit 43 generates the drive voltage waveform described above based on the timing signal and applies it to each of scan electrodes SC1 to SCn. Sustain electrode drive circuit 44 generates the drive voltage waveform described above based on the timing signal and applies it to sustain electrode SU1 through sustain electrode SUn.

  FIG. 7 is a circuit diagram of scan electrode drive circuit 43 of plasma display device 40 in accordance with the first exemplary embodiment of the present invention. Scan electrode drive circuit 43 includes sustain pulse generation circuit 50, ramp waveform voltage generation circuit 60, and scan pulse generation circuit 70.

  Sustain pulse generation circuit 50 includes power recovery circuit 51, switching element Q55, switching element Q56, and switching element Q59, and generates sustain pulses to be applied to scan electrode SC1 through scan electrode SCn. The power recovery circuit 51 recovers and reuses power when driving the scan electrodes SC1 to SCn. Switching element Q55 clamps scan electrode SC1 through scan electrode SCn to voltage Vs, and switching element Q56 clamps scan electrode SC1 through scan electrode SCn to voltage 0 (V). The switching element Q59 is a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43.

  Scan pulse generating circuit 70 includes switching element Q71H1 to switching element Q71Hn, switching element Q71L1 to switching element Q71Ln, and switching element Q72. Then, a scan pulse is generated based on the power source of voltage Va and the power source E71 of voltage (Vc−Va) superimposed on the reference potential of the scan pulse generating circuit 70 (the potential of the node A shown in FIG. 7). Scan pulses are sequentially applied to each of scan electrode SC1 through scan electrode SCn at the timing shown in FIG. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 50 as it is during the sustain operation. That is, the voltage at node A is output to scan electrode SC1 through scan electrode SCn.

  The ramp waveform voltage generation circuit 60 includes a Miller integration circuit 61 and a Miller integration circuit 63, and generates the ramp waveform voltage shown in FIG. Miller integrating circuit 61 includes transistor Q61, capacitor C61, and resistor R61. By applying a constant voltage to input terminal IN61, Miller integrating circuit 61 generates an upward ramp waveform voltage that gradually increases toward voltage Vr. Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63, and applies a constant voltage to input terminal IN63, thereby generating a downward ramp waveform voltage that gradually falls toward voltage Vi. The switching element Q69 is also a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode drive circuit 43.

  In addition, these switching elements and transistors can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the switching elements and transistors generated by the timing generation circuit 45.

  FIG. 8 is a circuit diagram of sustain electrode drive circuit 44 of plasma display device 40 in accordance with the first exemplary embodiment of the present invention. Sustain electrode drive circuit 44 includes sustain pulse generation circuit 80 and constant voltage generation circuit 85.

  Sustain pulse generation circuit 80 includes power recovery circuit 81, switching element Q83, and switching element Q84, and generates sustain pulses to be applied to sustain electrode SU1 through sustain electrode SUn. The power recovery circuit 81 recovers and reuses the power when driving the sustain electrodes SU1 to SUn. Switching element Q83 clamps sustain electrode SU1 through sustain electrode SUn to voltage Vs, and switching element Q84 clamps sustain electrode SU1 through sustain electrode SUn to voltage 0 (V).

  Constant voltage generation circuit 85 includes switching element Q86 and switching element Q87, and applies voltage Ve to sustain electrode SU1 through sustain electrode SUn.

  In addition, these switching elements can also be comprised using generally known elements, such as MOSFET and IGBT. These switching elements are also controlled by timing signals corresponding to the respective switching elements generated by the timing generation circuit 45.

  FIG. 9 is a circuit diagram of data electrode drive circuit 42 of plasma display device 40 in accordance with the first exemplary embodiment of the present invention. Data electrode drive circuit 42 includes switching element Q91H1 to switching element Q91Hm and switching element Q91L1 to switching element Q91Lm. The voltage 0 (V) is applied to the data electrode Dj by turning on the switching element Q91Lj, and the voltage Vd is applied to the data electrode Dj by turning on the switching element Q91Hj.

  Using such a drive circuit, the drive voltage waveform of the panel shown in FIG. 3 can be generated. However, the drive circuits shown in FIGS. 6 to 9 are examples, and the present invention is not limited to the circuit configurations of these drive circuits.

  As described above, in the panel driving method of the present embodiment, a stable write operation can be performed without using a forced initialization operation by applying a scan pulse that satisfies the above conditions to the scan electrodes. In addition, a panel driving method and a plasma display device with improved contrast can be provided.

(Embodiment 2)
Other drive voltage waveforms of the present invention will be described below with reference to the drawings. 10 and 11 are drive voltage waveform diagrams applied to the respective electrodes of the plasma display device according to the second embodiment of the present invention. FIG. 10 shows the drive voltage waveforms in the first field, and FIG. The drive voltage waveform in the second field is shown. In this embodiment, the panel is driven using the first field and the second field alternately. In the present embodiment, the same sub-field configuration as in (Embodiment 1) is used to drive panel 10 similar to that in (Embodiment 1).

  In the address period of SF1 in the first field, voltage 0 (V) is applied to data electrode D1 through data electrode Dm, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and voltage is applied to scan electrode SC1 through scan electrode SCn. Vc is applied. Next, a scan pulse of voltage Va is applied to scan electrode SC1 in the first row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light. Here, the voltage Va is set so as to satisfy (Condition 1) and (Condition 2) as in the first embodiment.

  Then, address discharge occurs between data electrode Dk and scan electrode SC1, and between scan electrode SC1 and sustain electrode SU1. A positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. In this way, an address operation is performed in which an address discharge is caused in the discharge cell to emit light in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection between the data electrode Dh and the scan electrode SC1 to which the address pulse is not applied does not exceed the discharge start voltage, so the address discharge does not occur.

  Hereinafter, scan pulses are sequentially applied to the scan electrode SC2 in the second row, the scan electrode SC3 in the third row,..., The scan electrode SCn-1 in the (n−1) th row, and the scan electrode SCn in the nth row. . Then, the address operation is performed in the order of the discharge cell in the first row, the discharge cell in the second row, the discharge cell in the third row,..., The discharge cell in the (n−1) row, and the discharge cell in the n row. Wall charges necessary for the subsequent sustain discharge are formed.

  In the subsequent maintenance period of SF1, the data electrodes D1, D4, D7,... Of the discharge cell coated with the red phosphor and the data electrodes D3, D6, D9 of the discharge cell coated with the blue phosphor. A voltage Vd is applied to..., And a voltage 0 (V) is applied to the data electrodes D2, D5, D8,. Then, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, and a sustain pulse of voltage Vs is applied to scan electrode SC1 through scan electrode SCn. Then, in the discharge cell in which the address discharge has occurred, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light due to the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. On the other hand, the sustain discharge does not occur in the discharge cells in which the address discharge has not occurred, and the wall voltage at the end of the initialization operation is maintained.

  Subsequently, voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn, and a sustain pulse of voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. Then, the sustain discharge occurs again in the discharge cell in which the sustain discharge has occurred, and the phosphor layer 35 emits light. Then, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, sustain pulses of the number corresponding to the luminance weight are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and the sustain discharge is continued in the discharge cells that have caused the address discharge. generate.

  In the subsequent erasing period of SF1, the data electrodes D1, D4, D7,... Of the discharge cell coated with the red phosphor and the data electrodes D3, D6, D9 of the discharge cell coated with the blue phosphor are continued. ,... Are applied with a voltage Vd, and a voltage of 0 (V) is applied to the data electrodes D2, D5, D8,. Then, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, and an upward ramp waveform voltage that gradually rises to voltage Vr is applied to scan electrode SC1 through scan electrode SCn. In the second embodiment, the voltage Vr is set to the same voltage as the voltage Vs. Then, in a discharge cell that has undergone a sustain discharge (a discharge cell that has undergone an address discharge when the sustain period is omitted), a first weak erase discharge is generated with scan electrode SCi as an anode and sustain electrode SUi as a cathode. . Then, the wall voltage on scan electrode SCi and sustain electrode SUi is weakened.

  Next, Vd is applied to the data electrodes D1 to Dm. Then, with the voltage 0 (V) applied to sustain electrode SU1 through sustain electrode SUn, a downward ramp waveform voltage that gently falls from voltage 0 (V) toward voltage Vi is applied to scan electrode SC1 through scan electrode SCn. . The voltage Vi at this time is also the fifth voltage Vi, and is higher than the voltage obtained by superimposing the fourth voltage Vd on the low-voltage side voltage Va of the scan pulse applied to the scan electrodes SC1 to SCn in the address period. . Then, the second weak discharge is generated in the discharge cell in which the first weak erase discharge is generated. The discharge at this time is the first discharge with the scanning electrode as the cathode and the data electrode as the anode.

  Thereafter, the voltage 0 (V) is applied to the data electrodes D2, D5, D8,... Of the discharge cells to which the green phosphor is applied, and a rectangular voltage Vr is applied to the scan electrodes SC1 to SCn. Apply. Then, the third discharge occurs particularly in the discharge cell in which abnormal charges are accumulated. The discharge at this time is a second discharge in which the scan electrode is the anode and the sustain electrode is the cathode, and is a weak discharge.

  Thereafter, the voltage Vd is applied to the data electrodes D1 to Dm. Then, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and a downward ramp waveform voltage that gently falls from voltage 0 (V) toward voltage Vi is applied to scan electrode SC1 through scan electrode SCn. Then, the fourth weak erase discharge is generated in the discharge cell that has generated the third discharge. Due to the discharge at this time, excessive portions of the wall voltage on scan electrode SCi, sustain electrode SUi, and data electrode Dk are discharged and adjusted to a wall voltage suitable for the address operation. In this way, the erase operation is completed.

  The subsequent operation in the writing period of SF2 is the same as that in the writing period of SF1, and the description thereof will be omitted.

  In the subsequent sustain period of SF2, the voltage Vd is applied to the data electrodes D1 to Dm of all the red, green, and blue discharge cells. Then, sustain pulses of the number corresponding to the luminance weight are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and sustain discharge is continuously generated in the discharge cells in which address discharge has occurred.

  In the subsequent erase period of SF2, the voltage Vd is continuously applied to the data electrodes D1 to Dm of all the discharge cells. A discharge cell in which sustain discharge is performed by applying voltage 0 (V) to sustain electrode SU1 through sustain electrode SUn and applying an upward ramp waveform voltage that gradually rises to voltage Vr to scan electrode SC1 through scan electrode SCn. A weak erasure discharge is generated in (a discharge cell in which an address discharge is performed when the sustain period is omitted). Thereafter, voltage Vd is continuously applied to data electrode D1 through data electrode Dm, and voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn while voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn. A downward ramp waveform voltage that gently falls toward Vi is applied. Thereafter, voltage Vd is continuously applied to data electrode D1 to data electrode Dm, and a rectangular voltage of voltage Vr is applied to scan electrode SC1 to scan electrode SCn. Thereafter, voltage Vd is continuously applied to data electrode D1 to data electrode Dm and voltage Ve is applied to sustain electrode SU1 to sustain electrode SUn. Scan electrode SC1 to scan electrode SCn are changed from voltage 0 (V) to voltage Vi. A downward ramp waveform voltage that gradually falls toward the bottom is applied. Thus, excessive portions of the wall voltage on scan electrode SCi, sustain electrode SUi, and data electrode Dk are discharged and adjusted to a wall voltage suitable for the address operation.

  The subsequent operations in SF3 to SF10 in the first field are the same as those in SF2 in the first field except for the number of sustain pulses.

  In the subsequent address period of SF1 in the second field, voltage 0 (V) is applied to data electrode D1 through data electrode Dm, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and scan electrode SC1 through scan electrode SCn are applied. A voltage Vc is applied. Next, a scan pulse of voltage Va is applied to scan electrode SCn in the nth row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light. Here, the voltage Va of the scan pulse is set so as to satisfy (Condition 1) and (Condition 2) as in (Embodiment 1).

  Then, an address discharge occurs between data electrode Dk and scan electrode SCn, and between scan electrode SCn and sustain electrode SUn, and an address operation for accumulating wall voltage on each electrode of the discharge cell to emit light in the nth row. Is done.

  Next, a scan pulse of voltage Va is applied to the (n-1) th scan electrode SCn-1, and an address pulse of voltage Vd is applied to the data electrode Dk corresponding to the discharge cell to emit light, 1) An address operation for accumulating wall voltage on each electrode of the discharge cells in the row is performed. Hereinafter, a scan pulse is sequentially applied to the (n-2) -th scan electrode SCn-2, the (n-3) -th scan electrode SCn-3,. The same write operation is performed until the scan electrode SC1 is reached.

  As described above, in the address period of the subfield belonging to the second field, the nth scan electrode SCn, the (n−1) th scan electrode SCn−1, and the (n−2) th scan electrode SCn. -2,... A scan pulse is sequentially applied to the scan electrode SC2 in the second row and the scan electrode SC1 in the first row. The discharge cell in the nth row, the discharge cell in the (n-1) th row, the discharge cell in the (n-2) th row, ..., the discharge cell in the second row, the discharge cell in the first row. Perform a write operation. Thus, the order of the write operations in the write period of the subfield belonging to the second field is the reverse of the order of the write operations in the write period of the subfield belonging to the first field.

  The subsequent operation of the sustain period and erase period of SF1 in the second field is the same as the operation of the sustain period and erase period of SF1 in the first field. The operations in SF2 to SF10 in the second field are the same as those in SF2 to SF10 in the first field except that the order of the write operations in the write period is reversed.

  Similarly, the panel 10 is driven by alternately using the first field and the second field.

  Thus, in the present embodiment, in the address period, the first field in which the scan pulse is sequentially applied from one scan electrode SC1 to the other scan electrode SCn of the plurality of scan electrodes, and the other scan electrode And a second field for sequentially applying a scan pulse from SCn to one scan electrode SC1. The panel 10 is driven by alternately using the first field and the second field. The reason for driving in this way will be described below.

  Consider the operation when the image signal is switched from black display on the entire screen to white display on the entire screen.

  In the present embodiment, as described above, no discharge is generated in the discharge cells displaying black. Therefore, there is little priming inside each discharge cell, and the discharge delay is large. If the address operation is performed in this state, the discharge delay becomes large, and there may be many discharge cells that fail in the address discharge. However, if address discharge is successful in a certain discharge cell, the priming generated in that discharge cell is supplied to the adjacent discharge cell. Accordingly, in the discharge cell that performs the address operation immediately after that, the discharge delay is reduced, and the probability of succeeding in the address discharge is remarkably increased.

  Assuming that the panel is driven using only the first field, scan pulses are always applied in order from the scan electrode SC1 at the upper part of the display screen to the scan electrode SCn at the lower part of the display screen in the address period. For this reason, the discharge cells located under the discharge cells that have succeeded in the address discharge and the discharge cells located obliquely below can succeed in the address discharge one after another, and can be switched to white display. However, since the priming is not supplied from any discharge cell above the discharge cell that succeeded in the address discharge, the probability that the address discharge fails remains high. Therefore, it takes time to switch to white display at the top of the display screen, and the image display quality is degraded.

  Assuming that the panel is driven using only the second field, scan pulses are always applied in order from the scan electrode SCn at the lower part of the display screen to the scan electrode SC1 at the upper part of the display screen in the address period. Therefore, it takes time to switch to white display at the bottom of the display screen, and the image display quality is degraded.

  However, in the present embodiment, the panel is driven by alternately using the first field and the second field, so that white display can be quickly switched over the entire screen.

  In the present embodiment, the voltage 0 (V) applied to the data electrode of the discharge cell coated with the green phosphor in the sustain period of SF1 is the voltage Vd applied to the data electrode of the other discharge cells. Is set lower. By setting in this way, the setting margin of the voltage Va can be expanded. The reason will be described below.

  The setting range of the voltage Va that satisfies (Condition 1) and (Condition 2) depends on the discharge start voltage VFsd and the discharge start voltage VFds. As described above, the discharge start voltage VFsd and the discharge start voltage VFds of the green phosphor tend to be higher than those of the red and blue phosphors. For this reason, in the discharge cell to which the green phosphor is applied, the setting range of the voltage Va of the scanning pulse is shifted to the high voltage side. In addition, since the charging characteristics of the green phosphor are negative, the wall voltage on the data electrode of the discharge cell coated with the green phosphor is on the data electrode of the discharge cell coated with another color phosphor. Is substantially lower than the wall voltage. This effect is added, and the setting range of the voltage Va of the discharge cell coated with the green phosphor is further shifted to the high voltage side.

  Of course, the common part of the setting range of the scan pulse voltage Va for the red discharge cell, the setting range of the scan pulse voltage Va for the green discharge cell, and the setting range of the scan pulse voltage Va for the blue discharge cell is the scan pulse voltage. Since this is the actual voltage setting range of Va, if only the setting range of scan voltage Va for green discharge cells is shifted, the actual voltage setting margin of scan pulse voltage Va is narrowed. In other words, the setting margin of the actual voltage Va can be widened by aligning the setting range of the voltage Va of the electric scanning pulse for the discharge cells of each color.

  In the present embodiment, voltage 0 (V) applied to the data electrode Dg of the discharge cell coated with green phosphor during the sustain period of the subfield is applied to the data electrode of the other discharge cells. By setting it lower than Vd, the setting range of the voltage Va of the scan pulse for the discharge cells of each color is made uniform, and the setting margin of the voltage Va of the actual scan pulse is expanded.

  In the present embodiment, as described above, no discharge is generated in the discharge cells displaying black. Therefore, the discharge start voltage of the discharge cell displaying black tends to be substantially higher than that of the discharge cell displaying gradation other than black. Accordingly, in the discharge cell displaying black, the setting range of the voltage Va satisfying (Condition 1) and (Condition 2) is shifted to the high voltage side as compared with the discharge cell emitting light. Therefore, in the sustain period of the subfield, the voltage 0 (V) applied to the data electrode of the discharge cell displaying black is set to be lower than the voltage Vd applied to the data electrode of the other discharge cells. It is possible to align the setting range of the voltage Va with respect to the cell and to widen the setting margin of the actual voltage Va. However, in the present embodiment, such driving is not performed. Instead, the voltage 0 (V) applied to the data electrode in the sustain period of subfield SF1 having the smallest luminance weight is set to other subfields SF2 to SF2. The voltage is set lower than the voltage Vd applied to the data electrode in the sustain period of SF10.

  In the present embodiment, coding is set so as to select a combination in which a subfield having a luminance weight as low as possible is lit when displaying gradation. This is a technique for suppressing the moving image pseudo contour. For example, it is described in detail in Japanese Patent Application Laid-Open No. 2008-197430. As a result, the probability of light emission increases as the subfield has a lower luminance weight. In particular, in a discharge cell that displays black, there is a high probability that a dark gradation will be continuously displayed. Therefore, when performing address discharge, the probability of performing address discharge with SF1 having the lowest luminance weight becomes very high. Therefore, voltage 0 (V) applied to the data electrode in the sustain period of subfield SF1 having the smallest luminance weight is set lower than voltage Vd applied to the data electrode in the sustain periods of other subfields SF2 to SF10. Thus, the setting range of the voltage Va for the discharge cells can be aligned, and the setting margin of the actual voltage Va can be widened.

  Of course, for a discharge cell displaying a high gradation, the setting range of the voltage Va in SF1 is shifted to the low voltage side. Therefore, the probability that a discharge cell that emits light with high luminance erroneously discharges in SF1 is high. However, since the luminance weight of SF1 is small, there is a possibility that image display quality may be deteriorated even if such discharge cell is erroneously discharged. Absent.

  The specific numerical values shown in (Embodiment 1) and (Embodiment 2) are merely examples, and are optimally set according to the panel characteristics, the specifications of the plasma display device, and the like. It is desirable.

  The present invention eliminates the forced initializing operation while stably generating the writing operation, eliminates the light emission not related to the gradation display, and can greatly improve the contrast. Therefore, the panel driving method and the plasma display device Useful as.

DESCRIPTION OF SYMBOLS 10 Panel 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 32 Data electrode 35 Phosphor layer 40 Plasma display apparatus 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 50,80 Sustain pulse generation circuit 51, 81 Power recovery circuit 60 Ramp waveform voltage generation circuit 61, 63 Miller integration circuit 70 Scanning pulse generation circuit 85 Constant voltage generation circuit E71 Power supply IN61, IN63 Input terminals SF1, SF2 Subfield

Claims (3)

A plasma display panel for driving a plasma display panel comprising a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, comprising a plurality of subfields having an address period, a sustain period, and an erase period. Driving method,
A voltage obtained by subtracting a voltage applied to the data electrode from a low-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period is set as a first voltage, and a high voltage of the sustain pulse applied to the scan electrode in the sustain period The voltage obtained by subtracting the voltage applied to the data electrode from the side voltage is set as the second voltage, and the low voltage side voltage of the data pulse applied to the data electrode from the low voltage side voltage of the scan pulse applied to the scan electrode in the address period Is a voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than a discharge start voltage using the data electrode as an anode and the scan electrode as a cathode, A voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage having the data electrode as an anode and the scan electrode as a cathode, and the data electrode as a cathode. The electrode is less than the sum of the discharge start voltage to the anode,
In addition, a positive fourth voltage is applied to the data electrode during the erasing period, and a voltage obtained by superimposing the fourth voltage on a low-voltage side voltage of a scan pulse applied to the scan electrode during the writing period A downward ramp waveform voltage falling toward a fifth voltage higher than that is applied to the scan electrode, and an erasing discharge is selectively generated only in the discharge cells that have generated an address discharge in the immediately preceding address period. A method for driving a plasma display panel. In the erasing period, an upward ramp waveform voltage is applied to the scan electrode, and then the fourth voltage is applied to the data electrode and a downward ramp waveform voltage that decreases toward the fifth voltage is applied to the scan electrode. Applying a positive rectangular voltage to the scan electrode, and then applying a fourth ramp voltage to the data electrode and a downward ramp waveform voltage falling towards the fifth voltage. 2. The method of claim 1, wherein the erase discharge is generated by applying the scan electrode. A plasma display panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, and a plurality of subfields having an address period, a sustain period, and an erase period are used to form one field and drive voltage waveform A plasma display device comprising a drive circuit that is generated and applied to each electrode of the plasma display panel,
The drive circuit is
A voltage obtained by subtracting a voltage applied to the data electrode from a low-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period is set as a first voltage, and a high voltage of the sustain pulse applied to the scan electrode in the sustain period The voltage obtained by subtracting the voltage applied to the data electrode from the side voltage is set as the second voltage, and the low voltage side voltage of the data pulse applied to the data electrode from the low voltage side voltage of the scan pulse applied to the scan electrode in the address period Is a voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than a discharge start voltage using the data electrode as an anode and the scan electrode as a cathode, A voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage having the data electrode as an anode and the scan electrode as a cathode, and the data electrode as a cathode. It sets the electrodes to a voltage that does not exceed the sum of the discharge start voltage to the anode,
In the erasing period, a positive fourth voltage is applied to the data electrode, and is higher than a voltage obtained by superimposing the fourth voltage on the low-voltage side voltage of the scan pulse applied to the scan electrode in the write period. A plasma having a downward ramp waveform voltage falling toward a fifth voltage applied to the scan electrode to selectively generate an erasing discharge only in a discharge cell that has generated an address discharge in the immediately preceding address period. Display device.

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