JP2012058652A - Method for driving plasma display panel and plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress black luminance of a plasma display device by performing a stable writing operation without using a forced initialization operation and to lower luminance of gradation being lower next to black.SOLUTION: When a voltage obtained by deducting a voltage of a data electrode from a low pressure side voltage of a sustaining pulse is a first voltage and a voltage obtained by deducting a low pressure side voltage of a writing pulse from a low pressure side voltage of a scanning pulse is a third voltage, a voltage obtained by deducting the third voltage from the first voltage is equal to or higher than a discharge start voltage having the data electrode as an anode and a scanning electrode as a cathode. One field includes a first kind of subfield for applying the sustaining pulse to the scanning electrode in a sustaining period and a second kind of subfield for applying a downward inclined waveform voltage to the scanning electrode after applying an upward inclined waveform voltage to the scanning electrode without applying the sustaining pulse to the scanning electrode in the sustaining period.

Description

  The present invention relates to an AC surface discharge type plasma display panel driving method and a plasma display apparatus.

  A plasma display panel (hereinafter abbreviated as “panel”) includes a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and is red with ultraviolet rays generated by gas discharge in the discharge cell. Color display is performed by exciting and emitting phosphors of green and blue colors.

  As a method for driving the panel, a subfield method, that is, a method in which a single field is formed using a plurality of subfields having an initialization period, an address period, and a sustain period, and gradation display is performed by combining subfields that emit light. Is common. An initialization operation is performed during the initialization period of each subfield, a write operation is performed during the write period, and a maintenance operation is performed during the sustain period. The initialization operation is an operation that generates initialization discharge and forms wall charges necessary for the subsequent address operation. The initializing operation includes a forced initializing operation that generates an initializing discharge regardless of the operation of the immediately preceding subfield, and a selective initializing operation that generates an initializing discharge in a discharge cell that has performed an address discharge in the immediately preceding subfield. There is. The address operation is an operation in which an address discharge is selectively generated in the discharge cells in accordance with an image to be displayed to form wall charges, and the sustain operation is to generate a sustain discharge by alternately applying a sustain pulse to the display electrode pair, This is an operation of causing the phosphor layer of the corresponding discharge cell to emit light. The light emission of the phosphor layer by the sustain discharge is light emission related to gradation display, and the light emission by the forced initialization operation is light emission not related to gradation display.

  There is a driving method that improves the contrast by lowering the luminance (hereinafter abbreviated as “black luminance”) when displaying black, which is the lowest gradation among the subfield methods, and reducing light emission not related to gradation display as much as possible. It is being considered. For example, Patent Document 1 discloses a driving method in which the forced initialization operation is performed once per field and the forced initialization operation is performed using a slowly changing ramp waveform voltage.

  Further, in Patent Document 2, the display electrode pair is divided into n, the number of times of forced initialization operation is set to once per n fields, light emission not related to gradation display is further reduced, black luminance is further reduced, and contrast is further increased. An improved driving method is disclosed.

JP 2000-242224 A JP 2006-091295 A

  However, even with the driving methods described in Patent Document 1 and Patent Document 2, since the forced initialization operation is performed, light emission not related to gradation display occurs. This means that even a discharge cell displaying black emits light, and thus there is a limit to improving the contrast. In addition, the forced initialization operation has a function of accumulating wall charges necessary for generating an address discharge in the subsequent address period, and in addition, a priming for surely generating an address discharge by shortening the discharge delay time. It also has the function of generating. Therefore, if the forced initializing operation is simply omitted, there is a problem that the address discharge does not occur, or the address delay becomes too long for the address discharge to become unstable, and normal image display cannot be performed.

  In addition, when the black luminance that is the lowest gradation is reduced, the luminance difference between the black luminance and the luminance of the next lowest gradation is increased, and the continuity of the luminance that can be displayed is impaired, particularly in dark images. There has been a problem that the image display quality of the camera deteriorates.

  The present invention has been made in view of these problems, and by performing a stable writing operation without using a forced initialization operation to suppress black luminance and lowering luminance of the next lower gradation after black. Another object of the present invention is to provide a panel driving method and a plasma display device capable of displaying an image with high contrast and high image display quality.

  In order to achieve the above object, the present invention forms a single field using a plurality of subfields each having an address period, a sustain period, and an erase period, and includes a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode. A plurality of subfields constituting one field include a first type subfield that applies a sustain pulse to a scan electrode in a sustain period, and a scan electrode in the sustain period. A second type subfield that applies an up-slope waveform voltage to the scan electrode without applying a sustain pulse and then applies a down-slope waveform voltage to the scan electrode, and is applied to the scan electrode in the sustain period of the first type subfield The voltage obtained by subtracting the voltage applied to the data electrode from the low-voltage side voltage of the sustain pulse to be used as the first voltage, The voltage obtained by subtracting the voltage applied to the data electrode from the high-voltage side voltage of the sustain pulse applied to the scan electrode in the holding period is set as the second voltage, and the voltage applied from the low-voltage side of the scan pulse applied to the scan electrode to the data electrode in the writing period When the voltage obtained by subtracting the low-voltage side voltage of the address pulse to be applied is the third voltage, the voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than the discharge start voltage having the data electrode as the anode and the scan electrode as the cathode. The voltage obtained by subtracting the third voltage from the second voltage is less than the sum of the discharge start voltage with the data electrode as the anode and the scan electrode as the cathode and the discharge start voltage with the data electrode as the cathode and the scan electrode as the anode It is characterized by being. This method suppresses black luminance by performing stable writing operation without using forced initialization operation, and lowers luminance of the next lowest gradation after black, thereby providing high contrast and high image display quality. A panel driving method capable of displaying an image can be provided.

  In the panel driving method of the present invention, even if the voltage applied to the sustain electrode in the address period of the second type subfield is lower than the voltage applied to the sustain electrode in the address period of the first type subfield. Good.

  The present invention also comprises a panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, and a plurality of subfields each having an address period, a sustain period, and an erase period. A plasma display apparatus comprising a drive circuit that generates a voltage waveform and applies the voltage waveform to each electrode of the panel, wherein the drive circuit includes a first type subfield that applies a sustain pulse to the scan electrode in the sustain period, and a sustain period And a second type subfield that applies a downward ramp waveform voltage to the scan electrode without applying a sustain pulse to the scan electrode and then applies a downward ramp waveform voltage to the scan electrode. The voltage applied to the data electrode from the low-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of one type of subfield The reduced voltage is set as the first voltage, the voltage obtained by subtracting the voltage applied to the data electrode from the high-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield is set as the second voltage, and the writing period A voltage obtained by subtracting the third voltage from the first voltage when the voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode from the low-voltage side voltage of the scan pulse applied to the scan electrode in FIG. Is equal to or higher than the discharge start voltage with the data electrode as the anode and the scan electrode as the cathode, and the voltage obtained by subtracting the third voltage from the second voltage is the discharge start voltage and the data electrode with the data electrode as the anode and the scan electrode as the cathode Is set to a voltage that does not exceed the sum of the discharge start voltage with the cathode as the cathode and the scan electrode as the anode. With this configuration, stable writing operation is performed without using forced initialization operation to suppress black luminance, and by reducing the luminance of the next lower gradation after black, high contrast and high image display quality are achieved. A plasma display device capable of high image display can be provided.

  According to the present invention, a stable writing operation is performed without using the forced initialization operation to suppress black luminance, and the luminance of the next lowest gradation after black is reduced, thereby providing high contrast and image display quality. It is possible to provide a panel driving method and a plasma display device capable of displaying a high image.

It is a disassembled perspective view of the panel used for the plasma display apparatus in Embodiment 1 of this invention. It is an electrode array figure of the panel used for the plasma display apparatus. It is a drive voltage waveform figure applied to each electrode of the plasma display apparatus. It is a figure for demonstrating the definition of a 1st voltage, a 2nd voltage, and a 3rd voltage. It is a figure which shows an example of the method of measuring a discharge start voltage simply. It is a circuit block diagram of the plasma display apparatus in Embodiment 1 of the present invention. It is a circuit diagram of the scan electrode drive circuit of the plasma display device. It is a circuit diagram of the sustain electrode drive circuit of the plasma display device. It is a circuit diagram of the data electrode drive circuit of the plasma display device.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the display electrode pair 24, and a protective layer 26 is formed on the dielectric layer 25. The protective layer 26 is formed using magnesium oxide, which is a material having high electron emission performance, in order to easily generate discharge. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33. For example, (Y, Gd) BO ₃ : Eu is used as the red phosphor, Zn ₂ SiO ₄ : Mn is used as the green phosphor, and BaMgAl ₁₀ O ₁₇ : Eu is used as the blue phosphor. Each of them uses a phosphor as a main component.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is sealed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) that are long in the row direction. M data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed.

  Next, a driving voltage waveform for driving panel 10 and its operation will be described. The plasma display apparatus displays an image by subfield method, that is, by dividing one field into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield.

  In this embodiment, one field is configured by using a plurality of subfields each having an address period, a sustain period, and an erase period. In the present embodiment, the forced initializing operation for forcibly generating the initializing discharge is not performed regardless of the presence or absence of the previous discharge.

  In the address period, an address operation is performed in which address discharge is selectively generated in the discharge cells to emit light to form wall charges. In the sustain period, a sustain operation is performed in which a sustain pulse of the number corresponding to the luminance weight determined in advance for each subfield is alternately applied to the display electrode pair to generate a sustain discharge in the discharge cell that generated the address discharge. I do. Alternatively, in order to suppress the luminance of the next lower gray level after black, without applying a sustain pulse, a ramp waveform in which the voltage gradually decreases after applying a ramp waveform voltage that gradually increases in voltage to the scan electrode. A sustain operation is performed in which a voltage is applied to the scan electrode to generate a weak sustain discharge in the discharge cell that has generated the address discharge to emit light. In the erasing period, an erasing discharge is selectively generated only in the discharge cells that generated the address discharge in the immediately preceding address period, and the history of wall charges formed by the address discharge or the subsequent sustain discharge is erased, and the subsequent address discharge is performed. An erasing operation is performed to form necessary wall charges on each electrode.

  As a subfield configuration, for example, one field is divided into 11 subfields (SF1, SF2,..., SF11), and each subfield is (1/2, 1, 2, 3, 6, 11). , 18, 30, 44, 60, 80).

  Here, the luminance weight of the subfield SF1 is described as “½”. This is after the subfield SF1 has applied the rising ramp waveform voltage to the scan electrode without applying the sustain pulse to the scan electrode in the sustain period. It shows that the second type subfield applies a downward ramp waveform voltage to the scan electrode. Subfield SF2 to subfield SF11 are first-type subfields that apply a sustain pulse to the scan electrodes in the sustain period. Here, the value of the luminance weight “1/2” of the subfield SF1 that is the second type subfield does not have a strict meaning, and the gradation is lower than those of the subfield SF2 to subfield SF11 that are the first type subfield. Indicates that display is to be performed.

  As described above, in the present embodiment, the plurality of subfields constituting one field are the first type subfield that applies the sustain pulse to the scan electrode in the sustain period, and the sustain pulse is applied to the scan electrode in the sustain period. And a second type sub-field that applies a descending ramp waveform voltage to the scan electrode after applying the ramp waveform voltage to the scan electrode without doing so.

  FIG. 3 is a drive voltage waveform diagram applied to each electrode of the plasma display device in accordance with the first exemplary embodiment of the present invention.

  In the address period of the subfield SF1, which is the second type subfield, the voltage 0 (V) is applied to the data electrodes D1 to Dm, the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn, and the scan electrodes A voltage Vc is applied to SC1 to scan electrode SCn. Next, a scan pulse of voltage Va is applied to scan electrode SC1 in the first row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light.

  Then, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is obtained by adding the positive wall voltage on the data electrode Dk to the difference between the externally applied voltages (Vd−Va) and scanning with the data electrode Dk as the anode. The discharge start voltage VFds with the electrode SCi as a cathode is exceeded, and a discharge is generated between the data electrode Dk and the scan electrode SC1. In this way, address discharge occurs in subfield SF1. A positive wall voltage is accumulated on scan electrode SC1, and a negative wall voltage is accumulated on data electrode Dk. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  Thus, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and a wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrode Dh to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage VFds, so the address discharge does not occur.

  Next, a scan pulse is applied to scan electrode SC2 in the second row, and an address pulse is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, an address discharge occurs between data electrode Dk and scan electrode SC2, and a positive wall voltage is accumulated on scan electrode SC2, and a negative wall voltage is accumulated on data electrode Dk. In this manner, an address operation is performed in which an address discharge is caused in the discharge cell to be lit in the second row and wall voltage is accumulated on each electrode. On the other hand, since the voltage at the intersection between the data electrode Dh and the scan electrode SC2 to which no address pulse is applied does not exceed the discharge start voltage VFds, no address discharge occurs.

  Thereafter, the same address operation is performed until the scan electrode SCn in the n-th row, and wall charges necessary for the subsequent sustain discharge are formed.

  In the present embodiment, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn in the address period, so that the discharge generated between data electrode Dk and scan electrode SC1 extends to sustain electrode SU1. There is nothing. Thereby, the luminance of light emission accompanying the address discharge can be suppressed, and the luminance displayed by the subfield SF1 can be suppressed low.

  Here, for the following description, the first voltage V1, the second voltage V2, and the third voltage V3 are defined as shown in FIG. A voltage obtained by subtracting the voltage applied to the data electrode Dj from the low-voltage side voltage of the sustain pulse applied to the scan electrode SCi in the sustain period of the subfield SF2 to the subfield SF11 which is a first type subfield described later is the first voltage V1. The voltage obtained by subtracting the voltage applied to the data electrode Dj from the high-voltage side voltage of the sustain pulse applied to the scan electrode SCi in the sustain period of the first type subfield is set as the second voltage V2, and the scan electrode SCi is applied to the scan electrode SCi in the write period. A voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode Dj from the low-voltage side voltage of the scan pulse to be applied is defined as a third voltage V3.

  As described above, the discharge start voltage VFds is the discharge start voltage with the data electrode Dj as the anode and the scan electrode SCi as the cathode, and the discharge start voltage VFsd with the data electrode Dj as the cathode and the scan electrode SCi as the anode. And The discharge with the data electrode Dj as the anode and the scan electrode SCi as the cathode is a discharge in which the electric field in the discharge cell when the discharge occurs is a high potential side on the data electrode Dj side and a low potential side on the scan electrode SCi side. It is. The discharge with the data electrode Dj as the cathode and the scan electrode SCi as the anode is a discharge in which the electric field in the discharge cell when the discharge occurs is a low potential side on the data electrode Dj side and a high potential side on the scan electrode SCi side. is there. Since the protective layer 26 of magnesium oxide having high electron emission performance is formed on the scan electrode SCi side, the discharge start voltage VFds is lower than the discharge start voltage VFsd.

  At this time, the voltage Va of the scan pulse applied to the scan electrode SCi is set so as to satisfy the following two conditions (condition 1) and (condition 2).

(Condition 1) For all discharge cells, the voltage obtained by subtracting the third voltage V3 from the first voltage V1 is equal to or higher than the discharge start voltage VFds with the data electrode Dj as the anode and the scan electrode SCi as the cathode,
(V1-V3) ≧ VFds is satisfied.

(Condition 2) For all the discharge cells, a voltage obtained by subtracting the third voltage V3 from the second voltage V2 is a discharge start voltage VFds and a data electrode Dj with the data electrode Dj as an anode and the scan electrode SCi as a cathode. Is less than the sum of the discharge start voltage VFsd with the scan electrode SCi as the anode, that is,
(V2−V3) <(VFds + VFsd) is satisfied.

  In the sustain period of subfield SF1, which is the second type subfield, voltage 0 (V) is continuously applied to sustain electrode SU1 through sustain electrode SUn, and voltage 0 (V) is applied to data electrode D1 through data electrode Dm. The rising ramp waveform voltage rising to voltage Vs is applied to scan electrode SC1 through scan electrode SCn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between the scan electrode SCi and the data electrode Dk is an upward ramp waveform voltage, and the difference between the wall voltage on the scan electrode SCi and the wall voltage on the data electrode Dk is added. It will be a thing. The discharge start voltage VFsd is exceeded during the rise of the rising ramp waveform voltage, and a weak sustain discharge occurs between the scan electrode SCi and the data electrode Dk, and the phosphor layer 35 emits light due to the ultraviolet rays generated at this time. However, since the ultraviolet rays generated by the weak discharge are also weak, the light emission at this time is also weak.

  Then, after the voltage applied to scan electrode SC1 through scan electrode SCn rises to voltage Vs, voltage Vs is further applied for a certain period. Then, the positive wall voltage on the scan electrode SCi decreases, and the negative wall voltage on the data electrode Dk also decreases. On the other hand, the sustain discharge does not occur in the discharge cell in which the address discharge has not occurred, and the wall voltage at the end of the immediately preceding field is maintained.

  Subsequently, voltage 0 (V) is continuously applied to sustain electrode SU1 through sustain electrode SUn, voltage Vd is applied to data electrode D1 through data electrode Dm, and voltage drops to scan electrode SC1 through scan electrode SCn to voltage Vg. Apply a falling ramp waveform voltage. The voltage Vg is set equal to (voltage Va + voltage Vd) or slightly higher than (voltage Va + voltage Vd).

  Then, a weak sustain discharge occurs again in the discharge cell in which the weak sustain discharge has occurred, and the phosphor layer 35 emits light. The light emission at this time is also weak light emission. Then, the negative wall voltage on the data electrode Dk increases and the positive wall voltage on the scan electrode SCi increases.

  In the subsequent erasing period of subfield SF1, voltage 0 (V) is continuously applied to sustain electrode SU1 through sustain electrode SUn, voltage Vd is applied to data electrode D1 through data electrode Dm, and voltage is applied to scan electrode SC1 through scan electrode SCn. An upward ramp waveform voltage that gradually rises to Vr is applied. In the present embodiment, the voltage Vr is set to the same voltage as the voltage Vs. Then, a weak erasing discharge is generated between scan electrode SCi and sustain electrode SUi in the discharge cell in which the weak sustain discharge has been performed. Then, the negative wall voltage on sustain electrode SUi decreases and the positive wall voltage on scan electrode SCi increases.

  Thereafter, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and voltage 0 (V) is applied to data electrode D1 through data electrode Dm. Then, a downward ramp waveform voltage that gently falls from voltage 0 (V) toward voltage Vi is applied to scan electrode SC1 through scan electrode SCn. The voltage Vi is set to be equal to or slightly higher than the voltage Va of the scanning pulse.

  Then, a weak discharge is generated again in the discharge cell in which the weak erasing discharge is generated, and an excessive portion of the wall voltage on scan electrode SCi, sustain electrode SUi, and data electrode Dk is discharged, and writing is performed. It is adjusted to a wall voltage suitable for operation. In this way, the erase operation is completed.

  In the address period of subfield SF2, which is the first type subfield, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn. Then, voltage 0 (V) is applied to data electrode D1 through data electrode Dm, and voltage Vc is applied to scan electrode SC1 through scan electrode SCn.

  Next, a scan pulse of voltage Va is applied to scan electrode SC1 in the first row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 exceeds the discharge start voltage VFds by adding the positive wall voltage on the data electrode Dk to the difference (Vd−Va) of the externally applied voltage. Then, a discharge is generated between data electrode Dk and scan electrode SC1. Further, the discharge generated between data electrode Dk and scan electrode SC1 extends between scan electrode SC1 and sustain electrode SU1. In this manner, address discharge occurs in subfield SF2. A positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk.

  Thus, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and a wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrode Dh to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage VFds, so the address discharge does not occur.

  Next, a scan pulse is applied to scan electrode SC2 in the second row, and an address pulse is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, an address discharge occurs between data electrode Dk and scan electrode SC2 and between sustain electrode SU2 and scan electrode SC2, a positive wall voltage is accumulated on scan electrode SC2, and a negative wall voltage is applied on sustain electrode SU2. And a negative wall voltage is also accumulated on the data electrode Dk. Thus, an address operation is performed in which the address discharge is caused in the discharge cells to be lit in the second row and the wall voltage is accumulated on each electrode. On the other hand, since the voltage at the intersection between the data electrode Dh and the scan electrode SC2 to which no address pulse is applied does not exceed the discharge start voltage VFds, no address discharge occurs.

  Thereafter, the same address operation is performed until the scan electrode SCn in the n-th row, and wall charges necessary for the subsequent sustain discharge are formed.

  In the sustain period of subfield SF2, which is the first type subfield, voltage 0 (V) is applied to data electrode D1 to data electrode Dm, voltage 0 (V) is applied to sustain electrode SU1 to sustain electrode SUn, A sustain pulse of voltage Vs is applied to scan electrode SC1 through scan electrode SCn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the voltage Vs plus the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. It exceeds the discharge start voltage VFss between scan electrode SCi and sustain electrode SUi. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. On the other hand, the sustain discharge does not occur in the discharge cell in which the address discharge has not occurred, and the wall voltage at the end of the immediately preceding field is maintained.

  Subsequently, voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn, and a sustain pulse of voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. Then, the sustain discharge occurs again in the discharge cell in which the sustain discharge has occurred, and the phosphor layer 35 emits light. Then, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, sustain pulses of the number corresponding to the luminance weight are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and the sustain discharge is continued in the discharge cells that have caused the address discharge. generate.

  In the subsequent erasing period of subfield SF2, voltage 0 (V) is applied to data electrode D1 to data electrode Dm, voltage 0 (V) is applied to sustain electrode SU1 to sustain electrode SUn, and scan electrode SC1 to scan electrode. An upward ramp waveform voltage that gradually rises to the voltage Vr is applied to SCn. Then, a weak erasing discharge occurs between scan electrode SCi and sustain electrode SUi in the discharge cell in which the sustain discharge has been performed. Then, the wall voltage on scan electrode SCi and sustain electrode SUi is weakened.

  Thereafter, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and a downward ramp waveform voltage that gently falls from voltage 0 (V) toward voltage Vi is applied to scan electrode SC1 through scan electrode SCn.

  Then, a weak discharge is generated again in the discharge cell in which the weak erasing discharge is generated, and an excessive portion of the wall voltage on scan electrode SCi, sustain electrode SUi, and data electrode Dk is discharged, and writing is performed. It is adjusted to a wall voltage suitable for operation. In this way, the erase operation is completed.

  The operations in the subfields SF3 to SF11 that are the first type subfield are the same as the operations in the subfield SF2 that is the first type subfield except for the number of sustain pulses.

  In this embodiment, the voltage Vc is −145 (V), the voltage Va is −280 (V), the voltage Vs is 200 (V), the voltage Vg is −200 (V), the voltage Vr is 200 (V), The voltage Vi is −260 (V), the voltage Ve is 20 (V), and the voltage Vd is 60 (V). The gradient of the ramp waveform voltage is 1 to 10 (V / μs). However, these voltage values are not limited to the values described above, and are desirably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.

  In the above description of the wall voltage, the wall voltage on each electrode is shown assuming a reference potential of wall voltage 0 (V) inside the discharge cell space. However, what is important in considering the wall voltage is, as is well known, the difference in the wall voltage between the electrodes and the change in the wall voltage on each electrode.

  Further, the discharge start voltage VFds and the discharge start voltage VFsd of the panel 10 used in the present embodiment are measured by the methods described later, and their values are as follows. The discharge start voltage varies depending on the phosphor, and the discharge start voltage VFds between the “data electrode-scan electrode” for the discharge cell coated with the red phosphor is 200 ± 10 (V), and the discharge start voltage VFsd is 320 ± 10 ( V), the discharge start voltage VFds between the “data electrode and the scan electrode” for the discharge cell coated with the green phosphor is 220 ± 10 (V), the discharge start voltage VFsd is 350 ± 10 (V), and the blue fluorescence The discharge start voltage VFds between the “data electrode and the scan electrode” for the discharge cell coated with the body was 200 ± 10 (V), and the discharge start voltage VFsd was 330 ± 10 (V). The discharge start voltage VFss between the “scan electrode and sustain electrode” is 250 ± 10 (V) for the discharge cells coated with red and blue phosphors, and for the discharge cells coated with green phosphors, It was 280 ± 10 (V).

  In the present embodiment, the voltage on the low voltage side of the sustain pulse is voltage 0 (V), and the voltage applied to the data electrode in the sustain period is voltage 0 (V), so the first voltage V1 is voltage 0 (V ). Further, since the low voltage side of the scan pulse is the voltage Va and the low voltage side voltage of the write pulse is the voltage 0 (V), the third voltage V3 is the voltage Va. Further, the maximum value of the discharge start voltage VFds is a voltage 230 (V) in consideration of variations. Therefore, (first voltage V1−third voltage V3) = − Va> (maximum value of VFds), that is, 280 (V)> 230 (V), and (condition 1) is satisfied in all discharge cells. You can see that

  Further, since the high voltage side of the sustain pulse is the voltage Vs and the voltage applied to the data electrode in the sustain period is the voltage 0 (V), the second voltage V2 is the voltage Vs. The minimum value of the sum of the discharge start voltage VFsd and the discharge start voltage VFds is a voltage 500 (V). Therefore, the minimum value of (second voltage V2−third voltage V3) = Vs−Va <(VFds + VFsd), that is, 480 (V) <500 (V), and (condition 2) also applies to all discharge cells. You can see that you are satisfied.

  Further, as apparent from the above voltage, a voltage lower than the low voltage side voltage Va of the scan pulse is applied to the scan electrode by applying a voltage not lower than the low voltage side voltage Va of the scan pulse and not higher than the high voltage side voltage Vs of the sustain pulse. A voltage exceeding the high voltage Vs of the sustain pulse is not applied. Therefore, a discharge cell that has not performed address discharge does not emit light.

  As apparent from the above voltage, when the voltage Va is set low so as to satisfy (Condition 1), the absolute value | Va | of the low-voltage side voltage Va of the scan pulse is the absolute value of the high-voltage side voltage Vs of the sustain pulse. It becomes larger than the value | Vs |.

  As described above, in this embodiment, the forcibly initializing operation is performed by setting the drive voltage waveform applied to each electrode, in particular, the voltage Va of the scan pulse so as to satisfy (Condition 1) and (Condition 2). Even if it is not used, the write operation can be generated stably. The reason is considered as follows.

  First, (Condition 1) will be described. In order to generate the address discharge, it is necessary to start the discharge between the data electrode Dj and the scan electrode SCi. In order to start a discharge by applying a relatively low voltage Vd to the data electrode Dj, a voltage substantially equal to the discharge start voltage VFds is applied between the data electrode Dj and the scan electrode SCi when a scan pulse is applied to the scan electrode SCi. A sufficient wall voltage must be stored on the data electrode Dj so that it is applied in between. As described above, in this embodiment, the forced initialization operation is not performed, and no discharge is generated in the discharge cells displaying black. Therefore, the wall voltage cannot be actively controlled, and the wall voltage of the discharge cell displaying black is indefinite. However, even in such a discharge cell, if there are a few charged particles in the discharge space, they move to each electrode so as to relax the electric field inside the discharge space and adhere to the wall of the discharge cell. Accumulate wall voltage.

  First, the wall voltage accumulated in this way will be described. During the sustain period, a large amount of charged particles are generated in the discharge cell that generates the sustain discharge, and when these particles diffuse, a small amount of charged particles are supplied to the space inside the discharge cell that displays black without causing the sustain discharge. It is thought that. In the discharge cell displaying black, wall voltages are slowly accumulated so as to alleviate the potential difference between the electrodes by the voltages applied to scan electrode SCi, sustain electrode SUi, and data electrode Dj. If the voltage at which the wall voltage gradually approaches (finally settles) is defined as the neglected wall voltage, the neglected wall voltage when the sustain pulse is continuously applied alternately to the scan electrode SCi and the sustain electrode SUi is the high voltage of the sustain pulse. The voltage is between the side voltage and the low voltage. Actually, since a drive voltage waveform other than the sustain pulse is also applied, it can be considered that the neglected wall voltage of each discharge cell is substantially close to the low-voltage side voltage of the sustain pulse.

  The neglected wall voltage is greatly affected by the charging characteristics of the phosphor applied inside the discharge cell. In this embodiment, the charging characteristics of the phosphor are +20 (μC / g) for the red phosphor, −30 (μC / g) for the green phosphor, and +10 (μC / g) for the blue phosphor, respectively. Since only the green phosphor is charged to a negative potential, the neglected wall voltage is lower than that of the red and blue phosphors.

  Next, the voltage inside the discharge cell in the address period will be described. On the data electrode Dj of the discharge cell displaying black, the wall voltage is gradually accumulated toward the low voltage side voltage of the sustain pulse or the neglected wall voltage close thereto. On the other hand, the voltage Va of the scan pulse in the present embodiment is a voltage that satisfies (Condition 1). Therefore, a wall voltage sufficient to generate the address discharge is accumulated on the data electrode Dj, and the address discharge can be generated without performing any forced initialization operation.

  In addition, the wall voltage of the discharge cell displaying black slowly approaches the left wall voltage, and when the voltage obtained by adding the wall voltage to the voltage between the “data electrode-scan electrode” approaches the discharge start voltage during the erasing period, the dark current is generated. The wall voltage on the data electrode Dj is lowered. And since the dark current flowing at this time plays a role of priming to assist the address discharge, it is considered that a stable address discharge can be generated without causing a large discharge delay even in a discharge cell displaying black. be able to.

  In this way, by setting the drive voltage applied to each electrode to satisfy (Condition 1), in particular, by setting the scan pulse voltage Va low so as to satisfy (Condition 1), the forced initialization operation is not performed. The wall voltage necessary for addressing can be accumulated, and priming for stabilizing the address discharge can also be generated.

  Next, (Condition 2) will be described. If the voltage Va of the scan pulse is too low, a discharge occurs regardless of whether or not an address operation is performed when the sustain pulse voltage Vs is applied to the scan electrode SCn in the sustain period, and an image cannot be displayed. In order to suppress this erroneous discharge, it is necessary to set the voltage between the “data electrode-scanning electrode” to be equal to or lower than the discharge start voltage VFsd when the sustain pulse voltage Vs is applied. This condition is (Condition 2).

  Thus, in the present embodiment, the drive voltage waveform is set so as to satisfy (Condition 1) and (Condition 2) in all the discharge cells. Therefore, it is possible to display an image without light emission not related to gradation display by omitting the forced initialization operation while stably generating the writing operation. Therefore, a stable writing operation can be performed without using the forced initialization operation to suppress black luminance and display an image with high contrast.

  In the present embodiment, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn and voltage is applied to data electrode D1 through data electrode Dm in the sustain period of subfield SF1, which is the second type subfield. 0 (V) is applied, and an upward ramp waveform voltage rising to voltage Vs is applied to scan electrode SC1 through scan electrode SCn. Then, after the voltage applied to scan electrode SC1 through scan electrode SCn rises to voltage Vs, voltage Vs is further applied for a certain period. Subsequently, voltage 0 (V) is continuously applied to sustain electrode SU1 through sustain electrode SUn, voltage Vd is applied to data electrode D1 through data electrode Dm, and voltage drops to scan electrode SC1 through scan electrode SCn to voltage Vg. Apply a falling ramp waveform voltage. Thereby, a weak sustain discharge can be generated.

  Furthermore, in the present embodiment, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn in the address period. That is, the voltage applied to sustain electrode SU1 through sustain electrode SUn in the second type subfield address period is lower than the voltage applied to sustain electrode SU1 through sustain electrode SUn in the first type subfield address period. As a result, the discharge generated between data electrode Dk and scan electrode SC1 does not extend to sustain electrode SU1, and the luminance of light emission associated with the address discharge can be suppressed.

  By these driving operations, the luminance displayed by the subfield SF1 can be kept low. In this embodiment, the luminance displayed by the subfield SF1 is the luminance displayed by the subfield in which the sustain pulse is applied to the display electrode pair once. The brightness of about 1/4 of that is realized.

  Next, the discharge start voltage VFsd, the discharge start voltage VFds, and the wall voltage are, for example, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-24, NO. 7, JULY, 1977 "Measurement of a Plasma in the AC Plasma Display panel Using RF Capacitance and Microwave Techniques". Or you may measure simply as follows. An example of a method for simply measuring the discharge start voltage will be described with reference to FIG.

  First, an operation for erasing wall charges is performed. Specifically, as shown in the wall charge erasing period of FIG. 5, a pulsed voltage Vers sufficiently higher than the expected discharge start voltage is alternately applied between the electrodes to be measured, for example, the data electrode and the scan electrode. To do. Next, the discharge start is observed. Specifically, as shown in the measurement period of FIG. 5, a pulsed voltage Vmsr lower than the expected discharge start voltage is applied to one electrode, for example, the data electrode, and the light emission associated with the discharge at that time is photogenerated. Detection is performed using a light detection sensor such as Maru. When no discharge is observed, after performing an operation of erasing wall charges during the wall charge erasing period, light emission is observed by applying a pulsed voltage Vmsr with a slightly increased absolute value of voltage during the measurement period.

  This operation is repeated, and the absolute value of the minimum voltage Vmsr in which light emission is observed in the measurement period is the discharge start voltage. At this time, if the voltage Vmsr applied in the measurement period is a positive voltage, the discharge start voltage VFds with the data electrode as the anode and the scan electrode as the cathode can be measured. If the voltage Vmsr applied during the measurement period is a negative voltage, the discharge start voltage VFsd with the data electrode as the cathode and the scan electrode as the anode can be measured.

  If the discharge start voltage is known, the voltage at which discharge starts is measured for the discharge cell in which the wall voltage is accumulated, and the wall voltage can be known as the difference between the voltage value and the discharge start voltage measured in advance. .

  Next, a drive circuit for driving the panel 10 will be described. FIG. 6 is a circuit block diagram of plasma display device 40 in accordance with the exemplary embodiment of the present invention. The plasma display device 40 forms one field using the panel 10 having a plurality of discharge cells having scan electrodes, sustain electrodes, and data electrodes, and a plurality of subfields having an address period, a sustain period, and an erase period. And a drive circuit for generating a drive voltage waveform and applying the waveform to each electrode of the panel 10. The drive circuit includes an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit (not shown) that supplies necessary power to each circuit block. It has.

  The image signal processing circuit 41 converts the input image signal into image data indicating light emission / non-light emission for each subfield. The data electrode driving circuit 42 converts the image data for each subfield into address pulses corresponding to the data electrodes D1 to Dm and applies them to the data electrodes D1 to Dm. The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block on the basis of the vertical and horizontal synchronization signals, and supplies them to the respective circuit blocks. Scan electrode drive circuit 43 generates the drive voltage waveform described above based on the timing signal and applies it to each of scan electrodes SC1 to SCn. Sustain electrode drive circuit 44 generates the drive voltage waveform described above based on the timing signal and applies it to sustain electrode SU1 through sustain electrode SUn.

  FIG. 7 is a circuit diagram of scan electrode drive circuit 43 of plasma display device 40 in accordance with the first exemplary embodiment of the present invention. Scan electrode drive circuit 43 includes sustain pulse generation circuit 50, ramp waveform voltage generation circuit 60, and scan pulse generation circuit 70.

  Sustain pulse generation circuit 50 includes power recovery circuit 51, switching element Q55, switching element Q56, and switching element Q59, and generates sustain pulses to be applied to scan electrode SC1 through scan electrode SCn. The power recovery circuit 51 recovers and reuses power when driving the scan electrodes SC1 to SCn. Switching element Q55 clamps scan electrode SC1 through scan electrode SCn to voltage Vs, and switching element Q56 clamps scan electrode SC1 through scan electrode SCn to voltage 0 (V). The switching element Q59 is a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43.

  Scan pulse generating circuit 70 includes switching element Q71H1 to switching element Q71Hn, switching element Q71L1 to switching element Q71Ln, and switching element Q72. Then, a scan pulse is generated based on the power source of voltage Va and the power source E71 of voltage (Vc−Va) superimposed on the reference potential of the scan pulse generating circuit 70 (the potential of the node A shown in FIG. 7). Scan pulses are sequentially applied to each of scan electrode SC1 through scan electrode SCn at the timing shown in FIG. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 50 as it is during the sustain operation. That is, the voltage at node A is output to scan electrode SC1 through scan electrode SCn.

  The ramp waveform voltage generation circuit 60 includes a Miller integration circuit 61 and a Miller integration circuit 63, and generates the ramp waveform voltage shown in FIG. Miller integrating circuit 61 includes transistor Q61, capacitor C61, and resistor R61. By applying a constant voltage to input terminal IN61, Miller integrating circuit 61 generates an upward ramp waveform voltage that gradually increases toward voltage Vr. Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63, and applies a constant voltage to input terminal IN63 to generate a downward ramp waveform voltage that gradually decreases toward voltage Vi. Further, by stopping the operation of Miller integrating circuit 63 when the output voltage becomes equal to voltage Vg, it is possible to generate a downward ramp waveform voltage that gradually decreases toward voltage Vg. The switching element Q69 is also a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode drive circuit 43.

  In addition, these switching elements and transistors can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the switching elements and transistors generated by the timing generation circuit 45.

  FIG. 8 is a circuit diagram of sustain electrode drive circuit 44 of plasma display device 40 in accordance with the first exemplary embodiment of the present invention. Sustain electrode drive circuit 44 includes sustain pulse generation circuit 80 and constant voltage generation circuit 85.

  Sustain pulse generation circuit 80 includes power recovery circuit 81, switching element Q83, and switching element Q84, and generates sustain pulses to be applied to sustain electrode SU1 through sustain electrode SUn. The power recovery circuit 81 recovers and reuses the power when driving the sustain electrodes SU1 to SUn. Switching element Q83 clamps sustain electrode SU1 through sustain electrode SUn to voltage Vs, and switching element Q84 clamps sustain electrode SU1 through sustain electrode SUn to voltage 0 (V).

  Constant voltage generation circuit 85 includes switching element Q86 and switching element Q87, and applies voltage Ve to sustain electrode SU1 through sustain electrode SUn.

  In addition, these switching elements can also be comprised using generally known elements, such as MOSFET and IGBT. These switching elements are also controlled by timing signals corresponding to the respective switching elements generated by the timing generation circuit 45.

  FIG. 9 is a circuit diagram of data electrode drive circuit 42 of plasma display device 40 in accordance with the first exemplary embodiment of the present invention. Data electrode drive circuit 42 includes switching element Q91H1 to switching element Q91Hm and switching element Q91L1 to switching element Q91Lm. The voltage 0 (V) is applied to the data electrode Dj by turning on the switching element Q91Lj, and the voltage Vd is applied to the data electrode Dj by turning on the switching element Q91Hj.

  Using such a drive circuit, the drive voltage waveform of the panel shown in FIG. 3 can be generated. However, the drive circuits shown in FIGS. 6 to 9 are examples, and the present invention is not limited to the circuit configurations of these drive circuits.

  As described above, in the panel driving method of the present embodiment, by applying a scan pulse that satisfies the above-described conditions to the scan electrode, a stable writing operation is performed without using a forced initialization operation, and black luminance is increased. By reducing the luminance of the second lowest gradation after black, an image with high contrast and high image display quality can be displayed.

  It should be noted that the specific numerical values and the like shown in (Embodiment 1) are merely examples, and are desirably set optimally according to the panel characteristics, the specifications of the plasma display device, and the like.

  The present invention suppresses black luminance by performing stable writing operation without using forced initialization operation, and lowers luminance of the next lower gradation after black, thereby providing high contrast and high image display quality. Since an image can be displayed, it is useful as a panel driving method and a plasma display device.

DESCRIPTION OF SYMBOLS 10 Panel 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 32 Data electrode 35 Phosphor layer 40 Plasma display apparatus 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 50,80 Sustain pulse generation circuit 51, 81 Power recovery circuit 60 Ramp waveform voltage generation circuit 61, 63 Miller integration circuit 70 Scan pulse generation circuit 85 Constant voltage generation circuit

Claims (3)

A plasma display panel for driving a plasma display panel comprising a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, comprising a plurality of subfields having an address period, a sustain period, and an erase period. Driving method,
The plurality of subfields constituting the one field are a first type subfield that applies a sustain pulse to the scan electrode in the sustain period, and an upward slope waveform on the scan electrode without applying the sustain pulse to the scan electrode in the sustain period. A second type subfield that applies a downward ramp waveform voltage to the scan electrode after applying the voltage,
A voltage obtained by subtracting a voltage applied to the data electrode from a low-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield is defined as a first voltage, and the sustain period of the first type subfield A voltage obtained by subtracting the voltage applied to the data electrode from the high-voltage side voltage of the sustain pulse applied to the scan electrode in step S2 is used as the second voltage, and the low-voltage side voltage of the scan pulse applied to the scan electrode in the address period When the voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode is the third voltage,
A voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than a discharge start voltage using the data electrode as an anode and the scan electrode as a cathode,
A voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage using the data electrode as an anode and the scan electrode as a cathode, and a discharge start voltage using the data electrode as a cathode and the scan electrode as an anode. And a method for driving a plasma display panel. The voltage applied to the sustain electrode in the address period of the second type subfield is lower than the voltage applied to the sustain electrode in the address period of the first type subfield. A method for driving a plasma display panel according to claim 1. A plasma display panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, and a plurality of subfields having an address period, a sustain period, and an erase period are used to form one field and drive voltage waveform A plasma display device comprising a drive circuit that is generated and applied to each electrode of the plasma display panel,
The drive circuit is
A first type sub-field that applies a sustain pulse to the scan electrode in the sustain period, and a ramp waveform voltage applied to the scan electrode without applying a sustain pulse to the scan electrode in the sustain period, and then descends to the scan electrode. One field is configured using the second type subfield to which the ramp waveform voltage is applied, and
A voltage obtained by subtracting a voltage applied to the data electrode from a low-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield is defined as a first voltage, and the sustain period of the first type subfield A voltage obtained by subtracting the voltage applied to the data electrode from the high-voltage side voltage of the sustain pulse applied to the scan electrode in step S2 is used as the second voltage, and the low-voltage side voltage of the scan pulse applied to the scan electrode in the address period When the voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode is the third voltage,
A voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than a discharge start voltage using the data electrode as an anode and the scan electrode as a cathode,
A voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage using the data electrode as an anode and the scan electrode as a cathode, and a discharge start voltage using the data electrode as a cathode and the scan electrode as an anode. The plasma display device is characterized in that the voltage is set so as not to exceed the sum.