JP2012189768A - Method for driving plasma display panel and plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce brightness of black displayed in a plasma display panel and to stably generate write discharge.SOLUTION: One field includes a first type sub-field where a sustain pulse is generated and is applied to a display electrode pair in a sustain period and a second type sub-field where a rising ramp voltage and a falling ramp voltage are generated and are applied to a scan electrode in a sustain period without generation of a sustain pulse. The second type sub-field is defined as a sub-field having the least brightness weight. Brightness around a plasma display device is compared with first illuminance. When an image to be displayed in a plasma display panel satisfies a prescribed condition, the sub-field having the least brightness weight is forcibly lit at a prescribed lighting rate in the case of the detected brightness being lower than the first illuminance, and the sub-field having the least brightness weight is forcibly lit at a lighting rate corresponding to the detected brightness in the case of the detected brightness being equal to or higher than the first illuminance.

Description

  The present invention relates to an AC surface discharge type plasma display panel driving method and a plasma display apparatus.

  A plasma display panel (hereinafter abbreviated as “panel”) includes a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and is an ultraviolet ray generated by gas discharge in the discharge cell. The phosphors of red, green, and blue are excited and emitted to display an image in color.

  A subfield method is generally used as a method for driving the panel. In the subfield method, a single field is formed using a plurality of subfields having an initialization period, an address period, and a sustain period, and gradation display is performed by a combination of subfields that emit light. In each subfield, an initialization operation is performed in the initialization period, an address operation is performed in the write period, and a sustain operation is performed in the sustain period.

  The initialization operation is an operation in which an initialization discharge is generated in the discharge cell and wall charges necessary for the subsequent address operation are formed in the discharge cell. The initializing operation includes a forced initializing operation in which an initializing discharge is generated in the discharge cell regardless of the operation in the immediately preceding subfield, and a selection in which the initializing discharge is generated in the discharge cell that has performed the address discharge in the immediately preceding subfield. There is an initialization operation.

  The address operation is an operation in which address discharge is selectively generated in the discharge cells in accordance with the image to be displayed, and wall charges are formed in the discharge cells. The sustain operation is an operation in which a sustain pulse is alternately applied to the display electrode pair to generate a sustain discharge in the discharge cell in which the address discharge is generated and to cause the phosphor layer of the discharge cell to emit light. The light emission of the phosphor layer due to the sustain discharge is light emission related to gradation display, and the light emission generated by the forced initialization operation is light emission not related to gradation display.

  Up to now, a plurality of subfield methods have been proposed. One of them is a luminance (hereinafter referred to as “below”) for reducing the light emission not related to the gradation display as much as possible and displaying the lowest gradation black. There is a driving method for improving contrast by lowering (abbreviated as “black luminance”). For example, Patent Document 1 discloses a driving method in which a forced initialization operation is performed using a gradually changing ramp waveform voltage, and the number of times the forced initialization operation is performed is once per field.

  In Patent Document 2, the display electrode pair is divided into n, and the number of times of performing the forced initialization operation is once per n fields, thereby further reducing light emission not related to gradation display and further reducing black luminance, A driving method with further improved contrast is disclosed.

JP 2000-242224 A JP 2006-091295 A

  If the driving method described in Patent Document 2 is used, the number of times of forced initialization operation per unit time (for example, 1 second) is reduced and the black luminance is further decreased as compared with the driving method described in Patent Document 1. Can do. However, in the forced initialization operation, priming particles for accumulating wall charges necessary for generating the address discharge in the subsequent address period in the discharge cell and generating the address discharge reliably by shortening the discharge delay time It works to generate. Therefore, if the forced initialization operation is omitted, normal image display cannot be performed because the address discharge does not occur or the address delay becomes too long due to the discharge delay time of the address discharge becoming unstable. Therefore, even with the driving method described in Patent Document 2, it is necessary to perform a forced initialization operation. As a result, even in a discharge cell that displays black without generating a sustain discharge, it is caused by the forced initialization operation. Luminescence occurs.

  As described above, in the prior art, it is difficult to omit the forced initializing operation, and thus there is a limit in improving the contrast.

  On the other hand, when the black luminance, which is the lowest gradation, is reduced, the luminance of the black gradation (for example, luminance of gradation value “0”) and the luminance of the second lowest gradation (for example, luminance of gradation value “1”) is reduced. ), The continuity of displayable luminance may be impaired. In such a case, the image display quality particularly when displaying a dark image may be deteriorated.

  The present invention has been made in view of these problems, and it is possible to perform a stable writing operation without performing a forced initialization operation, thereby suppressing the black luminance and increasing the contrast of the display image. Next, by reducing the brightness of the lower gradation, the gradation when displaying a dark image is improved, and the address discharge is stably generated when the display image is switched from a black image to a normal image, An object of the present invention is to provide a panel driving method and a plasma display device capable of displaying an image with high image display quality.

  The present invention forms a single field using a plurality of subfields each having an address period, a sustain period, and an erase period, and includes a plurality of discharge cells each having a display electrode pair and a data electrode each composed of a scan electrode and a sustain electrode. A panel driving method for driving a panel, wherein a plurality of subfields constituting one field generate a number of sustain pulses corresponding to luminance weights in a sustain period and apply them to display electrode pairs. A voltage obtained by subtracting the voltage applied to the data electrode from the low-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield in the sustain period of the first type subfield is defined as the first voltage. The second voltage is obtained by subtracting the voltage applied to the data electrode from the high-voltage side voltage of the sustain pulse applied to the scan electrode in FIG. When the voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode from the low-voltage side voltage of the scan pulse applied to the electrode is the third voltage, the voltage obtained by subtracting the third voltage from the first voltage is: The discharge start voltage of the discharge with the data electrode as the anode and the scan electrode as the cathode is equal to or higher than the discharge start voltage of the discharge with the data electrode as the anode and the scan electrode as the cathode. It is less than the sum of the voltage and the discharge start voltage of the discharge with the data electrode as the cathode and the scan electrode as the anode, and detects the brightness around the plasma display device on which the panel is mounted. If the detected brightness is less than the first illuminance, and the image displayed on the panel satisfies a predetermined condition, the subfield with the smallest luminance weight is set to a predetermined point. If the detected brightness is equal to or higher than the first illuminance, the subfield with the smallest luminance weight is forcibly turned on at the lighting rate according to the detected brightness. To do.

  This method makes it possible to perform a stable write operation without performing a forced initialization operation, thereby suppressing black luminance and increasing the contrast of a display image. In addition, the subfield with the smallest luminance weight can be forcibly turned on depending on the brightness around the plasma display device and whether the image displayed on the panel satisfies a predetermined condition, and the display image is black. Address discharge can be stably generated when switching from an image to a normal image. Thereby, an image with high image display quality can be displayed on the panel.

  Further, in the panel driving method of the present invention, the plurality of subfields constituting one field generate the first type subfield and the upslope waveform voltage and the downslope waveform voltage without generating the sustain pulse in the sustain period. In this case, the second type subfield may be a subfield having the smallest luminance weight. Thereby, the gradation at the time of displaying a dark image can be improved by lowering the luminance of the next lower gradation after black. In addition, when the display image is switched from a black image to a normal image, address discharge can be stably generated, and an image with high image display quality can be displayed on the panel.

  Further, the panel driving method of the present invention detects the average luminance level based on the image signal, determines whether the image displayed on the panel is a black image by comparing the average luminance level and the black image threshold, When the length of time for which black images are continuously displayed on the panel reaches the black image display time threshold value, it may be determined that the image displayed on the panel satisfies a predetermined condition. Thereby, when the display image is switched from a black image to a normal image, an address discharge can be stably generated, and an image with high image display quality can be displayed on the panel.

  In addition, the panel driving method of the present invention measures the length of time that a field in which no address operation is performed continuously occurs for each discharge cell as a non-lighting continuous time, and the non-lighting continuous time is not lighted. When the number of discharge cells whose non-lighting continuous time is equal to or greater than the non-lighting time threshold value reaches the black image threshold value compared with the time threshold value, the image displayed on the panel satisfies the predetermined condition You may judge that time. Thereby, when the display image is switched from a black image to a normal image, an address discharge can be stably generated, and an image with high image display quality can be displayed on the panel.

  In the panel driving method of the present invention, the total use time of the plasma display device equipped with the panel may be detected, and the black image display time threshold may be reduced according to the total use time. As a result, the black image display time threshold value can be reduced according to the discharge characteristics of the panel that changes according to the total usage time, and the image display quality can be further improved.

  Further, the panel driving method of the present invention may detect the total usage time of the plasma display device on which the panel is mounted, and reduce the non-lighting time threshold according to the total usage time. Thereby, the non-lighting time threshold value can be reduced in accordance with the discharge characteristics of the panel that changes in accordance with the total usage time, and the image display quality can be further improved.

  In the panel driving method of the present invention, the voltage applied to the sustain electrode in the second type subfield address period is lower than the voltage applied to the sustain electrode in the first type subfield address period. Also good. Thereby, the light emission luminance in the write period of the second type subfield can be made lower than that in the write period of the first type subfield.

  In the panel driving method of the present invention, the predetermined lighting rate when forcibly lighting is an area where the subfield with the smallest luminance weight is not lit when displaying an image on the panel based on the image signal. It may represent the lighting rate at.

  Also, the panel driving method of the present invention compares the detected brightness with a preset second illuminance, and if the detected brightness is equal to or greater than the second illuminance, the predetermined lighting rate is the highest. The subfield with the lowest luminance weight is forcibly lit, and if the detected brightness is equal to or higher than the first illuminance and lower than the second illuminance, the subfield with the lowest luminance weight at the lighting rate according to the detected brightness is selected. You may turn it on forcibly. This makes it possible to control the light emission luminance of the panel during the period in which the subfield with the smallest luminance weight is forcibly lit in accordance with the ambient brightness of the plasma display device, thereby further improving the image display quality. it can.

  In the panel driving method of the present invention, the total usage time of the plasma display device on which the panel is mounted may be detected, and the predetermined lighting rate may be increased according to the total usage time. As a result, the predetermined lighting rate when forcibly lighting the second type subfield can be increased according to the discharge characteristics of the panel that changes according to the total usage time, so that the image display quality can be further improved. .

  The present invention also provides a panel having a plurality of discharge cells each having a display electrode pair and data electrodes each composed of a scan electrode and a sustain electrode, and a plurality of subfields each having an address period, a sustain period, and an erase period. And a driving circuit that generates a driving voltage waveform corresponding to each electrode of the panel and applies the driving voltage waveform to each of the electrodes. The driving circuit includes a plurality of first fields in one field. In the sustain period of the first type subfield, the number of sustain pulses corresponding to the luminance weight is generated and applied to the display electrode pair, and the scan electrode is applied in the sustain period of the first type subfield. The voltage obtained by subtracting the voltage applied to the data electrode from the low-voltage side voltage of the sustain pulse applied to the first voltage is defined as the first voltage, and the first subfield sustain period In this case, the voltage obtained by subtracting the voltage applied to the data electrode from the high voltage on the sustain pulse applied to the scan electrode is used as the second voltage, and applied to the data electrode from the low voltage on the scan pulse applied to the scan electrode in the writing period. When the voltage obtained by subtracting the low-voltage side voltage of the address pulse to be used is the third voltage, the voltage obtained by subtracting the third voltage from the first voltage is the discharge start of discharge using the data electrode as the anode and the scan electrode as the cathode. The voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage for discharge using the data electrode as an anode and the scan electrode as a cathode, and a discharge using the data electrode as a cathode and the scan electrode as an anode. The drive circuit detects brightness around the plasma display device on which the panel is mounted, and compares the detected brightness with a preset first illuminance. If the detected brightness is less than the first illuminance, the second type subfield is forcibly lit at a predetermined lighting rate when the image displayed on the panel satisfies a predetermined condition, and the detected brightness If the illuminance is greater than or equal to the first illuminance, the subfield having the smallest luminance weight is forcibly lit at a lighting rate corresponding to the detected brightness.

  With this configuration, it is possible to perform a stable writing operation without performing a forced initialization operation, thereby suppressing black luminance and increasing the contrast of a display image. In addition, the subfield with the smallest luminance weight can be forcibly turned on depending on the brightness around the plasma display device and whether the image displayed on the panel satisfies a predetermined condition, and the display image is black. Address discharge can be stably generated when switching from an image to a normal image. Thereby, the plasma display apparatus which can display an image with high image display quality on a panel can be provided.

  In the plasma display device of the panel of the present invention, the drive circuit generates one ramp, a plurality of first-type subfields, and an up-slope waveform voltage and a down-slope waveform voltage without generating a sustain pulse in the sustain period. Thus, the second type subfield applied to the scan electrode may be used, and the second type subfield may be a subfield having the smallest luminance weight. Thereby, the gradation at the time of displaying a dark image can be improved by lowering the luminance of the next lower gradation after black. In addition, when the display image is switched from a black image to a normal image, address discharge can be stably generated, and an image with high image display quality can be displayed on the panel.

  According to the present invention, it is possible to perform a stable writing operation without performing a forced initializing operation, thereby suppressing the black luminance, thereby increasing the contrast of the display image and reducing the luminance of the next lower gradation after black. To improve the gradation when displaying a dark image, and stably generate an address discharge when the display image switches from a black image to a normal image, thereby displaying an image with high image display quality. It is possible to provide a panel driving method and a plasma display device that can be used.

It is a disassembled perspective view of the panel used for the plasma display apparatus in Embodiment 1 of this invention. It is an electrode array diagram of the panel used for the plasma display device in the first exemplary embodiment of the present invention. It is a figure which shows the drive voltage waveform applied to each electrode of the plasma display apparatus in Embodiment 1 of this invention. It is a figure for demonstrating the definition of the 1st voltage, 2nd voltage, and 3rd voltage in Embodiment 1 of this invention. It is a figure which shows an example of the method of measuring a discharge start voltage simply. It is a circuit block diagram of the plasma display apparatus in Embodiment 1 of the present invention. FIG. 3 is a circuit block diagram of a predetermined image display time detection circuit according to the first embodiment of the present invention. The relationship between the time when the image signal of the black image is continuously input when the brightness detected by the brightness detection circuit according to Embodiment 1 of the present invention is less than the first illuminance and the second type subfield forced lighting FIG. It is a figure which shows the relationship between the brightness around the plasma display apparatus in Embodiment 1 of this invention, and 2nd type subfield forced lighting. It is a circuit diagram of the scan electrode drive circuit of the plasma display apparatus in Embodiment 1 of the present invention. It is a circuit diagram of the sustain electrode drive circuit of the plasma display device in the first exemplary embodiment of the present invention. It is a circuit diagram of the data electrode drive circuit of the plasma display apparatus in Embodiment 1 of this invention. It is a circuit block diagram of the plasma display apparatus in Embodiment 2 of the present invention. It is a circuit block diagram of the predetermined image display time detection circuit in Embodiment 2 of the present invention. It is a circuit block diagram of the plasma display apparatus in Embodiment 3 of this invention. It is a circuit block diagram of the plasma display apparatus in Embodiment 4 of this invention.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the display electrode pair 24, and a protective layer 26 is formed on the dielectric layer 25. The protective layer 26 is formed using magnesium oxide, which is a material having high electron emission performance, in order to easily generate discharge. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33. For example, (Y, Gd) BO ₃ : Eu is used as the red phosphor, Zn ₂ SiO ₄ : Mn is used as the green phosphor, and BaMgAl ₁₀ O ₁₇ : Eu is used as the blue phosphor. Each of them uses a phosphor as a main component.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is sealed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) that are long in the row direction. M data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged. A discharge cell is formed at a portion where a pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects with one data electrode Dj (j = 1 to m). Therefore, m × n discharge cells are formed in the discharge space. The area formed in this way becomes an image display area for displaying an image on the panel 10.

  Next, a driving voltage waveform for driving panel 10 and its operation will be described. In the plasma display device, one field is divided into a plurality of subfields, and the panel 10 is driven by a subfield method in which light emission / non-light emission of each discharge cell is controlled for each subfield, and an image is displayed on the panel 10.

  In this embodiment, one field is configured by using a plurality of subfields each having an address period, a sustain period, and an erase period. In the present embodiment, the forced initializing operation for forcibly generating the initializing discharge in the discharge cells is not performed regardless of the presence or absence of the previous discharge.

  In the address period, an address discharge is selectively generated in the discharge cells to emit light, and an address operation is performed to form wall charges in the discharge cells.

  In the sustain period, a number of sustain pulses corresponding to a predetermined luminance weight for each subfield are generated and applied alternately to the display electrode pair, and a sustain discharge is generated in the discharge cell that has generated the address discharge. A sustain operation for causing the cell to emit light is performed. In the present embodiment, a sustain operation is performed in which the sustain pulse is not applied to the scan electrode 22 in order to suppress the luminance of the second lowest gradation after black (for example, the gradation value “0”) as much as possible. In this sustain operation, instead of the sustain pulse, an up-gradient waveform voltage (up-gradient waveform voltage L1 described later) whose voltage gradually rises is generated and applied to the scan electrode 22, and then the voltage gradually falls. A downward ramp waveform voltage (downward ramp waveform voltage L2 described later) is generated and applied to the scan electrode 22. In this way, a sustain operation is performed in which a weak sustain discharge is generated in the discharge cell in which the address discharge is generated as compared with the sustain discharge generated by the sustain pulse, and the discharge cell emits light with a weak luminance.

  In the erasing period, an erasing discharge is generated only in the discharge cells that have generated the address discharge in the address period of the subfield to which the erasing period belongs. Therefore, this erasing discharge is selectively generated only in the discharge cells that have generated the address discharge. By this erasing discharge, the history of wall charges formed by the address discharge or the subsequent sustain discharge is erased, and wall charges necessary for the subsequent address discharge are formed on each electrode. Hereinafter, these operations are also referred to as “erase operations”.

  Hereinafter, in the present embodiment, one field is divided into 11 subfields (SF1, SF2,..., SF11), and each subfield is (1/2, 1, 2, 3, 6, 11). , 18, 30, 44, 60, 80).

  In the present embodiment, the luminance weight of the subfield SF1 is expressed as “1/2”. This is because subfield SF1 does not generate a sustain pulse in the sustain period, but generates an up-slope waveform voltage (up-slope waveform voltage L1) and a down-slope waveform voltage (down-slope waveform voltage L2) instead of the sustain pulse. This is because the emission luminance is lower than that of the subfield SF2 of the luminance weight “1”, which is a subfield applied to the scan electrode 22 and the sustain pulse is applied to the display electrode pair 24. Hereinafter, as in the subfield SF1, a subfield in which no sustain pulse is generated in the sustain period and the rising ramp waveform voltage and the falling ramp waveform voltage are applied to the scan electrode 22 is referred to as a “second type subfield”. In addition, a subfield (for example, subfield SF2 to subfield SF11) in which a sustain pulse is applied to the display electrode pair 24 in the sustain period is referred to as a “first type subfield”.

  In the present embodiment, the luminance weight “1/2” of the subfield SF1 does not indicate that light is emitted with half the luminance of the subfield SF2 having the luminance weight “1”. The luminance weight “1/2” of the subfield SF1 that is the second type subfield only indicates that light is emitted with lower luminance than the subfield SF2 that is the first type subfield. It only shows that gradation display lower than the subfield SF11 is performed. In this case, the second type subfield is the subfield having the smallest luminance weight among the subfields constituting one field.

  Thus, in the present embodiment, the plurality of subfields constituting one field generate the sustain pulse in the sustain period and apply it to the display electrode pair 24, and the sustain pulse in the sustain period. A second sub-field that generates an up-slope waveform voltage (up-slope waveform voltage L1) and a down-slope waveform voltage (down-slope waveform voltage L2) and applies the scan electrode 22 without being generated. .

  The subfield configuration described above is merely an example in the present embodiment, and the present invention is not limited to this subfield configuration. It is desirable to optimally set the number of subfields constituting one field and the luminance weight of each subfield according to the characteristics of the panel and the specifications of the plasma display device.

  FIG. 3 is a diagram showing a driving voltage waveform applied to each electrode of the plasma display device in accordance with the first exemplary embodiment of the present invention.

  In the address period of subfield SF1, which is the second type subfield, voltage 0 (V) is applied to data electrode D1 to data electrode Dm, voltage 0 (V) is applied to sustain electrode SU1 to sustain electrode SUn, and scanning is performed. Voltage Vc is applied to electrode SC1 through scan electrode SCn. Next, a scan pulse of voltage Va is applied to scan electrode SC1 in the first row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light.

  As a result, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is obtained by adding the positive wall voltage on the data electrode Dk to the difference (Vd−Va) of the externally applied voltage, so that the data electrode Dk becomes the anode. The discharge start voltage VFds of the discharge having the scan electrode SC1 as a cathode is exceeded, and a discharge is generated between the data electrode Dk and the scan electrode SC1. This discharge is an address discharge, and when an address discharge occurs, a positive wall voltage is accumulated on scan electrode SC1, and a negative wall voltage is accumulated on data electrode Dk. The wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  Thus, an address operation is performed in which an address discharge is generated in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrode Dh to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage VFds, so the address discharge does not occur.

  Next, a scan pulse is applied to scan electrode SC2 in the second row, and an address pulse is applied to data electrode Dk corresponding to the discharge cell to emit light. Thereby, an address discharge is generated between data electrode Dk and scan electrode SC2, and a positive wall voltage is accumulated on scan electrode SC2, and a negative wall voltage is accumulated on data electrode Dk. In this way, an address operation is performed in which an address discharge is generated in the discharge cells to be lit in the second row and wall voltage is accumulated on each electrode. On the other hand, since the voltage at the intersection between the data electrode Dh and the scan electrode SC2 to which no address pulse is applied does not exceed the discharge start voltage VFds, no address discharge occurs.

  Thereafter, the same address operation is sequentially performed until reaching the n-th scan electrode SCn, and wall charges necessary for the subsequent sustain discharge are formed.

  In the present embodiment, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn in the address period. Therefore, it is considered that the discharge generated between data electrode Dk and scan electrode SC1 does not extend to sustain electrode SU1. As a result, the luminance of light emission generated along with the address discharge can be suppressed, and the luminance displayed by the subfield SF1 can be suppressed low.

  Here, for the following description, the first voltage V1, the second voltage V2, and the third voltage V3 are defined as follows. FIG. 4 is a diagram for explaining definitions of the first voltage, the second voltage, and the third voltage in the first embodiment of the present invention.

  In the present embodiment, from the low voltage side voltage (0 (V) in FIG. 4) of the sustain pulse applied to scan electrode SCi in the sustain period of subfield SF2 to subfield SF11 which is the first type subfield, data electrode A voltage obtained by subtracting a voltage applied to Dj (0 (V) in FIG. 4) is defined as a first voltage V1. Further, the voltage (0 (V) in FIG. 4) applied to the data electrode Dj from the high-voltage side voltage (voltage Vs in FIG. 4) of the sustain pulse applied to the scan electrode SCi in the sustain period of the first type subfield. The reduced voltage is set as the second voltage V2. Further, the low-voltage side voltage (0 (V) in FIG. 4) of the address pulse applied to the data electrode Dj is subtracted from the low-voltage side voltage (voltage Va in FIG. 4) of the scan pulse applied to the scan electrode SCi in the address period. This voltage is referred to as a third voltage V3.

  Further, as described above, the discharge start voltage of the discharge using the data electrode Dj as the anode and the scan electrode SCi as the cathode is the discharge start voltage VFds, and the discharge start voltage of the discharge using the data electrode Dj as the cathode and the scan electrode SCi as the anode. Is the discharge start voltage VFsd. The discharge with the data electrode Dj as the anode and the scan electrode SCi as the cathode is a discharge in which the electric field in the discharge cell when the discharge occurs is a high potential side on the data electrode Dj side and a low potential side on the scan electrode SCi side. It is. The discharge with the data electrode Dj as the cathode and the scan electrode SCi as the anode is a discharge in which the electric field in the discharge cell when the discharge occurs is a low potential side on the data electrode Dj side and a high potential side on the scan electrode SCi side. is there. Since the protective layer 26 of magnesium oxide having high electron emission performance is formed on the scan electrode SCi side, the discharge start voltage VFds is lower than the discharge start voltage VFsd.

  At this time, in this embodiment, the voltage Va of the scan pulse applied to the scan electrode SCi is set so as to satisfy the following two conditions (condition 1) and (condition 2).

(Condition 1): For all discharge cells, the voltage obtained by subtracting the third voltage V3 from the first voltage V1 is equal to or higher than the discharge start voltage VFds of the discharge using the data electrode Dj as the anode and the scan electrode SCi as the cathode. It is. That is,
(V1-V3) ≧ VFds
(Condition 2): For all the discharge cells, a voltage obtained by subtracting the third voltage V3 from the second voltage V2 is a discharge start voltage VFds of discharge using the data electrode Dj as an anode and the scan electrode SCi as a cathode. This is less than the sum of the discharge start voltage VFsd of the discharge with the data electrode Dj as the cathode and the scan electrode SCi as the anode. That is,
(V2-V3) <(VFds + VFsd)
Next, the maintenance period will be described. In the sustain period of subfield SF1, which is the second type subfield, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, voltage 0 (V) is applied to data electrode D1 through data electrode Dm, and scanning is performed. An upward ramp waveform voltage L1 that gently rises from voltage 0 (V) to voltage Vs is applied to electrode SC1 through scan electrode SCn. In the discharge cell in which the address discharge is generated, the voltage difference between the scan electrode SCi and the data electrode Dk is obtained by adding the difference between the wall voltage on the scan electrode SCi and the wall voltage on the data electrode Dk to the rising ramp waveform voltage L1. Will be. The voltage difference between scan electrode SCi and data electrode Dk exceeds discharge start voltage VFsd during the rise of upward ramp waveform voltage L1, and a weak sustain discharge occurs between scan electrode SCi and data electrode Dk. The phosphor layer 35 emits light due to the ultraviolet rays generated by this discharge. Since this discharge is a weak discharge compared to the discharge generated by the sustain pulse, the ultraviolet rays generated along with this discharge are also weak, and the light emission at this time is also weak.

  After the voltage applied to scan electrode SC1 through scan electrode SCn rises to voltage Vs, voltage Vs is applied to scan electrode SC1 through scan electrode SCn continuously for a certain period (for example, for 50 μsec). As a result, the positive wall voltage on the scan electrode SCi decreases, and the negative wall voltage on the data electrode Dk also decreases. On the other hand, the sustain discharge does not occur in the discharge cell in which the address discharge has not occurred, and the wall voltage at the end of the immediately preceding field is maintained. Thereafter, the voltage applied to scan electrode SC1 through scan electrode SCn is lowered to voltage 0 (V).

  Subsequently, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, voltage Vd is applied to data electrode D1 through data electrode Dm, and voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn. Is applied to the ramp-down waveform voltage L2 that gently falls from V to Vg. This voltage Vg is set equal to (voltage Va + voltage Vd) or slightly higher than (voltage Va + voltage Vd).

  As a result, a weak sustain discharge occurs again in the discharge cell that has generated a weak sustain discharge, and the phosphor layer 35 emits light. The light emission at this time is also weak light emission similar to the light emission by the upward ramp waveform voltage L1. Then, the negative wall voltage on the data electrode Dk increases, and the positive wall voltage on the scan electrode SCi increases. Thereafter, the voltage applied to scan electrode SC1 through scan electrode SCn is raised to voltage 0 (V).

  In the subsequent erasing period of subfield SF1, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, voltage Vd is applied to data electrode D1 through data electrode Dm, and scan electrode SC1 through scan electrode SCn. Applies an upward ramp waveform voltage L3 that gradually rises from voltage 0 (V) to voltage Vr. Thereby, in a discharge cell that has generated a weak sustain discharge during the sustain period, a weak erasure discharge occurs between scan electrode SCi and sustain electrode SUi. Then, the negative wall voltage on sustain electrode SUi decreases, and the positive wall voltage on scan electrode SCi increases. Thereafter, the voltage applied to scan electrode SC1 through scan electrode SCn is lowered to voltage 0 (V).

  Thereafter, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and voltage 0 (V) is applied to data electrode D1 through data electrode Dm. Then, a downward ramp waveform voltage L4 that gently falls from voltage 0 (V) to voltage Vi is applied to scan electrode SC1 through scan electrode SCn. This voltage Vi is set to be equal to or slightly higher than the voltage Va of the scanning pulse.

  As a result, a weak discharge is generated again in the discharge cell that has generated the weak erasing discharge, and an excessive portion of the wall voltage on the scan electrode SCi, the sustain electrode SUi, and the data electrode Dk is discharged, The wall voltage is adjusted to be suitable for the write operation. In this way, the erase operation is completed.

  In the present embodiment, the voltage Vr is set to the same voltage as the voltage Vs, but the voltage Vr may be a voltage different from the voltage Vs.

  In the address period of subfield SF2, which is the first type subfield, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn. This is different from the writing period of the subfield SF1, which is the second type subfield. Then, voltage 0 (V) is applied to data electrode D1 through data electrode Dm, and voltage Vc is applied to scan electrode SC1 through scan electrode SCn.

  Next, a scan pulse of voltage Va is applied to scan electrode SC1 in the first row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light. As a result, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is obtained by adding the positive wall voltage on the data electrode Dk to the difference between the externally applied voltages (Vd−Va), and the discharge start voltage VFds. Exceed. Then, a discharge is generated between data electrode Dk and scan electrode SC1. Further, since voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn during this address period, the discharge generated between data electrode Dk and scan electrode SC1 extends between scan electrode SC1 and sustain electrode SU1. Thus, an address discharge occurs in subfield SF2, positive wall voltage is accumulated on scan electrode SC1, negative wall voltage is accumulated on sustain electrode SU1, and negative wall voltage is also accumulated on data electrode Dk. Voltage is accumulated.

  Thus, an address operation is performed in which an address discharge is generated in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrode Dh to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage VFds, so the address discharge does not occur.

  Next, a scan pulse is applied to scan electrode SC2 in the second row, and an address pulse is applied to data electrode Dk corresponding to the discharge cell to emit light. As a result, an address discharge is generated between data electrode Dk and scan electrode SC2, and between sustain electrode SU2 and scan electrode SC2, and a positive wall voltage is accumulated on scan electrode SC2, and on sustain electrode SU2. A negative wall voltage is accumulated, and a negative wall voltage is also accumulated on the data electrode Dk. In this way, an address operation is performed in which an address discharge is generated in the discharge cell to emit light in the second row and a wall voltage is accumulated on each electrode. On the other hand, since the voltage at the intersection between the data electrode Dh and the scan electrode SC2 to which no address pulse is applied does not exceed the discharge start voltage VFds, no address discharge occurs.

  Thereafter, the same address operation is performed until the scan electrode SCn in the n-th row, and wall charges necessary for the subsequent sustain discharge are formed.

  In the sustain period of subfield SF2, which is the first type subfield, voltage 0 (V) is applied to data electrode D1 to data electrode Dm, voltage 0 (V) is applied to sustain electrode SU1 to sustain electrode SUn, and scanning is performed. A sustain pulse of voltage Vs is applied to electrode SC1 through scan electrode SCn. As a result, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is obtained by adding the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi to voltage Vs. This exceeds the discharge start voltage VFss between scan electrode SCi and sustain electrode SUi. Then, a sustain discharge is generated between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Furthermore, a positive wall voltage is also accumulated on the data electrode Dk. On the other hand, the sustain discharge does not occur in the discharge cell in which the address discharge has not occurred, and the wall voltage at the end of the immediately preceding subfield is maintained.

  Subsequently, voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn, and a sustain pulse of voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. As a result, the sustain discharge occurs again in the discharge cell that has generated the sustain discharge, and the phosphor layer 35 emits light. Then, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi. In the same manner, sustain pulses of the number corresponding to the luminance weight are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and the sustain discharge is continued in the discharge cell that has generated the address discharge. generate.

  In the subsequent erasing period of subfield SF2, voltage 0 (V) is applied to data electrode D1 to data electrode Dm, voltage 0 (V) is applied to sustain electrode SU1 to sustain electrode SUn, and scan electrode SC1 is scanned. An upward ramp waveform voltage L3 that gently rises from the voltage 0 (V) to the voltage Vr is applied to the electrode SCn. As a result, a weak erasing discharge occurs between scan electrode SCi and sustain electrode SUi in the discharge cell that has undergone the sustain discharge. Then, the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. When the rising ramp waveform voltage L3 reaches the voltage Vr, the voltage applied to scan electrode SC1 through scan electrode SCn is then lowered to voltage 0 (V).

  Thereafter, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and downward ramp waveform voltage L4 that gently falls from voltage 0 (V) to voltage Vi is applied to scan electrode SC1 through scan electrode SCn. As a result, a weak discharge is generated again in the discharge cell that has generated the weak erasing discharge, and an excessive portion of the wall voltage on the scan electrode SCi, the sustain electrode SUi, and the data electrode Dk is discharged, The wall voltage is adjusted to be suitable for the write operation. In this way, the erase operation is completed.

  The operations in the subfields SF3 to SF11 that are the first type subfield are the same as the operations in the subfield SF2 that is the first type subfield, except for the number of sustain pulses.

  In this embodiment, the voltage Vc is −145 (V), the voltage Va is −280 (V), the voltage Vs is 200 (V), the voltage Vg is −200 (V), the voltage Vr is 200 (V), The voltage Vi is −260 (V), the voltage Ve is 20 (V), and the voltage Vd is 60 (V). The slopes of the rising ramp waveform voltage L1 and the rising ramp waveform voltage L3 are set between 1 to 10 (V / μsec) (for example, 1.3 (V / μsec)), the falling ramp waveform voltage L2, and the falling ramp waveform. The gradient of the voltage L4 is set between −1 and −10 (V / μsec) (for example, −1.3 (V / μsec)). However, these voltage values are merely examples, and are not limited to the values described above, and are desirably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device. Further, with respect to the downward ramp waveform voltage L2 and the downward ramp waveform voltage L4, for example, the voltage is lowered with a steep slope until just before the discharge occurs, and then the slope is gradually lowered during the period when the discharge is occurring. The configuration may be such that the gradient is changed halfway, such as by lowering the voltage.

  In the above description of the wall voltage, the wall voltage on each electrode is shown assuming a reference potential of wall voltage 0 (V) inside the discharge cell space. However, what is important in considering the wall voltage is, as is well known, the difference in the wall voltage between the electrodes, and the change in the wall voltage on each electrode.

  Further, the discharge start voltage VFds and the discharge start voltage VFsd of the panel 10 used in the present embodiment are measured by the methods described later, and their values are as follows.

  The discharge start voltage varies depending on the phosphor. The inventor of the present application measured the panel 10, and in the discharge cell coated with the red phosphor, the discharge start voltage VFds between the “data electrode 32 and the scan electrode 22” was 200 ± 10 (V). The VFsd was 320 ± 10 (V). In the discharge cell coated with green phosphor, the discharge start voltage VFds between “data electrode 32 and scan electrode 22” is 220 ± 10 (V), and the discharge start voltage VFsd is 350 ± 10 (V). there were. In the discharge cell coated with blue phosphor, the discharge start voltage VFds between “data electrode 32 and scan electrode 22” is 200 ± 10 (V), and the discharge start voltage VFsd is 330 ± 10 (V). there were. Further, the discharge start voltage VFss between “scan electrode 22 and sustain electrode 23” is 250 ± 10 (V) in the discharge cell coated with red and blue phosphors, and the discharge cell coated with green phosphor. It was 280 ± 10 (V).

In the present embodiment, the voltage on the low voltage side of the sustain pulse is voltage 0 (V), and the voltage applied to the data electrode 32 in the sustain period is voltage 0 (V), so the first voltage V1 is the voltage 0 (V). Further, since the low voltage side of the scan pulse is the voltage Va and the low voltage side voltage of the write pulse is the voltage 0 (V), the third voltage V3 is the voltage Va (−280 (V)). Further, the discharge start voltage VFds is larger in the discharge cell coated with the green phosphor than the other discharge cells, and its maximum value is the voltage 230 (V) in consideration of variation. As described above, (Condition 1) is (V1−V3) ≧ VFds. And
(First voltage V1−third voltage V3) = 0−Va = 280 (V)
And
(Maximum value of VFds) = 230 (V)
It is. That is,
(First voltage V1−third voltage V3)> (maximum value of VFds)
Thus, it can be seen that (condition 1) is satisfied in all discharge cells.

  Further, since the high voltage side of the sustain pulse is the voltage Vs and the voltage applied to the data electrode 32 in the sustain period is the voltage 0 (V), the second voltage V2 is the voltage Vs (200 (V)). Further, the discharge start voltage VFsd is smaller in the discharge cell coated with the red phosphor than the other discharge cells, and its minimum value is the voltage 310 (V) in consideration of variation. The discharge start voltage VFds is smaller in discharge cells coated with red and blue phosphors than other discharge cells, and its minimum value is a voltage 190 (V) in consideration of variation. Therefore, the minimum value of the sum of the discharge start voltage VFsd and the discharge start voltage VFds is the voltage 500 (V).

As described above, (Condition 2) is (V2−V3) <(VFds + VFsd). And
(Second voltage V2−third voltage V3) = Vs−Va = (200 + 280) (V)
And
Minimum value of (VFds + VFsd) = 500 (V)
Therefore, 480 (V) <500 (V). That is,
The minimum value of (second voltage V2−third voltage V3) <(VFds + VFsd) is satisfied, and it is understood that (condition 2) is satisfied in all discharge cells.

  Further, as apparent from the above voltage, a voltage lower than the low voltage side voltage Va of the scan pulse is applied to the scan electrode 22 by applying a voltage not lower than the low voltage side voltage Va of the scan pulse and not higher than the high voltage side voltage Vs of the sustain pulse. Alternatively, a voltage exceeding the high voltage Vs of the sustain pulse is not applied. Therefore, the discharge cells that have not performed the address discharge do not emit light.

  As apparent from the above voltage, when the voltage Va is set low so as to satisfy (Condition 1), the absolute value | Va | of the low-voltage side voltage Va of the scan pulse is the absolute value of the high-voltage side voltage Vs of the sustain pulse. It becomes larger than the value | Vs |.

  Thus, in the present embodiment, the drive voltage waveform applied to each electrode, particularly the voltage Va of the scan pulse is set so as to satisfy (Condition 1) and (Condition 2). By doing so, the write operation can be stably generated without using the forced initialization operation. The reason is considered as follows.

  First, (Condition 1) will be described. In order to generate the address discharge, it is necessary to start the discharge between the data electrode Dj and the scan electrode SCi. In order to start a discharge by applying a relatively low voltage Vd to the data electrode Dj, a voltage substantially equal to the discharge start voltage VFds is applied between the data electrode Dj and the scan electrode SCi when a scan pulse is applied to the scan electrode SCi. A sufficient wall voltage must be stored on the data electrode Dj so that it is applied in between.

  As described above, in this embodiment, the forced initialization operation is not performed. Therefore, no discharge occurs in the discharge cells displaying black. Therefore, it is difficult to actively control the wall voltage, and the wall voltage of the discharge cell displaying black tends to be indefinite. However, even in such a discharge cell, if there are a few charged particles in the discharge space, they move to each electrode so as to relax the electric field inside the discharge space and adhere to the wall of the discharge cell. To accumulate wall voltage.

  The wall voltage accumulated in this way will be described. In the sustain period, a large amount of charged particles are generated in the discharge cell that generates the sustain discharge. For this reason, it is considered that a small amount of charged particles are supplied to the space inside the discharge cell that displays black without generating a sustain discharge by diffusing into the peripheral discharge cells. In the discharge cell displaying black, the wall voltage is slowly accumulated so as to alleviate the potential difference between the electrodes by the voltage applied to each of scan electrode SCi, sustain electrode SUi, and data electrode Dj. At this time, if the voltage at which the wall voltage is asymptotic (finally settled) is defined as the neglected wall voltage, the neglected wall voltage when the sustain pulse is alternately applied to the scan electrode SCi and the sustain electrode SUi is It is an intermediate voltage between the high voltage and the low voltage. Actually, since the drive voltage waveform other than the sustain pulse is also applied to the discharge cell, it is considered that the neglected wall voltage of each discharge cell is substantially close to the low-voltage side voltage of the sustain pulse.

  In addition, the neglected wall voltage is greatly affected by the charging characteristics of the phosphor applied inside the discharge cell. In this embodiment, the charging characteristics of the phosphor are +20 (μC / g) for the red phosphor, −30 (μC / g) for the green phosphor, and +10 (μC / g) for the blue phosphor, respectively. Since only the green phosphor is charged to a negative potential, the neglected wall voltage is lower than that of the red and blue phosphors.

  Next, the voltage inside the discharge cell in the address period will be described. On the data electrode Dj of the discharge cell displaying black, the wall voltage gradually accumulates toward the low voltage side voltage of the sustain pulse or the neglected wall voltage close thereto. On the other hand, the voltage Va of the scan pulse in the present embodiment is a voltage that satisfies (Condition 1). Therefore, a wall voltage sufficient to generate the address discharge is accumulated on the data electrode Dj, and the address discharge can be generated without performing any forced initialization operation.

  Further, the wall voltage of the discharge cell displaying black gradually approaches the left wall voltage. When the voltage obtained by adding the wall voltage to the voltage between the “data electrode 32 and the scan electrode 22” approaches the discharge start voltage in the erasing period, dark current (current that flows in a state where no discharge occurs) flows, and the wall on the data electrode Dj Reduce voltage. The dark current that flows at this time plays a role of priming particles that help to generate the address discharge. Therefore, it is considered that even a discharge cell displaying black can generate a stable address discharge without causing a large discharge delay.

  As described above, in this embodiment, by setting the driving voltage applied to each electrode so as to satisfy (Condition 1), the voltage Va of the scan pulse is particularly set low so as to satisfy (Condition 1). Thus, the wall voltage necessary for the address discharge can be accumulated in the discharge cell without performing the forced initialization operation, and priming particles that stabilize the address discharge can be generated.

  Next, (Condition 2) will be described. If the voltage Va of the scan pulse is too low, a discharge occurs regardless of whether or not the address operation is performed when the sustain pulse voltage Vs is applied to the scan electrode SCn in the sustain period, and an image cannot be displayed. In order to suppress this erroneous discharge, each voltage must be set so that the voltage between the “data electrode 32 and the scan electrode 22” becomes equal to or lower than the discharge start voltage VFsd when the sustain pulse voltage Vs is applied. I must. This condition is (Condition 2).

  Thus, in the present embodiment, the drive voltage waveform is set so as to satisfy (Condition 1) and (Condition 2) in all the discharge cells. Therefore, the write operation can be stably generated even if the forced initialization operation is omitted. As a result, it is possible to display an image without causing light emission not related to gradation display. That is, according to the present embodiment, a stable writing operation can be performed without performing a forced initialization operation, black luminance can be suppressed, and an image with high contrast can be displayed on the panel 10.

  In the present embodiment, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, and voltage is applied to data electrode D1 through data electrode Dm in the sustain period of subfield SF1, which is the second type subfield. 0 (V) is applied, and an upward ramp waveform voltage L1 that rises from voltage 0 (V) to voltage Vs is applied to scan electrode SC1 through scan electrode SCn. Then, after the voltage applied to scan electrode SC1 through scan electrode SCn rises to voltage Vs, voltage Vs is further applied for a certain period. Subsequently, voltage 0 (V) is continuously applied to sustain electrode SU1 through sustain electrode SUn, voltage Vd is applied to data electrode D1 through data electrode Dm, and voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn. ) To the voltage Vg, a downward ramp waveform voltage L2 is applied. Thereby, a weak sustain discharge can be generated as compared with the sustain discharge by the sustain pulse.

  Further, in the present embodiment, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn in the address period. That is, the voltage applied to sustain electrode SU1 through sustain electrode SUn in the second type subfield address period is lower than the voltage applied to sustain electrode SU1 through sustain electrode SUn in the first type subfield address period. . As a result, the discharge generated between data electrode Dk and scan electrode SC1 does not extend to sustain electrode SU1, and the luminance of light emission associated with the address discharge can be suppressed.

  With these driving operations, the luminance displayed in the subfield SF1 can be suppressed lower than the subfield having the luminance weight “1”. In the present embodiment, the luminance displayed by subfield SF1 is about ¼ of the luminance displayed by the subfield in which the sustain pulse is applied to each electrode of display electrode pair 24 once.

  In addition, the discharge start voltage VFsd, the discharge start voltage VFds, and the wall voltage can be easily measured by, for example, the method described below.

  FIG. 5 is a diagram illustrating an example of a method for simply measuring the discharge start voltage.

  First, an operation for erasing wall charges is performed. Specifically, as shown in the wall charge erasing period in FIG. 5, a pulse voltage Vers sufficiently higher than the expected discharge start voltage is alternately applied between the electrodes to be measured, for example, the data electrode 32 and the scan electrode 22. Apply to. Next, the discharge start is observed. Specifically, as shown in the measurement period of FIG. 5, a pulsed voltage Vmsr lower than the expected discharge start voltage is applied to one electrode (for example, the data electrode 32). Then, the light emission accompanying the discharge at that time is detected by using a light detection sensor such as a photomultiplier.

  When no light emission is observed, no discharge has occurred, so after performing the operation to erase the wall charge again during the wall charge elimination period, the pulse whose absolute value of the voltage was slightly increased from the previous time during the measurement period Is applied to the same electrode (for example, the data electrode 32) to observe light emission.

  This operation is repeated until luminescence is observed. Thus, the absolute value of the minimum voltage Vmsr in which light emission is observed in the measurement period is the discharge start voltage. At this time, if the voltage Vmsr applied in the measurement period is a positive voltage, the discharge start voltage VFds of the discharge with the data electrode 32 as the anode and the scan electrode 22 as the cathode can be measured. Further, when the voltage Vmsr applied in the measurement period is a negative voltage, the discharge start voltage VFsd of the discharge having the data electrode 32 as a cathode and the scan electrode 22 as an anode can be measured.

  If the discharge start voltage is known, the voltage at which discharge starts is measured for the discharge cell in which the wall voltage is accumulated, and the wall voltage can be known as the difference between the voltage value and the discharge start voltage measured in advance. .

  Alternatively, the discharge start voltage VFsd, the discharge start voltage VFds, and the wall voltage can be calculated according to IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-24, NO. 7, JULY, 1977 “Measurement of a Plasma in the AC Plasma Display panel Using RF Capacitance and Microwave Techniques” and the like.

  Next, a drive circuit for driving the panel 10 will be described. FIG. 6 is a circuit block diagram of plasma display device 1 in accordance with the first exemplary embodiment of the present invention.

  The plasma display apparatus 1 uses a panel 10 having a plurality of discharge cells each having a scan electrode 22, a sustain electrode 23, and a data electrode 32, and a plurality of subfields each having an address period, a sustain period, and an erase period. And a drive circuit that generates the drive voltage waveform shown in FIG. 3 and applies it to each electrode of the panel 10 to drive the panel 10.

  The drive circuit includes an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, a predetermined image display time detection circuit 46, a brightness detection circuit 47, and each circuit block. Is provided with a power supply circuit (not shown) for supplying the necessary power.

  The image signal processing circuit 41 assigns a gradation value to each discharge cell based on the input image signal. Then, each gradation value is converted into image data indicating light emission / non-light emission for each subfield. The image signal includes, for example, a red primary color signal R, a green primary color signal G, and a blue primary color signal B. The image signal processing circuit 41 separates the luminance signal when the image signal includes the luminance signal, and uses a generally known method when the image signal includes only the primary color signal. Then, a luminance signal is generated from the primary color signal, and the luminance signal is supplied to the predetermined image display time detection circuit 46.

  The predetermined image display time detection circuit 46 measures the length of time that an image in which the entire screen is black (hereinafter also referred to as “black image”) is displayed on the panel 10 continuously. To do. That is, in the present embodiment, the predetermined image is a “black image” in which the entire screen is black. Then, the measured time is compared with a preset black image display time threshold value, and the comparison result is output as a black image display time detection result and supplied to the timing generation circuit 45. Details of the predetermined image display time detection circuit 46 will be described later.

  The brightness detection circuit 47 includes an optical semiconductor element (Opto Semiconductor Elements: for example, a semiconductor element such as a phototransistor or a photodiode) that is generally used for brightness detection, and is provided around the plasma display device 1. Detect brightness. Then, the detected brightness is output to the timing generation circuit 45.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal, the vertical synchronization signal, the output from the predetermined image display time detection circuit 46, and the output from the brightness detection circuit 47. appear. Then, the generated timing signal is supplied to each circuit block. Note that the timing generation circuit 45 includes a comparison circuit that compares brightness information detected by the brightness detection circuit 47 with preset first and second illuminances. Then, the timing generation circuit 45 supplies the comparison result (first illuminance comparison result) between the brightness detected by the brightness detection circuit 47 and the first illuminance (first illuminance comparison result) to the predetermined image display time detection circuit 46. Further, the timing generation circuit 45 generates a timing signal for forcibly lighting the second type subfield based on the comparison result in the comparison circuit, and supplies the timing signal to the data electrode driving circuit 42.

  The data electrode drive circuit 42 converts the image data for each subfield into address pulses corresponding to the data electrodes D1 to Dm. Based on the timing signal supplied from the timing generation circuit 45, an address pulse is applied to each of the data electrodes D1 to Dm.

  Scan electrode drive circuit 43 includes a sustain pulse generation circuit and a scan pulse generation circuit. The sustain pulse generating circuit generates a sustain pulse to be applied to scan electrode SC1 through scan electrode SCn during the sustain period. The scan pulse generation circuit includes a plurality of scan electrode driving ICs (scan ICs), and generates scan pulses to be applied to scan electrode SC1 through scan electrode SCn in the address period. Scan electrode drive circuit 43 generates the above-described drive voltage waveform based on the timing signal supplied from timing generation circuit 45, and applies it to each of scan electrode SC1 through scan electrode SCn.

  Sustain electrode drive circuit 44 includes a sustain pulse generation circuit, generates the drive voltage waveform described above based on the timing signal supplied from timing generation circuit 45, and applies it to sustain electrode SU1 through sustain electrode SUn.

  FIG. 7 is a circuit block diagram of the predetermined image display time detection circuit 46 according to Embodiment 1 of the present invention.

  The predetermined image display time detection circuit 46 includes an APL detection circuit 55, a comparison circuit 56, a timer circuit 57, and a comparison circuit 58.

  The APL detection circuit 55 detects an average luminance level (hereinafter referred to as “APL”; APL: Average Picture Level) from the luminance signal output from the image signal processing circuit 41. The APL detection circuit 55 cumulatively adds the magnitude of the luminance signal assigned to each pixel over one screen of pixels (for example, 1920 × 1080 pixels). Then, the addition result is divided by the number of pixels for one screen and further divided by the maximum value of the luminance signal to normalize. Therefore, the value output from the APL detection circuit 55 is 0% for a black image and 100% for an image in which the entire screen is white.

  The comparison circuit 56 compares the APL detected by the APL detection circuit 55 with a preset black image threshold value. Then, the comparison result is output to the timer circuit 57. In the present embodiment, this black image threshold value is set to 0%. Therefore, the signal output from the comparison circuit 56 is a signal indicating whether the image displayed on the panel 10 is a black image (APL 0% image) or not.

  The black image determination method is not limited to the above-described method. For example, the above-described normalization may not be performed when detecting APL, or the number of discharge cells to be lit for each subfield may be obtained using image data instead of the luminance signal. In that case, an image in which the sum of the number of discharge cells lit in one field is a predetermined value or less (for example, 100 or less) may be a black image.

  The timer circuit 57 performs APL detection based on the output from the comparison circuit 56 and the first illuminance comparison result (the comparison result between the brightness detected by the brightness detection circuit 47 and the first illuminance) output from the timing generation circuit 45. The time during which the APL detected by the circuit 55 is continuously below the black image threshold is measured. That is, the timer circuit 57 determines how long a black image is continuously displayed on the panel 10 when the brightness detected by the brightness detection circuit 47 is less than the first illuminance. Measure the black image continuous display time. Then, a signal representing the result is output to the comparison circuit 58.

  The comparison circuit 58 compares the black image continuous display time output from the timer circuit 57 with the black image display time threshold value. Then, the comparison result is output to the timing generation circuit 45 as a black image display time detection result. In the present embodiment, this black image display time threshold is set to “60 minutes”. That is, the output of the comparison circuit 58 becomes a signal indicating whether or not the continuous display time of the black image has reached 60 minutes, and this signal becomes the output of the predetermined image display time detection circuit 46.

  That is, the predetermined image display time detection circuit 46 detects APL based on the image signal, and determines whether the image displayed on the panel 10 is a black image by comparing the APL with the black image threshold value. Then, when the brightness detected by the brightness detection circuit 47 is less than the first illuminance, the length of time that the black image is continuously displayed on the panel 10 is measured, and the measurement result is the black image display time. It is detected whether the threshold value has been reached, and the detection result is output to the timing generation circuit 45.

  In addition, the specific numerical value of each threshold value mentioned above is only an example in the present embodiment, and the present invention is not limited to these numerical values. Each threshold value is desirably set optimally according to the characteristics of the panel and the specifications of the plasma display device.

  In the present embodiment, as described above, the timing generation circuit 45 compares the brightness detected by the brightness detection circuit 47 with the first illuminance and the second illuminance, and drives the panel 10 based on the comparison result. .

  If the brightness detected by the brightness detection circuit 47 is less than the first illuminance (for example, 30 lux: a brightness that can be easily read by characters written on the book), the timing generation circuit 45 is predetermined. Based on the black image continuous display time measured in the image display time detection circuit 46, lighting and non-lighting of the second type subfield (subfield SF1 in this embodiment) are controlled.

  As described above, if the brightness detected by the brightness detection circuit 47 is less than the first illuminance, the timing generation circuit 45 supplies a signal indicating that to the predetermined image display time detection circuit 46. The predetermined image display time detection circuit 46 measures the black image continuous display time only when the brightness detected by the brightness detection circuit 47 is less than the first illuminance, and the black image continuous display time and the black image display time threshold. Compare the value (eg 60 minutes). Then, the comparison result is supplied to the timing generation circuit 45, and the timing generation circuit 45 generates a timing signal based on the comparison result supplied from the predetermined image display time detection circuit 46.

  The timing generation circuit 45 forces the second type subfield (subfield SF1 in the present embodiment) until the black image continuous display time reaches a black image display time threshold (for example, 60 minutes). The timing signal is generated so as to control the lighting and non-lighting of the second type subfield (subfield SF1 in the present embodiment) based on the image signal.

  When the black image continuous display time reaches a black image display time threshold (for example, 60 minutes), the timing generation circuit 45 forcibly turns on the discharge cell in the second type subfield (hereinafter referred to as “discharge cell”). A timing signal including image data (described later) for forced lighting is generated and supplied to the data electrode driving circuit 42 so that the forced lighting is also referred to as “forced lighting”. The data electrode drive circuit 42 receives the timing signal and applies an address pulse so that an address discharge is generated in the discharge cell in the second type subfield (subfield SF1) regardless of the image data from the image signal processing circuit 41. It is generated and applied to the data electrode 32. This forcibly turns on the discharge cell in the second type subfield.

  In the present embodiment, when the brightness detected by the brightness detection circuit 47 is less than the first illuminance, when the black image continuous display time reaches the black image display time threshold, the panel 10 It is determined that the image displayed on the screen satisfies a predetermined condition.

  Details of these operations will be described below.

  FIG. 8 shows the time when the image signal of the black image is continuously input when the brightness detected by the brightness detection circuit 47 according to Embodiment 1 of the present invention is less than the first illuminance, and the second type subfield. It is a figure which shows the relationship with forced lighting. In FIG. 8, the vertical axis represents the lighting rate when the discharge cells are forcibly turned on in the second type subfield, and the horizontal axis represents the time during which the black image signal is continuously input. Hereinafter, for example, when the discharge cell is turned on in the second type subfield, it is expressed as “turn on the second type subfield”.

  When the brightness detected by the brightness detection circuit 47 is less than the first illuminance, as shown in FIG. 8, in the present embodiment, the black image continuous display time is a black image display time threshold (for example, 60 The second type subfield (in this embodiment, the subfield SF1) is not forcibly lit until the second type subfield (in this embodiment, in this embodiment) is reached. The lighting / non-lighting of the subfield SF1) is controlled.

  When the black image continuous display time reaches the black image display time threshold at time t1, the second type subfield (subfield SF1 in the present embodiment) is forcibly lit at a predetermined lighting rate.

  Then, during the period from time t1 to time t2 (for example, 1 minute), the second type subfield is forcibly continuously lit at a predetermined lighting rate (hereinafter, this period is referred to as “subfield forced lighting period”). After the time t2 when the subfield forced lighting period ends, the forced lighting of the second type subfield ends and an image based on the image signal is displayed on the panel 10. If the image signal is an image signal of a black image, a black image whose whole screen is black is displayed again.

  In FIG. 8, at time t1, the lighting rate of the second type subfield increases from 0% to a predetermined lighting rate, and at time t2, the lighting rate of the second type subfield decreases from the predetermined lighting rate to 0%. Although a configuration is shown, the present invention is not limited to this configuration. For example, the configuration may be such that the lighting rate of the second type subfield gradually increases from 0% to a predetermined lighting rate over a predetermined time (for example, 5 seconds, not shown) at time t1. Alternatively, even at a time t2 (1), the lighting rate of the second type subfield gradually decreases from the predetermined lighting rate to 0% over a predetermined time (for example, 5 seconds, not shown). Good.

  During the subfield forced lighting period, the discharge cells are forcibly lit in the second type subfield having the smallest luminance weight, and the first type subfield having a larger luminance weight than the second type subfield ( In the present embodiment, the discharge cells are not forcibly turned on in the subfields except for subfield SF1.

  The timing generation circuit 45 drives the panel 10 as follows when the brightness detected by the brightness detection circuit 47 is equal to or higher than the first illuminance.

  When the brightness detected by the brightness detection circuit 47 is greater than or equal to the first illuminance, the timing generation circuit 45 performs image data (for forced lighting) so that the discharge cells are forcibly lit in the second type subfield. A timing signal including (described later) is generated and supplied to the data electrode driving circuit 42. The data electrode drive circuit 42 receives the timing signal and applies an address pulse so that an address discharge is generated in the discharge cell in the second type subfield (subfield SF1) regardless of the image data from the image signal processing circuit 41. It is generated and applied to the data electrode 32. As a result, the discharge cells are forcibly lit in the second type subfield.

  Details of this operation will be described below.

  FIG. 9 is a diagram showing the relationship between the brightness around the plasma display device 1 and the second-type subfield forced lighting in the first embodiment of the present invention. In FIG. 9, the vertical axis represents the lighting rate when the discharge cells are forcibly turned on in the second type subfield, and the horizontal axis represents the brightness detected by the brightness detection circuit 47, that is, the plasma display device. 1 represents the brightness of the surrounding area.

  If the brightness detected by the brightness detection circuit 47 is greater than or equal to the second illuminance (for example, 300 lux: general living room brightness) greater than the first illuminance, the timing generation circuit 45 is shown in FIG. As described above, the second type subfield (in this embodiment, subfield SF1) is forcibly lit at a predetermined lighting rate (for example, 50%) set in advance.

  If the brightness detected by the brightness detection circuit 47 is greater than or equal to the first illuminance and less than the second illuminance, the lighting rate according to the detected brightness, that is, in the range of the lighting rate from 0% to a predetermined lighting rate. The lighting rate is increased as the detected brightness becomes brighter, and the second type subfield (subfield SF1 in the present embodiment) is forcibly lit.

  In the present embodiment, when the brightness detected by the brightness detection circuit 47 is greater than or equal to the first illuminance, and when the brightness detected by the brightness detection circuit 47 is less than the first illuminance, the black image continuous display time is The reason why the second type subfield is forcibly lit during the subfield forced lighting period after the black image display time threshold (for example, 60 minutes) is reached is as follows.

  In this embodiment, as described above, the forced initialization operation is not performed. Therefore, when a black image in which the entire screen is black is displayed on the panel 10, no discharge is generated in the discharge cells.

  If the continuous display time of the black image is short, there is no particular problem. However, if the continuous display time of the black image is long (for example, 120 minutes or more), the time during which no discharge occurs in the discharge cell is long. Wall charges and priming particles are greatly reduced. For this reason, when switching from a black image to a normal image (an image in which light emission occurs in the discharge cells), the address discharge becomes unstable for a short period of time (for example, several fields), and the image display quality during that time becomes unstable. May deteriorate.

  However, if a discharge is generated in the discharge cell before the wall charge and priming particles in the discharge cell are greatly reduced, the wall charge and priming particles are recovered, and this phenomenon can be prevented from occurring.

  Then, the inventor of the present application has confirmed by experiments that the effect of stably generating the address discharge can be obtained only by forcibly lighting the second type subfield without lighting the first type subfield.

  Further, as described above, the light emission luminance in the second type subfield is weak and lower than the light emission luminance in the subfield having the luminance weight “1”. Therefore, if the surroundings of the plasma display device 1 have a certain level of brightness, even if only the second type subfield is forcibly turned on, the change in black luminance is difficult for the user to recognize.

  Therefore, in the present embodiment, if the brightness detected by the brightness detection circuit 47 is bright enough to determine that the surroundings of the plasma display device 1 are sufficiently bright, that is, the second illuminance or higher, the second type sub The field is forcibly lit at a predetermined lighting rate determined in advance. When the brightness detected by the brightness detection circuit 47 is equal to or higher than the first illuminance and lower than the second illuminance, the lighting rate increases as the detected brightness becomes brighter in the range of the lighting rate from 0% to the predetermined lighting rate. Then, the second type subfield is forcibly lit.

  As a result, when the surroundings of the plasma display device 1 are sufficiently bright and it is difficult for the user to recognize a change in black luminance, the second type subfield is forcibly lit to reduce wall charges and priming particles in the discharge cell. Can be prevented. Therefore, even when the continuous display time of the black image becomes long, the wall charge and priming particles in the discharge cell are prevented from decreasing, so that the address discharge is stabilized when switching from the black image to the normal image. It is possible to prevent the image display quality from deteriorating.

  In the present embodiment, when the brightness detected by the brightness detection circuit 47 is between the first illuminance and the second illuminance, the lighting rate of the second type subfield is changed according to the detected brightness. The reason is that, as the brightness around the plasma display device 1 becomes darker, the change in black brightness is more easily recognized by the user, so the light emission brightness when forcibly lighting the second type subfield is set to the ambient brightness. This is because it is desirable to make it lower accordingly.

  On the other hand, if the surroundings of the plasma display device 1 are sufficiently dark, there is a possibility that a change in black luminance may be recognized by the user due to light emission generated by forcibly lighting the second type subfield.

  Therefore, in the present embodiment, when the brightness detected by the brightness detection circuit 47 is less than the first illuminance, which is the brightness at which the surroundings of the plasma display device 1 can be determined to be sufficiently dark, the black image continuous display time After reaching the black image display time threshold (for example, 60 minutes), a subfield forced lighting period is provided. That is, when it is determined that the continuous display time of the black image has become longer, specifically, at the time t1 when the black image continuous display time reaches the black image display time threshold (for example, 60 minutes), the second type sub It is assumed that the field is forcibly lit, the period from time t1 to time t2 is a subfield forced lighting period, and the second type subfield is continuously forcibly lit during that period.

  This makes it possible to recover the reduced wall charge and priming particles in the discharge cells when the continuous display time of the black image becomes longer, and to stabilize the address discharge when switching from the black image to the normal image. It is possible to prevent the deterioration of the image display quality.

  The discharge cells are forcibly lit in the second type subfield having the smallest luminance weight, and the first type subfield having a luminance weight larger than that of the second type subfield (in this embodiment, the subfield). In the sub-field except SF1), the discharge cell is not forcibly lit. The second type subfield has lower emission luminance than any of the first type subfields. Therefore, for example, in the subfield forced lighting period, only the second type subfield is forcibly lit, so that the light emission luminance of the panel 10 in the subfield forced lighting period is higher than when the first type subfield is lit. Can be kept low. Accordingly, when the black image is displayed and switched to the subfield forced lighting period, the change in black luminance can be reduced, and the change in luminance can be made difficult for the viewer to recognize.

  In this embodiment, not all the discharge cells in the image display area of panel 10 are lit, but the discharge cells are lit at a predetermined lighting rate during the subfield forced lighting period. For example, by setting the predetermined lighting rate to 50%, the discharge cells that are forcibly lit in the second type subfield and the discharge cells that are not lit can be mixed in half. Thereby, it is possible to further suppress the increase in black luminance and further reduce the change in black luminance when the black image is displayed to switch to the subfield forced lighting period.

  When the second-type subfield is forcibly lit in the subfield forced lighting period or the like, in the image display area of the panel 10, a discharge cell (lighted cell) that is lit and a discharge cell that is not lit (non-lit) It is desirable that the area where the lighted cell) occurs is not affected. For example, when the second type subfield is forcibly lit at a predetermined lighting rate of 50%, the lit cell and the non-lit cell are adjacent to each other (lit cell, non-lit cell, lit in both row and column directions) Cell, non-lighted cell,...), And it is desirable to generate the write pulse so that the lighted cell and the non-lighted cell alternate for each field. This also applies to other lighting rates, and the lighted cells are generated in a distributed manner so that the region where the lighted cells are generated and the region where the non-lighted cells are generated are not affected. It is desirable to change the lighting cells for each field so that all the discharge cells in the image display area in the panel 10 are uniformly lit during

  Note that the number of times one discharge cell emits light per unit time (for example, 1 second) decreases as the lighting rate decreases. When the second type subfield is forcibly lit, the number of times one discharge cell emits light per unit time (for example, 1 second) is, for example, half when the lighting rate is 50% when the lighting rate is 25%, When the lighting rate is 10%, it is one fifth of that when the lighting rate is 50%. Therefore, if the lighting rate when the second type subfield is forcibly lit decreases, the emission luminance decreases accordingly, and the black luminance also decreases. On the other hand, the effect of replenishing wall charges and priming particles in the discharge cell is reduced as the number of occurrences of the discharge is reduced. However, as described above, the address discharge may become unstable when switching from a black image to a normal image when the black image is displayed continuously for a long time (for example, 120 minutes or more). is there. Therefore, even if the lighting rate is low, a sufficient number of discharges are generated by forcibly lighting the second type subfield during the continuous display of black images for such a long time. Charges and priming particles can be sufficiently replenished.

  On the other hand, if the continuous display time of the black image is short, the wall charges and priming particles are less reduced, so the lighting rate when the second type subfield is forcibly lit is low and the number of discharges generated in the discharge cells Even if there is little, there is little possibility that the address discharge becomes unstable when switching from a black image to a normal image.

  When the brightness detected by the brightness detection circuit 47 is equal to or higher than the first illuminance, the above-described “lighting rate when the second type subfield is forcibly turned on” is the panel 10 based on the image signal. When an image is displayed on the sub-field (the second type sub-field in the present embodiment) that is the target of forced lighting and in which the sub-field with the smallest luminance weight is not illuminated, the lighting rate (forced with respect to the number of discharge cells) The ratio of the number of discharge cells to be lit). For example, when an image in which the second type subfield is not lit in all the discharge cells in the image display area is displayed on the panel 10, if the lighting rate of forced lighting is 50%, the discharge of 50% in the image display area In the cell, the second type subfield is forcibly lit. Alternatively, when an image in which the second type subfield is not turned on in the discharge cells of 50% of the image display area is displayed on the panel 10, the second type subfield is not turned on if the lighting rate of forced lighting is 50%. The second type subfield is forcibly lit in 50% of the discharge cells in the area to be lit (25% of the discharge cells as viewed from the entire image display area).

  Note that the specific numerical values given as the first illuminance, the second illuminance, the predetermined lighting rate, and the black image display time threshold in the present embodiment are merely examples in the present embodiment, and the present invention is not limited to this. It is not limited to these numerical values. For example, the magnitude of the second illuminance is set to a value that is sufficiently larger than the above-described value, and the predetermined lighting rate when forcibly lighting the second type subfield is set to 100%, and the detected brightness is You may make it forcibly light all the discharge cells in the image display area of the panel 10 when it is 2nd illumination intensity or more. Alternatively, the first illuminance is set to 0 lux, and the second type subfield is forcibly set at a lighting rate according to the detected brightness regardless of the brightness of the surroundings of the plasma display device 1. It may be turned on. It is desirable to set optimally how to set the first illuminance, the second illuminance, the predetermined lighting rate, and the black image display time threshold based on the characteristics of the panel and the specifications of the plasma display device.

  In the present embodiment, forcible lighting is performed as follows, for example. For example, one field is composed of nine subfields (SF1, SF2,..., SF9), and (1/2, 1, 2, 4, 8, 16, 32, 64, 128) is included in each subfield. In the timing generation circuit 45, the image data (forced) (1, 0, 0, 0, 0, 0, 0, 0, 0) is only applied to the discharge cells that are forcibly lit. Image data for lighting) is generated and transmitted to the data electrode drive circuit 42. The data electrode drive circuit 42 performs a logical OR operation on the image data based on the image signal transmitted from the image signal processing circuit 41 and the image data for forced lighting transmitted from the timing generation circuit 45. The logical sum operation is a logical operation that outputs “0” only when two input values are both “0”, and outputs “1” otherwise. For example, if the image data transmitted from the image signal processing circuit 41 is (0, 0, 0, 0, 0, 0, 0, 0, 0), the result of the above OR operation is (1, 0 , 0, 0, 0, 0, 0, 0, 0). Alternatively, if the image data transmitted from the image signal processing circuit 41 is (0, 0, 0, 1, 1, 1, 0, 0, 0), the result of the above OR operation is (1, 0 , 0, 1, 1, 1, 0, 0, 0). Based on the result of the logical sum operation, the image signal processing circuit 41 generates a write pulse in a subfield where the image data is “1” and performs a write operation. In the above example, if the image data is (1, 0, 0, 0, 0, 0, 0, 0, 0), the write operation is performed in the subfield SF1, and the write operation is performed in the other subfields. Absent. If the image data is (1, 0, 0, 1, 1, 1, 0, 0, 0), the write operation is performed in the subfield SF1 and the subfields SF4 to SF6, and the other subfields. Then, the write operation is not performed. Thereby, forced lighting can be performed in the subfield SF1, which is the second type subfield.

  If the image data transmitted from the image signal processing circuit 41 is data that lights up in the subfield with the smallest luminance weight, the image data is before and after the above logical sum operation. It does not change. For example, if the image data transmitted from the image signal processing circuit 41 is (1, 0, 0, 1, 1, 1, 0, 0, 0), the result of the above OR operation is (1, 0, 0, 1, 1, 1, 0, 0, 0), and there is no change in the image data. Therefore, for example, when forcible lighting is performed so that the lighting rate is 50%, the timing generation circuit 45 performs (1, 0, 0, 0, 0, 0, 0) on 50% of the discharge cells in the image display area. , 0, 0) may be generated and transmitted to the data electrode driving circuit 42. Thereby, the lighting rate of forced lighting in the area where the subfield having the smallest luminance weight is not lighted when displaying an image on the panel 10 based on the image signal can be set to 50%.

  Note that the first illuminance and the second illuminance may be set to the same numerical value. In this case, if the detected brightness is less than the first illuminance, the second type subfield is forcibly lit according to the continuous display time of the black image. If the detected brightness is equal to or greater than the first illuminance, the second type subfield is forcibly lit at a predetermined lighting rate determined in advance.

  In the sub-field forced lighting period, the predetermined lighting rate may be set to 100%, and all the discharge cells in the image display area of the panel 10 may be forcibly lighted in the second type sub-field. In this case, the black luminance increases as compared with the case where the predetermined lighting rate is 50%, but the length of the subfield forced lighting period can be halved. Alternatively, if the predetermined lighting rate is 25%, the length of the subfield forced lighting period is doubled compared to when the predetermined lighting rate is 50%, but the black luminance can be halved.

  How to set the length of the subfield forced lighting period and the predetermined lighting rate during the subfield forced lighting period, respectively, the brightness of the black luminance of the subfield forced lighting period and the length of the subfield forced lighting period, It is desirable to set optimally based on the characteristics of the panel and the specifications of the plasma display device.

  In the present embodiment, when the second type subfield is forcibly turned on and the image signal of the normal image is input to the image signal processing circuit 41, the second type subfield is forcibly turned on. Is immediately interrupted, and an image based on the image signal is displayed on the panel 10.

  The timer circuit 57 resets the measurement time until the subfield forced lighting period starts (or ends), and newly measures the black image continuous display time after the subfield forced lighting period ends. Shall begin to do. Therefore, for example, in a plasma display device in which the black image display time threshold is set to 60 minutes and the subfield forced lighting period is set to 1 minute, the time for continuously displaying black images is 2 hours 2 If the minute is exceeded, the subfield forced lighting period occurs twice in the meantime.

  FIG. 10 is a circuit diagram of scan electrode drive circuit 43 of plasma display device 1 in accordance with the first exemplary embodiment of the present invention. Scan electrode drive circuit 43 includes sustain pulse generation circuit 50, ramp waveform voltage generation circuit 60, and scan pulse generation circuit 70, and operates each circuit based on a timing signal. Note that details of the timing signal are omitted in the drawings.

  Sustain pulse generation circuit 50 includes a power recovery circuit 51, a switching element Q55, a switching element Q56, and a switching element Q59. Then, sustain pulses to be applied to scan electrode SC1 through scan electrode SCn are generated. The power recovery circuit 51 recovers the power stored in the panel 10 from the panel 10 using LC resonance, and reuses the recovered power as power when driving the scan electrodes SC1 to SCn. The panel 10 is supplied again. Switching element Q55 clamps scan electrode SC1 through scan electrode SCn to voltage Vs, and switching element Q56 clamps scan electrode SC1 through scan electrode SCn to voltage 0 (V). The switching element Q59 is a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43.

  Scan pulse generation circuit 70 includes switching element Q71H1 to switching element Q71Hn, switching element Q71L1 to switching element Q71Ln, switching element Q72, a power supply for negative voltage Va, and a power supply E71 for generating voltage VC. The voltage VC is superimposed on the reference potential of the scan pulse generation circuit 70 (the potential at the node A shown in FIG. 10) to generate a voltage (Vc = VC + Va), and the scan electrode SC1 is switched while switching between the voltage Va and the voltage Vc. A scan pulse is generated by applying to scan electrode SCn. For example, if the voltage Va = −280 (V) and the voltage VC = 135 (V), the voltage Vc = −145 (V). Then, scan pulses are sequentially applied to scan electrode SC1 through scan electrode SCn at the timing shown in FIG. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 50 as it is during the sustain period. That is, the voltage at node A is output to scan electrode SC1 through scan electrode SCn.

  The ramp waveform voltage generation circuit 60 includes a Miller integration circuit 61 and a Miller integration circuit 63, and generates the ramp waveform voltage shown in FIG. Miller integrating circuit 61 includes transistor Q61, capacitor C61, and resistor R61, and applies a constant voltage to input terminal IN61 (giving a constant voltage difference between two circles shown as input terminal IN61). As a result, the rising ramp waveform voltage L3 and the rising ramp waveform voltage L1 (voltage Vs = voltage Vr) that gently rises toward the voltage Vr are generated. Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63, and applies a constant voltage to input terminal IN63 (giving a constant voltage difference between two circles shown as input terminal IN63). As a result, a downward ramp waveform voltage L4 that gradually decreases toward the voltage Vi is generated. Further, when the output voltage becomes equal to the voltage Vg, the operation of the Miller integrating circuit 63 is stopped (the voltage difference between two circles illustrated as the input terminal IN63 is set to 0 (V)), whereby the voltage Vg It is also possible to generate a downward ramp waveform voltage L2 that gradually decreases toward. The switching element Q69 is a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43.

  That is, scan electrode drive circuit 43 conducts switching element Q71L1 to switching element Q71Ln and switching element Q69 when applying upward ramp waveform voltage L3 that gradually rises to voltage Vr to scan electrode SC1 to scan electrode SCn. In this case, the Miller integrating circuit 61 is operated by applying a constant voltage to the input terminal IN61 (giving a constant voltage difference between two circles shown as the input terminal IN61). When voltage Vr and voltage Vs are set to the same voltage, ascending ramp waveform voltage L1 is applied to scan electrode SC1 through scan electrode SCn by the same operation as that for generating ascending ramp waveform voltage L3. be able to.

  When a downward ramp waveform voltage L4 that gently falls from voltage 0 (V) toward voltage Vi is applied to scan electrode SC1 through scan electrode SCn, a voltage of 0 (V) is applied to input terminal IN61 of Miller integrating circuit 61. Applied (the voltage difference between two circles shown as the input terminal IN61 is set to 0 (V)), the transistor Q61 is cut off (hereinafter referred to as “off”), the switching element Q56 is turned on, Voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn. Then, the switching element Q56 and the switching element Q69 are turned off, and a constant voltage is applied to the input terminal IN63 (giving a constant voltage difference between two circles shown as the input terminal IN63), and the Miller integrating circuit 63 To work. In addition, when the downward ramp waveform voltage L2 that gradually decreases from the voltage 0 (V) toward the voltage Vg is applied to the scan electrodes SC1 to SCn, the same operation as that for generating the downward ramp waveform voltage L4 is performed. When the output voltage becomes equal to the voltage Vg, the operation of Miller integrating circuit 63 is stopped (the voltage difference between two circles shown as input terminal IN63 is set to 0 (V)).

  In addition, these switching elements and transistors can be configured using generally known semiconductor elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the respective switching elements and transistors generated by the timing generation circuit 45.

  FIG. 11 is a circuit diagram of sustain electrode drive circuit 44 of plasma display device 1 in accordance with the first exemplary embodiment of the present invention. Sustain electrode drive circuit 44 includes sustain pulse generation circuit 80 and constant voltage generation circuit 85, and operates each circuit based on a timing signal. Note that details of the timing signal are omitted in the drawings.

  Sustain pulse generation circuit 80 includes a power recovery circuit 81, a switching element Q83, and a switching element Q84. Then, sustain pulses to be applied to sustain electrode SU1 through sustain electrode SUn are generated. The power recovery circuit 81 recovers the power stored in the panel 10 from the panel 10 using LC resonance, and reuses the recovered power as power when driving the sustain electrodes SU1 to SUn. The panel 10 is supplied again. Switching element Q83 clamps sustain electrode SU1 through sustain electrode SUn to voltage Vs, and switching element Q84 clamps sustain electrode SU1 through sustain electrode SUn to voltage 0 (V).

  Constant voltage generation circuit 85 includes switching element Q86 and switching element Q87, and applies voltage Ve to sustain electrode SU1 through sustain electrode SUn.

  In addition, these switching elements can also be comprised using generally known elements, such as MOSFET and IGBT. These switching elements are also controlled by timing signals corresponding to the respective switching elements generated by the timing generation circuit 45.

  FIG. 12 is a circuit diagram of data electrode drive circuit 42 of plasma display device 1 in accordance with the first exemplary embodiment of the present invention. Data electrode drive circuit 42 includes switching element Q91H1 to switching element Q91Hm and switching element Q91L1 to switching element Q91Lm. Then, based on the image data (details of the image data are omitted in the drawing), the switching element Q91Lj is turned on to apply the voltage 0 (V) to the data electrode Dj and the switching element Q91Hj is turned on. A voltage Vd is applied to the electrode Dj. Note that the timing signal shown in FIG. 12 includes image data for forced lighting transmitted from the timing generation circuit 45. The data electrode drive circuit 42 includes a circuit that performs a logical OR operation on the image data based on the image signal transmitted from the image signal processing circuit 41 and the image data for forced lighting transmitted from the timing generation circuit 45. However, it is omitted in FIG.

  Using such a drive circuit, the drive voltage waveform of the panel shown in FIG. 3 can be generated. However, the drive circuits shown in FIGS. 10 to 12 are examples, and the present invention is not limited to the circuit configurations of these drive circuits.

  As described above, according to the present embodiment, by generating a scan pulse that satisfies the above-described conditions in the address period and applying it to the scan electrode 22, a stable address operation without using the forced initialization operation It can be performed. As a result, it is possible to display an image with high contrast while suppressing black luminance on the panel 10.

  In addition, by providing the second type subfield capable of generating light emission that is weaker than the light emission by the sustain pulse, it is possible to reduce the luminance of the next lower gradation after black. Thereby, the gradation at the time of displaying a dark image can be improved, and image display quality can be improved.

  Also, the brightness detection circuit 47 detects the brightness around the plasma display device 1, and if the detected brightness is equal to or higher than the first illuminance, the second-type sub is selected at a lighting rate according to the detected brightness. Force the field to light up. Thereby, the address discharge can be stably generated when the black image is switched to the normal image. In the present embodiment, these enable the plasma display device 1 to display an image with high contrast and excellent gradation on the panel 10 and when switching from a black image to a normal image. In addition, it is possible to stably generate the address discharge to prevent the deterioration of the image display quality, and the image display quality of the plasma display device 1 can be improved.

  If the detected brightness is less than the first illuminance, the predetermined image display time detection circuit 46 measures the black image continuous display time, and the black image continuous display time is a black image display time threshold (for example, The second type subfield is forcibly lit during the subfield forced lighting period after reaching 60 minutes. Thereby, the address discharge can be stably generated when the black image is switched to the normal image. In the present embodiment, these enable the plasma display device 1 to display an image with high contrast and excellent gradation on the panel 10 and when switching from a black image to a normal image. In addition, it is possible to stably generate the address discharge to prevent the deterioration of the image display quality, and the image display quality of the plasma display device 1 can be improved.

  In the present embodiment, the configuration has been described in which the second type subfield is the subfield SF1, but the second type subfield may be a subfield other than the subfield SF1.

  In the present embodiment, a configuration in which one field includes a second type subfield and a plurality of first type subfields has been described. However, for example, one field is configured by only the first type subfield. Also good. In that case, the subfield with the smallest luminance weight among the first type subfields (for example, the subfield with the luminance weight “1”) is forcibly lit at the lighting rate according to the detected brightness. And

  In the present embodiment, the brightness detection circuit 47 detects the brightness around the plasma display device 1 and forcibly turns on the second-type subfield at a lighting rate corresponding to the detected brightness. However, for example, the second type subfield and the subfield having the smallest luminance weight among the first type subfields (in this embodiment, the subfield SF2 having the luminance weight “1”) are detected. It can also be set as the structure lighted forcibly with the lighting rate according to the brightness.

  It should be noted that the specific numerical values and the like shown in the first embodiment are merely examples, and are desirably set optimally according to the panel characteristics, the specifications of the plasma display device, and the like.

(Embodiment 2)
In the first embodiment, the “black image” is detected as a predetermined image in the predetermined image display time detection circuit 46, and when the brightness detected by the brightness detection circuit 47 is less than the first illuminance, The black image continuous display time, which is the display time, is measured, and when the black image continuous display time reaches a black image display time threshold (for example, 60 minutes), the image displayed on the panel 10 satisfies a predetermined condition. The configuration for determining when the time has passed has been described. However, the present invention is not limited to this configuration.

  FIG. 13 is a circuit block diagram of plasma display device 2 in the second exemplary embodiment of the present invention.

  The plasma display device 2 includes a panel 10 and a drive circuit that drives the panel 10. The drive circuit includes an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, a predetermined image display time detection circuit 49, a brightness detection circuit 47, and each circuit block. Is provided with a power supply circuit (not shown) for supplying the necessary power. In the present embodiment, the same reference numerals are given to circuit blocks that perform the same operations as the circuit blocks included in the plasma display device 1 described in the first embodiment, and description thereof is omitted.

  The plasma display device 2 shown in the present embodiment has substantially the same configuration as the plasma display device 1 shown in the first embodiment, but the plasma display device 2 is different from the plasma display device 1 in that a predetermined image display time is detected. The configuration of the circuit 49 is different from the predetermined image display time detection circuit 46.

  FIG. 14 is a circuit block diagram of the predetermined image display time detection circuit 49 according to Embodiment 2 of the present invention. The predetermined image display time detection circuit 49 includes a non-lighting determination circuit 91, a non-lighting continuous time detection circuit 92, a predetermined cell number counting circuit 93, and a comparison circuit 94.

  Based on the image data, the non-lighting determination circuit 91 determines, for each discharge cell, whether or not the discharge cell is a non-lighting cell that does not perform an address operation once in one field period. For example, if one piece of image data is all “0”, it can be determined that the discharge cell to which the image data is assigned is a non-lighting cell that does not perform an addressing operation in the field.

  The non-lighting continuous time detection circuit 92 includes a determination result in the non-lighting determination circuit 91 and a first illuminance comparison result output from the timing generation circuit 45 (a comparison result between the brightness detected by the brightness detection circuit 47 and the first illuminance). ), When the brightness detected by the brightness detection circuit 47 is lower than the first illuminance, the length of time during which a field in which no address operation is performed continuously occurs for each discharge cell is not lit continuously. Measure as time. Then, for each discharge cell, the measured non-lighting continuous time is compared with a preset non-lighting time threshold (for example, 60 minutes), and whether the non-lighting continuous time is equal to or greater than the non-lighting time threshold. Determine if.

  The predetermined cell number counting circuit 93 counts the number of discharge cells whose non-lighting continuous time is equal to or greater than the non-lighting time threshold based on the detection result of the non-lighting continuous time detection circuit 92.

  The comparison circuit 94 compares the counting result in the predetermined cell number counting circuit 93 with a preset black image threshold value (for example, a numerical value corresponding to 20% of the total number of discharge cells in the image display area in the panel 10). Then, the comparison result is output as a predetermined image display time detection result.

  That is, the predetermined image display time detection circuit 49 is a time during which a field in which no address operation is performed continuously occurs for each discharge cell when the brightness detected by the brightness detection circuit 47 is less than the first illuminance. The non-lighting continuous time is compared with the non-lighting time threshold, and the number of discharge cells whose non-lighting continuous time is equal to or greater than the non-lighting time threshold is displayed as a black image. It is detected whether the threshold value has been reached, and the detection result is output to the timing generation circuit 45.

  In addition, the specific numerical value of each threshold value mentioned above is only an example in the present embodiment, and the present invention is not limited to these numerical values. Each threshold value is desirably set optimally according to the characteristics of the panel and the specifications of the plasma display device.

  Then, the timing generation circuit 45 is continuously turned off based on the output from the predetermined image display time detection circuit 49 when the brightness detected by the brightness detection circuit 47 is less than the first illuminance (for example, 30 lux). Timing signal including image data for forced lighting so that when the number of discharge cells whose time is equal to or greater than the non-lighting time threshold reaches the black image threshold, the discharge cells are forcibly lit in the second type subfield. Is supplied to the data electrode drive circuit 42.

  In other words, in the present embodiment, the number of discharge cells whose brightness detected by the brightness detection circuit 47 is less than the first illuminance and whose non-lighting continuous time is equal to or greater than the non-lighting time threshold is black. When the image threshold is reached, it is determined that the image displayed on the panel 10 satisfies a predetermined condition.

  As described in the first embodiment, when a state in which no discharge occurs in the discharge cell continues for a long time, there is a possibility that the wall charge and priming particles in the discharge cell are reduced and the address operation becomes unstable. Some are not limited to black images. A similar phenomenon may occur when the continuous display time of a black region where no discharge occurs becomes long. However, in the configuration shown in this embodiment, when the continuous display time of the black region where no discharge is generated becomes long, the reduced wall charges and priming particles in the discharge cells can be recovered. Therefore, it is possible to stably generate the address discharge when the black area is switched to the normal image and prevent the deterioration of the image display quality.

(Embodiment 3)
FIG. 15 is a circuit block diagram of plasma display device 3 in accordance with the third exemplary embodiment of the present invention.

  The plasma display device 3 includes a panel 10 and a driving circuit that generates the driving voltage waveform shown in FIG. 3 and applies the waveform to each electrode of the panel 10 to drive the panel 10. In the present embodiment, plasma display device 3 is configured to include total use time detection circuit 147 in plasma display device 1 shown in the first embodiment. Therefore, the same reference numerals are given to circuit blocks that perform the same operations as the circuit blocks included in the plasma display device 1, and description thereof is omitted.

  The drive circuit includes an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, a predetermined image display time detection circuit 48, a total use time detection circuit 147, brightness. A detection circuit 47 and a power supply circuit (not shown) for supplying necessary power to each circuit block are provided.

  The total usage time detection circuit 147 has a timer circuit (not shown), and measures the total usage time (total usage time) of the plasma display device 3. Specifically, the total usage time detection circuit 147 cumulatively adds a predetermined value (for example, “1”) every unit time (for example, every minute) during the period in which the plasma display device 3 is operating. This cumulative added value is not reset even when the power of the plasma display device 3 is turned off, and the cumulative added value at the time when the power of the plasma display device 3 is turned off is held. When the power source of the plasma display device 3 is turned on, a predetermined value is cumulatively added to the held numerical value every unit time again. The total usage time detection circuit 147 measures the total usage time of the plasma display device 3 in this way, and the measured total usage time is output to the predetermined image display time detection circuit 48.

  The predetermined image display time detection circuit 48 has substantially the same configuration as the predetermined image display time detection circuit 46 shown in the first embodiment, and performs substantially the same operation. However, the predetermined image display time detection circuit 48 differs from the predetermined image display time detection circuit 46 in that the black image display time threshold value is changed based on the output from the total use time detection circuit 147. Specifically, the predetermined image display time detection circuit 48 includes a plurality of threshold values for comparison with the total use time output from the total use time detection circuit 147, and each time the total use time exceeds each threshold value. In addition, the black image display time threshold is decreased by a predetermined time. This is due to the following reason.

  The discharge characteristics of the panel 10 gradually change according to the usage time of the panel 10 (change in discharge characteristics with time). Specifically, as the total use time of the panel 10 becomes longer, the discharge characteristics of the panel 10 change in a direction in which discharge is less likely to occur. Therefore, in the panel 10 driven by the driving method shown in the present embodiment, the black image continuous display time during which unstable address discharge is likely to occur when switching from a black image to a normal image is as follows. As the total usage time increases, it gradually decreases. Therefore, it is desirable to reduce the black image display time threshold according to the total usage time of the plasma display device 3.

  Therefore, in the present embodiment, the predetermined image display time detection circuit 48 changes the black image display time threshold value based on the total use time of the plasma display device 3 output from the total use time detection circuit 147. To do.

  For example, the predetermined image display time detection circuit 48 has six threshold values set to 500 hours, 1000 hours, 2000 hours, 4000 hours, 7000 hours, and 10000 hours, and is output from the total use time detection circuit 147. Each time the total usage time of the plasma display device 3 exceeds each threshold value, the black image display time threshold value is decreased by a predetermined time (for example, 5 minutes). As a specific example, the predetermined image display time detection circuit 48 changes the black image display time threshold from 60 minutes to 55 minutes when the total use time reaches 500 hours, and when the total use time reaches 1000 hours. When the black image display time threshold is changed from 55 minutes to 50 minutes and the total usage time reaches 2000 hours, the black image display time threshold is changed from 50 minutes to 45 minutes, and when the total usage time reaches 4000 hours When the black image display time threshold is changed from 45 minutes to 40 minutes and the total usage time reaches 7000 hours, the black image display time threshold is changed from 40 minutes to 35 minutes, and when the total usage time reaches 10,000 hours The black image display time threshold is changed from 35 minutes to 30 minutes.

  The predetermined image display time detection circuit 48 may be configured to have a larger threshold value than the above-described threshold value, and the change amount of the black image display time threshold value may be the numerical value ( The configuration may be set more finely than (5 minutes).

  As a result, in the present embodiment, the black image display time threshold can be changed according to the discharge characteristics of the panel 10 that changes based on the total usage time of the plasma display device 3. The image display quality can be further improved.

  It should be noted that the amount of change with time in the discharge characteristics of panel 10 is large when the total usage time of panel 10 is short, but gradually decreases as the total usage time of panel 10 increases. Therefore, the black image display time threshold value may not be changed after the total use time exceeds a certain time (for example, 10,000 hours).

  Strictly speaking, the total use time of the panel 10 and the total use time of the plasma display device 3 may be different from each other. However, in the present embodiment, they are substantially equal to each other, and the predetermined image display time is set. The detection circuit 48 is operated.

  Note that the structure described in this embodiment can also be used for the plasma display device 2 described in Embodiment 2. That is, the plasma display device 2 shown in the second embodiment is configured to include the total use time detection circuit 147, and the non-lighting time is determined based on the total use time of the plasma display device output from the total use time detection circuit 147. It is good also as a structure which changes a threshold value. Since this configuration is the same as that described above except that the black image display time threshold value is changed to the non-lighting time threshold value, a description thereof will be omitted.

(Embodiment 4)
FIG. 16 is a circuit block diagram of plasma display device 4 in the fourth exemplary embodiment of the present invention.

  The plasma display device 4 includes a panel 10 and a drive circuit that generates the drive voltage waveform shown in FIG. In the present embodiment, plasma display device 4 is configured to include total use time detection circuit 149 in plasma display device 1 shown in the first embodiment. Therefore, the same reference numerals are given to circuit blocks that perform the same operations as the circuit blocks included in the plasma display device 1, and description thereof is omitted.

  The drive circuit includes an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 148, a predetermined image display time detection circuit 46, a total use time detection circuit 149, and brightness. A detection circuit 47 and a power supply circuit (not shown) for supplying necessary power to each circuit block are provided.

  The total usage time detection circuit 149 includes a timer circuit (not shown), and measures the total usage time (total usage time) of the plasma display device 4. Then, the measured total usage time is output to the timing generation circuit 148. Note that the operation of the total use time detection circuit 149 is the same as that of the total use time detection circuit 147 shown in Embodiment 3, and thus the description thereof is omitted.

  The timing generation circuit 148 has substantially the same configuration as the timing generation circuit 45 shown in the first embodiment, and operates almost the same. However, the timing generation circuit 148 differs from the timing generation circuit 45 in that the magnitude of the predetermined lighting rate is changed based on the output from the total usage time detection circuit 149. Specifically, the timing generation circuit 148 includes a plurality of threshold values for comparison with the total usage time output from the total usage time detection circuit 149, and each time the total usage time exceeds the threshold, The predetermined lighting rate when forcibly lighting the seed subfield (subfield SF1 in the present embodiment) is increased. This is due to the following reason.

  The discharge characteristics of the panel 10 gradually change according to the usage time of the panel 10 (change in discharge characteristics with time). Specifically, as the total use time of the panel 10 becomes longer, the discharge characteristics of the panel 10 change in a direction in which discharge is less likely to occur. Therefore, in panel 10 driven by the driving method shown in the present embodiment, the lighting rate of the second subfield at the time of forced lighting is gradually increased as the total usage time of panel 10 becomes longer, and discharge is performed. It is desirable to increase the amount of wall charge and priming particles replenished in the cell.

  Therefore, in the present embodiment, the timing generation circuit 148 changes the predetermined lighting rate based on the total usage time of the plasma display device 4 output from the total usage time detection circuit 149.

  For example, the timing generation circuit 148 has six threshold values set to 500 hours, 1000 hours, 2000 hours, 4000 hours, 7000 hours, and 10,000 hours, and is output from the total usage time detection circuit 149. Each time the total usage time of the device 4 exceeds each threshold, the predetermined lighting rate is increased by a predetermined value (for example, 5%). That is, the timing generation circuit 148 changes the predetermined lighting rate from 50% to 55% when the total usage time reaches 500 hours, and changes the predetermined lighting rate from 55% to 60% when the total usage time reaches 1000 hours. When the total usage time reaches 2000 hours, the predetermined lighting rate is changed from 60% to 65%. When the total usage time reaches 4000 hours, the predetermined lighting rate is changed from 65% to 70%. When it reaches 7000 hours, the predetermined lighting rate is changed from 70% to 75%, and when the total usage time reaches 10,000 hours, the predetermined lighting rate is changed from 75% to 80%.

  Thus, in the present embodiment, the predetermined lighting rate can be changed according to the discharge characteristics of the panel 10 that changes based on the total usage time of the plasma display device 4, and the image display quality in the plasma display device 4 can be changed. Can be further improved.

  It should be noted that the amount of change with time in the discharge characteristics of panel 10 is large when the total usage time of panel 10 is short, but gradually decreases as the total usage time of panel 10 increases. Therefore, the predetermined lighting rate may not be changed after the total usage time exceeds a certain time (for example, 10,000 hours).

  Strictly speaking, the total use time of the panel 10 and the total use time of the plasma display device 4 are different from each other, but in this embodiment, the timing generation circuit 148 is operated assuming that they are substantially equal to each other. ing.

  Note that the structure described in this embodiment can be used for the plasma display devices described in Embodiment 2 and Embodiment 3. That is, the plasma display device 2 shown in the second exemplary embodiment includes the total use time detection circuit 149, and a predetermined lighting rate is set based on the total use time of the plasma display device output from the total use time detection circuit 149. It is good also as a structure to change. Alternatively, in the plasma display device 3 shown in the third exemplary embodiment, the predetermined lighting rate may be changed based on the total use time of the plasma display device output from the total use time detection circuit 147.

  In the embodiment of the present invention, the configuration in which the second type subfield is the subfield SF1 has been described. However, the second type subfield may be a subfield other than the subfield SF1.

  In the embodiment of the present invention, the configuration in which one field includes a second type subfield and a plurality of first type subfields has been described. However, for example, one field includes only a plurality of first type subfields. You may comprise. In this case, during the subfield forced lighting period, the subfield with the smallest luminance weight (for example, the subfield with the luminance weight “1”) is forcibly lit at a predetermined lighting rate.

  Alternatively, during the subfield forced lighting period, the second type subfield and the subfield having the lowest luminance weight (for example, the subfield having the luminance weight “1”) among the first type subfields are forcibly set at a predetermined lighting rate. It is good also as a structure which lights up.

  The configuration of each circuit block such as the predetermined image display time detection circuit shown in the embodiment of the present invention is merely an example, and the present invention is not limited to such a circuit configuration. is not. Any other circuit configuration may be used as long as it performs an operation similar to that described in the embodiment, or it may be realized by a computer programmed to perform the same operation.

  It should be noted that depending on the threshold for comparison with the total usage time shown in the embodiment of the present invention, the black image threshold, the black image display time threshold, the non-lighting time threshold, and the total usage time The specific numerical values related to the numerical values subtracted from the black image display time threshold value and the non-lighting time threshold value are merely examples, and the present invention is not limited to the numerical values shown here. is not. Each numerical value is desirably set to an optimum value based on the characteristics of the panel, the specifications of the plasma display device, and the like.

  The present invention makes it possible to perform a stable writing operation without performing a forced initialization operation, thereby suppressing the black luminance, thereby increasing the contrast of the display image and lowering the luminance of the next lower gradation after black. This improves the gradation when displaying a dark image, and can stably generate an address discharge when the display image is switched from a black image to a normal image, thereby displaying an image with high image display quality. Therefore, it is useful as a panel driving method and a plasma display device.

1, 2, 3, 4 Plasma display device 10 Panel 21 Front substrate 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25 Dielectric layer 26 Protective layer 31 Rear substrate 32 Data electrode 33 Dielectric layer 34 Partition 35 Phosphor layer 41 Image Signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45, 148 Timing generation circuit 47 Brightness detection circuit 46, 48, 49 Predetermined image display time detection circuit 147, 149 Total use time detection circuit 50, 80 sustain pulse generation circuit 51, 81 power recovery circuit 55 APL detection circuit 56, 58, 94 comparison circuit 57 timer circuit 60 ramp waveform voltage generation circuit 61, 63 Miller integration circuit 70 scan pulse generation circuit 85 constant voltage generation circuit 91 non-lighting Judgment circuit 92 Non-lighting continuous time detection circuit 9 3 Predetermined cell count circuit Q55, Q56, Q59, Q61, Q63, Q69, Q71H1 to Q71Hn, Q71L1 to Q71Ln, Q72, Q83, Q84, Q86, Q87, Q91H1 to Q91Hm, Q91L1 to Q91Lm Switching element E71 Power supply Q61, Q63 Transistor C61, C63 Capacitor R61, R63 Resistor IN61, IN63 Input terminal L1, L3 Up-slope waveform voltage L2, L4 Down-slope waveform voltage

Claims (12)

A plasma display panel comprising a plurality of sub-fields having an address period, a sustain period, and an erase period, forming a single field, and having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode A driving method of a plasma display panel to be driven,
The plurality of subfields constituting the one field include a first type subfield that generates a number of sustain pulses corresponding to a luminance weight in the sustain period and applies the sustain pulses to the display electrode pair,
A voltage obtained by subtracting a voltage applied to the data electrode from a low-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield is defined as a first voltage, A voltage obtained by subtracting a voltage applied to the data electrode from a high-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period is set as a second voltage, and a low voltage of the scan pulse applied to the scan electrode in the address period When the voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode from the side voltage is the third voltage,
A voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than a discharge start voltage of discharge using the data electrode as an anode and the scan electrode as a cathode,
The voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage of discharge using the data electrode as an anode and the scan electrode as a cathode, and the data electrode as a cathode and the scan electrode as an anode. Less than the sum of the discharge start voltage of the discharge,
Detecting the ambient brightness of the plasma display device on which the plasma display panel is mounted, and comparing the detected brightness with a preset first illuminance;
If the detected brightness is less than the first illuminance, the subfield with the lowest luminance weight is forcibly turned on at a predetermined lighting rate when an image displayed on the plasma display panel satisfies a predetermined condition. And
If the detected brightness is equal to or higher than the first illuminance, the subfield having the smallest luminance weight is forcibly lit at a lighting rate according to the detected brightness. Driving method. A plurality of subfields constituting one field generate the rising ramp waveform voltage and the falling ramp waveform voltage without generating the sustain pulse in the sustain period and applying the same to the scan electrodes. A second type subfield,
The method of claim 1, wherein the second type subfield is a subfield having the smallest luminance weight. Detecting an average luminance level based on an image signal, determining whether an image displayed on the plasma display panel is a black image by comparing the average luminance level with a black image threshold;
When the length of time during which black images are continuously displayed on the plasma display panel reaches a black image display time threshold, when the image displayed on the plasma display panel satisfies the predetermined condition; The method of driving a plasma display panel according to claim 1, wherein the determination is made. For each discharge cell, measure the length of time that the field that does not perform an address operation continuously occurs as a non-lighting continuous time, and compare the non-lighting continuous time with a non-lighting time threshold,
When the number of discharge cells in which the non-lighting continuous time is equal to or greater than the non-lighting time threshold reaches a black image threshold, and when the image displayed on the plasma display panel satisfies the predetermined condition The method of driving a plasma display panel according to claim 1, wherein the determination is made. 4. The plasma display panel according to claim 3, wherein a total use time of a plasma display device mounted with the plasma display panel is detected, and the black image display time threshold value is reduced according to the total use time. Driving method. 5. The plasma display panel according to claim 4, wherein a total use time of a plasma display device mounted with the plasma display panel is detected, and the non-lighting time threshold value is reduced according to the total use time. Driving method. The voltage applied to the sustain electrode in the address period of the second type subfield is lower than the voltage applied to the sustain electrode in the address period of the first type subfield. A method for driving a plasma display panel according to claim 1. The predetermined lighting rate when forcibly lighting is characterized in that it represents the lighting rate in a region where the subfield with the smallest luminance weight is not lit when displaying an image on the plasma display panel based on the image signal. The method for driving a plasma display panel according to claim 1. Comparing the detected brightness with a preset second illuminance;
If the detected brightness is greater than or equal to the second illuminance, the subfield with the smallest luminance weight is forcibly lit at a preset predetermined lighting rate, and the detected brightness is greater than or equal to the first illuminance and 2. The method of driving a plasma display panel according to claim 1, wherein if the illumination intensity is less than the second illuminance, the subfield having the smallest luminance weight is forcibly lit at a lighting rate corresponding to the detected brightness. . 2. The method of driving a plasma display panel according to claim 1, wherein a total use time of a plasma display device mounted with the plasma display panel is detected, and the predetermined lighting rate is increased according to the total use time. One field is formed by using a plasma display panel having a plurality of discharge cells each having a display electrode pair and data electrodes each including a scan electrode and a sustain electrode, and a plurality of subfields having an address period, a sustain period, and an erase period. And a driving circuit for generating a driving voltage waveform corresponding to each electrode of the plasma display panel and applying the driving voltage waveform to each electrode,
The drive circuit is
One field is configured using a plurality of first type subfields, and a number of sustain pulses corresponding to luminance weights are generated and applied to the display electrode pairs in the sustain period of the first type subfield,
A voltage obtained by subtracting a voltage applied to the data electrode from a low-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield is defined as a first voltage, A voltage obtained by subtracting a voltage applied to the data electrode from a high-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period is set as a second voltage, and a low voltage of the scan pulse applied to the scan electrode in the address period When the voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode from the side voltage is the third voltage,
A voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than a discharge start voltage of a discharge having the data electrode as an anode and the scan electrode as a cathode;
A voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage of discharge using the data electrode as an anode and the scan electrode as a cathode, and the data electrode as a cathode and the scan electrode as an anode. Less than the sum of the discharge start voltage of the discharge,
The drive circuit is
Detecting the ambient brightness of the plasma display device on which the plasma display panel is mounted, and comparing the detected brightness with a preset first illuminance;
If the detected brightness is less than the first illuminance, the second type subfield is forcibly lit at a predetermined lighting rate when an image displayed on the plasma display panel satisfies a predetermined condition. ,
If the detected brightness is equal to or higher than the first illuminance, a subfield having the smallest luminance weight is forcibly lit at a lighting rate according to the detected brightness. The drive circuit is
One field includes a plurality of first-type subfields, and a second-type subfield that generates an up-slope waveform voltage and a down-slope waveform voltage and applies them to the scan electrodes without generating the sustain pulse in the sustain period. The plasma display apparatus according to claim 11, wherein the second type subfield is a subfield having the smallest luminance weight.

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