JP2012247465A - Method of driving plasma display panel, and plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably generate a write discharge when an image in black is changed to a normal image by suppressing brightness of black displayed on a plasma display panel by performing stable writing operation without performing forcible initializing operation, and also lowering brightness of a lower gradation following the black.SOLUTION: One field includes a subfield of first kind which generates and applies a maintenance pulse to a display electrode pair in a maintenance period, and a subfield of second kind which does not generate a maintenance pulse in the maintenance period, but generates and applies an up inclined waveform voltage and a down inclined waveform voltage to a scanning electrode. An average brightness level of a displayed image is detected, and one of a subfield having minimum brightness weight among subfields of first kind and the subfield of second kind is made to illuminate at a lighting rate according to the detection result.

Description

  The present invention relates to an AC surface discharge type plasma display panel driving method and a plasma display apparatus.

  A plasma display panel (hereinafter abbreviated as “panel”) includes a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and is an ultraviolet ray generated by gas discharge in the discharge cell. The phosphors of red, green, and blue are excited and emitted to display an image in color.

  A subfield method is generally used as a method for driving the panel. In the subfield method, a single field is formed using a plurality of subfields having an initialization period, an address period, and a sustain period, and gradation display is performed by a combination of subfields that emit light. In each subfield, an initialization operation is performed in the initialization period, an address operation is performed in the write period, and a sustain operation is performed in the sustain period.

  The initialization operation is an operation in which an initialization discharge is generated in the discharge cell and wall charges necessary for the subsequent address operation are formed in the discharge cell. The initializing operation includes a forced initializing operation in which an initializing discharge is generated in the discharge cell regardless of the operation in the immediately preceding subfield, and a selection in which the initializing discharge is generated in the discharge cell that has performed the address discharge in the immediately preceding subfield. There is an initialization operation.

  The address operation is an operation in which address discharge is selectively generated in the discharge cells in accordance with the image to be displayed, and wall charges are formed in the discharge cells. The sustain operation is an operation in which a sustain pulse is alternately applied to the display electrode pair to generate a sustain discharge in the discharge cell in which the address discharge is generated and to cause the phosphor layer of the discharge cell to emit light. The light emission of the phosphor layer due to the sustain discharge is light emission related to gradation display, and the light emission generated by the forced initialization operation is light emission not related to gradation display.

  Up to now, a plurality of subfield methods have been proposed. One of them is a luminance (hereinafter referred to as “below”) for reducing the light emission not related to the gradation display as much as possible and displaying the lowest gradation black. There is a driving method for improving contrast by lowering (abbreviated as “black luminance”). For example, Patent Document 1 discloses a driving method in which a forced initialization operation is performed using a gradually changing ramp waveform voltage, and the number of times the forced initialization operation is performed is once per field.

  In Patent Document 2, the display electrode pair is divided into n, and the number of times of performing the forced initialization operation is once per n fields, thereby further reducing light emission not related to gradation display and further reducing black luminance, A driving method with further improved contrast is disclosed.

JP 2000-242224 A JP 2006-091295 A

  According to the driving method of the plasma display apparatus of the present invention, one field is formed by using a plurality of subfields having an address period, a sustain period, and an erase period, and a display electrode pair and a data electrode including scan electrodes and sustain electrodes are arranged. A plasma display panel driving method for driving a plasma display panel having a plurality of discharge cells, wherein a plurality of subfields are applied to display electrode pairs by applying a number of sustain pulses according to luminance weight during a sustain period And a second type subfield for applying an up-slope waveform voltage and a down-slope waveform voltage to the scan electrode during the sustain period, and applying each to the sustain electrode, the scan electrode, and the data electrode The sustain pulse for applying the drive voltage waveform to the scan electrode in the sustain period of the first type subfield The voltage obtained by subtracting the voltage applied to the data electrode from the low-voltage side voltage is set as the first voltage, and the voltage applied to the data electrode is subtracted from the high-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield. When the voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode from the low-voltage side voltage of the scan pulse applied to the scan electrode during the write period is the third voltage, The voltage obtained by subtracting the third voltage from the voltage becomes equal to or higher than the discharge start voltage of the discharge using the data electrode as the anode and the scan electrode as the cathode, and the voltage obtained by subtracting the third voltage from the second voltage is the data. The discharge start voltage of the discharge with the electrode as the anode and the scan electrode as the cathode and the discharge start voltage of the discharge with the data electrode as the cathode and the scan electrode as the anode Detecting an average luminance level of an image signal displayed on the display panel, depending on the average luminance level, it is characterized in that forcibly turns on the first two sub-fields.

  This method makes it possible to perform a stable write operation without performing a forced initialization operation, thereby suppressing black luminance and increasing the contrast of a display image. Further, when the display image is switched from a black image to a normal image, an address discharge can be stably generated, and an image with high image display quality can be displayed on the panel.

  The plasma display apparatus of the present invention includes a plasma display panel having a plurality of discharge cells each having a display electrode pair and data electrodes each composed of a scan electrode and a sustain electrode, and a plurality of subfields each having an address period, a sustain period, and an erase period. And a driving circuit that generates a driving voltage waveform corresponding to each electrode of the plasma display panel and applies the driving voltage waveform to each electrode. The driving circuit includes: One field is configured by using the first type subfield and the second type subfield, and the sustain period of the first type subfield generates a number of sustain pulses corresponding to the luminance weight and applies them to the display electrode pair, During the sustain period of the second type subfield, no sustain pulse is generated, and the rising ramp waveform voltage and the falling ramp waveform A voltage is generated and applied to the scan electrode, and a drive voltage waveform applied to each of the sustain electrode, the scan electrode, and the data electrode is applied to the low voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield. The voltage obtained by subtracting the voltage applied to the data electrode from the first voltage is obtained by subtracting the voltage applied to the data electrode from the high-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield. When the voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode from the low-voltage side voltage of the scan pulse applied to the scan electrode during the write period is the third voltage, The voltage obtained by subtracting the third voltage is equal to or higher than the discharge start voltage of the discharge using the data electrode as the anode and the scan electrode as the cathode, and the voltage obtained by subtracting the third voltage from the second voltage is The drive circuit is generated by setting the discharge start voltage of the discharge with the data electrode as the anode and the scan electrode as the cathode and the discharge start voltage of the discharge with the data electrode as the cathode and the scan electrode as the anode. Includes an image detection circuit for detecting an average luminance level of an image signal displayed on the plasma display device, and forcibly turns on the second type subfield according to the average luminance level detected by the image detection circuit. It is a feature.

  The drive circuit may increase the lighting rate of the discharge cells for forcibly lighting the second type subfield as the average luminance level increases.

  With the plasma display device of the present invention, it is possible to realize a display device that realizes a high-quality screen by reliably performing a writing operation without performing initialization driving.

  The present invention forms a single field using a plurality of subfields each having an address period, a sustain period, and an erase period, and includes a plurality of discharge cells each having a display electrode pair and a data electrode each composed of a scan electrode and a sustain electrode. A plasma display panel driving method for driving a plasma display panel, wherein a plurality of subfields are a first type subfield that is applied to a display electrode pair by applying a number of sustain pulses according to a luminance weight in a sustain period. A second-type subfield that applies an up-slope waveform voltage and a down-slope waveform voltage to the scan electrode in the sustain period, and the drive voltage waveform applied to each of the sustain electrode, the scan electrode, and the data electrode The voltage applied to the data electrode is subtracted from the low voltage side voltage of the sustain pulse applied to the scan electrode during the sustain period of the field. The voltage is the first voltage, the voltage obtained by subtracting the voltage applied to the data electrode from the high-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield is the second voltage, and the scan is performed in the write period. When the voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode from the low-voltage side voltage of the scan pulse applied to the electrode is the third voltage, the voltage obtained by subtracting the third voltage from the first voltage is: The discharge start voltage of the discharge with the data electrode as the anode and the scan electrode as the cathode is equal to or higher than the discharge start voltage of the discharge with the data electrode as the anode and the scan electrode as the cathode. A specific signal of the image signal that is generated and set to be less than the sum of the voltage and the discharge start voltage of the discharge with the data electrode as the cathode and the scan electrode as the anode Detecting a number or more of the discharge cells bell, characterized in that it forcibly light the second type sub-field lighting rate according to the number the discharge cells. Furthermore, the lighting rate of the discharge cells forcibly lighting the second type subfield is characterized in that the larger the lighting rate according to the number of discharge cells equal to or higher than a specific signal level, the larger the lighting rate.

  This method makes it possible to perform a stable write operation without performing a forced initialization operation, thereby suppressing black luminance, increasing the contrast of the display image, and further switching the display image from a black image to a normal image. Sometimes, address discharge is stably generated, and an image with high image display quality can be displayed on the panel.

  The plasma display apparatus of the present invention also includes a plasma display panel having a plurality of discharge cells each having a display electrode pair and data electrodes each composed of a scan electrode and a sustain electrode, and a subfield having an address period, a sustain period, and an erase period. And a drive circuit that generates a drive voltage waveform corresponding to each electrode of the plasma display panel and applies the drive voltage waveform to each electrode, and the drive circuit defines one field as the first field. A seed subfield and a second seed subfield are used. During the sustain period of the first seed subfield, the number of sustain pulses corresponding to the luminance weight is generated and applied to the display electrode pair. During the sustain period of the field, the sustain pulse is not generated, and the rising ramp waveform voltage and the falling ramp waveform voltage are generated and the scanning power is generated. The voltage applied to the data electrode from the low-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield is applied to the sustain electrode, the scan electrode, and the data electrode. The voltage obtained by subtracting the voltage applied to the data electrode from the high-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield is used as the second voltage. When the voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode from the low-voltage side voltage of the scan pulse applied to the scan electrode in the period is the third voltage, the third voltage is subtracted from the first voltage. The voltage is equal to or higher than the discharge start voltage of the discharge with the data electrode as the anode and the scan electrode as the cathode, and the voltage obtained by subtracting the third voltage from the second voltage becomes the data electrode as the anode. Generated by setting the discharge start voltage of the discharge with the scan electrode as the cathode and the discharge start voltage of the discharge with the data electrode as the cathode and the scan electrode as the anode, and the drive circuit is displayed An image detection circuit for detecting the number of discharge cells equal to or higher than a specific signal level of the image is provided, and the second type subfield is forcibly lit at a lighting rate corresponding to the number of discharge cells detected by the image detection circuit. It is a feature. Further, this drive circuit is characterized in that the lighting rate of the discharge cells for forcibly lighting the second type subfield is larger as the lighting rate according to the number of discharge cells equal to or higher than a specific signal level is larger.

  With this plasma display device, it is possible to realize a display device that realizes a high-quality screen by reliably performing a writing operation without performing initialization driving.

  According to the present invention, it is possible to perform a stable writing operation without performing a forced initializing operation, thereby suppressing the black luminance, thereby increasing the contrast of the display image and reducing the luminance of the next lower gradation after black. To improve the gradation when displaying a dark image, and stably generate an address discharge when the display image switches from a black image to a normal image, thereby displaying an image with high image display quality. It is possible to provide a panel driving method and a plasma display device that can be used.

The exploded perspective view of the panel used for the plasma display apparatus in Embodiment 1 of this invention Electrode arrangement diagram of panel used in plasma display device in embodiment 1 of the present invention The figure which shows the drive voltage waveform applied to each electrode of the plasma display apparatus in Embodiment 1 of this invention. The figure for demonstrating the definition of the 1st voltage, 2nd voltage, and 3rd voltage in Embodiment 1 of this invention The figure which shows an example of the method of measuring a discharge start voltage simply Circuit block diagram of plasma display device according to Embodiment 1 of the present invention 1 is a circuit block diagram of an image detection circuit of a plasma display device in accordance with the first exemplary embodiment of the present invention. The figure which shows the relationship between the average luminance level in Embodiment 1 of this invention, and 2nd kind subfield forced lighting. Circuit diagram of scan electrode driving circuit of plasma display device in accordance with the first exemplary embodiment of the present invention. Circuit diagram of sustain electrode drive circuit of plasma display device in accordance with the first exemplary embodiment of the present invention. 1 is a circuit diagram of a data electrode drive circuit of a plasma display device in accordance with the first exemplary embodiment of the present invention. Circuit block diagram of plasma display device in accordance with the second exemplary embodiment of the present invention Circuit block diagram of an image detection circuit of the plasma display device in the second exemplary embodiment of the present invention The figure which shows the relationship between the pixel lighting rate and 2nd kind subfield forced lighting in Embodiment 2 of this invention. Circuit block diagram of plasma display device according to Embodiment 3 of the present invention Circuit block diagram of the image detection circuit of the plasma display device in the third exemplary embodiment of the present invention The figure which shows the relationship between APL and the 1st forced lighting rate coefficient in Embodiment 3 of this invention. The figure which shows the relationship between the pixel lighting rate in Embodiment 3 of this invention, and a 2nd forced lighting rate coefficient.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the display electrode pair 24, and a protective layer 26 is formed on the dielectric layer 25. The protective layer 26 is formed using magnesium oxide, which is a material having high electron emission performance, in order to easily generate discharge. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33. For example, (Y, Gd) BO ₃ : Eu is used as the red phosphor, Zn ₂ SiO ₄ : Mn is used as the green phosphor, and BaMgAl ₁₀ O ₁₇ : Eu is used as the blue phosphor. Each of them uses a phosphor as a main component.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is sealed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) that are long in the row direction. M data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged. A discharge cell is formed at a portion where a pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects with one data electrode Dj (j = 1 to m). Therefore, m × n discharge cells are formed in the discharge space.

  Next, a driving voltage waveform for driving panel 10 and its operation will be described. In the plasma display device, one field is divided into a plurality of subfields, and the panel 10 is driven by a subfield method in which light emission / non-light emission of each discharge cell is controlled for each subfield, and an image is displayed on the panel 10.

  In this embodiment, one field is configured by using a plurality of subfields each having an address period, a sustain period, and an erase period. In the present embodiment, the forced initializing operation for forcibly generating the initializing discharge in the discharge cells is not performed regardless of the presence or absence of the previous discharge.

  In the address period, an address discharge is selectively generated in the discharge cells to emit light, and an address operation is performed to form wall charges in the discharge cells.

  In the sustain period, a sustain operation is performed in which a sustain pulse of the number corresponding to the luminance weight determined in advance for each subfield is alternately applied to the display electrode pair, and a sustain discharge is generated in the discharge cell in which the address discharge is generated in the address period. Do. In the present embodiment, a sustain operation is performed in which the sustain pulse is not applied to the scan electrode 22 in order to suppress the luminance of the second lowest gradation after black (for example, the gradation value “0”) as much as possible. In this sustain operation, instead of the sustain pulse, an up-gradient waveform voltage (up-gradient waveform voltage L1 described later) whose voltage gradually rises is generated and applied to the scan electrode 22, and then the voltage gradually falls. A downward ramp waveform voltage (downward ramp waveform voltage L2 described later) is generated and applied to the scan electrode 22. In this way, a sustain operation is performed in which a weak sustain discharge is generated in the discharge cell in which the address discharge is generated as compared with the sustain discharge generated by the sustain pulse, and the discharge cell emits light with a weak luminance.

  In the erasing period, an erasing discharge is generated only in the discharge cells that have generated the address discharge in the address period of the subfield to which the erasing period belongs. Therefore, this erasing discharge is selectively generated only in the discharge cells that have generated the address discharge. By this erasing discharge, the history of wall charges formed by the address discharge or the subsequent sustain discharge is erased, and wall charges necessary for the subsequent address discharge are formed on each electrode. Hereinafter, these operations are also referred to as “erase operations”.

  Hereinafter, in the present embodiment, one field is divided into 11 subfields (SF1, SF2,..., SF11), and each subfield is (1/2, 1, 2, 3, 6, 11). , 18, 30, 44, 60, 80).

  In the present embodiment, the luminance weight of the first subfield SF1 is expressed as “1/2”. This is because the first subfield SF1 does not apply the sustain pulse in the sustain period, and instead of the sustain pulse, the up-slope waveform voltage (up-slope waveform voltage L1) and the down-slope waveform voltage (down-slope waveform voltage L2) are used. This is because the emission luminance is lower than that of the second subfield SF2 of the luminance weight “1”, which is a subfield generated and applied to the scan electrode 22, and the sustain pulse is applied to the display electrode pair 24. Hereinafter, as in the first subfield SF1, a subfield in which no sustain pulse is generated in the sustain period and the rising ramp waveform voltage and the falling ramp waveform voltage are applied to the scan electrode 22 is referred to as a “second type subfield”. To do. In addition, a subfield (for example, the second subfield SF2 to the eleventh subfield SF11) that applies the sustain pulse to the display electrode pair 24 in the sustain period is referred to as a “first type subfield”.

  In the present embodiment, the luminance weight “1/2” of the first subfield SF1, which is the second type subfield, emits light with a luminance lower than that of the second subfield SF2, which is the first type subfield. Only a lower gradation display than the second subfield SF2 to the eleventh subfield SF11, and the luminance weight “1/2” of the second type subfield is not necessarily shown. Does not indicate that light is emitted with half the luminance of the first type subfield.

  Thus, in the present embodiment, the plurality of subfields constituting one field generate the sustain pulse in the sustain period and apply it to the display electrode pair 24, and the sustain pulse in the sustain period. And a second type subfield that generates and applies an up ramp waveform voltage (up ramp waveform voltage L1) and a down ramp waveform voltage (down ramp waveform voltage L2) to scan electrode 22 without being generated. Yes.

  The subfield configuration described above is merely an example in the present embodiment, and the present invention is not limited to this subfield configuration. It is desirable to optimally set the number of subfields constituting one field and the luminance weight of each subfield according to the characteristics of the panel and the specifications of the plasma display device.

  FIG. 3 is a diagram showing a driving voltage waveform applied to each electrode of the plasma display device in accordance with the first exemplary embodiment of the present invention.

  In the address period of the first subfield SF1, which is the second type subfield, voltage 0 (V) is applied to data electrode D1 to data electrode Dm, and voltage 0 (V) is applied to sustain electrode SU1 to sustain electrode SUn. A voltage Vc is applied to scan electrode SC1 through scan electrode SCn. Next, a scan pulse of voltage Va is applied to scan electrode SC1 in the first row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light.

  As a result, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is obtained by adding the positive wall voltage on the data electrode Dk to the difference (Vd−Va) of the externally applied voltage, so that the data electrode Dk becomes the anode. The discharge start voltage VFds of the discharge having the scan electrode SCi as the cathode is exceeded, and a discharge is generated between the data electrode Dk and the scan electrode SC1. This discharge is an address discharge, and when an address discharge occurs, a positive wall voltage is accumulated on scan electrode SC1, and a negative wall voltage is accumulated on data electrode Dk. The wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  Thus, an address operation is performed in which an address discharge is generated in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrode Dh to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage VFds, so the address discharge does not occur.

  Next, a scan pulse is applied to scan electrode SC2 in the second row, and an address pulse is applied to data electrode Dk corresponding to the discharge cell to emit light. Thereby, an address discharge is generated between data electrode Dk and scan electrode SC2, and a positive wall voltage is accumulated on scan electrode SC2, and a negative wall voltage is accumulated on data electrode Dk. In this way, an address operation is performed in which an address discharge is generated in the discharge cells to be lit in the second row and wall voltage is accumulated on each electrode. On the other hand, since the voltage at the intersection between the data electrode Dh and the scan electrode SC2 to which no address pulse is applied does not exceed the discharge start voltage VFds, no address discharge occurs.

  Thereafter, the same address operation is sequentially performed until reaching the n-th scan electrode SCn, and wall charges necessary for the subsequent sustain discharge are formed.

  In the present embodiment, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn in the address period. Therefore, it is considered that the discharge generated between data electrode Dk and scan electrode SC1 does not extend to sustain electrode SU1. As a result, the luminance of light emission generated along with the address discharge can be suppressed, and the luminance displayed by the first subfield SF1 can be suppressed low.

  Here, for the following description, the first voltage V1, the second voltage V2, and the third voltage V3 are defined as follows. FIG. 4 is a diagram for explaining definitions of the first voltage, the second voltage, and the third voltage in the first embodiment of the present invention, and is applied to the scan electrode and the data electrode in one subfield. It is a figure which shows a voltage. In the present embodiment, the low-voltage side voltage (0 (V) in FIG. 4) of the sustain pulse applied to scan electrode SCi in the sustain period of second subfield SF2 to eleventh subfield SF11 that is the first type subfield. ) Minus the voltage applied to the data electrode Dj (in FIG. 4, 0 (V)) is defined as the first voltage V1. Further, the voltage (0 (V) in FIG. 4) applied to the data electrode Dj from the high-voltage side voltage (voltage Vs in FIG. 4) of the sustain pulse applied to the scan electrode SCi in the sustain period of the first type subfield. The reduced voltage is set as the second voltage V2. Further, the low-voltage side voltage (0 (V) in FIG. 4) of the address pulse applied to the data electrode Dj is subtracted from the low-voltage side voltage (voltage Va in FIG. 4) of the scan pulse applied to the scan electrode SCi in the address period. This voltage is referred to as a third voltage V3.

  Further, as described above, the discharge start voltage in the address period in which the data electrode Dj is the anode and the scan electrode SCi is the cathode is the discharge start voltage VFds, and the sustain period is the data electrode Dj is the cathode and the scan electrode SCi is the anode. Let the discharge start voltage of the discharge be the discharge start voltage VFsd. The discharge with the data electrode Dj as the anode and the scan electrode SCi as the cathode is a discharge in which the electric field in the discharge cell when the discharge occurs is a high potential side on the data electrode Dj side and a low potential side on the scan electrode SCi side. It is. The discharge with the data electrode Dj as the cathode and the scan electrode SCi as the anode is a discharge in which the electric field in the discharge cell when the discharge occurs is a low potential side on the data electrode Dj side and a high potential side on the scan electrode SCi side. is there. Since the protective layer 26 of magnesium oxide having high electron emission performance is formed on the front plate with the scan electrode SCi, the discharge start voltage VFds is lower than the discharge start voltage VFsd.

  In the present embodiment, the voltage Va of the scan pulse applied to the scan electrode SCi is set so as to satisfy the following two conditions (condition 1) and (condition 2).

(Condition 1): For all discharge cells, the voltage obtained by subtracting the third voltage V3 from the first voltage V1 is equal to or higher than the discharge start voltage VFds of the discharge using the data electrode Dj as the anode and the scan electrode SCi as the cathode. It is. That is,
(V1-V3) ≧ VFds is satisfied.

(Condition 2): For all the discharge cells, a voltage obtained by subtracting the third voltage V3 from the second voltage V2 is a discharge start voltage VFds of discharge using the data electrode Dj as an anode and the scan electrode SCi as a cathode. This is less than the sum of the discharge start voltage VFsd of the discharge with the data electrode Dj as the cathode and the scan electrode SCi as the anode. That is,
(V2−V3) <(VFds + VFsd) is satisfied.

  Next, the maintenance period will be described. In the sustain period of the first subfield SF1, which is the second type subfield of FIG. 3, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, and voltage 0 (V) is applied to data electrode D1 through data electrode Dm. Is applied to the scan electrode SC1 to the scan electrode SCn with an upward ramp waveform voltage L1 that gradually rises from the voltage 0 (V) to the voltage Vs. In the discharge cell in which the address discharge is generated, the voltage difference between the scan electrode SCi and the data electrode Dk is obtained by adding the difference between the wall voltage on the scan electrode SCi and the wall voltage on the data electrode Dk to the rising ramp waveform voltage L1. Will be. The voltage difference between the scan electrode SCi and the data electrode Dk exceeds the discharge start voltage VFsd while the upward ramp waveform voltage L1 is rising, and a weak discharge is generated between the scan electrode SCi and the data electrode Dk. The phosphor layer 35 emits light by the ultraviolet rays generated by this discharge. Since the discharge due to the rising ramp waveform voltage L1 is a weak discharge compared to the discharge generated by the sustain pulse applied in the sustain period of the other subfields, the ultraviolet rays generated by this discharge are also weak. The light emission at this time is also weak.

  After the voltage applied to scan electrode SC1 through scan electrode SCn rises to voltage Vs, voltage Vs is applied to scan electrode SC1 through scan electrode SCn continuously for a certain period (for example, for 50 μsec). As a result, the positive wall voltage on the scan electrode SCi decreases, and the negative wall voltage on the data electrode Dk also decreases. On the other hand, the sustain discharge does not occur in the discharge cell in which the address discharge has not occurred, and the wall voltage at the end of the immediately preceding field is maintained. Thereafter, the voltage applied to scan electrode SC1 through scan electrode SCn is lowered to voltage 0 (V).

  Subsequently, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, voltage Vd is applied to data electrode D1 through data electrode Dm, and voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn. Is applied to the ramp-down waveform voltage L2 that gently falls from V to Vg. This voltage Vg is set equal to (voltage Va + voltage Vd) or slightly higher than (voltage Va + voltage Vd).

  As a result, a weak sustain discharge occurs again in the discharge cell that has generated a weak sustain discharge, and the phosphor layer 35 emits light. The light emission at this time is also weak light emission similar to the light emission by the upward ramp waveform voltage L1. Then, the negative wall voltage on the data electrode Dk increases, and the positive wall voltage on the scan electrode SCi increases. Thereafter, the voltage applied to scan electrode SC1 through scan electrode SCn is raised to voltage 0 (V).

  In the subsequent erase period of first subfield SF1, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, voltage Vd is applied to data electrode D1 through data electrode Dm, and scan electrode SC1 through scan electrode. An upward ramp waveform voltage L3 that gently rises from voltage 0 (V) to voltage Vr is applied to SCn. As a result, a weak erasing discharge is generated between scan electrode SCi and sustain electrode SUi in the discharge cell that has generated a weak discharge during the sustain period. Then, the negative wall voltage on sustain electrode SUi decreases, and the positive wall voltage on scan electrode SCi decreases. Thereafter, the voltage applied to scan electrode SC1 through scan electrode SCn is lowered to voltage 0 (V).

  Thereafter, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and voltage 0 (V) is applied to data electrode D1 through data electrode Dm. Then, a downward ramp waveform voltage L4 that gently falls from voltage 0 (V) to voltage Vi is applied to scan electrode SC1 through scan electrode SCn. This voltage Vi is set to be equal to or slightly higher than the voltage Va of the scanning pulse.

  As a result, a weak discharge is generated again in the discharge cell that has generated the weak erasing discharge, and an excessive portion of the wall voltage on the scan electrode SCi, the sustain electrode SUi, and the data electrode Dk is discharged, The wall voltage is adjusted to be suitable for the write operation. In this way, the erase operation is completed.

  In the present embodiment, the voltage Vr is set to the same voltage as the voltage Vs, but the voltage Vr may be a voltage different from the voltage Vs.

  In the subsequent address period of the second subfield SF2, which is the first type subfield, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn. This is different from the writing period of the first subfield SF1, which is the second type subfield. Then, voltage 0 (V) is applied to data electrode D1 through data electrode Dm, and voltage Vc is applied to scan electrode SC1 through scan electrode SCn.

  Next, a scan pulse of voltage Va is applied to scan electrode SC1 in the first row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light. As a result, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is obtained by adding the positive wall voltage on the data electrode Dk to the difference between the externally applied voltages (Vd−Va), and the discharge start voltage VFds. Exceed. Then, a discharge is generated between data electrode Dk and scan electrode SC1. Further, since voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn during this address period, the discharge generated between data electrode Dk and scan electrode SC1 extends between scan electrode SC1 and sustain electrode SU1. Thus, an address discharge occurs in subfield SF2, positive wall voltage is accumulated on scan electrode SC1, negative wall voltage is accumulated on sustain electrode SU1, and negative wall voltage is also accumulated on data electrode Dk. Voltage is accumulated.

  Thus, an address operation is performed in which an address discharge is generated in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrode Dh to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage VFds, so the address discharge does not occur.

  Next, a scan pulse is applied to scan electrode SC2 in the second row, and an address pulse is applied to data electrode Dk corresponding to the discharge cell to emit light. As a result, an address discharge is generated between data electrode Dk and scan electrode SC2, and between sustain electrode SU2 and scan electrode SC2, and a positive wall voltage is accumulated on scan electrode SC2, and on sustain electrode SU2. A negative wall voltage is accumulated, and a negative wall voltage is also accumulated on the data electrode Dk. In this way, an address operation is performed in which an address discharge is generated in the discharge cell to emit light in the second row and a wall voltage is accumulated on each electrode. On the other hand, since the voltage at the intersection between the data electrode Dh and the scan electrode SC2 to which no address pulse is applied does not exceed the discharge start voltage VFds, no address discharge occurs.

  Thereafter, the same address operation is performed until the scan electrode SCn in the n-th row, and wall charges necessary for the subsequent sustain discharge are formed.

  In the sustain period of second subfield SF2, voltage 0 (V) is applied to data electrode D1 to data electrode Dm, voltage 0 (V) is applied to sustain electrode SU1 to sustain electrode SUn, and scan electrode SC1 to scan electrode. A sustain pulse of voltage Vs is applied to SCn. As a result, in the discharge cell in which the address discharge is generated in the address period of the second subfield SF2, the voltage difference between the scan electrode SCi and the sustain electrode SUi is the voltage Vs to the wall voltage on the scan electrode SCi and the sustain electrode SUi. The difference from the upper wall voltage is added, and exceeds the discharge start voltage VFss between scan electrode SCi and sustain electrode SUi. Then, a sustain discharge is generated between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Furthermore, a positive wall voltage is also accumulated on the data electrode Dk. On the other hand, the sustain discharge does not occur in the discharge cell in which the address discharge has not occurred, and the wall voltage at the end of the immediately preceding subfield is maintained.

  Subsequently, voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn, and a sustain pulse of voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. As a result, the sustain discharge occurs again in the discharge cell that has generated the sustain discharge, and the phosphor layer 35 emits light. Then, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi. In the same manner, sustain pulses of the number corresponding to the luminance weight are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and the sustain discharge is continued in the discharge cell that has generated the address discharge. generate.

  In the subsequent erasing period of second subfield SF2, voltage 0 (V) is applied to data electrode D1 to data electrode Dm, voltage 0 (V) is applied to sustain electrode SU1 to sustain electrode SUn, and scan electrode SC1 is applied. Upward ramp waveform voltage L3 that gently rises from voltage 0 (V) to voltage Vr is applied to scan electrode SCn. As a result, a weak erasing discharge occurs between scan electrode SCi and sustain electrode SUi in the discharge cell that has undergone the sustain discharge. Then, the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. When the rising ramp waveform voltage L3 reaches the voltage Vr, the voltage applied to scan electrode SC1 through scan electrode SCn is then lowered to voltage 0 (V).

  Thereafter, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and downward ramp waveform voltage L4 that gently falls from voltage 0 (V) to voltage Vi is applied to scan electrode SC1 through scan electrode SCn. As a result, a weak discharge is generated again in the discharge cell that has generated the weak erasing discharge, and an excessive portion of the wall voltage on the scan electrode SCi, the sustain electrode SUi, and the data electrode Dk is discharged, The wall voltage is adjusted to be suitable for the write operation. In this way, the erase operation is completed.

  The operations in the third subfield SF3 to the eleventh subfield SF11 as the first type subfield are the same as the operations in the second subfield SF2 except for the number of sustain pulses.

  In this embodiment, the voltage Vc is −145 (V), the voltage Va is −280 (V), the voltage Vs is 200 (V), the voltage Vg is −200 (V), the voltage Vr is 200 (V), The voltage Vi is −260 (V), the voltage Ve is 20 (V), and the voltage Vd is 60 (V). The slopes of the rising ramp waveform voltage L1 and the rising ramp waveform voltage L3 are set between 1 to 10 (V / μsec) (for example, 1.3 (V / μsec)), the falling ramp waveform voltage L2, and the falling ramp waveform. The gradient of the voltage L4 is set between −1 and −10 (V / μsec) (for example, −1.3 (V / μsec)). However, these voltage values are merely examples, and are not limited to the values described above, and are desirably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device. Further, with respect to the downward ramp waveform voltage L2 and the downward ramp waveform voltage L4, for example, the voltage is lowered with a steep slope until just before the discharge occurs, and then the slope is gradually lowered during the period when the discharge is occurring. The configuration may be such that the gradient is changed halfway, such as by lowering the voltage.

  In the above description of the wall voltage, the wall voltage on each electrode is shown assuming a reference potential of wall voltage 0 (V) inside the discharge cell space. However, what is important in considering the wall voltage is, as is well known, the difference in the wall voltage between the electrodes, and the change in the wall voltage on each electrode.

  Further, the discharge start voltage VFds and the discharge start voltage VFsd of the panel 10 used in the present embodiment are measured by the methods described later, and their values are as follows.

  The discharge start voltage varies depending on the phosphor. When the inventor measured the panel 10, the discharge start voltage VFds between the “data electrode 32 and the scan electrode 22” was 200 ± 10 (V) in the discharge cell coated with the red phosphor, and the discharge start voltage was The VFsd was 320 ± 10 (V). In the discharge cell coated with green phosphor, the discharge start voltage VFds between “data electrode 32 and scan electrode 22” is 220 ± 10 (V), and the discharge start voltage VFsd is 350 ± 10 (V). there were. In the discharge cell coated with blue phosphor, the discharge start voltage VFds between “data electrode 32 and scan electrode 22” is 200 ± 10 (V), and the discharge start voltage VFsd is 330 ± 10 (V). there were. Further, the discharge start voltage VFss between “scan electrode 22 and sustain electrode 23” is 250 ± 10 (V) in the discharge cell coated with red and blue phosphors, and the discharge cell coated with green phosphor. It was 280 ± 10 (V).

  In the present embodiment, the voltage on the low voltage side of the sustain pulse is voltage 0 (V), and the voltage applied to the data electrode 32 in the sustain period is voltage 0 (V), so the first voltage V1 is the voltage 0 (V). Further, since the low voltage side of the scan pulse is the voltage Va and the low voltage side voltage of the write pulse is the voltage 0 (V), the third voltage V3 is the voltage Va (−280 (V)). Further, the discharge start voltage VFds is larger in the discharge cell coated with the green phosphor than the other discharge cells, and its maximum value is the voltage 230 (V) in consideration of variation.

As described above, (Condition 1) is (V1−V3) ≧ VFds. And (first voltage V1−third voltage V3) = 0−Va = 280 (V),
(The maximum value of VFds) = 230 (V). That is,
(First voltage V1−third voltage V3)> (maximum value of VFds), and it is understood that (condition 1) is satisfied in all discharge cells.

  Further, since the high voltage side of the sustain pulse is the voltage Vs and the voltage applied to the data electrode 32 in the sustain period is the voltage 0 (V), the second voltage V2 is the voltage Vs (200 (V)). Further, the discharge start voltage VFsd is smaller in the discharge cell coated with the red phosphor than the other discharge cells, and its minimum value is the voltage 310 (V) in consideration of variation. The discharge start voltage VFds is smaller in discharge cells coated with red and blue phosphors than other discharge cells, and its minimum value is a voltage 190 (V) in consideration of variation. Therefore, the minimum value of the sum of the discharge start voltage VFsd and the discharge start voltage VFds is the voltage 500 (V).

As described above, (Condition 2) is (V2−V3) <(VFds + VFsd). And
Since (second voltage V2−third voltage V3) = Vs−Va = (200 + 280) (V) and the minimum value of (VFds + VFsd) = 500 (V), 480 (V) <500 (V ) That is,
The minimum value of (second voltage V2−third voltage V3) <(VFds + VFsd) is satisfied, and it is understood that (condition 2) is satisfied in all discharge cells.

  Thus, in the present embodiment, the drive voltage waveform applied to each electrode, particularly the voltage Va of the scan pulse is set so as to satisfy (Condition 1) and (Condition 2). By doing so, the write operation can be stably generated without using the forced initialization operation. The reason is considered as follows.

  First, (Condition 1) will be described. In order to generate the address discharge, it is necessary to start the discharge between the data electrode Dj and the scan electrode SCi. In order to start a discharge by applying a relatively low voltage Vd to the data electrode Dj, a voltage substantially equal to the discharge start voltage VFds is applied between the data electrode Dj and the scan electrode SCi when a scan pulse is applied to the scan electrode SCi. A sufficient wall voltage must be stored on the data electrode Dj so that it is applied in between.

  As described above, in this embodiment, the forced initialization operation is not performed. Therefore, since no discharge is generated in the discharge cell displaying black, the wall voltage of the discharge cell tends to be indefinite. However, even in such a discharge cell, if there are a few charged particles in the discharge space, they move to each electrode so as to relax the electric field inside the discharge space and adhere to the wall of the discharge cell. To accumulate wall voltage.

  The wall voltage accumulated in this way will be described. In the sustain period, a large amount of charged particles are generated in the discharge cell that generates the sustain discharge. For this reason, it is considered that a small amount of charged particles are supplied to the space inside the discharge cell that displays black without generating a sustain discharge by diffusing into the peripheral discharge cells. In a discharge cell that does not generate discharge (displays black), the wall voltage is slowly applied so as to alleviate the potential difference between the electrodes due to the voltages applied to scan electrode SCi, sustain electrode SUi, and data electrode Dj. Accumulate. At this time, if the voltage at which the wall voltage is asymptotic (finally settled) is defined as the neglected wall voltage, the neglected wall voltage when the sustain pulse is alternately applied to the scan electrode SCi and the sustain electrode SUi is It is an intermediate voltage between the high voltage and the low voltage. Actually, since the drive voltage waveform other than the sustain pulse is also applied to the discharge cell, it is considered that the neglected wall voltage of each discharge cell is substantially close to the low-voltage side voltage of the sustain pulse.

  In addition, the neglected wall voltage is greatly affected by the charging characteristics of the phosphor applied inside the discharge cell. In this embodiment, the charging characteristics of the phosphor are +20 (μC / g) for the red phosphor, −30 (μC / g) for the green phosphor, and +10 (μC / g) for the blue phosphor, respectively. Since only the green phosphor is charged to a negative potential, the neglected wall voltage is lower than that of the red and blue phosphors.

  Next, the voltage inside the discharge cell in the address period will be described. On the data electrode Dj of the discharge cell that does not perform the write discharge (displays black), the wall voltage is gradually accumulated toward the low-voltage side voltage of the sustain pulse or the neglected wall voltage close thereto. On the other hand, the voltage Va of the scan pulse in the present embodiment is a voltage that satisfies (Condition 1). Therefore, a wall voltage sufficient to generate the address discharge is accumulated on the data electrode Dj, and the address discharge can be generated without performing any forced initialization operation.

  Further, the wall voltage of the discharge cell displaying black gradually approaches the left wall voltage. When the voltage obtained by adding the wall voltage to the voltage between the “data electrode 32 and the scan electrode 22” approaches the discharge start voltage in the erasing period, dark current (current that flows in a state where no discharge occurs) flows, and the wall on the data electrode Dj Reduce voltage. The dark current that flows at this time plays a role of priming particles that help to generate the address discharge. Therefore, it is considered that even a discharge cell displaying black can generate a stable address discharge without causing a large discharge delay.

  As described above, in this embodiment, by setting the driving voltage applied to each electrode so as to satisfy (Condition 1), the voltage Va of the scan pulse is particularly set low so as to satisfy (Condition 1). Accordingly, the wall voltage necessary for the address discharge can be accumulated in the discharge cell without performing the forced initializing operation before the address period, and priming particles that stabilize the address discharge can be generated.

  Next, (Condition 2) will be described. If the voltage Va of the scan pulse is too low, a discharge occurs even in a display cell that is not performing an address operation when the sustain pulse voltage Vs is applied to the scan electrode SCn in the sustain period. In order to suppress this erroneous discharge, each voltage must be set so that the voltage between the “data electrode 32 and the scan electrode 22” becomes equal to or lower than the discharge start voltage VFsd when the sustain pulse voltage Vs is applied. I must. This condition is (Condition 2).

  Thus, in the present embodiment, the drive voltage waveform is set so as to satisfy (Condition 1) and (Condition 2) in all the discharge cells. Therefore, the write operation can be stably generated even if the forced initialization operation is omitted. As a result, it is possible to display an image without causing light emission not related to gradation display. That is, according to the present embodiment, a stable writing operation can be performed without performing a forced initialization operation, black luminance can be suppressed, and an image with high contrast can be displayed on the panel 10.

  In the present embodiment, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn in the sustain period of first subfield SF1, which is the second type subfield, and data electrode D1 through data electrode Dm are applied. A voltage 0 (V) is applied to the scan electrode SC1, and an upward ramp waveform voltage L1 rising from the voltage 0 (V) to the voltage Vs is applied to scan electrode SC1 through scan electrode SCn. Then, after the voltage applied to scan electrode SC1 through scan electrode SCn rises to voltage Vs, voltage Vs is further applied for a certain period. Subsequently, voltage 0 (V) is continuously applied to sustain electrode SU1 through sustain electrode SUn, voltage Vd is applied to data electrode D1 through data electrode Dm, and voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn. ) To the voltage Vg, a downward ramp waveform voltage L2 is applied. Thereby, a weak sustain discharge can be generated as compared with the sustain discharge by the sustain pulse.

  Further, in the present embodiment, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn in the address period. That is, the voltage applied to sustain electrode SU1 through sustain electrode SUn in the second type subfield address period is lower than the voltage applied to sustain electrode SU1 through sustain electrode SUn in the first type subfield address period. . As a result, the discharge generated between data electrode Dk and scan electrode SC1 does not extend to sustain electrode SU1, and the luminance of light emission associated with the address discharge can be suppressed.

  With these driving operations, the luminance displayed in the first subfield SF1 can be suppressed lower than the subfield having the luminance weight “1”. In the present embodiment, the luminance displayed by the first subfield SF1 is about ¼ of the luminance displayed by the subfield in which the sustain pulse is applied to each electrode of the display electrode pair 24 once.

  In addition, the discharge start voltage VFsd, the discharge start voltage VFds, and the wall voltage can be easily measured by, for example, the method described below.

  FIG. 5 is a diagram illustrating an example of a method for simply measuring the discharge start voltage.

  First, an operation for erasing wall charges is performed. Specifically, as shown in the wall charge erasing period in FIG. 5, a pulse voltage Vers sufficiently higher than the expected discharge start voltage is alternately applied between the electrodes to be measured, for example, the data electrode 32 and the scan electrode 22. Apply to. Next, the discharge start is observed. Specifically, as shown in the measurement period of FIG. 5, a pulsed voltage Vmsr lower than the expected discharge start voltage is applied to one electrode (for example, the data electrode 32). Then, the light emission accompanying the discharge at that time is detected by using a light detection sensor such as a photomultiplier.

  When no light emission is observed, no discharge has occurred, so after performing the operation to erase the wall charge again during the wall charge elimination period, the pulse whose absolute value of the voltage was slightly increased from the previous time during the measurement period Is applied to the same electrode (for example, the data electrode 32) to observe light emission.

  This operation is repeated until luminescence is observed. Thus, the absolute value of the minimum voltage Vmsr in which light emission is observed in the measurement period is the discharge start voltage. At this time, if the voltage Vmsr applied in the measurement period is a positive voltage, the discharge start voltage VFds of the discharge with the data electrode 32 as the anode and the scan electrode 22 as the cathode can be measured. Further, when the voltage Vmsr applied in the measurement period is a negative voltage, the discharge start voltage VFsd of the discharge having the data electrode 32 as a cathode and the scan electrode 22 as an anode can be measured.

  If the discharge start voltage is known, the voltage at which discharge starts is measured for the discharge cell in which the wall voltage is accumulated, and the wall voltage can be known as the difference between the voltage value and the discharge start voltage measured in advance. .

  Alternatively, the discharge start voltage VFsd, the discharge start voltage VFds, and the wall voltage can be calculated according to IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-24, NO. 7, JULY, 1977 “Measurement of a Plasma in the AC Plasma Display panel Using RF Capacitance and Microwave Techniques” and the like.

  Next, a drive circuit for driving the panel 10 will be described. FIG. 6 is a circuit block diagram of plasma display device 1 in accordance with the first exemplary embodiment of the present invention.

  The plasma display apparatus 1 uses a panel 10 having a plurality of discharge cells each having a scan electrode 22, a sustain electrode 23, and a data electrode 32, and a plurality of subfields each having an address period, a sustain period, and an erase period. And a drive circuit that generates the drive voltage waveform shown in FIG. 3 and applies it to each electrode of the panel 10 to drive the panel 10.

  The drive circuit supplies necessary power to the image signal processing circuit 41, the data electrode drive circuit 42, the scan electrode drive circuit 43, the sustain electrode drive circuit 44, the timing generation circuit 45, the first image detection circuit 46, and each circuit block. Power supply circuit (not shown).

  The image signal processing circuit 41 assigns a gradation value to each discharge cell based on the input image signal. Then, each gradation value is converted into image data indicating light emission / non-light emission for each subfield. The image signal includes, for example, a red primary color signal R, a green primary color signal G, and a blue primary color signal B.

  FIG. 7 is a circuit block diagram of the image detection circuit 46 according to Embodiment 1 of the present invention. The image detection circuit 46 has an APL detection circuit 55. The APL detection circuit 55 detects an average luminance level (hereinafter referred to as “APL”; APL: Average Picture Level) from the luminance signal output from the image signal processing circuit 41. The APL detection circuit 55 cumulatively adds the magnitude of the luminance signal assigned to each pixel over one screen of pixels (for example, 1920 × 1080 pixels). Then, the addition result is divided by the number of pixels for one screen and further divided by the maximum value of the luminance signal to normalize. Therefore, the value output from the APL detection circuit 55 is 0% when the entire screen is a black image and 100% when the entire screen is white. The image detection circuit 46 detects APL and outputs the result to the timing generation circuit 45.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal, the vertical synchronization signal, and the output from the image detection circuit 46. Then, the generated timing signal is supplied to each circuit block. The data electrode drive circuit 42 converts the image data for each subfield into address pulses corresponding to the data electrodes D1 to Dm. Based on the timing signal supplied from the timing generation circuit 45, an address pulse is applied to each of the data electrodes D1 to Dm.

  Scan electrode drive circuit 43 includes a sustain pulse generation circuit and a scan pulse generation circuit. The sustain pulse generating circuit generates a sustain pulse to be applied to scan electrode SC1 through scan electrode SCn during the sustain period. The scan pulse generation circuit includes a plurality of scan electrode driving ICs (scan ICs), and generates scan pulses to be applied to scan electrode SC1 through scan electrode SCn in the address period. Scan electrode drive circuit 43 generates the above-described drive voltage waveform based on the timing signal supplied from timing generation circuit 45, and applies it to each of scan electrode SC1 through scan electrode SCn.

  Sustain electrode drive circuit 44 includes a sustain pulse generation circuit, generates the drive voltage waveform described above based on the timing signal supplied from timing generation circuit 45, and applies it to sustain electrode SU1 through sustain electrode SUn.

  In the present embodiment, when the APL detected by the first image detection circuit 46 is equal to or higher than the first average luminance level threshold value, the discharge cell is forcibly lit in the second type subfield. The circuit 45 generates a timing signal and supplies it to the data electrode driving circuit 42. In response to the timing signal from the timing generation circuit 45, the data electrode driving circuit 42 generates an address pulse so that an address discharge is generated in the discharge cell in the second type subfield regardless of the image data from the image signal processing circuit 41. Applied to the data electrode 32. This forcibly turns on the discharge cell in the second type subfield. The details will be described below.

  FIG. 8 is a diagram showing the relationship between APL and second-type subfield forced lighting in Embodiment 1 of the present invention. In FIG. 8, the vertical axis represents the lighting rate when the discharge cells are forcibly lighted during the sustain period of the second type subfield, and the horizontal axis represents the APL detected by the image detection circuit 46. In the following description, for example, when the second type subfield is turned on, it is expressed as “turn on the second type subfield”.

  As shown in FIG. 8, in the first embodiment, if the APL detected by the image detection circuit 46 is less than the first average luminance level threshold (for example, APL 15%), the second type sub-field in the field is used. The field (in this embodiment, the first subfield SF1 in FIG. 3) is not forcibly lit, and the lighting of the second type subfield is controlled based on the image signal.

  If APL detected by image detection circuit 46 is equal to or greater than a second average luminance level threshold value (for example, APL 25%), the second type subfield (in this embodiment, first subfield SF1 in FIG. 3). Are forcibly lit at a predetermined lighting rate (for example, 50%) set in advance.

  If the APL detected by the image detection circuit 46 is greater than or equal to the first average luminance level threshold value and less than the second average luminance level threshold value, the second type subfield (book) is selected according to the APL of the detected image signal. In the embodiment, the number of discharge cells forcibly lit in the first subfield SF1) is controlled. In this embodiment, the larger the APL of the image signal, the higher the lighting rate of the discharge cells that are forcibly lit in the second type subfield.

  In the present embodiment, the discharge cells are forcibly lit only in the second type subfield, and in the first type subfield (in this embodiment, the subfield excluding the first subfield SF1). The discharge cell is not forcibly lit.

  When the lighting rate when forcibly lighting the second type subfield is set to 50%, in the image display area of panel 10, the discharge cells (lighted cells) that are lit and the discharge cells (lighted cells that are not lit) ( It is desirable to prevent each of the regions where non-lighted cells) are concentrated. Specifically, the lighting cell and the non-lighting cell are adjacent to each other (so that the row direction and the column direction are the lighting cell, the non-lighting cell, the lighting cell, the non-lighting cell,...) In addition, it is desirable to generate an address pulse so that the lit cell and the non-lit cell alternate every field. The same applies to the other lighting rates, and the lighted cells are generated in a distributed manner so that a region where the lighted cells are concentrated and a region where the non-lighted cells are concentrated are not generated. It is desirable to change the lighting cells for each field so that all the discharge cells in the image display area in the panel 10 are uniformly lit during the second).

  The first average luminance level threshold value and the second average luminance level threshold value may be set to the same numerical value. In this case, if the detected APL is less than the first average luminance level, the second type subfield is not forcibly lit, and the second type subfield is lit or not lit based on the image signal. To control. If the detected APL is equal to or higher than the first average luminance level, the second type subfield is forcibly lit at a predetermined lighting rate determined in advance.

  In the present embodiment, the second type subfield is forcibly lit according to the APL detected by the image detection circuit 46 for the following reason.

  In this embodiment, as described above, the forced initialization operation is not performed. Therefore, when a black image in which the entire screen is black is displayed on the panel 10, no discharge is generated in the discharge cells.

  If the continuous display time of the black image is short, there is no particular problem. However, if the continuous display time of the black image is long (for example, 120 minutes or more), the time during which no discharge occurs in the discharge cell is long. Wall charges and priming particles are greatly reduced. For this reason, when switching from a black image to a normal image (an image in which light emission occurs in the discharge cells), the address discharge becomes unstable for a short period of time (for example, several fields), and the image display quality during that time becomes unstable. May deteriorate.

  However, if a discharge is generated in the discharge cell before the wall charge and priming particles in the discharge cell are greatly reduced, the wall charge and priming particles are recovered, and this phenomenon can be prevented from occurring.

  Further, as described above, the light emission luminance in the second type subfield is weak and lower than the light emission luminance in the subfield having the luminance weight “1”. Therefore, if the APL of the image displayed on the panel is more than a certain level, even if only the second type subfield is forcibly turned on, it is difficult for the user to recognize the change in black luminance.

  Therefore, in the present embodiment, if the APL detected by the first image detection circuit 46 is greater than the APL that can be determined to be sufficiently large and the second average luminance level threshold value, the second type subfield is It shall be forcibly lit at a predetermined lighting rate determined in advance. Further, when the APL detected by the image detection circuit 46 is equal to or higher than the first average luminance level and lower than the second average luminance level, the lighting rate is increased as the detected APL increases within the range of the lighting rate 0% to the predetermined lighting rate. It is assumed that the second type subfield is forcibly turned on by enlarging.

  As a result, when the APL is sufficiently large and it is difficult for the viewer to recognize the change in black luminance, the second type subfield is forcibly lit to prevent the wall charges and priming particles in the discharge cells from decreasing. it can. Therefore, even when the continuous display time of the black image becomes long, the wall charge and priming particles in the discharge cell are prevented from decreasing, so that the address discharge is stabilized when the black image is switched to the normal image. It is possible to prevent the image display quality from deteriorating.

  The timing generation circuit 45 in the present embodiment compares the APL information output from the image detection circuit 46 with the first average luminance level threshold value and the second average luminance level threshold value set in advance. A comparison circuit is provided inside. The timing generation circuit 45 generates a timing signal for forcibly lighting the second type subfield based on the comparison result in the comparison circuit, and supplies the timing signal to the data electrode drive circuit 42.

  Then, based on the timing signal supplied from the timing generation circuit 45, the data electrode driving circuit 42 applies an address pulse to each of the data electrodes D1 to Dm. As a result, the second type subfield is forcibly lit in the discharge cells corresponding to the lighting rate according to APL.

  In the present embodiment, when the APL detected by the image detection circuit 46 is between the first average luminance level threshold and the second average luminance level threshold, the second type is selected according to the detected APL. The lighting rate of the subfield is changed. This is because, as the APL becomes smaller, the change in the black luminance is more easily recognized by the user, and therefore it is desirable to lower the emission luminance when the second type subfield is forcibly lit according to the APL.

  Note that the number of times one discharge cell emits light per unit time (for example, 1 second) decreases as the lighting rate decreases. When the second type subfield is forcibly lit, the number of times one discharge cell emits light per unit time (for example, 1 second) is, for example, half when the lighting rate is 50% when the lighting rate is 25%, When the lighting rate is 10%, it is one fifth of that when the lighting rate is 50%. Therefore, if the lighting rate when the second type subfield is forcibly lit decreases, the emission luminance decreases accordingly, and the black luminance also decreases. On the other hand, the effect of replenishing wall charges and priming particles in the discharge cell is reduced as the number of occurrences of the discharge is reduced. However, as described above, the address discharge may become unstable when switching from a black image to a normal image when the black image is displayed continuously for a long time (for example, 120 minutes or more). is there. Therefore, even if the lighting rate is low, a sufficient number of discharges are generated while displaying a black image continuously for such a long time, so that wall charges and priming particles can be sufficiently supplemented. it can.

  On the other hand, if the continuous display time of the black image is short, the wall charges and priming particles are less reduced, so the lighting rate when the second type subfield is forcibly lit is low and the number of discharges generated in the discharge cells Even if there is little, there is little possibility that the address discharge becomes unstable when switching from a black image to a normal image.

  It should be noted that the specific numerical values given as the first average luminance level threshold, the second average luminance level threshold, and the predetermined lighting rate in this embodiment are merely examples in the present embodiment, and the present invention. Is not limited to these values. For example, the magnitude of the second average luminance level is set to a value sufficiently larger than the above-described value, and the predetermined lighting rate when the second type subfield is forcibly lit is set to 100%, and the detected APL May be forcibly lit on all the discharge cells in the image display area of the panel 10 when is equal to or greater than the second average luminance level threshold value. Alternatively, the first average luminance level is set to APL 0%, and the second type subfield is forcibly lit at a lighting rate corresponding to the detected APL regardless of the APL. It may be. How to set the first average luminance level threshold, the second average luminance level threshold, and the predetermined lighting rate can be optimally set based on the characteristics of the panel, the specifications of the plasma display device, and the like. desirable.

  FIG. 9 is a circuit diagram of scan electrode drive circuit 43 of plasma display device 1 in the first exemplary embodiment of the present invention. Scan electrode drive circuit 43 includes sustain pulse generation circuit 50, ramp waveform voltage generation circuit 60, and scan pulse generation circuit 70, and operates each circuit based on a timing signal. Note that details of the timing signal are omitted in the drawings.

  Sustain pulse generation circuit 50 includes a power recovery circuit 51, a switching element Q55, a switching element Q56, and a switching element Q59. Then, sustain pulses to be applied to scan electrode SC1 through scan electrode SCn are generated. The power recovery circuit 51 recovers the power stored in the panel 10 from the panel 10 using LC resonance, and reuses the recovered power as power when driving the scan electrodes SC1 to SCn. The panel 10 is supplied again. Switching element Q55 clamps scan electrode SC1 through scan electrode SCn to voltage Vs, and switching element Q56 clamps scan electrode SC1 through scan electrode SCn to voltage 0 (V). The switching element Q59 is a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43.

  Scan pulse generation circuit 70 includes switching element Q71H1 to switching element Q71Hn, switching element Q71L1 to switching element Q71Ln, switching element Q72, a power supply for negative voltage Va, and a power supply E71 for generating voltage VC. The voltage VC is superimposed on the reference potential of the scan pulse generating circuit 70 (the potential at the node A shown in FIG. 9) to generate a voltage (Vc = VC + Va), and the scan electrode SC1 is switched while switching between the voltage Va and the voltage Vc. A scan pulse is generated by applying to scan electrode SCn. For example, if the voltage Va = −280 (V) and the voltage VC = 135 (V), the voltage Vc = −145 (V). Then, scan pulses are sequentially applied to scan electrode SC1 through scan electrode SCn at the timing shown in FIG. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 50 as it is during the sustain period. That is, the voltage at node A is output to scan electrode SC1 through scan electrode SCn.

  The ramp waveform voltage generation circuit 60 includes a Miller integration circuit 61 and a Miller integration circuit 63, and generates the ramp waveform voltage shown in FIG. Miller integrating circuit 61 includes transistor Q61, capacitor C61, and resistor R61, and applies a constant voltage to input terminal IN61 (giving a constant voltage difference between two circles shown as input terminal IN61). As a result, the rising ramp waveform voltage L3 and the rising ramp waveform voltage L1 (voltage Vs = voltage Vr) that gently rises toward the voltage Vr are generated. Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63, and applies a constant voltage to input terminal IN63 (giving a constant voltage difference between two circles shown as input terminal IN63). As a result, a downward ramp waveform voltage L4 that gradually decreases toward the voltage Vi is generated. Further, when the output voltage becomes equal to the voltage Vg, the operation of the Miller integrating circuit 63 is stopped (the voltage difference between two circles illustrated as the input terminal IN63 is set to 0 (V)), whereby the voltage Vg It is also possible to generate a downward ramp waveform voltage L2 that gradually decreases toward. The switching element Q69 is a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43.

  That is, scan electrode drive circuit 43 conducts switching element Q71L1 to switching element Q71Ln and switching element Q69 when applying upward ramp waveform voltage L3 that gradually rises to voltage Vr to scan electrode SC1 to scan electrode SCn. In this case, the Miller integrating circuit 61 is operated by applying a constant voltage to the input terminal IN61 (giving a constant voltage difference between two circles shown as the input terminal IN61). When voltage Vr and voltage Vs are set to the same voltage, ascending ramp waveform voltage L1 is applied to scan electrode SC1 through scan electrode SCn by the same operation as that for generating ascending ramp waveform voltage L3. be able to.

  When a downward ramp waveform voltage L4 that gently falls from voltage 0 (V) toward voltage Vi is applied to scan electrode SC1 through scan electrode SCn, a voltage of 0 (V) is applied to input terminal IN61 of Miller integrating circuit 61. Applied (the voltage difference between two circles shown as the input terminal IN61 is set to 0 (V)), the transistor Q61 is cut off (hereinafter referred to as “off”), the switching element Q56 is turned on, Voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn. Then, the switching element Q56 and the switching element Q69 are turned off, and a constant voltage is applied to the input terminal IN63 (giving a constant voltage difference between two circles shown as the input terminal IN63), and the Miller integrating circuit 63 To work. In addition, when the downward ramp waveform voltage L2 that gradually decreases from the voltage 0 (V) toward the voltage Vg is applied to the scan electrodes SC1 to SCn, the same operation as that for generating the downward ramp waveform voltage L4 is performed. When the output voltage becomes equal to the voltage Vg, the operation of Miller integrating circuit 63 is stopped (the voltage difference between two circles shown as input terminal IN63 is set to 0 (V)).

  In addition, these switching elements and transistors can be configured using generally known semiconductor elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the respective switching elements and transistors generated by the timing generation circuit 45.

  FIG. 10 is a circuit diagram of sustain electrode drive circuit 44 of plasma display device 1 in accordance with the first exemplary embodiment of the present invention. Sustain electrode drive circuit 44 includes sustain pulse generation circuit 80 and constant voltage generation circuit 85, and operates each circuit based on a timing signal. Note that details of the timing signal are omitted in the drawings.

  Sustain pulse generation circuit 80 includes a power recovery circuit 81, a switching element Q83, and a switching element Q84. Then, sustain pulses to be applied to sustain electrode SU1 through sustain electrode SUn are generated. The power recovery circuit 81 recovers the power stored in the panel 10 from the panel 10 using LC resonance, and reuses the recovered power as power when driving the sustain electrodes SU1 to SUn. The panel 10 is supplied again. Switching element Q83 clamps sustain electrode SU1 through sustain electrode SUn to voltage Vs, and switching element Q84 clamps sustain electrode SU1 through sustain electrode SUn to voltage 0 (V).

  Constant voltage generation circuit 85 includes switching element Q86 and switching element Q87, and applies voltage Ve to sustain electrode SU1 through sustain electrode SUn.

  In addition, these switching elements can also be comprised using generally known elements, such as MOSFET and IGBT. These switching elements are also controlled by timing signals corresponding to the respective switching elements generated by the timing generation circuit 45.

  FIG. 11 is a circuit diagram of data electrode drive circuit 42 of plasma display device 1 in accordance with the first exemplary embodiment of the present invention. Data electrode drive circuit 42 includes switching element Q91H1 to switching element Q91Hm and switching element Q91L1 to switching element Q91Lm. Then, based on the image data (details of the image data are omitted in the drawing), the switching element Q91Lj is turned on to apply the voltage 0 (V) to the data electrode Dj and the switching element Q91Hj is turned on. A voltage Vd is applied to the electrode Dj.

  Using such a drive circuit, the drive voltage waveform of the panel shown in FIG. 3 can be generated. However, the drive circuits shown in FIGS. 9 to 11 are examples, and the present invention is not limited to the circuit configurations of these drive circuits.

  As described above, according to the present embodiment, the forced initialization operation is used by generating the scan pulse satisfying (condition 1) and (condition 2) and applying the scan pulse to the scan electrode 22 in the address period. A stable write operation can be performed. As a result, it is possible to display an image with high contrast while suppressing black luminance on the panel 10. Furthermore, by applying a specific pulse without applying a sustain pulse during the sustain period, the second type subfield that emits light that is weaker than the light emission of the discharge by the sustain pulse is driven, so that the second lower level next to black is driven. The luminance of the tone can be reduced. Thereby, the gradation at the time of displaying a dark image can be improved, and image display quality can be improved.

  Further, APL is detected by the first image detection circuit 46, and the second type subfield is forcibly lit in accordance with this APL. Thereby, when the black image is switched to the normal image, the address discharge in the address period can be stably generated. In the present embodiment, in the plasma display device 1 that drives a subfield that is not provided with a forced initializing period, an image with high contrast and excellent gradation can be displayed on the panel 10 and black. When switching from an image to a normal image, it is possible to stably generate an address discharge to prevent deterioration of the image display quality, and to improve the image display quality of the plasma display device 1.

  It should be noted that the specific numerical values and the like shown in the first embodiment are merely examples, and are desirably set optimally according to the panel characteristics, the specifications of the plasma display device, and the like. Further, in the present embodiment, the configuration has been described in which the second type subfield is the first subfield SF1 which is the first subfield of the field, but the second type subfield is a subfield other than the first subfield SF1. It may be.

  Furthermore, in the present embodiment, a configuration has been described in which the first image detection circuit 46 detects APL and forcibly lights the second type subfield at a lighting rate corresponding to the detected APL. It is possible to forcibly turn on the two types of subfields and the subfield having the smallest luminance weight among the first type subfields (in this embodiment, the subfield SF2 having the luminance weight “1”). . In the present embodiment, a configuration in which one field includes a second type subfield and a plurality of first type subfields has been described. However, for example, one field is configured by only the first type subfield. Also good. In that case, the subfield having the smallest luminance weight (for example, the subfield having the luminance weight “1”) among the first-type subfields is forcibly lit at the lighting rate according to the detected APL. It is desirable to do.

(Embodiment 2)
Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 12 is a circuit block diagram of plasma display device 2 in the second exemplary embodiment of the present invention.

  The plasma display device 2 includes a panel 10 and a driving circuit that generates the driving voltage waveform shown in FIG. 3 and applies the waveform to each electrode of the panel 10 to drive the panel 10. In the present embodiment, the same reference numerals are given to circuit blocks that perform the same operation as the circuit included in the plasma display device 1 shown in the first embodiment, and the description thereof is omitted. The drive circuit supplies necessary power to the image signal processing circuit 41, the data electrode drive circuit 42, the scan electrode drive circuit 43, the sustain electrode drive circuit 44, the timing generation circuit 45, the second image detection circuit 47, and each circuit block. Power supply circuit (not shown).

  The plasma display device 2 shown in the present embodiment has almost the same configuration as the plasma display device 1 shown in the first embodiment, except that the configuration of the second image detection circuit 47 is the first configuration shown in FIG. This is different from the image detection circuit 46.

  FIG. 13 is a circuit block diagram of the second image detection circuit 47 in the second embodiment of the present invention. The second image detection circuit 47 includes a signal level detection circuit 91, a comparison circuit 92, and a predetermined pixel number counting circuit 93.

  The signal level detection circuit 91 detects the signal level of the image data for each pixel. The signal calculated by the signal level detection circuit 91 is compared with the signal level threshold value by the comparison circuit 92 for each pixel, and the comparison result is output to the predetermined pixel number counting circuit 93.

  The predetermined pixel number counting circuit 93 counts the number of pixels equal to or higher than the signal level threshold based on the output of the comparison circuit 92, normalizes the result to a rate, and outputs the result as a pixel lighting rate. When all the pixels are equal to or higher than the signal level threshold, the pixel lighting rate is 100%, and when all the pixels are equal to or lower than the signal level threshold, the pixel lighting rate is 0%.

  That is, the image detection circuit 47 detects the ratio of the number of pixels equal to or greater than the signal level threshold to the number of pixels on the entire screen, and outputs the result to the timing generation circuit 45 as the pixel lighting rate.

  In the second embodiment, when the pixel lighting rate detected by the second image detection circuit 47 is equal to or higher than the first pixel lighting rate threshold, the discharge cell is forcibly turned on in the second type subfield. A timing signal is generated in the timing generation circuit 45 and supplied to the data electrode driving circuit 42. The data electrode drive circuit 42 receives the timing signal, and regardless of the image data from the image signal processing circuit 41, the address discharge is performed on the discharge cells in the second type subfield (first subfield SF1 in the present embodiment). An address pulse is generated so as to be generated and applied to the data electrode 32. This forcibly turns on the discharge cell in the second type subfield. The details will be described below.

  FIG. 14 is a diagram showing a relationship between APL and second-type subfield forced lighting in Embodiment 2 of the present invention. In FIG. 14, the vertical axis represents the lighting rate when the discharge cells are forcibly turned on in the second type subfield, and the horizontal axis represents the pixel lighting rate detected by the second image detection circuit 47. Hereinafter, for example, when the discharge cell is turned on in the second type subfield, it is expressed as “turn on the second type subfield”.

  As shown in FIG. 14, in the present embodiment, if the pixel lighting rate detected by the second image detection circuit 47 is less than the first pixel lighting rate threshold (for example, 30%), the second type The subfield (first subfield SF1 in the present embodiment) is not forcibly lit, and the second type subfield (first subfield SF1 in the present embodiment) of the second subfield (in the present embodiment) is not forcedly lit. Controls lighting and non-lighting.

  If the pixel lighting rate detected by the image detection circuit 47 is equal to or higher than the second pixel lighting rate threshold (for example, 50%), the second type subfield (first subfield SF1 in the present embodiment) is set. The light is forcibly lit at a predetermined lighting rate (for example, 50%) set in advance.

  If the pixel lighting rate detected by the second image detection circuit 47 is equal to or higher than the first pixel lighting rate threshold and lower than the second pixel lighting rate threshold, the lighting rate corresponding to the detected pixel lighting rate is used. That is, in the range of the lighting rate from 0% to the predetermined lighting rate, the larger the detected APL, the larger the lighting rate, and the second type subfield (first subfield SF1 in the present embodiment) is forced. Lights up.

  In the present embodiment, the discharge cells are forcibly lit only in the second type subfield, and in the first type subfield (in this embodiment, the subfield excluding the first subfield SF1). The discharge cell is not forcibly lit.

  Note that the first pixel lighting rate threshold value and the second pixel lighting rate threshold value may be set to the same numerical value. In that case, if the detected pixel lighting rate is less than the first pixel lighting rate, the second type subfield is not forcibly turned on, and the second type subfield is turned on based on the image signal. Controls non-lighting. If the detected pixel lighting rate is equal to or higher than the first pixel lighting rate, the second type subfield is forcibly lit at a predetermined lighting rate determined in advance.

  In the present embodiment, the second type subfield is forcibly lit according to the pixel lighting rate detected by the second image detection circuit 47 for the following reason.

  As described in the first embodiment, the light emission luminance in the second type subfield is weak and lower than the light emission luminance in the subfield having the luminance weight “1”. Therefore, if the pixel lighting rate is larger than a certain level, even if only the second type subfield is forcibly lit, the change in black luminance is difficult for the user to recognize.

  Therefore, in the present embodiment, if the pixel lighting rate detected by the second image detection circuit 47 is a pixel lighting rate that can be determined to be sufficiently high, that is, the second pixel lighting rate threshold value or more, the second The seed subfield is forcibly lit at a predetermined lighting rate determined in advance. Further, when the APL detected by the second image detection circuit 47 is equal to or higher than the first pixel lighting rate threshold and lower than the second pixel lighting rate threshold, the detection is performed within a range of the lighting rate from 0% to a predetermined lighting rate. It is assumed that the higher the pixel lighting rate is, the higher the lighting rate is, and the second type subfield is forcibly lit.

  As a result, when the pixel lighting rate is sufficiently large and it is difficult for the panel viewer to recognize the change in black luminance, the second type subfield is forcibly lit to reduce wall charges and priming particles in the discharge cells. Can be prevented. Therefore, even when the continuous display time of the black image becomes long, the wall charge and priming particles in the discharge cell are prevented from decreasing, so that the address discharge is stabilized when switching from the black image to the normal image. It is possible to prevent the image display quality from deteriorating.

  Note that the timing generation circuit 45 in the present embodiment calculates the pixel lighting rate information output from the second image detection circuit 47, the preset first pixel lighting rate threshold value, and the second pixel lighting rate. A comparison circuit for comparing the threshold value is provided inside. The timing generation circuit 45 generates a timing signal for forcibly lighting the second type subfield based on the comparison result in the comparison circuit, and supplies the timing signal to the data electrode drive circuit 42.

  Then, based on the timing signal supplied from the timing generation circuit 45, the data electrode driving circuit 42 applies an address pulse to each of the data electrodes D1 to Dm. Thus, the second type subfield is forcibly lit at a lighting rate corresponding to the pixel lighting rate. When the pixel lighting rate detected by the second image detection circuit 47 is between the first pixel lighting rate threshold value and the second pixel lighting rate threshold value, the second type subfield is set according to the detected pixel lighting rate. The lighting rate is changed. This is because, as the pixel lighting rate decreases, the change in black luminance is more easily recognized by the user, and therefore it is desirable to lower the emission luminance when forcibly lighting the second type subfield in accordance with the pixel lighting rate. is there.

  The specific numerical values given as the first pixel lighting rate threshold value, the second pixel lighting rate threshold value, and the predetermined lighting rate in the second embodiment are merely examples in the present embodiment. The invention is not limited to these numerical values. For example, the magnitude of the second pixel lighting rate threshold is set to a value sufficiently larger than the above-mentioned value, and the predetermined lighting rate when the second type subfield is forcibly turned on is set to 100%. It is also possible to forcibly light all the discharge cells in the image display area of the panel 10 when the APL is equal to or greater than the second pixel lighting rate threshold value. Alternatively, the first pixel lighting rate threshold is set to 0%, and the second type subfield is forcibly set at a lighting rate corresponding to the detected APL, regardless of the pixel lighting rate. You may make it light up. How to set the first pixel lighting rate threshold, the second pixel lighting rate threshold, and the predetermined lighting rate can be optimally set based on the characteristics of the panel, the specifications of the plasma display device, and the like. desirable.

  Further, in the present embodiment, when the second type subfield is forcibly turned on and the image signal of the normal image is input to the image signal processing circuit 41, the second type subfield is forcibly turned on. It is assumed that the display is interrupted immediately and an image based on the image signal is displayed on the panel 10.

  As described above, in the present embodiment, in the plasma display device 2, it is possible to display an image with high contrast and excellent gradation on the panel 10 without providing a forced initialization period. At the same time, it is possible to stably generate an address discharge when switching from a black image to a normal image to prevent deterioration of the image display quality, and to improve the image display quality of the plasma display device 2.

(Embodiment 3)
Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 15 is a circuit block diagram of plasma display device 3 in accordance with the third exemplary embodiment of the present invention.

  The plasma display device 3 includes a panel 10 and a driving circuit that generates the driving voltage waveform shown in FIG. 3 and applies the waveform to each electrode of the panel 10 to drive the panel 10. In the present embodiment, the same reference numerals are given to circuit blocks that perform the same operation as the circuit included in the plasma display device 1 shown in the first embodiment, and the description thereof is omitted.

  The plasma display device 3 shown in the present embodiment has substantially the same configuration as the plasma display device 1 shown in the first embodiment, but the difference between the plasma display device 3 and the plasma display device 1 is the third image detection. The configuration of the circuit 48 is different from that of the first image detection circuit 46.

  FIG. 16 is a circuit block diagram of the third image detection circuit 48 according to Embodiment 3 of the present invention. The third image detection circuit 48 includes an APL detection circuit 101, a signal level detection circuit 102, a comparison circuit 103, and a predetermined pixel number counting circuit 104.

  The APL detection circuit 101 detects APL and outputs the result. The signal level detection circuit 102 detects the signal level for each pixel. The signal calculated by the signal level detection circuit 102 is compared with the signal level threshold value by the comparison circuit 103 for each pixel, and the comparison result is output to the predetermined pixel number counting circuit 104.

  The predetermined pixel number counting circuit 104 counts the number of pixels equal to or greater than the signal level threshold based on the output of the comparison circuit 103, and divides the result by the number of pixels for one screen and outputs it as a pixel lighting rate. When all the pixels are equal to or higher than the signal level threshold, the pixel lighting rate is 100%, and when all the pixels are equal to or lower than the signal level threshold, the pixel lighting rate is 0%. The third image detection circuit 48 detects the APL and the pixel lighting rate and outputs it to the timing generation circuit 45.

  In the present embodiment, when the APL detected by the third image detection circuit 48 is not less than the first average luminance level threshold value and the pixel lighting rate is not less than the first pixel lighting rate threshold value, the discharge cell is the second A timing signal is generated in the timing generation circuit 45 so as to forcibly light up in the seed subfield, and is supplied to the data electrode driving circuit 42. The data electrode drive circuit 42 receives the timing signal, and writes data so that address discharge occurs in the discharge cells in the second type subfield (first subfield SF1) regardless of the image data from the image signal processing circuit 41. A pulse is generated and applied to the data electrode 32. This forcibly turns on the discharge cell in the second type subfield. Hereinafter, for example, when the discharge cell is turned on in the second type subfield, it is expressed as “turn on the second type subfield”. The details will be described below.

  In Embodiment 3 of the present invention, the second-type subfield is forcibly lit at a lighting rate corresponding to the APL and the pixel lighting rate. An example of calculating the lighting rate will be described. First, the first forced lighting rate coefficient (hereinafter referred to as forced lighting rate coefficient A) according to APL, and the second forced lighting rate coefficient (hereinafter referred to as forced lighting rate coefficient B) according to the pixel lighting rate. calculate. A product obtained by multiplying the calculated forced lighting rate coefficient A, the forced lighting rate coefficient B, and a predetermined lighting rate set in advance is used as the lighting rate for forcibly lighting the second type subfield.

  FIG. 17 is a diagram showing the relationship between APL and forced lighting rate coefficient A in Embodiment 3 of the present invention. In FIG. 17, the horizontal axis represents the APL detected by the image detection circuit 48, and the vertical axis represents the second-type subfield forced lighting rate coefficient A. The forced lighting rate coefficient A is a value normalized so that the maximum value is 1.

  FIG. 18 is a diagram showing the relationship between the pixel lighting rate and the forced lighting rate coefficient B in Embodiment 3 of the present invention. In FIG. 18, the horizontal axis represents the pixel lighting rate detected by the image detection circuit 48, and the vertical axis represents the forced lighting rate coefficient B. The forced lighting rate coefficient B is a value normalized so that the maximum value is 1.

  As shown in FIG. 17, when the APL of the image signal detected by the image detection circuit 48 is less than the first average luminance level threshold value (less than 15% in the present embodiment), the forced lighting rate coefficient A becomes 0 and is detected. When the detected APL is equal to or higher than the second average luminance level threshold (25% or higher in the present embodiment), the forced lighting rate coefficient A is 1, and the detected APL is equal to or higher than the first average luminance level threshold. When the luminance level is less than the second average luminance level, the forced lighting rate coefficient A is a value corresponding to the detected APL, that is, the larger the APL detected between 0 and 1, the larger the value.

  As shown in FIG. 18, when the pixel lighting rate detected by the image detection circuit 48 is less than the first pixel lighting rate threshold value (less than 30% in the present embodiment), the forced lighting rate coefficient B becomes 0 and is detected. When the pixel lighting rate is equal to or higher than the second pixel lighting rate threshold value (50% or higher in this embodiment), the forced lighting rate coefficient B is 1, and the detected pixel lighting rate is the first pixel lighting rate threshold. When the pixel lighting rate coefficient B is greater than the threshold value and less than the second pixel lighting rate threshold value, the forced lighting rate coefficient B is a value corresponding to the detected pixel lighting rate, that is, the larger the pixel lighting rate detected between 0 and 1, the larger the value. Become.

In Embodiment 3, the lighting rate is
Forced lighting rate coefficient A × Forced lighting rate coefficient B × The second type subfield is forcibly turned on in the discharge cell based on the lighting rate calculated by the formula for calculating the predetermined lighting rate (hereinafter, this formula is used for calculating the lighting rate) Formula A), the APL detected by the third image detection circuit 48 is less than the first average luminance level threshold value, or the pixel lighting rate detected by the third image detection circuit 48 is the first pixel lighting rate. When the value is less than the threshold value, the second type subfield is not forcibly lit, and the second type subfield (first subfield SF1 in this embodiment) is lit or not lit based on the image signal. To control.

  This is because when the APL detected by the image detection circuit 48 is less than the first average luminance level threshold value, or when the pixel lighting rate detected by the image detection circuit 48 is less than the first pixel lighting rate threshold value, FIG. This is because one of the forced lighting rate coefficient A and the forced lighting rate coefficient B is 0 as shown in FIG. 18, and thus the lighting rate calculated by the lighting rate calculation formula C is 0.

  When the APL detected in the image detection circuit is equal to or higher than the second average luminance level threshold value and the pixel lighting rate detected in the image detection circuit is equal to or higher than the second pixel lighting rate threshold value, a predetermined lighting rate (for example, 50%), the second type subfield is forcibly turned on.

  This is shown in FIGS. 17 and 18 when the APL detected by the image detection circuit 48 is not less than the second average luminance level and the pixel lighting rate detected by the image detection circuit 48 is not less than the second pixel lighting rate threshold value. This is because, as shown, both the forced lighting rate coefficient A and the forced lighting rate coefficient B are 1, so that the lighting rate calculated by the lighting rate calculation formula C is a predetermined lighting rate.

  When the APL detected by the third image detection circuit 48 is not less than the first average brightness level and less than the second average brightness level, and the pixel lighting rate detected by the image detection circuit is not less than the first pixel lighting rate, and image detection When the APL detected in the circuit is equal to or higher than the first average luminance level and the pixel lighting rate detected in the image detection circuit is equal to or higher than the first pixel lighting rate and lower than the second pixel lighting rate, the detected APL and the pixel lighting rate According to the lighting rate, that is, the lighting rate calculated by the lighting rate calculation formula C, that is, the greater the APL detected between the lighting rate 0% and the predetermined lighting rate, the greater the detected pixel lighting rate, The second type subfield is forcibly lit at a high lighting rate.

  This is because the APL detected in the third image detection circuit 48 is equal to or higher than the first average luminance level and lower than the second average luminance level, and the pixel lighting rate detected in the image detection circuit is equal to or higher than the first pixel lighting rate. When the APL detected by the third image detection circuit 48 is equal to or higher than the first average luminance level, and the pixel lighting rate detected by the third image detection circuit 48 is equal to or higher than the first pixel lighting rate and lower than the second pixel lighting rate. Since either the forced lighting rate coefficient A or the forced lighting rate coefficient B is a value between 0 and less than 1, the lighting rate calculated by the lighting rate calculation formula C is a lighting between 0% and a predetermined lighting rate. This is because it becomes a rate.

  As described in the first embodiment, the light emission luminance in the second type subfield is weak and lower than the light emission luminance in the subfield having the luminance weight “1”. Therefore, if the APL of the image displayed on the plasma display is more than a certain level, even if only the second type subfield is forcibly turned on, it is difficult for the viewer to recognize the change in black luminance. Furthermore, if the pixel lighting rate displayed on the plasma display is more than a certain level, the area in which the black luminance changes is small, so that the change in black luminance is less visible.

  Therefore, in the present embodiment, the pixels that can be determined that the APL detected by the third image detection circuit 48 is sufficiently large and that the pixel lighting rate detected by the image detection circuit can be determined to be sufficiently large. At the lighting rate, that is, when APL is equal to or higher than the second average luminance level threshold value and the pixel lighting rate is equal to or higher than the second pixel lighting rate threshold value, the second type subfield is set to a predetermined lighting rate determined in advance. Forcibly turn on. Further, the APL detected by the image detection circuit 48 is not less than the first average brightness level threshold value and less than the second average brightness level threshold value, and the pixel lighting rate detected by the image detection circuit 48 is not less than the first average brightness level. And when the detected APL is equal to or higher than the first average luminance level and the detected pixel lighting rate is equal to or higher than the first pixel lighting rate and lower than the second pixel lighting rate, the lighting rate ranges from 0% to a predetermined lighting rate. In the range, the larger the detected APL and the larger the detected pixel lighting rate, the larger the lighting rate and forcibly light the second type subfield.

  As a result, when the APL and the pixel lighting rate are sufficiently large and it is difficult for the user to recognize the change in black luminance, the second type subfield is forcibly lit to reduce wall charges and priming particles in the discharge cell. Can be prevented. Therefore, even when the continuous display time of the black image becomes long, the wall charge and priming particles in the discharge cell are prevented from decreasing, so that the address discharge is stabilized when switching from the black image to the normal image. It is possible to prevent the image display quality from deteriorating.

  In the present embodiment, the first average luminance level threshold value, the second average luminance level threshold value, the first pixel lighting rate threshold value, the second pixel lighting rate threshold value, and the specific lighting rate are exemplified. The numerical values are merely examples in the present embodiment, and the present invention is not limited to these numerical values. Each numerical value is preferably set to an optimum value based on the characteristics of the panel, the specifications of the plasma display device, and the like.

  In the present embodiment, the forced lighting rate coefficient A and the forced lighting rate coefficient B are normalized values so that the minimum value is 0 and the maximum value is 1. However, this is merely an example in the present embodiment. However, the present invention is not limited to this.

  In FIG. 17 showing the relationship between the detected APL and the forced lighting rate coefficient A in the present embodiment, it is detected when the detected APL is between the first average luminance level and less than the second average luminance level. Although the example in which the relationship between the APL and the forced lighting rate coefficient A is linear is given, this is merely an example in the present embodiment, and the present invention is not limited to this. For example, you may control so that it may become a nonlinear relationship.

  In FIG. 18 showing the relationship between the pixel lighting rate detected in the present embodiment and the forced lighting rate coefficient B, the detected APL is equal to or higher than the first pixel lighting rate threshold, and the second pixel lighting rate threshold. In the case of less than 1, the example in which the relationship between the detected pixel lighting rate and the forced lighting rate coefficient B is linear is given. However, this is merely an example in the present embodiment, and the present invention is not limited to this. It is not a thing. For example, you may control so that it may become a nonlinear relationship.

  In the present embodiment, the calculation formula given for calculating the lighting rate when forcibly lighting the second type subfield is merely an example in the present embodiment, and the present invention is not limited to this. It is not a thing. Any calculation formula can be used as long as the detected APL is larger, the detected pixel lighting rate is larger, and the lighting rate when the second type subfield is forcibly lit is increased. May be. Also, it is not always necessary to use a calculation formula. A lookup table for setting the lighting rate in advance for APL and pixel lighting rate is prepared, and the second type subfield is forcibly turned on by referring to the lookup table. You may determine the lighting rate at the time of making.

  The present invention makes it possible to perform a stable writing operation without performing a forced initialization operation, thereby suppressing the black luminance, thereby increasing the contrast of the display image and lowering the luminance of the next lower gradation after black. Can improve the gradation when displaying a dark image, and can stably generate an address discharge when a full screen is switched from a black image to a normal image, thereby displaying an image with high image display quality. Therefore, it is useful as a panel driving method and a plasma display device.

DESCRIPTION OF SYMBOLS 1, 2 Plasma display apparatus 10 Panel 21 Front substrate 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25 Dielectric layer 26 Protective layer 31 Back substrate 32 Data electrode 33 Dielectric layer 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 46, 47, 48 Image detection circuit 50, 80 Sustain pulse generation circuit 51, 81 Power recovery circuit 55, 101 APL detection circuit 60 Ramp waveform voltage generation Circuit 61, 63 Miller integration circuit 70 Scan pulse generation circuit 85 Constant voltage generation circuit 91, 102 Signal level detection circuit 92, 103 Comparison circuit 93, 104 Predetermined pixel count circuit Q55, Q56, Q59, Q69, Q71H1-Q71Hn, Q71L1 ~ Q71Ln, Q72, Q83, Q84, Q86, Q87, Q91H1-Q91Hm, Q91L1-Q91Lm Switching element E71 Power supply Q61, Q63 Transistor C61, C63 Capacitor R61, R63 Resistor IN61, IN63 Input terminal L1, L3 Ramp waveform voltage L2, L4 Waveform voltage

Claims (8)

A plasma display panel comprising a plurality of sub-fields having an address period, a sustain period, and an erase period, forming a single field, and having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode A driving method of a plasma display panel to be driven,
The plurality of subfields includes a first type subfield that is applied to the display electrode pair by applying a number of sustain pulses corresponding to a luminance weight in the sustain period, and an up-slope waveform voltage and a down-slope waveform voltage in the sustain period. A second type subfield applied to the scan electrode;
The drive voltage waveform applied to each of the sustain electrode, the scan electrode, and the data electrode is changed from the low voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield. The voltage obtained by subtracting the voltage applied to is set as the first voltage, and the voltage applied to the data electrode is subtracted from the high-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield. When the voltage is the second voltage, and the voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode from the low-voltage side voltage of the scan pulse applied to the scan electrode in the write period is the third voltage,
A voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than a discharge start voltage of a discharge having the data electrode as an anode and the scan electrode as a cathode,
The voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage of discharge using the data electrode as an anode and the scan electrode as a cathode, and the data electrode as a cathode and the scan electrode as an anode. Generated by setting to be less than the sum of the discharge start voltage of the discharge,
A method for driving a plasma display panel, comprising: detecting an average luminance level of an image signal displayed on the plasma display panel; and forcibly lighting the second type subfield according to the average luminance level. 2. The driving method of the plasma display panel according to claim 1, wherein the lighting rate of the discharge cells for forcibly lighting the second type subfield increases as the average luminance level increases. One field is formed by using a plasma display panel having a plurality of discharge cells each having a display electrode pair and data electrodes each including a scan electrode and a sustain electrode, and a plurality of subfields having an address period, a sustain period, and an erase period. And a driving circuit for generating a driving voltage waveform corresponding to each electrode of the plasma display panel and applying the driving voltage waveform to each electrode,
The driving circuit is configured by using a first-type subfield and a second-type subfield in one field, and the sustain period of the first-type subfield generates a number of sustain pulses corresponding to a luminance weight. Applying to the display electrode pair, generating the rising ramp waveform voltage and the falling ramp waveform voltage without generating the sustain pulse in the sustain period of the second type subfield,
The drive voltage waveform applied to each of the sustain electrode, the scan electrode, and the data electrode is changed from the low voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield. The voltage obtained by subtracting the voltage applied to is set as the first voltage, and the voltage applied to the data electrode is subtracted from the high-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield. When the voltage is the second voltage, and the voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode from the low-voltage side voltage of the scan pulse applied to the scan electrode in the write period is the third voltage,
A voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than a discharge start voltage of a discharge having the data electrode as an anode and the scan electrode as a cathode,
The voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage of discharge using the data electrode as an anode and the scan electrode as a cathode, and the data electrode as a cathode and the scan electrode as an anode. Generated by setting to be less than the sum of the discharge start voltage of the discharge,
The drive circuit includes an image detection circuit that detects an average luminance level of an image signal displayed on the plasma display device,
The plasma display apparatus characterized in that the second type subfield is forcibly lit in accordance with the average luminance level detected by the image detection circuit. 4. The plasma display apparatus according to claim 3, wherein the driving circuit increases the lighting rate of the discharge cells for forcibly lighting the second type subfield as the average luminance level increases. A plasma display panel comprising a plurality of sub-fields having an address period, a sustain period, and an erase period, forming a single field, and having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode A driving method of a plasma display panel to be driven,
The plurality of subfields includes a first type subfield that is applied to the display electrode pair by applying a number of sustain pulses corresponding to a luminance weight in the sustain period, and an up-slope waveform voltage and a down-slope waveform voltage in the sustain period A second type subfield for applying to the scan electrode,
The drive voltage waveform applied to each of the sustain electrode, the scan electrode, and the data electrode is changed from the low voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield. The voltage obtained by subtracting the voltage applied to is set as the first voltage, and the voltage applied to the data electrode is subtracted from the high-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield. When the voltage is the second voltage, and the voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode from the low-voltage side voltage of the scan pulse applied to the scan electrode in the write period is the third voltage,
A voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than a discharge start voltage of a discharge having the data electrode as an anode and the scan electrode as a cathode,
The voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage of discharge using the data electrode as an anode and the scan electrode as a cathode, and the data electrode as a cathode and the scan electrode as an anode. Generated by setting to be less than the sum of the discharge start voltage of the discharge,
Detecting the number of discharge cells equal to or higher than a specific signal level of an image signal displayed on the plasma display panel, and forcibly lighting the second type subfield at a lighting rate according to the number of discharge cells. A method for driving a plasma display panel. 6. The plasma display panel according to claim 5, wherein the lighting rate of the discharge cells forcibly lighting the second type subfield is larger as the lighting rate according to the number of discharge cells equal to or higher than a specific signal level is larger. Driving method. One field is formed by using a plasma display panel having a plurality of discharge cells each having a display electrode pair and data electrodes each including a scan electrode and a sustain electrode, and a plurality of subfields having an address period, a sustain period, and an erase period. And a driving circuit for generating a driving voltage waveform corresponding to each electrode of the plasma display panel and applying the driving voltage waveform to each electrode,
The drive circuit is
One field is composed of a first type subfield and a second type subfield, and the number of sustain pulses corresponding to a luminance weight is generated in the sustain period of the first type subfield to generate the display electrode. Applying a pair, and generating an up-slope waveform voltage and a down-slope waveform voltage without applying the sustain pulse in the sustain period of the second type subfield, and applying them to the scan electrodes;
The drive voltage waveform applied to each of the sustain electrode, the scan electrode, and the data electrode is changed from the low voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield. The voltage obtained by subtracting the voltage applied to is set as the first voltage, and the voltage applied to the data electrode is subtracted from the high-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period of the first type subfield. When the voltage is the second voltage, and the voltage obtained by subtracting the low-voltage side voltage of the write pulse applied to the data electrode from the low-voltage side voltage of the scan pulse applied to the scan electrode in the write period is the third voltage,
A voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than a discharge start voltage of a discharge having the data electrode as an anode and the scan electrode as a cathode,
The voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage of discharge using the data electrode as an anode and the scan electrode as a cathode, and the data electrode as a cathode and the scan electrode as an anode. Generated by setting to be less than the sum of the discharge start voltage of the discharge,
The drive circuit includes an image detection circuit that detects the number of discharge cells equal to or higher than a specific signal level of a displayed image;
The plasma display device, wherein the second type subfield is forcibly lit at a lighting rate corresponding to the number of discharge cells detected by the image detection circuit. 8. The driving circuit according to claim 7, wherein the lighting rate of the discharge cells forcibly lighting the second type subfield increases as the lighting rate according to the number of discharge cells equal to or higher than a specific signal level increases. Plasma display device.

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