WO2012017648A1

WO2012017648A1 - Plasma display panel driving method and plasma display apparatus

Info

Publication number: WO2012017648A1
Application number: PCT/JP2011/004389
Authority: WO
Inventors: 豊吉濱; 久美子新井; 広史本田
Original assignee: パナソニック株式会社
Priority date: 2010-08-04
Filing date: 2011-08-03
Publication date: 2012-02-09

Abstract

When an image is displayed on a plasma display panel (10), a stable write operation can be performed without performing the forced initializing operation, thereby suppressing the black intensity to enhance the contrast of the displayed image and further enhancing the precision of the values of gray scales to be artificially displayed on the panel. For this purpose, the voltages to be applied to data and scan electrodes are established such that during the sustain interval, the voltage obtained by subtracting, from a first voltage, a third voltage is equal to or greater than a discharge start voltage occurring with each data electrode used as the anode electrode and each scan electrode used as the cathode electrode and further the voltage obtained by subtracting, from a second voltage, the third voltage is equal to or lower than the sum of a discharge start voltage occurring with each data electrode used as the anode electrode and each scan electrode used as the cathode electrode and a discharge start voltage occurring with each data electrode used as the cathode electrode and each scan electrode used as the anode electrode. Then, an input image signal is amplified by use of a given amplification factor, thereby displaying the image on the plasma display panel (10). An input image signal having a magnitude smaller than a given magnitude is amplified by use of an amplification factor equal to or greater than a amplification factor used for an input image signal having a magnitude equal to or greater than the given magnitude.

Description

Plasma display panel driving method and plasma display device

The present invention relates to an AC surface discharge type plasma display panel driving method and a plasma display apparatus.

A typical plasma display panel (hereinafter abbreviated as “panel”) as a display device has a large number of discharge cells formed between a front substrate and a rear substrate arranged to face each other. In the front substrate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other. A dielectric layer and a protective layer are formed so as to cover the display electrode pairs.

The back substrate has a plurality of parallel data electrodes formed on the glass substrate on the back side, a dielectric layer is formed so as to cover the data electrodes, and a plurality of barrier ribs are formed thereon in parallel with the data electrodes. ing. And the fluorescent substance layer is formed in the surface of a dielectric material layer, and the side surface of a partition.

Then, the front substrate and the rear substrate are arranged opposite to each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed. In the sealed internal discharge space, for example, a discharge gas containing xenon at a partial pressure ratio of 5% is sealed, and a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of each color of red (R), green (G) and blue (B) are excited and emitted by the ultraviolet rays. Display an image.

The subfield method is generally used as a method for driving the panel. In the subfield method, one field is divided into a plurality of subfields, and light emission and non-light emission of each discharge cell are controlled in each subfield. Then, gradation display is performed by controlling the number of times of light emission generated in one field.

Each subfield has an initialization period, an address period, and a sustain period.

In the initialization period, an initialization waveform is applied to each scan electrode, and an initialization operation is performed to generate an initialization discharge in each discharge cell. Thereby, in each discharge cell, wall charges necessary for the subsequent address operation are formed, and priming particles (excited particles for generating the discharge) for generating the address discharge stably are generated.

Initializing operation includes forced initializing operation that generates initializing discharge in each discharge cell regardless of the operation of the previous subfield, and initializing discharge is generated only in the discharge cell that has generated address discharge in the immediately preceding subfield. There is a selective initialization operation to do.

In the address period, an address discharge is selectively generated in the discharge cells according to the image to be displayed, and an address operation is performed to form wall charges in the discharge cells. In the address period, scan pulses are sequentially applied to the scan electrodes, and address pulses are selectively applied to the data electrodes based on the image signal to be displayed. Thereby, an address discharge is generated between the scan electrode and the data electrode of the discharge cell to emit light, and a wall charge is formed in the discharge cell.

In the sustain period, the sustain pulses of the number based on the luminance weight determined for each subfield are alternately applied to the display electrode pairs composed of the scan electrodes and the sustain electrodes, and the sustain discharge is generated in the discharge cells that have generated the address discharge. Then, the sustaining operation for causing the phosphor layer of the discharge cell to emit light is performed (hereinafter, the discharge cell is caused to emit light by the sustain discharge is also referred to as “lighting” and the light emission is not referred to as “non-lighting”). Thereby, each discharge cell is made to emit light with the luminance according to the luminance weight. The light emission of the phosphor layer due to the sustain discharge is light emission related to gradation display, and the other light emission is light emission not related to gradation display. As an example of other light emission, there is light emission caused by a forced initialization operation.

In this way, each discharge cell of the panel is caused to emit light with a luminance corresponding to the gradation value of the image signal, and an image is displayed in the image display area of the panel.

One of the important factors in improving the image display quality on the panel is the improvement in contrast. As one of the subfield methods, light emission not related to gradation display is reduced as much as possible, the luminance when displaying the lowest gradation (black gradation value “0”) is reduced, and the contrast ratio is improved. A driving method is disclosed.

In this driving method, the forced initialization operation is performed using a gradually changing ramp waveform voltage. Of the plurality of subfields constituting one field, the forced initializing operation is performed in the initializing period of one subfield, and the selective initializing operation is performed in the initializing period of the other subfield. In this way, the number of times of forced initialization operation is set to once per field.

The luminance of the black display area where no sustain discharge occurs (hereinafter abbreviated as “black luminance”) varies depending on light emission not related to image display, for example, light emission caused by initialization discharge. In the above driving method, light emission in the black display region is only weak light emission when the initialization operation is performed on all the discharge cells. Thereby, it is possible to reduce the black luminance and display an image with high contrast (see, for example, Patent Document 1).

In addition, by dividing the display electrode pair into n and performing the forced initialization operation once per n fields, light emission not related to gradation display is further reduced to further reduce black luminance and further improve contrast. A driving method is disclosed (for example, see Patent Document 2).

If the driving method described in Patent Document 2 is used, the number of forced initialization operations per unit time (for example, 1 second) can be reduced and the black luminance can be further decreased as compared with the driving method described in Patent Document 1. it can.

However, in the forced initializing operation, the wall charge necessary for generating the address discharge in the subsequent address period is accumulated in the discharge cell, and the discharge delay time is shortened to surely generate the address discharge. Has the function of generating priming particles. The discharge delay time is the time required from when the voltage applied to the discharge cell exceeds the discharge start voltage until the actual discharge occurs. The longer the discharge delay time, the more unstable the generation of discharge.

For this reason, if the forced initialization operation is omitted, the address discharge operation becomes unstable due to a long discharge delay time of the address discharge, or a malfunction such as no address discharge occurs, resulting in normal image display. become unable.

Therefore, even with the driving method described in Patent Document 2, it is necessary to perform a forced initialization operation. As a result, even in a discharge cell that displays black without generating a sustain discharge, it is caused by the forced initialization operation. Luminescence occurs.

Thus, with the conventional technology, it is difficult to omit the forced initialization operation. This means that even a discharge cell that should display black emits light, and thus there is a limit to improving the contrast.

Also, when displaying an image on the panel, there is a problem that the gradation value to be displayed cannot be correctly displayed in the area where the low luminance pattern is displayed.

JP 2000-242224 A JP 2006-091295 A

The present invention is a panel driving method for driving a panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode. In this panel driving method, a single field is formed by using a plurality of subfields each having an address period, a sustain period, and an erase period. In the address period, a scan pulse is applied to the scan electrode and an address pulse is applied to the data electrode. This is applied to selectively generate an address discharge in the discharge cell, and in the sustain period, sustain pulses of the number corresponding to the luminance weight are alternately applied to the scan electrode and the sustain electrode to maintain the address discharge in the discharge cell. In the erasing period, a ramp waveform voltage is applied to the scan electrode, and an erasing discharge is selectively generated only in the discharge cells in which the address discharge is generated in the immediately preceding address period. The voltage obtained by subtracting the voltage applied to the data electrode from the low-voltage side voltage of the sustain pulse applied to the scan electrode during the sustain period is defined as the first voltage, and the data is obtained from the high-voltage side voltage of the sustain pulse applied to the scan electrode during the sustain period The voltage obtained by subtracting the voltage applied to the electrode is the second voltage, and the voltage obtained by subtracting the low voltage side voltage of the write pulse applied to the data electrode from the low voltage side voltage of the scan pulse applied to the scan electrode in the write period is the third voltage. When setting the voltage, the voltage applied to each electrode is set so that the voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than the discharge start voltage of the discharge using the data electrode as an anode and the scan electrode as a cathode. In addition, a voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage of discharge using the data electrode as an anode and the scan electrode as a cathode, and the data electrode as a cathode and the scan electrode as an anode. As the discharge start voltage of the discharge to the sum following sets the voltage applied to the electrodes. Further, the input image signal is amplified at a predetermined amplification factor and an image is displayed on the panel. At this time, an input image signal less than a predetermined size is amplified with an amplification factor equal to or higher than an amplification factor for an input image signal having a predetermined size or more.

This makes it possible to perform a stable writing operation without performing a forced initialization operation, and to increase the contrast of the display image by suppressing the black luminance. Furthermore, when displaying the gradation value to be displayed on the panel in a pseudo manner using a dithering process or the like, it is possible to compensate in advance for the gradation value to be displayed with the luminance reduced by the discharge failure. Therefore, the gradation value to be displayed can be correctly displayed on the panel. Thereby, it is possible to improve the image display quality in the plasma display device.

In the panel driving method of the present invention, it is desirable to increase the amplification factor as the input image signal becomes smaller for an input image signal less than a predetermined size.

In the panel driving method of the present invention, the predetermined size may be a size in which only the subfield having the smallest luminance weight in one field emits light and the other subfields do not emit light.

In the panel driving method of the present invention, the temperature of the panel is detected and the detected temperature is compared with a preset temperature threshold value. When the detected temperature is lower than the temperature threshold value, the detected temperature is You may enlarge the amplification factor regarding the input image signal below a predetermined magnitude | size rather than the time more than a temperature threshold value.

In the panel driving method of the present invention, the cumulative operation time of the panel is measured and the measured cumulative operation time is compared with a preset cumulative time threshold value. When the cumulative operation time is equal to or greater than the cumulative time threshold value, The amplification factor relating to an input image signal having a size less than a predetermined magnitude may be larger than when the cumulative operation time is less than the cumulative time threshold.

Further, the present invention is a plasma display device including a panel including a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, and a drive circuit that drives the panel and displays an image on the panel. The drive circuit forms a single field using a plurality of subfields having an address period, a sustain period, and an erase period, and applies a scan pulse to the scan electrode and an address pulse to the data electrode in the address period. Then, an address discharge is selectively generated in the discharge cell, and in the sustain period, a sustain pulse of the number corresponding to the luminance weight is alternately applied to the scan electrode and the sustain electrode to sustain the discharge cell in which the address discharge is generated. In the erasing period, an erasing discharge is selectively generated only in the discharge cells in which the ramp waveform voltage is applied to the scan electrodes and the address discharge is generated in the immediately preceding address period. Then, the drive circuit sets the voltage obtained by subtracting the voltage applied to the data electrode from the low-voltage side voltage of the sustain pulse applied to the scan electrode during the sustain period as the first voltage, and sets the high voltage of the sustain pulse applied to the scan electrode during the sustain period. The voltage obtained by subtracting the voltage applied to the data electrode from the side voltage is the second voltage, and the voltage obtained by subtracting the low voltage side voltage of the write pulse applied to the data electrode from the low voltage side voltage of the scan pulse applied to the scan electrode in the write period Is applied to each electrode so that the voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than the discharge start voltage of the discharge having the data electrode as the anode and the scan electrode as the cathode. In addition to setting the voltage, the voltage obtained by subtracting the third voltage from the second voltage is the discharge start voltage of the discharge using the data electrode as the anode and the scan electrode as the cathode and the data electrode as the cathode. Electrodes to set the voltage applied to each electrode so that the following sum of the discharge start voltage of the discharge of the anode. Then, the drive circuit amplifies the input image signal with a predetermined amplification factor and displays an image on the panel. At this time, an input image signal less than a predetermined size is amplified with an amplification factor equal to or higher than an amplification factor for an input image signal having a predetermined size or more.

In the plasma display device of the present invention, it is desirable that the drive circuit increases the amplification factor as the input image signal becomes smaller for the input image signal less than a predetermined size.

In the plasma display device of the present invention, the drive circuit includes a temperature detection circuit that detects the temperature of the panel, compares the temperature detected by the temperature detection circuit with a preset temperature threshold value, and the detected temperature is the temperature. When the detected temperature is lower than the threshold value, the amplification factor related to the input image signal less than the predetermined magnitude may be set larger than when the detected temperature is equal to or higher than the temperature threshold value.

In the plasma display device of the present invention, the drive circuit includes a cumulative operation time measurement circuit that measures the cumulative operation time of the panel, and a cumulative time threshold value that is preset with the cumulative operation time measured by the cumulative operation time measurement circuit. In contrast, when the cumulative operation time is equal to or greater than the cumulative time threshold, the amplification factor for the input image signal less than the predetermined magnitude may be larger than when the cumulative operation time is less than the cumulative time threshold. .

FIG. 1 is an exploded perspective view showing a structure of a panel used in a plasma display device according to an embodiment of the present invention. FIG. 2 is an electrode array diagram of a panel used in the plasma display device according to one embodiment of the present invention. FIG. 3 is a diagram schematically showing a drive voltage waveform applied to each electrode of the panel used in the plasma display device according to one embodiment of the present invention. FIG. 4 is a waveform diagram schematically showing voltage waveforms applied to scan electrodes and data electrodes in one subfield in one embodiment of the present invention. FIG. 5 is a diagram illustrating an example of a method for simply measuring the discharge start voltage. FIG. 6A is a diagram schematically showing an example of a dither pattern used for dither processing in the plasma display apparatus according to one embodiment of the present invention. FIG. 6B is a diagram schematically showing another example of a dither pattern used for dither processing in the plasma display apparatus according to one embodiment of the present invention. FIG. 6C is a diagram schematically showing still another example of the dither pattern used for the dither processing in the plasma display device in accordance with the exemplary embodiment of the present invention. FIG. 7 is a circuit block diagram of the plasma display device according to one embodiment of the present invention. FIG. 8 is a diagram schematically showing an operation in the low luminance amplifier circuit of the plasma display device in accordance with the exemplary embodiment of the present invention. FIG. 9 is an enlarged view showing a part of the operation of the low-intensity amplifier circuit of the plasma display device according to one embodiment of the present invention. FIG. 10A is a diagram showing an example of the amplification factor for the input signal in the first correction in the embodiment of the present invention. FIG. 10B is a diagram showing an example of the amplification factor for the input signal in the second correction according to the embodiment of the present invention. FIG. 10C is a diagram showing an example of the amplification factor for the input signal in the third correction according to the embodiment of the present invention. FIG. 10D is a diagram showing an example of the amplification factor for the input signal in the fourth correction in the embodiment of the present invention. FIG. 11 shows the temperature detected by the temperature detection circuit and the accumulated operation time measured by the accumulated operation time measurement circuit and the first correction, the second correction, the third correction, It is a figure which shows the relationship with correction | amendment of 4 schematically. FIG. 12 is a circuit diagram schematically showing a configuration of a scan electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention. FIG. 13 is a circuit diagram schematically showing a configuration of a sustain electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention. FIG. 14 is a circuit diagram schematically showing a configuration of a data electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention.

Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the plasma display device according to one embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

This protective layer 26 is made of a material using magnesium oxide (MgO) having high electron emission performance and excellent durability in order to easily generate discharge by lowering the discharge start voltage in the discharge cell.

A plurality of data electrodes 32 are formed on the rear substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. On the side surfaces of the partition walls 34 and the dielectric layer 33, a phosphor layer 35R that emits red (R), a phosphor layer 35G that emits green (G), and a phosphor layer 35B that emits blue (B). Is provided. Hereinafter, the phosphor layer 35R, the phosphor layer 35G, and the phosphor layer 35B are collectively referred to as a phosphor layer 35.

In the present embodiment, as the red phosphor, for example, a phosphor mainly composed of (Y, Gd) BO ₃ : Eu is used, and as the green phosphor, for example, Zn ₂ SiO ₄ : Mn is mainly composed. For example, a phosphor mainly composed of BaMgAl ₁₀ O ₁₇ : Eu is used as the blue phosphor. However, in the present invention, the phosphor forming the phosphor layer 35 is not limited to the above-described phosphor.

The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween. And the outer peripheral part is sealed with sealing materials, such as glass frit. Then, for example, a mixed gas of neon and xenon is sealed in the discharge space inside as a discharge gas.

The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32.

Then, discharge is generated in these discharge cells, and the phosphor layer 35 of the discharge cells emits light (lights the discharge cells), thereby displaying a color image on the panel 10.

In the panel 10, three continuous discharge cells arranged in the extending direction of the display electrode pair 24, that is, discharge cells that emit red (R), and discharge cells that emit green (G), One pixel is composed of three discharge cells that emit blue (B) light.

Note that the structure of the panel 10 is not limited to that described above. For example, the rear substrate 31 may include a stripe-shaped partition wall.

FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device according to one embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrode 22 in FIG. 1) extended in the horizontal direction (row direction) and n sustain electrodes SU1 to SUn (sustain electrodes in FIG. 1). 23) are arranged, and m data electrodes D1 to Dm (data electrodes 32 in FIG. 1) extending in the vertical direction (column direction) are arranged. A discharge cell is formed at a portion where a pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects with one data electrode Dj (j = 1 to m). That is, m discharge cells are formed on one display electrode pair 24, and m / 3 pixels are formed. Then, m × n discharge cells are formed in the discharge space, and an area where m × n discharge cells are formed becomes an image display area of the panel 10. For example, in a panel having 1920 × 1080 pixels, m = 1920 × 3 and n = 1080.

For example, a red phosphor is applied as a phosphor layer 35R to the discharge cell having the data electrode Dp (p = 3 × q−2: q is an integer excluding 0 of m / 3 or less), and the data electrode Dp + 1. A green phosphor is applied as a phosphor layer 35G to a discharge cell having a blue color, and a blue phosphor is applied as a phosphor layer 35B to a discharge cell having a data electrode Dp + 2.

Next, a driving voltage waveform for driving the panel 10 and an outline of its operation will be described.

The plasma display device in the present embodiment drives the panel 10 by the subfield method. In the subfield method, one field is divided into a plurality of subfields on the time axis, and a luminance weight is set for each subfield. Therefore, each field has a plurality of subfields. An image is displayed on the panel 10 by controlling light emission / non-light emission of each discharge cell for each subfield.

The luminance weight represents a ratio of the luminance magnitudes displayed in each subfield, and the number of sustain pulses corresponding to the luminance weight is generated in the sustain period in each subfield. Therefore, for example, the subfield with the luminance weight “8” emits light with a luminance about eight times that of the subfield with the luminance weight “1”, and emits light with about four times the luminance of the subfield with the luminance weight “2”. Therefore, by selectively causing each subfield to emit light in a combination corresponding to an image signal, various gradations can be displayed on the panel 10 and an image can be displayed.

In this embodiment, each subfield has a write period, a sustain period, and an erase period. In this embodiment, the forced initialization operation is not performed. The forced initializing operation is an initializing operation that forcibly generates an initializing discharge in a discharge cell regardless of whether or not there has been a discharge so far.

In the address period, a scan pulse is applied to the scan electrode 22 and an address pulse (data pulse) is selectively applied to the data electrode 32 to perform an address operation that selectively generates an address discharge in the discharge cells to emit light. By the address operation, wall charges for generating a sustain discharge in the subsequent sustain period are formed in the discharge cell.

In the sustain period, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined proportional constant is alternately applied to the scan electrode 22 and the sustain electrode 23. This proportionality constant is the luminance magnification. For example, when the luminance magnification is two, the sustain pulse is applied to the scan electrode 22 and the sustain electrode 23 four times in the sustain period of the subfield having the luminance weight “2”. Therefore, the number of sustain pulses generated in the sustain period is 8. Then, a sustain discharge is generated in the discharge cell that has generated the address discharge in the immediately preceding address period, and the discharge cell emits light. Thus, the operation of applying the sustain pulse to the discharge cell and emitting the discharge is the sustain operation.

Note that a subfield in which the sustain period is omitted may be provided in order to keep the emission luminance low.

In the erasing period, an erasing discharge is generated only in the discharge cells that have generated the address discharge in the address period of the subfield to which the erasing period belongs. Therefore, this erasing discharge is selectively generated only in the discharge cells that have generated the address discharge. When this erasing discharge is generated, wall charges formed by the address discharge or the subsequent sustain discharge are erased, and wall charges necessary for the address discharge in the subsequent subfield are formed on each electrode. Hereinafter, these operations are also referred to as “erase operations”.

Hereinafter, in the present embodiment, one field is divided into 10 subfields (SF1, SF2,..., SF10), and each subfield is (1, 2, 3, 6, 11, 18, 30). , 44, 60, 80).

However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values. Moreover, the structure which switches the structure of a subfield based on an image signal etc. may be sufficient.

FIG. 3 is a diagram schematically showing drive voltage waveforms applied to the respective electrodes of panel 10 used in the plasma display device according to one embodiment of the present invention.

FIG. 3 shows scan electrode SC1 that performs the address operation first in the address period, scan electrode SCn that performs the address operation last in the address period, sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data electrode Dm. The drive voltage waveform to be applied is shown. Scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected based on image data (data indicating light emission / non-light emission for each subfield) from among the electrodes.

FIG. 3 mainly shows drive voltage waveforms in three subfields, that is, subfield SF1, subfield SF2, and subfield SF3.

In the address period of subfield SF1, voltage 0 (V) is applied to data electrode D1 to data electrode Dm, voltage Ve is applied to sustain electrode SU1 to sustain electrode SUn, and scan electrode SC1 to scan electrode SCn are applied to scan electrode SC1. A voltage Vc is applied.

Next, a scan pulse having a negative voltage Va is applied to the scan electrode SC1 in the first row where the address operation is first performed. Then, an address pulse of a positive voltage Vd is applied to the data electrode Dk corresponding to the discharge cell that should emit light in the first row of the data electrodes D1 to Dm.

The voltage difference at the intersection between the data electrode Dk of the discharge cell to which the address pulse of the voltage Vd is applied and the scan electrode SC1 is the difference between the externally applied voltage (voltage Vd−voltage Va) and the wall voltage on the data electrode Dk and the scan electrode. The difference from the wall voltage on SC1 is added. As a result, the voltage difference between data electrode Dk and scan electrode SC1 exceeds discharge start voltage VFds, and a discharge is generated between data electrode Dk and scan electrode SC1.

Since voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is the difference between the externally applied voltages (voltage Ve−voltage Va), and sustain electrode SU1. The difference between the upper wall voltage and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do.

Thus, a discharge is generated between the sustain electrode SU1 and the scan electrode SC1 in a region intersecting the data electrode Dk, induced by a discharge generated between the data electrode Dk and the scan electrode SC1. Thus, address discharge is generated in the discharge cells (discharge cells to emit light) to which the scan pulse and address pulse are simultaneously applied. In the discharge cell in which the address discharge has occurred, positive wall voltage is accumulated on scan electrode SC1, negative wall voltage is accumulated on sustain electrode SU1, and negative wall voltage is also accumulated on data electrode Dk. Is done.

The wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer 25 covering the electrode, the protective layer 26, the phosphor layer 35, and the like.

In this way, an address operation is performed in which an address discharge is generated in the discharge cells that should emit light in the first row and a wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrode Dh to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage VFds, so the address discharge does not occur.

Next, a scan pulse is applied to the scan electrode SC2 in the second row, and an address pulse is applied to the data electrode Dk corresponding to the discharge cell to emit light in the second row. As a result, an address discharge is generated between data electrode Dk and scan electrode SC2 and between sustain electrode SU2 and scan electrode SC2, a positive wall voltage is accumulated on scan electrode SC2, and a negative voltage is applied on sustain electrode SU2. And a negative wall voltage is also accumulated on the data electrode Dk. On the other hand, since the voltage at the intersection between the data electrode Dh and the scan electrode SC2 to which no address pulse is applied does not exceed the discharge start voltage VFds, no address discharge occurs. In this way, an address operation is performed in which an address discharge is generated in the discharge cells that should emit light in the second row, and a wall voltage is accumulated on each electrode.

Hereinafter, the same addressing operation is performed by scanning electrode SC3 in the third row, scanning electrode SC4 in the fourth row,..., Scanning electrode SC (n−1) in the (n−1) th row, scanning in the nth row. The process is sequentially performed from the discharge cell in the third row to the discharge cell in the nth row in the order of the electrode SCn, and the address period of the subfield SF1 is completed.

Here, for the following explanation, the first voltage V1, the second voltage V2, and the third voltage V3 are defined as follows.

FIG. 4 is a waveform diagram schematically showing voltage waveforms applied to scan electrode 22 and data electrode 32 in one subfield in one embodiment of the present invention.

In the present embodiment, in the sustain period, the voltage (FIGS. 3 and 4) applied to the data electrode Dj from the low-voltage side voltage (voltage 0 (V) in FIGS. 3 and 4) of the sustain pulse applied to the scan electrode SCi. Then, the voltage obtained by subtracting the voltage 0 (V)) is set as the first voltage V1. Further, in the sustain period, the voltage applied to the data electrode Dj from the high-voltage side voltage (voltage Vs in FIGS. 3 and 4) of the sustain pulse applied to the scan electrode SCi (voltage 0 (V) in FIGS. 3 and 4). ) Is defined as a second voltage V2. In the address period, the low-voltage side voltage (in FIG. 3 and FIG. 4, the voltage Va) of the scan pulse applied to the scan electrode SCi to the low-voltage side voltage (in FIG. 3 and FIG. 4) of the address pulse applied to the data electrode Dj. A voltage obtained by subtracting the voltage 0 (V)) is defined as a third voltage V3.

Further, the discharge start voltage VFds is the discharge start voltage in the address period in which the data electrode Dj is the anode and the scan electrode SCi is the cathode, and the discharge start voltage is the discharge start voltage in the sustain period in which the data electrode Dj is the cathode and the scan electrode SCi is the anode. The voltage is VFsd.

The discharge with the data electrode Dj as the anode and the scan electrode SCi as the cathode is a discharge in which the electric field in the discharge cell when the discharge occurs is a high potential side on the data electrode Dj side and a low potential side on the scan electrode SCi side. It is.

The discharge with the data electrode Dj as the cathode and the scan electrode SCi as the anode is a discharge in which the electric field in the discharge cell when the discharge occurs is a low potential side on the data electrode Dj side and a high potential side on the scan electrode SCi side. is there.

And, since the protective layer 26 of magnesium oxide having high electron emission performance is formed on the front substrate 21 with the scan electrode SCi, the discharge start voltage VFds is lower than the discharge start voltage VFsd.

In this embodiment, the voltage Va of the scan pulse applied to the scan electrode SCi is set so as to satisfy the following two conditions (condition 1) and (condition 2).

(Condition 1): For all discharge cells, the voltage obtained by subtracting the third voltage V3 from the first voltage V1 is equal to or higher than the discharge start voltage VFds of the discharge using the data electrode Dj as the anode and the scan electrode SCi as the cathode. It is. That is,
(V1-V3) ≧ VFds
It is.

(Condition 2): For all the discharge cells, a voltage obtained by subtracting the third voltage V3 from the second voltage V2 is a discharge start voltage VFds of discharge using the data electrode Dj as an anode and the scan electrode SCi as a cathode. , And the discharge start voltage VFsd of the discharge having the data electrode Dj as the cathode and the scan electrode SCi as the anode. That is,
(V2−V3) ≦ (VFds + VFsd)
It is.

Next, the maintenance period will be described. In the sustain period of subfield SF1 following the address period shown in FIG. 3, first, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, and positive voltage Vs is applied to scan electrode SC1 through scan electrode SCn. A sustain pulse is applied.

In the discharge cell in which the address discharge is generated by the application of the sustain pulse, the voltage difference between the scan electrode SCi and the sustain electrode SUi causes the voltage Vs of the sustain pulse to be the wall voltage on the scan electrode SCi and the wall voltage on the sustain electrode SUi. The difference between and is added.

Thereby, the voltage difference between scan electrode SCi and sustain electrode SUi exceeds discharge start voltage VFss, and a sustain discharge is generated between scan electrode SCi and sustain electrode SUi. And the fluorescent substance layer 35 light-emits with the ultraviolet-ray which generate | occur | produced by this discharge. In addition, due to this discharge, negative wall voltage is accumulated on scan electrode SCi, and positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is also accumulated on the data electrode Dk. On the other hand, in the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization operation is maintained.

Subsequently, voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn, and a sustain pulse of voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. In the discharge cell that has generated the sustain discharge immediately before, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage VFss. As a result, the sustain discharge again occurs between the sustain electrode SUi and the scan electrode SCi, and the phosphor layer 35 of the discharge cell in which the sustain discharge has occurred emits light. Then, negative wall voltage is accumulated on sustain electrode SUi, and positive wall voltage is accumulated on scan electrode SCi.

Thereafter, similarly, sustain pulses of the number obtained by multiplying the luminance weight by a predetermined luminance magnification are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. As described above, by applying a potential difference between the electrodes of the display electrode pair 24, the sustain discharge is continuously generated in the discharge cells in which the address discharge is generated in the address period.

Thus, the maintenance operation in the maintenance period of subfield SF1 is completed.

Next, the erase period will be described.

In the erasing period of subfield SF1, voltage 0 (V) is gradually increased from voltage 0 (V) to voltage Vr while voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm. An upward ramp waveform voltage is applied to scan electrode SC1 through scan electrode SCn.

A discharge cell that generates a sustain discharge in the sustain period of the subfield while the upward ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn exceeds the discharge start voltage (a subfield in which the sustain period is omitted) Then, in the discharge cell in which the address discharge has occurred, a weak erasure discharge is continuously generated between the scan electrode SCi and the sustain electrode SUi. The charged particles generated by the erasing discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to alleviate the voltage difference between the sustain electrode SUi and the scan electrode SCi. Thereby, the wall voltage on scan electrode SCi and sustain electrode SUi is weakened while the positive wall voltage on data electrode Dk remains. That is, unnecessary wall charges in the discharge cells are erased by the erase discharge.

When the voltage applied to scan electrode SC1 through scan electrode SCn reaches voltage Vr, the voltage applied to scan electrode SC1 through scan electrode SCn is lowered to voltage 0 (V).

In the present embodiment, the voltage Vr is set to the same voltage value as the voltage Vs, but the voltage Vr may be a voltage value different from the voltage Vs. The voltage Vr is desirably set to an optimum voltage value according to the characteristics of the panel 10 and the specifications of the plasma display device.

Thereafter, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and voltage 0 (V) is applied to data electrode D1 through data electrode Dm. Then, a downward ramp waveform voltage that gently falls from voltage 0 (V) to voltage Vi is applied to scan electrode SC1 through scan electrode SCn.

This causes a weak discharge again in the discharge cell that generated the weak erase discharge.

Note that the voltage Vi is set to be equal to or slightly higher than the voltage Va of the scanning pulse.

This weak discharge discharges an excessive portion of the wall voltage on the scan electrode SCi, the wall voltage on the sustain electrode SUi, and the wall voltage on the data electrode Dk, and the wall voltage in the discharge cell The wall voltage is adjusted to a suitable level.

When the voltage applied to scan electrode SC1 through scan electrode SCn reaches voltage Vi, the voltage applied to scan electrode SC1 through scan electrode SCn is increased to voltage Vc in preparation for the address period of the subsequent subfield.

In this way, in the erasing period, erasing that selectively generates erasing discharges in the discharge cells that generated the sustaining discharge in the immediately preceding sustaining period (in the subfield in which the sustaining period is omitted, the discharge cell in which the addressing discharge occurred) Perform the action.

Thus, the erasing period in the subfield SF1 ends.

Thus, subfield SF1 is completed.

In the write period, sustain period, and erase period from subfield SF2 to subfield SF10, drive voltage waveforms similar to those in the write period, sustain period, and erase period of subfield SF1 are applied to each electrode, except for the number of sustain pulses. .

In the present embodiment, in the erasing period of each subfield, an erasing discharge is generated only in the discharge cells in which the address discharge is generated in the address period of the subfield to which the erasing period belongs, and in the discharge cells in which the address discharge is not generated. Erase discharge does not occur. Accordingly, in a discharge cell displaying black (gradation value “0”) that does not generate a sustain discharge, neither an initializing discharge, an address discharge, a sustain discharge, nor an erasing discharge is generated. There is no light emission.

In this embodiment, the voltage value applied to each electrode is, for example, voltage Vi = −260 (V), voltage Vc = −145 (V), voltage Va = −280 (V), voltage Vs = 200 (V ), Voltage Vr = 200 (V), voltage Ve = 20 (V), and voltage Vd = 60 (V).

Note that the specific numerical values of the voltage values described above are merely examples, and the present invention is not limited to the numerical values described above. Each voltage value is desirably set optimally based on the discharge characteristics of panel 10 and the specifications of the plasma display device.

The subfield configuration described above is merely an example in the present embodiment, and the present invention is not limited to this subfield configuration. It is desirable to optimally set the number of subfields constituting one field and the luminance weight of each subfield according to the characteristics of the panel and the specifications of the plasma display device.

In the above description of the wall voltage, the wall voltage on each electrode is shown assuming a reference potential of wall voltage 0 (V) inside the discharge cell space. However, what is important in considering the wall voltage is, as is well known, the difference in the wall voltage between the electrodes, and the change in the wall voltage on each electrode.

The discharge start voltage VFds and the discharge start voltage VFsd of the panel 10 used in the present embodiment are measured by the method described later, and their values are as follows.

The discharge start voltage varies depending on the phosphor. The inventor of the present application measured the panel 10, and in the discharge cell coated with the red phosphor, the discharge start voltage VFds between the “data electrode 32 and the scan electrode 22” was 200 ± 10 (V), and the discharge start voltage was The VFsd was 320 ± 10 (V).

In the discharge cell coated with green phosphor, the discharge start voltage VFds between “data electrode 32 and scan electrode 22” is 220 ± 10 (V), and the discharge start voltage VFsd is 350 ± 10 (V). there were.

In the discharge cell coated with blue phosphor, the discharge start voltage VFds between the “data electrode 32 and the scan electrode 22” is 200 ± 10 (V), and the discharge start voltage VFsd is 330 ± 10 (V). there were.

The discharge start voltage VFss between the “scan electrode 22 and the sustain electrode 23” is 250 ± 10 (V) in the discharge cell coated with the red phosphor and the discharge cell coated with the blue phosphor. It was 280 ± 10 (V) in the discharge cell coated with the phosphor.

In the present embodiment, the low-voltage side voltage of the sustain pulse is the voltage 0 (V), and the voltage applied to the data electrode 32 during the sustain period is the voltage 0 (V), so the first voltage V1 is the voltage 0. (V). Further, since the low-voltage side voltage of the scan pulse is the voltage Va and the low-voltage side voltage of the write pulse is the voltage 0 (V), the third voltage V3 is the voltage Va (−280 (V)).

Further, the discharge start voltage VFds is larger in the discharge cell coated with the green phosphor than the other discharge cells, and its maximum value is the voltage 230 (V) in consideration of variation. As described above, (Condition 1) is (first voltage V1−third voltage V3) ≧ VFds. And
(First voltage V1−third voltage V3) = 0−Va = 280 (V)
And
(Maximum value of VFds) = 230 (V)
It is. That is,
(First voltage V1−third voltage V3)> (maximum value of VFds)
Thus, it can be seen that (condition 1) is satisfied in all discharge cells.

Further, since the high-voltage side voltage of the sustain pulse is the voltage Vs and the voltage applied to the data electrode 32 in the sustain period is the voltage 0 (V), the second voltage V2 is the voltage Vs (200 (V)). . Further, the discharge start voltage VFsd is smaller in the discharge cell coated with the red phosphor than the other discharge cells, and its minimum value is the voltage 310 (V) in consideration of variation. The discharge start voltage VFds is smaller in discharge cells coated with red and blue phosphors than other discharge cells, and its minimum value is a voltage 190 (V) in consideration of variation. Therefore, the minimum value of the sum of the discharge start voltage VFsd and the discharge start voltage VFds is the voltage 500 (V).

As described above, (condition 2) is (second voltage V2−third voltage V3) <(VFds + VFsd). And
(Second voltage V2−third voltage V3) = Vs−Va = (200 + 280) (V)
And
Minimum value of (VFds + VFsd) = 500 (V)
Therefore, 480 (V) <500 (V). That is,
The minimum value of (second voltage V2−third voltage V3) <(VFds + VFsd) is satisfied, and it can be seen that (condition 2) is satisfied in all discharge cells.

Further, as apparent from the above voltage, a voltage not lower than the voltage Va which is the low voltage side voltage of the scan pulse and not higher than the voltage Vs which is the high voltage side voltage of the sustain pulse is applied to the scan electrode 22. In other words, a voltage lower than the voltage Va that is the low-voltage side voltage of the scan pulse or a voltage that exceeds the voltage Vs that is the high-voltage side voltage of the sustain pulse is not applied to the scan electrode 22. Therefore, the discharge cells that did not generate the address discharge do not emit light.

Further, as apparent from the above voltage, when the voltage Va is set low so as to satisfy (Condition 1), the absolute value | Va | of the voltage Va which is the low-voltage side voltage of the scan pulse is the high-voltage side voltage of the sustain pulse. Is larger than the absolute value | Vs | of the voltage Vs.

As described above, in this embodiment, the drive voltage waveform applied to each electrode, in particular, the voltage Va of the scan pulse is set so as to satisfy (Condition 1) and (Condition 2).

That is, during the erasing period, an erasing discharge is selectively generated only in the discharge cells that have generated the address discharge in the address period of the subfield to which the erasing period belongs. As described with reference to FIG. 4, the voltage obtained by subtracting the third voltage V3 from the first voltage V1 is equal to or higher than the discharge start voltage VFds (Condition 1), and the second voltage V2 to the third voltage. The voltage obtained by subtracting V3 does not exceed the sum of the discharge start voltage VFds and the discharge start voltage VFsd (condition 2).

By setting in this way, address discharge is generated in the discharge cells that should generate address discharge, and address discharge is not generated in discharge cells that should not generate address discharge, even if forced initialization is not performed. Can do. That is, the write operation can be performed stably. The reason is considered as follows.

First, (Condition 1) will be described.

In order to generate the address discharge, it is necessary to start the discharge between the data electrode Dj and the scan electrode SCi. In order to start a discharge by applying a relatively low voltage Vd to the data electrode Dj, a voltage substantially equal to the discharge start voltage VFds is applied between the data electrode Dj and the scan electrode SCi when a scan pulse is applied to the scan electrode SCi. A sufficient positive wall voltage must be accumulated on the data electrode Dj so as to be applied between them.

As described above, the forced initialization operation is not performed in this embodiment. Therefore, in the discharge cell displaying black (gradation value “0”), neither an initializing discharge, an addressing discharge, a sustaining discharge, nor an erasing discharge is generated. Therefore, it is difficult to appropriately control the wall voltage, and the wall voltage of the discharge cell displaying black tends to be unstable.

However, even in such a discharge cell, if there are a few charged particles in the discharge space, they move to each electrode so as to relax the electric field inside the discharge space and adhere to the wall of the discharge cell. Then, wall voltage is accumulated.

The wall voltage accumulated in this way will be described.

During the sustain period, a large amount of charged particles are generated in the discharge cell that generates the sustain discharge. Therefore, it is considered that a small amount of charged particles are supplied to the inside of the discharge cell that does not generate the sustain discharge by diffusing these charged particles into the peripheral discharge cells.

In the discharge cell supplied with charged particles, the wall voltage is slowly accumulated on the electrodes so as to alleviate the potential difference between the electrodes by the voltages applied to the scan electrodes SCi, the sustain electrodes SUi, and the data electrodes Dj. It will be done.

At this time, if the voltage at which the wall voltage is asymptotic (finally settled) is defined as the neglected wall voltage, the neglected wall voltage when the sustain pulse is alternately applied to the scan electrode SCi and the sustain electrode SUi is It is a voltage between the high voltage and the low voltage. Actually, since the drive voltage waveform other than the sustain pulse is also applied to the discharge cell, it is considered that the neglected wall voltage of each discharge cell is substantially close to the low voltage of the sustain pulse.

Also, the neglected wall voltage is greatly affected by the charging characteristics of the phosphor applied inside the discharge cell. In the present embodiment, the charging characteristics of the phosphor are +20 (μC / g) for the red phosphor, −30 (μC / g) for the green phosphor, and +10 (μC) for the blue phosphor. / G). As described above, since only the green phosphor has a characteristic of being charged to a negative potential, the leaving wall voltage of the discharge cell coated with the green phosphor is lower than that of the discharge cell coated with the red or blue phosphor. .

Next, the voltage inside the discharge cell during the address period will be described.

The wall voltage is gradually accumulated on the data electrode Dh of the discharge cell displaying black without generating the address discharge, generally toward the low-voltage side voltage of the sustain pulse or the neglected wall voltage higher than that.

On the other hand, the voltage Va of the scan pulse in the present embodiment is a voltage satisfying (Condition 1). Therefore, a positive wall voltage sufficient to generate the address discharge is accumulated on the data electrode Dh, and the address discharge can be generated in the discharge cells without performing any forced initialization operation.

Also, the wall voltage of the discharge cell displaying black gradually approaches the left wall voltage. When the voltage obtained by adding the wall voltage to the voltage between the “data electrode 32 and the scanning electrode 22” approaches the discharge start voltage in the erasing period, a dark current (current that flows in a state where no discharge occurs) flows, and the wall on the data electrode Dh The voltage drops.

And the dark current flowing at this time plays a role of priming particles that help to generate the address discharge. Therefore, it is considered that even a discharge cell displaying black can generate a stable address discharge without causing a large discharge delay time.

As described above, in this embodiment, by setting each voltage value so that the drive voltage applied to each electrode satisfies (Condition 1), the voltage Va of the scan pulse in the address period is particularly (Condition 1). By setting it low so as to satisfy the above condition, the wall voltage necessary for the address discharge can be accumulated in the discharge cell without performing the forced initialization operation before the address period. Furthermore, a dark current that plays the role of priming particles for stably generating the address discharge can be generated in the discharge cell.

Next, (Condition 2) will be described.

If the voltage Va of the scan pulse is too low, a sustain discharge is generated even in a discharge cell that does not perform an address operation and should not generate a sustain discharge when the sustain pulse voltage Vs is applied to the scan electrode SCn in the sustain period. Resulting in. In order to suppress this erroneous discharge, each voltage must be set so that the voltage between the “data electrode 32 and the scan electrode 22” becomes equal to or lower than the discharge start voltage VFsd when the sustain pulse voltage Vs is applied. I must. This condition is (Condition 2).

Thus, in this embodiment, the drive voltage waveform is set so as to satisfy (Condition 1) and (Condition 2) in all the discharge cells. Therefore, the address discharge can be stably generated even if the forced initialization operation is omitted. As a result, it is possible to display an image without causing light emission not related to gradation display.

In the present embodiment, in the erase period of each subfield, an erase discharge is generated only in the discharge cells in which the address discharge is generated in the address period of the subfield to which the erase period belongs, and the discharge in which the address discharge is not generated. Erase discharge does not occur in the cell. Accordingly, in a discharge cell displaying black (gradation value “0”) that does not generate a sustain discharge, neither an initializing discharge, an address discharge, a sustain discharge, nor an erasing discharge is generated. There is no light emission.

That is, according to the present embodiment, a stable writing operation can be performed without performing a forced initialization operation, black luminance can be suppressed, and an image with high contrast can be displayed on the panel 10.

In the present embodiment, the slope of the rising ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn in the erasing period is 10 (V / μsec), and the slope of the falling ramp waveform voltage is −1.5 (V / μsec). However, this numerical value is only one example when generating an up-slope waveform voltage and a down-slope waveform voltage, and the present invention does not limit the slope of the up-slope waveform voltage and the down-slope waveform voltage to these values. Absent.

Thus, in the present embodiment, a weak erasing discharge is repeatedly generated a plurality of times during the erasing period without using the forced initialization operation, and a weak erasing discharge is repeatedly generated several times. Since the wall voltage can be accumulated in the discharge cell and the priming particles can be generated, the address discharge can be stably generated in the subsequent address period.

Note that the discharge start voltage VFsd, the discharge start voltage VFds, and the wall voltage can be easily measured, for example, by the method described below.

FIG. 5 is a diagram showing an example of a method for simply measuring the discharge start voltage.

First, the wall charge is erased. Specifically, as shown in the wall charge erasing period of FIG. 5, a pulse voltage Vers sufficiently higher than the expected discharge start voltage is alternately applied between the electrodes to be measured, for example, the data electrode 32 and the scan electrode 22. Apply to.

Next, observe the start of discharge. Specifically, as shown in the measurement period of FIG. 5, a pulsed voltage Vmsr lower than the expected discharge start voltage is applied to one electrode (for example, the data electrode 32). Then, light emission due to the discharge at that time is detected by using a light detection sensor such as a photomultiplier.

When no light emission is observed, no discharge has occurred, so after performing the operation to erase the wall charge again during the wall charge elimination period, the pulse whose absolute value of the voltage was slightly increased from the previous time during the measurement period Is applied to the same electrode (for example, the data electrode 32) to observe light emission.

This operation is repeated until luminescence is observed. Thus, the minimum value of the absolute value of the voltage Vmsr when light emission is observed in the measurement period is the discharge start voltage.

At this time, if the voltage Vmsr applied in the measurement period is a positive voltage, the discharge start voltage VFds of the discharge with the data electrode 32 as the anode and the scan electrode 22 as the cathode can be measured. Further, when the voltage Vmsr applied in the measurement period is a negative voltage, the discharge start voltage VFsd of the discharge having the data electrode 32 as a cathode and the scan electrode 22 as an anode can be measured.

If the discharge start voltage is known, the voltage at which discharge starts is measured for the discharge cell in which the wall voltage is accumulated, and the wall voltage can be known as the difference between the voltage value and the discharge start voltage measured in advance. .

Alternatively, the discharge start voltage VFsd, the discharge start voltage VFds, and the wall voltage can be obtained from IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-24, NO. 7, JULY, 1977 “Measurement of a Plasma in the AC Plasma Display panel Usage RF Capacitance and Microwave Techniques”, etc.

Next, a method for emitting light from the discharge cell with brightness according to the gradation value will be described. In this embodiment, an image is displayed on panel 10 using a subfield method. In the subfield method, one field is composed of a plurality of subfields whose luminance weights are determined in advance, and a subfield that emits light is selected according to the magnitude of the gradation value to be displayed.

For example, in the discharge cell displaying the gradation value “0”, the address operation is not performed in all the subfields from the subfield SF1 to the subfield SF10. As a result, the sustain discharge never occurs in the discharge cell, and the gradation value “0” having the lowest luminance is displayed.

Also, for example, in the discharge cell displaying the gradation value “1”, the address operation is performed only in the subfield SF1 that is the subfield having the luminance weight “1”, and the address operation is not performed in the other subfields. As a result, the number of sustain discharges corresponding to the luminance weight “1” is generated in the discharge cell, and light emission with brightness corresponding to the gradation value “1” is generated, and the gradation value “1” is displayed.

Further, for example, in a discharge cell displaying a gradation value “9”, a subfield SF1 having a luminance weight “1”, a subfield SF2 having a luminance weight “2”, and a subfield SF4 having a luminance weight “6”. The write operation is performed, and the write operation is not performed in the other subfields. As a result, the number of sustain discharges corresponding to the luminance weight “9” is generated in the discharge cell, and the light emission having the brightness corresponding to the gradation value “9” is generated to display the gradation value “9”.

The same applies to the case where other gradation values are displayed on the panel 10. That is, subfields for which an address operation is performed are selected for each discharge cell according to the magnitude of the gradation value assigned to each discharge cell, and the address operation is performed in those subfields. Thereby, in each discharge cell, the sustain discharge is generated a number of times according to the gradation value assigned to each discharge cell, and light emission having brightness corresponding to each gradation value is generated and the gradation value is displayed. .

As described above, in the plasma display device that displays an image on the panel 10 by the subfield method, each subfield generates a sustain pulse as many times as the luminance weight and emits light according to the gradation value to be displayed. Select. By doing so, each discharge cell generates sustain discharges the number of times corresponding to the gradation value to be displayed, causes the discharge cell to emit light with the luminance corresponding to the gradation value, and displays an image on the panel 10. .

Therefore, the gradation value that can be displayed on the panel 10 does not continuously change from the minimum gradation value to the maximum gradation value. The gradation values that can be displayed on the panel 10 change discretely, and the amount of change is additive. For example, in the subfield configuration described above, the minimum value when increasing the gradation value is the gradation value “1”, and the gradation value that can be displayed on the panel 10 is from the minimum value to the maximum value of the gradation value. Gradation value “1” such as gradation value “0”, gradation value “1”, gradation value “2”,..., Gradation value “255”. Increase by increments.

On the other hand, the brightness perceived by humans changes logarithmically with changes in luminance, as is generally known. Therefore, for example, when the gradation value is changed from the minimum value to the maximum value that can be displayed on the panel 10, the gradation value is changed at equal intervals (for example, the gradation value). Despite being changed by “1”, a person observing the change in the brightness of the panel 10 does not perceive that the brightness is changing at equal intervals. For humans observing changes in the brightness of the panel 10, the brightness changes more greatly when the gradation value is small than when the gradation value is large. Perceived as.

A specific example will be described. When the gradation value displayed on the panel 10 changes from the gradation value “0” to the gradation value “1”, the gradation value “199” changes to the gradation value “1”. When the change to 200 is compared, the amount of change is equal to the gradation value “1”. However, the change in brightness perceived by humans is changed from the gradation value “199” to the gradation value “200”. It is larger when the gradation value is changed from “0” to the gradation value “1” than when it is changed.

Therefore, for a user who appreciates the image displayed on the panel 10, when the dark image is displayed on the panel 10, the gradation changes more roughly than when the bright image is displayed. May be perceived.

Therefore, if the gradation values used for display are limited to only the gradation values that can be displayed on the panel 10, the gradation display capability (ability to display an image smoothly) when displaying a dark image is reduced.

Therefore, in the plasma display device according to the present embodiment, an intermediate gradation value can be displayed in a pseudo manner by performing dither processing or error diffusion processing on the image signal, and the gradation value that can be displayed on the panel 10. Has increased. Thereby, the gradation display capability in the plasma display device is improved, and a smoother image can be displayed.

Next, dither processing will be described.

Hereinafter, a method of displaying the gradation value (intermediate gradation value) between the gradation value “0” and the gradation value “1” on the panel 10 in a pseudo manner will be described as an example. The gradation value “0” is black, and is a gradation value that does not emit light (emission by sustain discharge) in all subfields. The gradation value “1” is a gradation value in which only the subfield with the smallest luminance weight (for example, subfield SF1) emits light and the other subfields do not emit light. Therefore, the gradation value between the gradation value “0” and the gradation value “1” cannot be displayed on the panel 10 without performing the dither process (or error diffusion process).

In the present embodiment, when an intermediate gradation value between the gradation value “0” and the gradation value “1” is displayed on the panel 10, the gradation value “0” is based on a predetermined dither pattern. The dither processing is performed by arranging the discharge cells displaying "" and the discharge cells displaying the gradation value "1".

In the following FIGS. 6A, 6B, and 6C, black wrinkles represent discharge cells that display a gradation value “0”, and white wrinkles represent discharge cells that display a gradation value “1”.

FIG. 6A is a diagram schematically showing an example of a dither pattern used for dither processing in the plasma display device according to one embodiment of the present invention.

FIG. 6A shows an example of a dither pattern when the minimum value of the intermediate gradation value is the gradation value “1/2”. In this case, the dither block, which is the minimum block constituting the dither pattern, is composed of two discharge cells.

In FIG. 6A, the discharge cell displaying the gradation value “0” and the discharge cell displaying the gradation value “1” are adjacent to each other. However, in the dither pattern of FIG. Although omitted, the discharge cells are not actually adjacent. For example, when dither processing is performed for a blue gradation value, a discharge cell displaying a gradation value “0” and a discharge cell displaying a gradation value “1” for a blue discharge cell are based on a dither pattern. Arrange. The same applies to the gradation values of other colors, and the same applies to the other dither patterns shown below.

In the dither pattern shown in FIG. 6A, as shown in the dither block in FIG. 6A, the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are generated at a ratio of 1: 1. To do. As a result, a dither pattern (checkered dither pattern) is generated in which discharge cells displaying the gradation value “0” and discharge cells displaying the gradation value “1” are arranged in a checkered pattern at a ratio of 1: 1. The gradation value “1/2” can be displayed on the panel 10 in a pseudo manner.

FIG. 6B is a diagram schematically showing another example of a dither pattern used for dither processing in the plasma display device according to one embodiment of the present invention.

In FIG. 6B, the minimum value of the intermediate gradation value is the gradation value “1/4”, the gradation value “1/4”, the gradation value “2/4”, and the gradation value “3/4”. An example of a dither pattern when each gradation value is displayed on the panel 10 is shown. In this case, the dither block, which is the smallest block constituting the dither pattern, is composed of four discharge cells.

In the dither pattern shown in FIG. 6B, as shown in the dither block in FIG. 6B, when the gradation value “1/4” is displayed, the discharge cell displaying the gradation value “0” and the gradation value “1” are displayed. The discharge cells to be displayed are generated at a ratio of 3: 1. As a result, a dither pattern in which the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are arranged at a ratio of 3: 1 can be generated. The tone value “1/4” can be displayed on the panel 10.

When displaying the gradation value “2/4”, the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are generated at a ratio of 2: 2. As a result, a dither pattern (checkered dither pattern) is generated in which discharge cells displaying gradation value “0” and discharge cells displaying gradation value “1” are arranged in a checkered pattern at a ratio of 2: 2. The gradation value “2/4” can be displayed on the panel 10 in a pseudo manner.

When displaying the gradation value “3/4”, the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are generated at a ratio of 1: 3. As a result, a dither pattern in which the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are arranged at a ratio of 1: 3 can be generated. The tone value “3/4” can be displayed on the panel 10.

FIG. 6C is a diagram schematically showing still another example of the dither pattern used for the dither process in the plasma display device according to the embodiment of the present invention.

In FIG. 6C, the minimum value of the intermediate gradation value is the gradation value “1/8”, the gradation value “1/8”, the gradation value “2/8”, the gradation value “3/8”, The dither pattern for displaying the gradation value “4/8”, gradation value “5/8”, gradation value “6/8”, gradation value “7/8” on the panel 10 An example is shown. In this case, the dither block, which is the minimum block constituting the dither pattern, is composed of eight discharge cells. However, in this case, the discharge cells are not arranged in 2 rows and 4 columns or 4 rows and 2 columns, but the discharge cells are arranged in a “+” shape to form a dither block.

In the dither pattern shown in FIG. 6C, as shown in the dither block in FIG. 6C, when the gradation value “1/8” is displayed, the discharge cell displaying the gradation value “0” and the gradation value “1” are displayed. The discharge cells to be displayed are generated at a ratio of 7: 1. As a result, a dither pattern can be generated in which the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are arranged at a ratio of 7: 1. The tone value “1/8” can be displayed on the panel 10.

When displaying the gradation value “2/8”, the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are generated at a ratio of 6: 2. As a result, a dither pattern in which the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are arranged at a ratio of 6: 2 can be generated. The tone value “2/8” can be displayed on the panel 10.

When displaying the gradation value “3/8”, the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are generated at a ratio of 5: 3. As a result, a dither pattern can be generated in which the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are arranged at a ratio of 5: 3. The tone value “3/8” can be displayed on the panel 10.

When displaying the gradation value “4/8”, the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are generated at a ratio of 4: 4. As a result, a dither pattern (checkered dither pattern) is generated in which the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are arranged in a checkered pattern at a ratio of 4: 4. The pseudo gradation value “4/8” can be displayed on the panel 10.

When displaying the gradation value “5/8”, the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are generated at a ratio of 3: 5. As a result, a dither pattern in which the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are arranged at a ratio of 3: 5 can be generated. The tone value “5/8” can be displayed on the panel 10.

When displaying the gradation value “6/8”, discharge cells displaying the gradation value “0” and discharge cells displaying the gradation value “1” are generated at a ratio of 2: 6. As a result, a dither pattern in which the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are arranged at a ratio of 2: 6 can be generated. The tone value “6/8” can be displayed on the panel 10.

When displaying the gradation value “7/8”, the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are generated at a ratio of 1: 7. As a result, a dither pattern in which the discharge cells displaying the gradation value “0” and the discharge cells displaying the gradation value “1” are arranged at a ratio of 1: 7 can be generated. The tone value “7/8” can be displayed on the panel 10.

In the above-described example, the example in which the gradation value between the gradation value “0” and the gradation value “1” is pseudo-displayed on the panel 10 has been described. However, in the present embodiment, the following rules are used. By creating a dither pattern on the basis, a gradation value between any two gradation values can be displayed on the panel 10 in a pseudo manner.

Hereinafter, an example in which the gradation value between the gradation value “a” and the gradation value “b” is displayed on the panel 10 in a pseudo manner using the gradation value “a” and the gradation value “b”. explain.

The gradation value “a” and the gradation value “b” are equally divided into N, and (N−1) intermediate gradations between the gradation value “a” and the gradation value “b”. In order to be able to display the value on the panel 10 in a pseudo manner, the dither block is composed of N discharge cells. At this time, the discharge cells may be arranged so that the dither block has a square shape. However, when the number of N is large, for example, as shown in FIG. 6C, the discharge cells are arranged so as to have a non-rectangular shape. May be. Note that a is an integer greater than or equal to “0”, b is an integer greater than or equal to “1”, and N is an integer greater than or equal to “2”.

When the gradation value “(na + (N−n) b) / N” is displayed on the panel 10 in a pseudo manner, the gradation value “a” is displayed in n discharge cells of the dither block, The gradation value “b” is displayed by the remaining (N−n) discharge cells. Then, this dither block is generated so that no gap is generated in the area of the panel 10 where the gradation value “(na + (N−n) b) / N” is displayed and no overlap occurs. By doing so, the pseudo gradation value “(na + (N−n) b) / N” can be displayed on the panel 10. Note that n is an integer of 1 or more and less than N.

For example, the gradation value “5” (a = 5) and the gradation value “6” (b = 6) are equally divided into four (N = 4), and the gradation value “5.25” In order to make it possible to display three intermediate gradation values (N−1 = 3) of the value “5.50” and the gradation value “5.75” on the panel 10 in a pseudo manner, FIG. As shown in the example, the dither block is composed of four discharge cells. When the gradation value “5.25” (n = 1) is displayed on the panel 10 in a pseudo manner, the gradation value “5” is displayed in one discharge cell of the dither block, and the remaining three The gradation value “6” is displayed in the discharge cell. The dither block is generated so that no gap is generated in the area of the panel 10 where the gradation value “5.25” is displayed and no overlap occurs. In this way, the gradation value “5.25” can be displayed on the panel 10 in a pseudo manner.

This makes it possible to display an arbitrary number of intermediate gradation values between arbitrary gradation values on the panel 10 in a pseudo manner.

Next, a drive circuit for driving the panel 10 will be described.

FIG. 7 is a circuit block diagram of the plasma display device 40 in one embodiment of the present invention.

The plasma display apparatus 40 uses a panel 10 having a plurality of discharge cells each having a scan electrode 22, a sustain electrode 23, and a data electrode 32, and a single field using a plurality of subfields having an address period, a sustain period, and an erase period. And a drive circuit that generates the drive voltage waveform shown in FIGS. 3 and 4 and applies it to each electrode of the panel 10 to drive the panel 10.

The drive circuit is necessary for the image signal processing circuit 41, the data electrode drive circuit 42, the scan electrode drive circuit 43, the sustain electrode drive circuit 44, the timing generation circuit 45, the temperature detection circuit 96, the cumulative operation time measurement circuit 98, and each circuit block. A power supply circuit (not shown) for supplying a proper power supply is provided.

The temperature detection circuit 96 includes a temperature sensor 97 made of a generally known element such as a thermocouple used for detecting the temperature, and detects the temperature of the panel 10. Then, the temperature of the panel 10 detected by the temperature sensor 97 is compared with a plurality of predetermined temperature thresholds to determine what the temperature of the panel 10 is, and the result is subjected to image signal processing. Output to the circuit 41. Specifically, the temperature threshold is set to 5 ° C., 10 ° C., 20 ° C., and the panel temperature is lower than 5 ° C., 5 ° C. or higher, lower than 10 ° C. And a signal indicating the result is output to the image signal processing circuit 41 (low luminance amplification circuit 46).

The accumulated operation time measuring circuit 98 has a generally known timer 99 having an integration function in which a numerical value increases by a certain amount per unit time during an energization period of the panel 10 (during the operation period of the panel 10). In the timer 99, the measurement time is accumulated without being reset. That is, even when the power of the plasma display device 40 is turned off, the measurement time is not reset and the measurement time immediately before the power is turned off is held in the timer 99, and the plasma display device 40 is turned on again. The operation time of the plasma display device 40 is measured by the timer 99 following the measurement time up to the previous time. Thereby, the accumulated operation time measuring circuit 98 can measure the accumulated operation time (accumulated operation time) of the plasma display device 40 after the plasma display device 40 starts the operation for the first time. That is, the cumulative operation time measuring circuit 98 measures the cumulative operation time of the panel 10.

Then, the cumulative operation time measuring circuit 98 compares the cumulative operation time of the panel 10 measured by the timer 99 with a plurality of predetermined cumulative time thresholds to determine whether or not the cumulative operation time of the panel 10 has exceeded a predetermined time. A signal representing the result of the determination is output to the image signal processing circuit 41. Specifically, 500 hours, 1000 hours, and 2000 hours are set as the cumulative time threshold, and the cumulative operation time is less than 500 hours, 500 hours or more and less than 1000 hours, 1000 hours or more and less than 2000 hours, or 2000 hours. Whether it is the above or not is determined, and a signal indicating the result is output to the image signal processing circuit 41 (low luminance amplification circuit 46).

Note that each of the above-described threshold values is merely an example in the present embodiment, and the present invention is not limited to the above-described numerical values. Each threshold value is desirably set to an optimum value based on the characteristics of the panel 10 and the specifications of the plasma display device 40.

The image signal processing circuit 41 includes a low luminance amplification circuit 46, a dither processing circuit 47, and a subfield conversion circuit 48.

The low luminance amplifying circuit 46 converts each of the input image signals of the red primary color signal sigR, the green primary color signal sigG, and the blue primary color signal sigB (hereinafter simply referred to as “image signal”) of the image signal. Amplification is performed at an amplification factor corresponding to the magnitude and the temperature detected by the temperature detection circuit 96 and the cumulative operation time measured by the cumulative operation time measurement circuit 98. Although details will be described later, in this embodiment, the amplification factor is non-linear, and the low luminance amplifier circuit 46 outputs an image signal having a signal level (signal magnitude) less than the gradation value “1”. Amplification is performed with an amplification factor larger than the amplification factor of an image signal equal to or higher than the signal level corresponding to the gradation value “1”. Hereinafter, an image signal having a signal level corresponding to the gradation value “1” is simply referred to as an “image signal having a gradation value“ 1 ””. In the discharge cell displaying the gradation value “1”, only the subfield with the smallest luminance weight (for example, subfield SF1) emits light, and the other subfields do not emit light.

As will be described later, the correction performed in the low luminance amplifier circuit 46 is to amplify the input signal at an amplification factor corresponding to the probability of occurrence of a defective discharge and output it to compensate for a decrease in luminance caused by the defective discharge. This is not a correction such as contrast adjustment or brightness adjustment that is generally performed to improve the brightness of the display image.

The dither processing circuit 47 sets a gradation value for each discharge cell based on the image signal output from the low luminance amplification circuit 46 and the luminance weight assigned to each subfield. The image signals input to the dither processing circuit 47 are a red primary color signal sigR, a green primary color signal sigG, and a blue primary color signal sigB. The dither processing circuit 47 converts the primary color signal sigR, the primary color signal sigG, and the primary color signal sigB. First, R, G, and B gradation values (gradation values expressed in one field) are set in each discharge cell. Then, with respect to intermediate gradation values that cannot be expressed by light emission and non-light emission for each subfield, dither processing using the above-described dither pattern or the like is performed. The dither processing can be realized, for example, using a circuit described in JP-A-2004-138383.

The subfield conversion circuit 48 converts the signal (grayscale value) output from the dither processing circuit 47 into image data indicating light emission / non-light emission for each subfield (light emission / non-light emission is a digital signal “1”, “0 ”). That is, the subfield conversion circuit 48 converts the image signal for each field (gradation value based on the image signal) into image data indicating light emission / non-light emission for each subfield. The subfield conversion circuit 48 can be configured using, for example, a semiconductor memory device that stores a conversion table in which gradation values and image data are associated with each other.

Note that the image signal processing circuit 41 does not input a primary color image signal but a luminance signal (Y signal) and a saturation signal (C signal, or RY signal and BY signal, or u signal, and u signal). 7), the primary color signal sigR, the primary color signal sigG, and the primary color signal sigB are calculated based on the luminance signal and the saturation signal (a circuit block for calculating the primary color signal based on the luminance signal and the saturation signal is shown in FIG. 7). The calculated primary color signal is input to the low luminance amplification circuit 46.

The timing generation circuit 45 forms a single field using a plurality of subfields having a write period, a sustain period, and an erase period based on the horizontal synchronization signal and the vertical synchronization signal, and controls various operations of each circuit block. Generate timing signals. The generated timing signal is supplied to each circuit block (data electrode drive circuit 42, scan electrode drive circuit 43, sustain electrode drive circuit 44, image signal processing circuit 41, etc.).

Scan electrode drive circuit 43 includes a ramp waveform voltage generation circuit, a sustain pulse generation circuit, and a scan pulse generation circuit (not shown in FIG. 7) so as to satisfy the above-described two conditions (condition 1) and (condition 2). The drive voltage waveforms shown in FIGS. 3 and 4 are generated based on the timing signal supplied from the timing generation circuit 45 and applied to each of the scan electrodes SC1 to SCn. The ramp waveform voltage generating circuit generates a descending ramp waveform voltage to be applied to scan electrode SC1 through scan electrode SCn based on the timing signal during the erase period. The sustain pulse generating circuit generates a sustain pulse to be applied to scan electrode SC1 through scan electrode SCn based on the timing signal during the sustain period. The scan pulse generating circuit includes a plurality of scan electrode driving ICs (scan ICs), and generates scan pulses to be applied to scan electrode SC1 through scan electrode SCn based on a timing signal during an address period.

Sustain electrode drive circuit 44 includes a sustain pulse generation circuit and a circuit for generating voltage Ve (not shown in FIG. 7), and the drive voltage shown in FIG. 3 based on the timing signal supplied from timing generation circuit 45. A waveform is created and applied to each of sustain electrode SU1 through sustain electrode SUn. In the sustain period, a sustain pulse is generated based on the timing signal, and in the erase period and the write period, voltage Ve is generated based on the timing signal and applied to sustain electrode SU1 through sustain electrode SUn.

The data electrode drive circuit 42 converts the data for each subfield constituting the image data based on the image signal into signals corresponding to the data electrodes D1 to Dm. Then, based on the signal and the timing signal supplied from the timing generation circuit 45, the data electrodes D1 to Dm are driven. In the address period, an address pulse is generated and applied to each of the data electrodes D1 to Dm.

Next, the operation of the low luminance amplifier circuit 46 will be described.

FIG. 8 is a diagram schematically showing an operation in the low luminance amplification circuit 46 of the plasma display device 40 in one embodiment of the present invention.

FIG. 9 is an enlarged view showing a part of the operation of the low luminance amplifier circuit 46 of the plasma display device 40 according to the embodiment of the present invention. FIG. 9 is an enlarged view of a part of FIG. 8, that is, an operation when the input image signal is equal to or lower than the gradation value “1” (region surrounded by a circle in FIG. 8).

8 and 9, the horizontal axis indicates the magnitude of an image signal (hereinafter simply referred to as “input signal”) input to the low luminance amplifier circuit 46, and the vertical axis indicates the image signal output by the low luminance amplifier circuit 46. (Hereinafter simply referred to as “output signal”). However, in FIG. 8 and FIG. 9, each of the input signal and the output signal is converted into a gradation value.

In this embodiment, as shown in FIG. 8, the low luminance amplifier circuit 46 sets the amplification factor to “1” when the signal level (signal magnitude) of the input signal is equal to or higher than the gradation value “1”. The output signal is output as the input signal without changing the magnitude of the input signal.

Also, if the signal level of the input signal is less than the gradation value “1”, the low luminance amplification circuit 46 sets the amplification factor to a numerical value of “1” or more, and outputs as output signal ≧ input signal.

However, in the present embodiment, the amplification factor when the signal level of the input signal is less than the gradation value “1” is not maintained at a constant magnitude. The low luminance amplification circuit 46 sets the amplification factor relatively large when the signal level of the input signal is close to the gradation value “0”, and gradually increases the amplification factor from the gradation value “0” to the gradation value “1”. The gain is changed according to the signal level of the input signal (except for the first correction described later) so that the gain becomes “1” when the gradation value is “1”. Therefore, the magnitude of the output signal changes nonlinearly with respect to the magnitude of the input signal (except for the first correction).

In the present embodiment, the low-brightness amplification circuit 46 uses the temperature detected by the temperature detection circuit 96 and the accumulated operation time measurement circuit to calculate the amplification factor when the signal level of the input signal is less than the gradation value “1”. The operation is changed based on the accumulated operation time measured in 98, and details of this operation will be described later.

First, the amplification factor when the signal level of the input signal is less than the gradation value “1” will be described with reference to FIGS. 9, 10A, 10B, 10C, and 10D.

When the signal level of the input signal is less than the gradation value “1”, the low-brightness amplification circuit 46 is different from, for example, the first correction, the second correction, the third correction, and the fourth correction. The input signal is amplified using any one of the amplification factors. As shown in FIG. 9, the amplification factor of each correction has the largest fourth correction, the third correction next, and the second correction next. The first correction has the smallest amplification factor, and the amplification factor is “1”.

FIG. 10A is a diagram illustrating an example of an amplification factor for an input signal in the first correction according to the embodiment of the present invention. FIG. 10B is a diagram showing an example of the amplification factor for the input signal in the second correction according to the embodiment of the present invention. FIG. 10C is a diagram showing an example of the amplification factor for the input signal in the third correction according to the embodiment of the present invention. FIG. 10D is a diagram showing an example of the amplification factor for the input signal in the fourth correction in the embodiment of the present invention. In FIG. 10A, FIG. 10B, FIG. 10C, and FIG. 10D, the input signal and the output signal are respectively converted into gradation values.

In the first correction in the present embodiment, as described above, the amplification factor is set to “1”. Accordingly, when the first correction is applied to the input signal in the low luminance amplifier circuit 46, the magnitude of the output signal is equal to the magnitude of the input signal, as shown in FIG. 10A.

In the second correction in the present embodiment, as described above, the amplification factor is set larger than that in the first correction. As shown in FIG. 10B, the amplification factor when the second correction is applied to the input signal in the low luminance amplifier circuit 46 is “1.370” when the gradation value of the input signal is “0.1”. ”, The amplification factor when the gradation value of the input signal is“ 0.2 ”is“ 1.270 ”, and the amplification factor when the gradation value of the input signal is“ 0.3 ”is“ 1 ”. .237 ”, the amplification factor when the gradation value of the input signal is“ 0.4 ”is“ 1.200 ”, and the amplification factor when the gradation value of the input signal is“ 0.5 ”. The amplification factor is “1.120” when the gradation value of the input signal is “0.6”, and the amplification factor when the gradation value of the input signal is “0.7”. The rate is “1.083”, the amplification factor is “1.055” when the tone value of the input signal is “0.8”, and the tone value of the input signal is “0.9” The amplification factor of Is .029 ", the amplification factor when the gradation value of the input signal is" 1.0 "is" 1.000 ".

Therefore, when the second correction is used in the low luminance amplifier circuit 46, as shown in FIG. 10B, for example, if the gradation value of the input signal is “0.1”, the gradation value of the output signal is “0.1”. If the gradation value of the input signal is “0.5”, the gradation value of the output signal is “0.578”, and the gradation value of the input signal is “0.9”. In this case, the gradation value of the output signal is “0.926”.

In the third correction in the present embodiment, as described above, the amplification factor is set larger than that in the second correction. As shown in FIG. 10C, the amplification factor when the third correction is applied to the input signal in the low luminance amplifier circuit 46 is “1.800” when the gradation value of the input signal is “0.1”. ”, The amplification factor when the gradation value of the input signal is“ 0.2 ”is“ 1.620 ”, and the amplification factor when the gradation value of the input signal is“ 0.3 ”is“ 1 ”. .497 ”, the amplification factor when the gradation value of the input signal is“ 0.4 ”is“ 1.388 ”, and the amplification factor when the gradation value of the input signal is“ 0.5 ”. The amplification factor is “1.217” when the gradation value of the input signal is “0.6”, and the amplification factor when the gradation value of the input signal is “0.7”. The rate is “1.150”, the amplification factor is “1.094” when the gradation value of the input signal is “0.8”, and the gradation value of the input signal is “0.9” The amplification factor of Is .046 ", the amplification factor when the gradation value of the input signal is" 1.0 "is" 1.000 ".

Therefore, when the third correction is used in the low luminance amplifier circuit 46, as shown in FIG. 10C, for example, if the gradation value of the input signal is “0.1”, the gradation value of the output signal is “0.1”. If the gradation value of the input signal is “0.5”, the gradation value of the output signal is “0.645”, and the gradation value of the input signal is “0.9”. In this case, the gradation value of the output signal is “0.941”.

In the fourth correction in the present embodiment, as described above, the amplification factor is set larger than that in the third correction. As shown in FIG. 10D, the amplification factor when the fourth correction is applied to the input signal in the low luminance amplifier circuit 46 is “3.130” when the gradation value of the input signal is “0.1”. The amplification factor when the gradation value of the input signal is “0.2” is “2.400”, and the amplification factor when the gradation value of the input signal is “0.3” is “1”. .980 ”, the amplification factor when the gradation value of the input signal is“ 0.4 ”is“ 1.710 ”, and the amplification factor when the gradation value of the input signal is“ 0.5 ”. The amplification factor when the gradation value of the input signal is “0.6” is “1.355”, and the amplification factor when the gradation value of the input signal is “0.7” The rate is “1.233”, the amplification factor when the gradation value of the input signal is “0.8” is “1.143”, and the gradation value of the input signal is “0.9” The amplification factor of Is .063 ", the amplification factor when the gradation value of the input signal is" 1.0 "is" 1.000 ".

Therefore, when the fourth correction is used in the low luminance amplifier circuit 46, as shown in FIG. 10D, for example, if the gradation value of the input signal is “0.1”, the gradation value of the output signal is “0.1”. If the gradation value of the input signal is “0.5”, the gradation value of the output signal is “0.750” and the gradation value of the input signal is “0.9”. In this case, the gradation value of the output signal is “0.957”.

As described above, in any of the second correction, the third correction, and the fourth correction in the present embodiment, an input image signal having a predetermined magnitude less than the gradation value “1” is converted to the gradation value “ The input image signal is amplified with an amplification factor larger than that of the input image signal of “1” or more, and the amplification factor of the input image signal less than the gradation value “1” is increased as the input image signal becomes smaller (except for the first correction). ).

The low luminance amplifier circuit 46 in the present embodiment is configured to perform the first correction, the second correction, based on the temperature detected by the temperature detection circuit 96 and the accumulated operation time measured by the accumulated operation time measurement circuit 98. Either the third correction or the fourth correction is selected to amplify the input signal.

FIG. 11 shows the temperature detected by the temperature detection circuit 96 and the cumulative operation time measured by the cumulative operation time measurement circuit 98 and the first correction, the second correction, and the third correction in the embodiment of the present invention. FIG. 10 is a diagram schematically showing a relationship with a fourth correction. In FIG. 11, the temperature detected by the temperature detection circuit 96 and the accumulated operation time measurement circuit 98 are selected from the first correction, the second correction, the third correction, and the fourth correction in the low luminance amplifier circuit 46. FIG. 6 schematically shows a selection method when selecting based on the accumulated operation time measured in FIG. In FIG. 11, the vertical cells represent changes in the accumulated operation time (hereinafter simply referred to as “accumulated operation time”) measured by the accumulated operation time measurement circuit 98, and the horizontal cells are detected by the temperature detection circuit 96. Represents the change in temperature.

If the temperature detected by the temperature detection circuit 96 is less than 5 ° C., the low luminance amplification circuit 46 in the present embodiment selects the fourth correction regardless of the accumulated operation time.

In addition, when the temperature detected by the temperature detection circuit 96 is 5 ° C. or higher and lower than 10 ° C., the low luminance amplifier circuit 46 selects the third correction if the cumulative operation time is less than 2000 hours, and the cumulative operation time is If it is 2000 hours or longer, the fourth correction is selected.

Further, when the temperature detected by the temperature detection circuit 96 is not lower than 10 ° C. and lower than 20 ° C., the low luminance amplifier circuit 46 selects the second correction if the cumulative operation time is less than 1000 hours, and the cumulative operation time. If 1000 hours or more and less than 2000 hours, the third correction is selected, and if the cumulative operation time is 2000 hours or more, the fourth correction is selected.

In addition, when the temperature detected by the temperature detection circuit 96 is 20 ° C. or higher, the low luminance amplifier circuit 46 selects the first correction if the cumulative operation time is less than 500 hours, and the cumulative operation time is 500 hours or more. If the accumulated operation time is 1000 hours or less and less than 2000 hours, the third correction is selected. If the accumulated operation time is 2000 hours or more, the fourth correction is selected. select.

As described above, when the temperature detected by the temperature detection circuit 96 is lower than the preset temperature threshold value, the low luminance amplifier circuit 46 according to the present embodiment is when the detected temperature is equal to or higher than the temperature threshold value. Rather, the amplification factor relating to the input image signal having the gradation value less than “1” is increased.

Further, the low luminance amplifier circuit 46 in the present embodiment has a cumulative operation time less than the cumulative time threshold when the cumulative operation time measured by the cumulative operation time measurement circuit 98 is equal to or greater than a preset cumulative time threshold. The amplification factor for the input image signal with the gradation value less than “1” is increased compared to

Next, the reason why the low luminance amplifier circuit 46 in this embodiment performs the above-described operation will be described.

As described above, in the present embodiment, if the signal level of the input signal is less than the gradation value “1”, the gradation value is assigned to the panel 10 using the above-described dither processing (or error diffusion processing) or the like. Is displayed in a pseudo manner.

When an image signal having a gradation value less than “1” is displayed on the panel 10 in a pseudo manner using a dither process such as that shown in FIGS. 6A to 6C, for example, several fields are displayed in the area where the gradation value is displayed. In this case, a discharge cell in which light emission (light emission due to address discharge and sustain discharge) occurs only once occurs.

On the other hand, the probability that the address discharge does not occur normally in the discharge cell (hereinafter also referred to as “discharge failure”) depends on the amount of priming particles present in the discharge cell, and the priming particles are insufficient. The probability of occurrence of defective discharge increases.

Priming particles are generated in the discharge cell by the initialization discharge or the sustain discharge. However, as described above, the plasma display device 40 in the present embodiment does not perform the forced initialization operation. Therefore, in panel 10, the chance of generating priming particles decreases as the discharge cell generates a sustain discharge less frequently. Therefore, in a discharge cell having a large number of fields that do not emit light, the priming particles generated by the sustain discharge are likely to be insufficient, and the probability of occurrence of a discharge failure increases.

In the plasma display device 40 that artificially displays an image signal having a gradation value less than “1” on the panel 10 using dither processing, the frequency of occurrence of the light-emitting field depends on the magnitude of the gradation value. .

For example, if the gradation value of the image signal is relatively small (if the gradation value is close to “0”), the discharge cell that displays the image signal has a low frequency of light emission, and the light emission field. The number of non-light-emitting fields generated from one to the next light-emitting field is relatively increased. Therefore, in the discharge cell, priming particles are likely to be insufficient, and the probability of occurrence of a discharge failure is relatively high.

On the contrary, if the gradation value of the image signal is relatively large (if the gradation value is close to “1”), the discharge cell displaying the image signal has a higher frequency of occurrence of a light emitting field and emits light. The number of non-light emitting fields that occur between the field and the next light emitting field is relatively reduced. Therefore, in the discharge cell, since the priming particles are relatively increased, the probability of occurrence of a discharge failure is relatively low.

Next, the relationship between the probability that a discharge failure will occur in a discharge cell and the gradation value that is displayed on the panel 10 in a pseudo manner using a dither process will be described.

Hereinafter, a case where the gradation value “0.5” is displayed on the panel 10 in a pseudo manner using the dither processing will be described as an example. For example, if the probability of a discharge failure occurring in a discharge cell displaying a gradation value of “0.5” is 20%, the probability that an address discharge will normally occur in that discharge cell is 80%. In that case, the gradation value actually displayed in the discharge cell to display the gradation value “0.5” is
0.5 x 0.8 = 0.4
It becomes. That is, in the discharge cell, a gradation value “0.4” smaller than the gradation value “0.5” to be displayed is displayed.

However, if the probability of occurrence of a discharge failure is known in advance, the gradation value to be displayed is compensated in advance for the gradation value to be displayed in the panel 10 by compensating for the luminance reduced by the discharge failure in advance. It is possible to display.

For example, as described above, if the probability of occurrence of a discharge failure is 20% when the gradation value “0.5” is displayed on the panel 10, the probability that the address discharge will normally occur in that discharge cell is 80%. Therefore, the gradation value “0.5” to be displayed is 0.5 × 1 / 0.8 = 0.625.
And Thereby, if the probability of occurrence of defective discharge is 20%,
0.625 × 0.8 = 0.5
Thus, the gradation value “0.5” to be displayed can be correctly displayed on the panel 10.

In this embodiment, when the signal level of the input signal is less than the gradation value “1”, the amplification factor is set to a numerical value of “1” or more, and the output signal ≧ the input signal is output for this reason. This is because the gradation value to be displayed is pseudo-displayed on the panel 10 with the correct gradation value.

Strictly speaking, in the above-described example, the probability that a discharge failure occurs when the gradation value “0.5” is displayed on the panel 10 in a pseudo manner using the dither processing, and the gradation value “0. This is different from the probability that a discharge failure occurs when “625” is displayed on the panel 10 in a pseudo manner using a dither process. Therefore, even if the gradation value “0.625” is displayed on the panel 10 by using the dither processing, the gradation value that is pseudo-displayed on the panel 10 is not strictly “0.5”. As described above, since the probability of occurrence of a discharge failure decreases as the gradation value increases, the level displayed in a pseudo manner when the gradation value “0.625” is displayed on the panel 10 using the dither processing. The tone value is slightly larger than “0.5”. Therefore, it is desirable to set the amplification factor in consideration of these points.

Note that the temperature of the panel 10 is one factor that increases the probability that a discharge failure will occur in the discharge cell.

It is considered that initial electrons that cause discharge in the discharge cell are released from magnesium oxide used in the protective layer 26. The amount of initial electrons generated in the discharge cell depends on the temperature of magnesium oxide, and it is considered that the amount of initial electrons generated decreases as the temperature decreases. Therefore, when the panel 10 is at a low temperature, it is considered that the amount of initial electrons generated in the discharge cell is reduced compared with when the panel 10 is at a high temperature, and the probability that a discharge failure occurs is increased.

For these reasons, when setting the amplification factor described above, the temperature of the panel 10 is taken into consideration, and if the temperature of the panel 10 is low, the amplification factor is increased as compared with the case where the temperature of the panel 10 is high. It is desirable.

In the present embodiment, the amplification factor when the signal level of the input signal is less than the gradation value “1” is set larger when the temperature detected by the temperature detection circuit 96 is lower than when the temperature is high. This is the reason.

Also, one of the factors that increase the probability that a discharge failure occurs in the discharge cell is the cumulative operation time of the panel 10. The amount of initial electrons generated in the discharge cell depends on the degree of deterioration of magnesium oxide, and it is believed that as the deterioration progresses, the electron emission ability of magnesium oxide decreases and the amount of initial electrons generated also decreases. The progress of this degradation is considered to be one of the causes of ion bombardment (impact caused by ions colliding with the protective layer 26 at a high speed when a discharge is generated). It is thought that deterioration progresses. Therefore, when the cumulative operation time of the panel 10 is increased, the amount of initial electrons generated in the discharge cell is decreased and the probability of occurrence of a discharge failure is increased as compared with the case where the cumulative operation time of the panel 10 is small.

Therefore, when setting the above-described amplification factor, the accumulated operation time of the panel 10 is considered, and if the accumulated operation time of the panel 10 is increased, the amplification is performed more than when the accumulated operation time of the panel 10 is small. It is desirable to increase the rate.

In this embodiment, when the accumulated operation time measured by the accumulated operation time measuring circuit 98 is increased when the signal level of the input signal is less than the gradation value “1”, the accumulated operation time is increased. This is why it is larger than when it is small.

An example of the amplification factor set in consideration of the probability of occurrence of a discharge failure based on the temperature detected by the temperature detection circuit 96 and the cumulative operation time measured by the cumulative operation time measurement circuit 98 is shown in FIG. These are the first correction, the second correction, the third correction, and the fourth correction shown in 10B, FIG. 10C, FIG. 10D, and FIG.

Next, the scan electrode drive circuit 43 will be described.

FIG. 12 is a circuit diagram schematically showing a configuration of scan electrode drive circuit 43 of plasma display device 40 in one embodiment of the present invention. Scan electrode drive circuit 43 includes sustain pulse generation circuit 50, ramp waveform voltage generation circuit 60, and scan pulse generation circuit 70, and operates each circuit based on a timing signal. In the drawings, details of signal paths of control signals (timing signals supplied from the timing generation circuit 45) input to each circuit are omitted.

Sustain pulse generation circuit 50 includes power recovery circuit 51, switching element Q55, switching element Q56, and switching element Q59. Then, sustain pulses to be applied to scan electrode SC1 through scan electrode SCn are generated.

The power recovery circuit 51 recovers the power stored in the panel 10 from the panel 10 using LC resonance, and reuses the recovered power as power when driving the scan electrodes SC1 to SCn. The panel 10 is supplied again.

Switching element Q55 clamps scan electrode SC1 through scan electrode SCn to voltage Vs, and switching element Q56 clamps scan electrode SC1 through scan electrode SCn to voltage 0 (V). The switching element Q59 is a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43.

Scan pulse generation circuit 70 has switching element Q71H1 to switching element Q71Hn, switching element Q71L1 to switching element Q71Ln, switching element Q72, a power supply for negative voltage Va, and a power supply E71 for generating voltage VC. Then, a voltage Vc (Vc = VC + Va) is generated by superimposing the voltage VC on the reference potential (the potential at the node A shown in FIG. 12) of the scan pulse generation circuit 70, and the scan electrode is switched between the voltage Va and the voltage Vc. A scan pulse is generated by applying to SC1 to scan electrode SCn.

For example, if the voltage Va = −280 (V) and the voltage VC = 135 (V), the voltage Vc = −145 (V). Then, a scan pulse is applied to each of scan electrode SC1 through scan electrode SCn at the timing shown in FIG. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 50 as it is during the sustain period. That is, the voltage at node A is output to scan electrode SC1 through scan electrode SCn.

The ramp waveform voltage generation circuit 60 includes a Miller integration circuit 61 and a Miller integration circuit 63, and generates the rising ramp waveform voltage and the falling ramp waveform voltage shown in FIGS.

Miller integrating circuit 61 includes transistor Q61, capacitor C61, and resistor R61, and applies a constant voltage to input terminal IN61 (giving a constant voltage difference between two circles shown as input terminal IN61). As a result, an upward ramp waveform voltage that gently rises from the voltage 0 (V) toward the voltage Vr is generated.

Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63, and applies a constant voltage to input terminal IN63 (giving a constant voltage difference between two circles shown as input terminal IN63). As a result, a downward ramp waveform voltage that gradually decreases from voltage 0 (V) toward voltage Vi is generated.

The switching element Q69 is a separation switch, and is provided to prevent a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode drive circuit 43.

Note that these switching elements and transistors can be configured using generally known semiconductor elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the respective switching elements and transistors generated by the timing generation circuit 45.

Next, the sustain electrode drive circuit 44 will be described.

FIG. 13 is a circuit diagram schematically showing the configuration of the sustain electrode drive circuit 44 of the plasma display device 40 in one embodiment of the present invention. Sustain electrode drive circuit 44 includes sustain pulse generation circuit 80 and constant voltage generation circuit 85, and operates each circuit based on a timing signal. In the drawings, details of signal paths of control signals (timing signals supplied from the timing generation circuit 45) input to each circuit are omitted.

Sustain pulse generation circuit 80 includes a power recovery circuit 81, a switching element Q83, and a switching element Q84. Then, sustain pulses to be applied to sustain electrode SU1 through sustain electrode SUn are generated.

The power recovery circuit 81 recovers the power stored in the panel 10 from the panel 10 using LC resonance and stores it in the power recovery capacitor. Further, in order to reuse the collected power as power for driving sustain electrode SU1 to sustain electrode SUn, the power is supplied again to panel 10 using LC resonance.

Switching element Q83 clamps sustain electrode SU1 through sustain electrode SUn to voltage Vs. Switching element Q84 clamps sustain electrode SU1 through sustain electrode SUn to voltage 0 (V).

The constant voltage generation circuit 85 includes a switching element Q86 and a switching element Q87, and applies the voltage Ve to the sustain electrodes SU1 to SUn.

Note that these switching elements can also be configured by using generally known semiconductor elements such as MOSFETs and IGBTs. These switching elements are also controlled by timing signals corresponding to the respective switching elements generated by the timing generation circuit 45.

Next, the data electrode drive circuit 42 will be described.

FIG. 14 is a circuit diagram schematically showing the configuration of the data electrode drive circuit 42 of the plasma display device 40 in one embodiment of the present invention. In the drawing, details of signal paths of control signals (a timing signal supplied from the timing generation circuit 45 and image data supplied from the image signal processing circuit 41) input to each circuit are omitted.

The data electrode driving circuit 42 has switching elements Q91H1 to Q91Hm and switching elements Q91L1 to Q91Lm. Then, based on the image data (details of the image data are omitted in the drawing), the switching element Q91Lj is turned on to apply the voltage 0 (V) to the data electrode Dj and the switching element Q91Hj is turned on. A voltage Vd is applied to the electrode Dj.

In this embodiment, for example, the drive voltage waveforms shown in FIGS. 3 and 4 can be generated using these drive circuits. However, the drive circuits shown in FIG. 7, FIG. 12, FIG. 13, and FIG. 14 are merely examples of circuit configurations in this embodiment, and the present invention is not limited to these circuit configurations. Is not to be done.

As described above, according to the present embodiment, by generating a scan pulse that satisfies the above-described conditions in the address period and applying it to the scan electrode 22, a stable address operation can be performed without performing a forced initialization operation. It can be carried out. Thereby, black brightness can be suppressed and an image with high contrast can be displayed on the panel 10.

Further, in the present embodiment, when the signal level of the input signal is less than the gradation value “1” in the low luminance amplifier circuit 46, the input signal is amplified with an amplification factor of “1” or more, and the amplified image The panel 10 is driven based on the signal. At this time, when the signal level of the input signal is close to the gradation value “0”, the amplification factor is set relatively large, and the amplification factor is gradually decreased from the gradation value “0” to the gradation value “1”. The gain is changed according to the signal level of the input signal (except for the first correction) so that the gain becomes “1” when the gradation value is “1”.

The amplification factor when the signal level of the input signal is less than the gradation value “1” is made larger when the temperature detected by the temperature detection circuit 96 is low than when the temperature is high.

Further, the amplification factor when the signal level of the input signal is less than the gradation value “1” is greater when the cumulative operation time measured by the cumulative operation time measurement circuit 98 is increased than when the cumulative operation time is small. Enlarge.

Thus, when the gradation value to be displayed is displayed on the panel 10 in a pseudo manner using a dithering process or the like, the luminance corresponding to the decrease due to the discharge failure can be compensated in advance for the gradation value to be displayed. Thus, the gradation value to be displayed can be correctly displayed on the panel 10.

In the present embodiment, the low luminance amplifier circuit 46 performs the first correction, the second correction, the third correction, and the fourth correction when the signal level of the input signal is less than the gradation value “1”. Although the configuration of amplifying the input signal using any one of the corrections has been described, in the present invention, the low luminance amplifier circuit 46 may have five or more types of amplification factors, or three or less types. It may be.

In the present embodiment, the configuration in which the amplification factor is changed based on the temperature detected by the temperature detection circuit 96 and the cumulative operation time measured by the cumulative operation time measurement circuit 98 has been described. However, the present invention is not limited to this configuration. It is not limited to. For example, the gain may be changed based on only the temperature detected by the temperature detection circuit 96, or the gain may be changed based only on the cumulative operation time measured by the cumulative operation time measurement circuit 98. It may be. Alternatively, the amplification factor may be set regardless of the temperature detected by the temperature detection circuit 96 and the cumulative operation time measured by the cumulative operation time measurement circuit 98.

In the present embodiment, the configuration using the dither processing for pseudo display of the intermediate gradation value on the panel has been described. However, the present invention is not limited to this configuration. For example, a configuration may be used in which halftone values are pseudo-displayed on a panel using a generally known error diffusion processing, or a configuration in which dither processing and error diffusion processing are used in combination. May be.

In this embodiment, an upward ramp waveform voltage that gently rises from voltage 0 (V) to voltage Vr is generated during the erasing period, and a downward slope that gently falls from voltage 0 (V) to voltage Vi. The configuration for generating the ramp waveform voltage has been described. However, when starting the ramp waveform voltage and the ramp waveform voltage, the voltage is not limited to voltage 0 (V) at all. When the rising ramp waveform voltage is generated, the voltage applied to scan electrode SC1 through scan electrode SCn may be increased steeply until immediately before discharge is generated in the discharge cell. When generating the downward ramp waveform voltage, the voltage applied to scan electrode SC1 through scan electrode SCn may be sharply reduced until immediately before discharge occurs in the discharge cells. Therefore, the rising ramp waveform voltage may be generated as a ramp waveform voltage that gradually rises toward the voltage Vr from the voltage immediately before the discharge is generated in the discharge cell. What is necessary is just to generate | occur | produce as a ramp waveform voltage which falls gradually toward the voltage Vi from the voltage just before generate | occur | producing.

In the embodiment of the present invention, an example in which one field is composed of 10 subfields has been described. However, in the present invention, the number of subfields constituting one field is limited to the above number. is not.

The drive voltage waveform shown in FIG. 3 is merely an example in the embodiment of the present invention, and the present invention is not limited to these drive voltage waveforms. Further, the circuit configurations shown in FIGS. 7, 12, 13, and 14 are merely examples in the embodiment of the present invention, and the present invention is not limited to these circuit configurations. .

Note that each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or a microcomputer that is programmed to perform the same operation. May be used.

In the present embodiment, an example in which one pixel is configured by discharge cells of three colors of R, G, and B has been described. However, in a panel in which one pixel is configured by discharge cells of four colors or more. It is possible to apply the structure shown in this embodiment mode, and the same effect can be obtained.

The specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 24 of 1024. It is just an example. The present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with the characteristics of the panel and the specifications of the plasma display device. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained. Also, the number of subfields constituting one field, the luminance weight of each subfield, etc. are not limited to the values shown in the embodiment of the present invention, and the subfield configuration is based on the image signal or the like. It may be configured to switch.

The present invention makes it possible to perform a stable write operation without performing a forced initializing operation, to suppress the black luminance, to increase the contrast of the display image, and to improve the accuracy of the gradation value displayed on the panel in a pseudo manner. Therefore, it is useful as a panel driving method and a plasma display device.

DESCRIPTION OF SYMBOLS 10 Panel 21 Front substrate 22 Scan electrode 23 Sustain electrode 24

Display electrode pair

25,33 Dielectric layer 26 Protective layer 31 Back substrate 32 Data electrode 34

Partition

35,35R, 35G, 35B Phosphor layer 40 Plasma display device 41 Image signal processing Circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 46 Low luminance amplifier circuit 47 Dither processing circuit 48

Subfield conversion circuit

50, 80 Sustain

pulse generation circuit

51, 81 Power recovery circuit 60 Inclination waveform Voltage generation circuit 61, 63 Miller integration circuit 70 Scan pulse generation circuit 85 Constant voltage generation circuit 96 Temperature detection circuit 97 Temperature sensor 98 Cumulative operation time measurement circuit 99 Timer Q55, Q56, Q59, Q69, Q71H1 to Q7 Hn, Q71L1 ~ Q71Ln, Q72, Q83, Q84, Q86, Q87, Q91H1 ~ Q91Hm, Q91L1 ~ Q91Lm switching element E71 power Q61, Q63 transistors C61, C63 capacitor R61, R63 resistor IN61, IN63 input terminal

Claims

A plasma display panel driving method for driving a plasma display panel including a plurality of discharge cells having scan electrodes, sustain electrodes, and data electrodes,
A single field is configured using a plurality of subfields having an address period, a sustain period, and an erase period,
In the address period, a scan pulse is applied to the scan electrode and an address pulse is applied to the data electrode to selectively generate an address discharge in the discharge cell. In the sustain period, a number corresponding to a luminance weight is applied. A sustain pulse is alternately applied to the scan electrode and the sustain electrode to generate a sustain discharge in the discharge cell that has generated the address discharge. In the erasing period, a ramp waveform voltage is applied to the scan electrode to An erase discharge is selectively generated only in the discharge cells that have generated an address discharge during the address period,
A voltage obtained by subtracting a voltage applied to the data electrode from a low-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period is set as a first voltage, and a high voltage of the sustain pulse applied to the scan electrode in the sustain period The voltage obtained by subtracting the voltage applied to the data electrode from the side voltage is set as the second voltage, and the low voltage side voltage of the write pulse applied to the data electrode from the low voltage side voltage of the scan pulse applied to the scan electrode in the write period When the voltage obtained by subtracting is used as the third voltage,
The voltage applied to each electrode is set so that the voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than the discharge start voltage of the discharge using the data electrode as an anode and the scan electrode as a cathode. A voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage of discharge using the data electrode as an anode and the scan electrode as a cathode, and the data electrode as a cathode and the scan electrode as an anode. Set the voltage to be applied to each electrode to be less than the sum of the discharge start voltage of the discharge,
Amplifying the input image signal at a predetermined amplification factor to display an image on the plasma display panel,
A method for driving a plasma display panel, comprising: amplifying an input image signal having a size smaller than a predetermined size with an amplification factor equal to or higher than an amplification factor for the input image signal having a predetermined size or more.
2. The method of driving a plasma display panel according to claim 1, wherein for the input image signal less than the predetermined size, the amplification factor is increased as the input image signal decreases.
2. The plasma display panel drive according to claim 1, wherein the predetermined size is a size in which only the subfield having the smallest luminance weight in one field emits light and the other subfields do not emit light. Method.
The temperature of the plasma display panel is detected and the detected temperature is compared with a preset temperature threshold value. When the temperature is lower than the temperature threshold value, the temperature is equal to or higher than the temperature threshold value. 2. The method of driving a plasma display panel according to claim 1, wherein the amplification factor for the input image signal less than the predetermined size is increased.
The cumulative operation time of the plasma display panel is measured, and the measured cumulative operation time is compared with a preset cumulative time threshold. When the cumulative operation time is equal to or greater than the cumulative time threshold, the cumulative operation time 2. The method of driving a plasma display panel according to claim 1, wherein the amplification factor for the input image signal less than the predetermined magnitude is made larger than when the value is less than the cumulative time threshold.
A plasma display panel including a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode;
In a plasma display device comprising a drive circuit for driving the plasma display panel and displaying an image on the plasma display panel,
The drive circuit is
A plurality of subfields each having an address period, a sustain period, and an erase period are used to form one field. In the address period, a scan pulse is applied to the scan electrode and an address pulse is applied to the data electrode. An address discharge is selectively generated in the discharge cell, and in the sustain period, a number of sustain pulses corresponding to a luminance weight are alternately applied to the scan electrode and the sustain electrode to the discharge cell that has generated the address discharge. A sustain discharge is generated, and in the erasing period, a ramp waveform voltage is applied to the scan electrode, and an erasing discharge is selectively generated only in a discharge cell that has generated an address discharge in the immediately preceding address period,
A voltage obtained by subtracting a voltage applied to the data electrode from a low-voltage side voltage of the sustain pulse applied to the scan electrode in the sustain period is set as a first voltage, and a high voltage of the sustain pulse applied to the scan electrode in the sustain period The voltage obtained by subtracting the voltage applied to the data electrode from the side voltage is set as the second voltage, and the low voltage side voltage of the write pulse applied to the data electrode from the low voltage side voltage of the scan pulse applied to the scan electrode in the write period When the voltage obtained by subtracting is used as the third voltage,
The voltage applied to each electrode is set so that the voltage obtained by subtracting the third voltage from the first voltage is equal to or higher than the discharge start voltage of the discharge using the data electrode as an anode and the scan electrode as a cathode. A voltage obtained by subtracting the third voltage from the second voltage is a discharge start voltage of discharge using the data electrode as an anode and the scan electrode as a cathode, and the data electrode as a cathode and the scan electrode as an anode. Set the voltage to be applied to each electrode to be less than the sum of the discharge start voltage of the discharge,
Amplifying the input image signal at a predetermined amplification factor to display an image on the plasma display panel,
A plasma display device, wherein an input image signal less than a predetermined size is amplified at an amplification factor equal to or greater than an amplification factor for an input image signal greater than the predetermined size.
The drive circuit is
The plasma display apparatus according to claim 6, wherein the amplification factor is increased as the input image signal becomes smaller with respect to the input image signal less than the predetermined size.
The drive circuit is
A temperature detection circuit for detecting the temperature of the plasma display panel;
The temperature detected by the temperature detection circuit is compared with a preset temperature threshold, and when the temperature is lower than the temperature threshold, the predetermined temperature is higher than when the temperature is equal to or higher than the temperature threshold. The plasma display device according to claim 6, wherein the amplification factor for an input image signal having a magnitude less than is increased.
The drive circuit is
A cumulative operation time measuring circuit for measuring a cumulative operation time of the plasma display panel;
The cumulative operation time measured in the cumulative operation time measuring circuit is compared with a preset cumulative time threshold value. When the cumulative operation time is equal to or greater than the cumulative time threshold value, the cumulative operation time is calculated as the cumulative time. 7. The plasma display apparatus according to claim 6, wherein the amplification factor for the input image signal less than the predetermined magnitude is made larger than when it is less than a threshold value.