JP2011033964A - Driving method for plasma display panel, and plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve image display quality by suppressing abnormal electric discharge during a write period, even in a panel having a larger screen, higher luminance and higher definition. <P>SOLUTION: The driving method for a plasma display panel drives a plasma display panel having a plurality of sub-fields in one field, for grayscale display. In three successive discharge cells arrayed in a direction where a display electrode pair extends, when the center discharge cells in all the sub-fields are turned off, and two discharge cells on both sides of the center discharge cell are turned on in predetermined sub-fields, one of the two discharge cells in the predetermined sub-field, is turned off, and the one discharge cell is turned on in a sub-field where luminance weight is the largest next to that of the predetermined sub-field. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a driving method of a plasma display panel and a plasma display device used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other. A dielectric layer and a protective layer are formed so as to cover the display electrode pairs. In the back plate, a plurality of parallel data electrodes are formed on a back glass substrate, a dielectric layer is formed so as to cover the data electrodes, and a plurality of barrier ribs are formed thereon in parallel with the data electrodes. . And the fluorescent substance layer is formed in the surface of a dielectric material layer, and the side surface of a partition. Then, the front plate and the back plate are arranged to face each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed. In the sealed internal discharge space, for example, a discharge gas containing xenon at a partial pressure ratio of 5% is sealed, and a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  A subfield method is generally used as a method for driving the panel. In the subfield method, one field is divided into a plurality of subfields, and gradation display is performed by causing each discharge cell to emit light or not emit light in each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In the initialization period, an initialization waveform is applied to each scan electrode, and an initialization discharge is generated in each discharge cell. Thus, in each discharge cell, wall charges necessary for the subsequent address operation are formed, and priming particles (excited particles for generating the address discharge) for generating the address discharge stably are generated.

  In the address period, a scan pulse is applied to the scan electrode, and an address pulse is applied to the data electrode based on an image signal to be displayed to generate an address discharge in a discharge cell to be displayed to form a wall charge (hereinafter referred to as a wall charge). This operation is also referred to as “writing”).

  In the sustain period, the number of sustain pulses determined for each subfield is alternately applied to the display electrode pairs including the scan electrodes and the sustain electrodes. Thereby, a sustain discharge is generated in the discharge cell in which the address discharge has occurred, and the phosphor layer of the discharge cell is caused to emit light. As a result, each discharge cell emits light at a luminance corresponding to the luminance weight determined for each subfield. In this way, each discharge cell of the panel is caused to emit light with a luminance corresponding to the gradation value of the image signal, thereby performing image display.

  In addition, as one of the subfield methods, gradation discharge is performed by performing initializing discharge using a slowly changing voltage waveform and selectively performing initializing discharge on discharge cells that have undergone sustain discharge. A driving method is disclosed in which light emission not related to the above is reduced as much as possible and the contrast ratio is improved.

  Specifically, among the plurality of subfields, in the initialization period of one subfield, an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed, and in an initializing period of the other subfield. Performs a selective initializing operation in which initializing discharge is generated only in the discharge cells that have undergone sustain discharge in the immediately preceding sustain period. By driving in this way, the luminance of the black display region (hereinafter abbreviated as “black luminance”) that changes due to light emission not related to image display is only weak light emission in the all-cell initialization operation, and has high contrast. Image display is possible (see, for example, Patent Document 1).

  In addition, a technique is disclosed in which an initialization waveform having a portion where the voltage rises with a gentle slope and a portion where the voltage falls with a gentle slope is applied to the discharge cell during the initialization period (for example, Patent Document 2). reference).

JP 2000-242224 A JP 2004-37883 A

  In recent years, further miniaturization of discharge cells has been progressed with higher definition of panels. In this miniaturized discharge cell, it has been confirmed that the wall charges formed in the discharge cell by the initialization discharge are likely to change due to the influence of the address discharge and sustain discharge generated in the adjacent discharge cells. .

  In addition, it has been confirmed that in the panel where the xenon partial pressure is increased in order to increase the luminance, the variation in the discharge start voltage tends to increase.

  In addition, the panel drive impedance tends to increase with an increase in the screen size and resolution. Therefore, even if the discharge cells are formed on the same display electrode pair, the voltage drop of the drive voltage is different between the discharge cells formed near the drive circuit and the discharge cells formed far from the drive circuit. The difference between them tends to widen.

  For these reasons, in large-screen, high-brightness, high-definition panels, the occurrence of discharge tends to vary, and discharge cells that are more likely to cause discharge and those that are less likely to cause discharge May be mixed.

  In such a panel, in order to stably generate a discharge, the voltage applied to the discharge cell may be increased so that the discharge is surely generated even in a discharge cell that is relatively difficult to generate a discharge.

  However, when the voltage applied to the discharge cell is high, the discharge cell is relatively easy to generate a discharge. For example, an erroneous address discharge (hereinafter also referred to as “erroneous address”) occurs in a subfield where an address discharge should not be generated. There is a possibility that erroneous discharge such as occurrence is likely to occur, and image display quality may be deteriorated.

  The present invention has been made in view of such problems, and even in a panel with a large screen, high brightness, and high definition, the occurrence of abnormal discharge in the address period is suppressed, the address operation is stabilized, and the image display is performed. An object of the present invention is to provide a panel driving method and a plasma display apparatus capable of improving quality.

  In the panel driving method of the present invention, a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode is set for each address period and address field for generating address discharge in the discharge cells. A plurality of subfields having a sustain period in which sustain pulses of the number of times corresponding to the luminance weight are alternately applied to the display electrode pairs are provided and driven in one field, and the sustain period is generated in the subfield in which the address discharge is generated in the address period A method for driving a panel that performs gradation display by generating a sustain discharge and lighting a discharge cell, and among three consecutive discharge cells arranged in a direction in which display electrode pairs extend, all of the central discharge cells are When the two discharge cells on both sides of the central discharge cell are turned on in the predetermined subfield, In addition, one of the two discharge cells is changed from lighting to non-lighting, and the one discharge cell is turned on in a subfield having a luminance weight next to a predetermined subfield. And

  As a result, even in a plasma display device using a panel with a large screen, high brightness, and high definition, in the discharge cell that suppresses the occurrence of abnormal discharge in the address period, stabilizes the address operation, and changes the lighting pattern. It is possible to reduce the luminance change and improve the image display quality.

  Also, in this panel driving method, one field is limited to all cell initialization subfields that generate initialization discharges in all discharge cells and only discharge cells that have generated sustain discharges in the sustain period of the immediately preceding subfield. A configuration having a plurality of selective initializing subfields that generate initializing discharge and a configuration in which a predetermined subfield is an all-cell initializing subfield may be adopted. Thereby, it is possible to suppress the occurrence of erroneous writing in the all-cell initialization subfield, stabilize the writing operation, and improve the image display quality.

  Further, in this panel driving method, in the current field, the above-mentioned central discharge cell is not lit in all subfields, and the above two discharge cells are both lit in a predetermined subfield, immediately before the current field. In this field, when the discharge cell in the center is turned on in any one or more subfields of one field, either one of the two discharge cells in a predetermined subfield of the current field. The discharge cell may be changed from lighting to non-lighting, and one of the discharge cells may be turned on in a subfield having a luminance weight next to a predetermined subfield. As a result, when an “erroneous address generation pattern” occurs in three consecutive discharge cells, it is determined whether or not to change the lighting pattern in accordance with the lighting pattern in the immediately preceding field. Therefore, it is possible to change the lighting pattern only, so that it is possible to reduce erroneous writing while minimizing the luminance change occurring in the discharge cells, and to further improve the image display quality. .

  The plasma display device of the present invention includes a plurality of discharge cells each having a display electrode pair including a scan electrode and a sustain electrode, and a plurality of subfields each having an address period and a sustain period are provided in one field. In the subfield in which the address discharge is generated, a panel that generates gradation display by generating the sustain discharge of the number of times corresponding to the luminance weight set for each subfield in the sustain period, and the input image signal are represented by one field. And an image signal processing circuit for converting into image data indicating light emission / non-light emission for each subfield in the discharge cell in accordance with the magnitude of the gradation value, the image signal processing circuit in a direction in which the display electrode pair extends. In the three consecutive discharge cells arranged, the central discharge cell is not lit in all subfields, and two discharges on both sides of the central discharge cell. When both of the two discharge cells are turned on in a predetermined subfield, one of the two discharge cells is changed from lighting to non-lighting in the predetermined subfield, and the one discharge cell is changed to the predetermined subfield. It is characterized in that it is turned on in a subfield having the next highest luminance weight after the field.

  As a result, even in a plasma display device using a panel with a large screen, high brightness, and high definition, in the discharge cell that suppresses the occurrence of abnormal discharge in the address period, stabilizes the address operation, and changes the lighting pattern. It is possible to reduce the luminance change and improve the image display quality.

  According to the present invention, even in a panel with a large screen, high brightness, and high definition, it is possible to suppress the occurrence of abnormal discharge in the address period, stabilize the address operation, and improve the image display quality. A driving method and a plasma display device can be provided.

It is a disassembled perspective view which shows the structure of the panel in Embodiment 1 of this invention. It is an electrode array figure of the panel. It is a drive voltage waveform figure applied to each electrode of the panel. It is a circuit block diagram of the plasma display apparatus in Embodiment 1 of the present invention. It is a figure which shows schematically the discharge cell formed in the panel in Embodiment 1 of this invention. An example of an “erroneous address generation pattern” generated in discharge cell (i, j−1), discharge cell (i, j), and discharge cell (i, j + 1) shown in FIG. 5 in the first embodiment of the present invention. It is the figure shown typically. It is a figure which shows typically the example of a change of the lighting pattern when "an erroneous address generation | occurrence | production pattern" arises in three continuous discharge cells in Embodiment 1 of this invention. It is a figure which shows typically the example of a change of the lighting pattern when an "erroneous address generation pattern" arises in the same three discharge cells. FIG. 6 is a diagram schematically illustrating an example of an “erroneous address generation pattern” generated in the discharge cell (i, j−1), the discharge cell (i, j), and the discharge cell (i, j + 1) illustrated in FIG. 5. It is a figure which shows typically another example of the "wrong address generation | occurrence | production pattern" produced in discharge cell (i, j-1), discharge cell (i, j), and discharge cell (i, j + 1). It is a figure which shows typically the example of a change of the lighting pattern when "an erroneous address generation | occurrence | production pattern" arises in three continuous discharge cells in Embodiment 2 of this invention.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 in accordance with the first exemplary embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustain electrode 23 are formed on a glass front plate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25. The protective layer 26 is made of a material mainly composed of magnesium oxide (MgO).

  A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween. And the outer peripheral part is sealed with sealing materials, such as glass frit. A mixed gas of neon and xenon is sealed as a discharge gas in the internal discharge space. In the present embodiment, a discharge gas having a xenon partial pressure of about 10% is used in order to improve luminous efficiency. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, a structure having a stripe-shaped partition may be used. Further, the mixing ratio of the discharge gas is not limited to the above-described numerical values, and may be other mixing ratios.

  FIG. 2 is an electrode array diagram of panel 10 in accordance with the first exemplary embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) that are long in the row direction. M data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dk (k = 1 to m), and the discharge cell is in the discharge space. M × n are formed. A region where m × n discharge cells are formed becomes a display region of the panel 10.

  Next, a driving voltage waveform for driving the panel 10 and an outline of the operation will be described. In the plasma display device according to the present embodiment, one field is divided into a plurality of subfields on the time axis, luminance weights are set for each subfield, and light emission / non-light emission of each discharge cell is performed for each subfield. It is assumed that gradation display is performed by a subfield method for controlling the above.

  In this subfield method, for example, one field is composed of eight subfields (first SF, second SF,..., Eighth SF), and each weight is increased so that the luminance weight increases in the later subfield. Each subfield may have a luminance weight of (1, 2, 4, 8, 16, 32, 64, 128). In addition, in the initializing period of one subfield among a plurality of subfields, an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed (hereinafter, the subfield for performing the all-cell initializing operation is referred to as a subfield for performing all-cell initializing operations). In the initializing period of other subfields, a selective initializing operation for selectively generating initializing discharge is performed for the discharge cells that have undergone sustain discharge (hereinafter referred to as “all-cell initializing subfield”). The subfield that performs the selective initialization operation is referred to as “selective initialization subfield”), and it is possible to reduce light emission not related to gradation display as much as possible and improve the contrast ratio.

  In the present embodiment, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the eighth SF. Thereby, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initializing operation in the first SF. Therefore, the black luminance, which is the luminance of the black display region where no sustain discharge is generated, is only weak light emission in the all-cell initializing operation, and an image display with high contrast is possible. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each display electrode pair 24.

  However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  FIG. 3 is a drive voltage waveform diagram applied to each electrode of panel 10 in accordance with the first exemplary embodiment of the present invention. FIG. 3 shows scan electrode SC1 that scans first in the address period, scan electrode SCn that scans last in the address period (for example, scan electrode SC1080), sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data. The drive waveform of the electrode Dm is shown.

  FIG. 3 also shows driving voltage waveforms of two subfields, that is, a first subfield (first SF) that is an all-cell initializing subfield and a second subfield (second SF) that is a selective initializing subfield. It shows. The drive voltage waveform in the other subfields is substantially the same as the drive voltage waveform of the second SF except that the number of sustain pulses generated in the sustain period is different. Scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected based on image data (data indicating light emission / non-light emission for each subfield) from among the electrodes.

  First, the first SF, which is an all-cell initialization subfield, will be described.

  In the first half of the initializing period of the first SF, 0 (V) is applied to data electrode D1 to data electrode Dm, sustain electrode SU1 to sustain electrode SUn, and voltage Vi1 is applied to scan electrode SC1 to scan electrode SCn. To do. At this time, voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn. Further, a ramp voltage (hereinafter referred to as “up-ramp voltage”) L1 that gently rises from the voltage Vi1 toward the voltage Vi2 (for example, with a slope of about 1.3 V / μsec) is applied. At this time, voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn.

  While the rising ramp voltage L1 rises, between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm. Each weak initializing discharge occurs continuously. Negative wall voltage is accumulated above scan electrode SC1 through scan electrode SCn, and positive wall voltage is accumulated above data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn. The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, 0 (V) is applied to data electrode D1 through data electrode Dm, and scan electrode SC1 through scan electrode SCn. Sustain electrode SU1 to sustain electrode SUn gradually decrease from voltage Vi3 that is less than the discharge start voltage toward negative voltage Vi4 that exceeds the discharge start voltage (for example, with a gradient of about −2.5 V / μsec). A ramp voltage (hereinafter referred to as “down-ramp voltage”) L2 is applied.

  During this time, weak initialization discharges occur between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm, respectively. . Then, the negative wall voltage above scan electrode SC1 through scan electrode SCn and the positive wall voltage above sustain electrode SU1 through sustain electrode SUn are weakened, and the positive wall voltage above data electrode D1 through data electrode Dm is used for the write operation. It is adjusted to a suitable value. Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  In the subsequent address period, scan pulse voltage Va is sequentially applied to scan electrode SC1 through scan electrode SCn, and data electrode Dk (k = k = corresponding to the discharge cell to emit light to data electrode D1 through data electrode Dm). 1 to m) is applied with a positive address pulse voltage Vd to selectively generate an address discharge in each discharge cell.

  Specifically, voltage Ve2 is first applied to sustain electrode SU1 through sustain electrode SUn, and voltage Vc (voltage Vc = voltage Va + voltage Vsc) is applied to scan electrode SC1 through scan electrode SCn.

  The negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm. A positive write pulse voltage Vd is applied to. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the externally applied voltage (voltage Vd−voltage Va) between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1. The difference is added and exceeds the discharge start voltage. As a result, a discharge is generated between data electrode Dk and scan electrode SC1. Further, since voltage Ve2 is applied to sustain electrode SU1 through sustain electrode SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is maintained at a difference between externally applied voltages (voltage Ve2−voltage Va). The difference between the wall voltage on the electrode SU1 and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve2 to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do. Thereby, the discharge generated between data electrode Dk and scan electrode SC1 can be triggered to generate a discharge between sustain electrode SU1 and scan electrode SC1 in the region intersecting with data electrode Dk. Thus, an address discharge occurs in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Accumulated.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of data electrode D1 to data electrode Dm to which scan pulse SC1 is not applied with address pulse voltage Vd does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, sustain pulses of the number obtained by multiplying the luminance weight by a predetermined luminance magnification are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission.

  In this sustain period, first, positive sustain pulse voltage Vs is applied to scan electrode SC1 through scan electrode SCn, and a ground potential serving as a base potential, that is, 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeds the discharge start voltage.

  Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as the base potential is applied to scan electrode SC1 through scan electrode SCn, and sustain pulse voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between sustain electrode SUi and scan electrode SCi exceeds the discharge start voltage, so that a sustain discharge occurs again between sustain electrode SUi and scan electrode SCi, and the sustain cell is maintained. Negative wall voltage is accumulated on electrode SUi, and positive wall voltage is accumulated on scan electrode SCi. Similarly, the address discharge was caused in the address period by alternately applying the number of sustain pulses obtained by multiplying the brightness weight to the brightness magnification to scan electrode SC1 to scan electrode SCn and sustain electrode SU1 to sustain electrode SUn. Sustain discharge is continuously generated in the discharge cell.

  Then, after the sustain pulse is generated in the sustain period, 0 (V) is applied to scan electrode SC1 to scan electrode SCn while 0 (V) is applied to sustain electrode SU1 to sustain electrode SUn and data electrode D1 to data electrode Dm. Is applied with a ramp voltage (hereinafter referred to as “erasing ramp voltage”) L3 that gradually increases (for example, about 10 V / μsec) toward the voltage Vers exceeding the discharge start voltage. Thereby, a weak discharge is generated between sustain electrode SUi and scan electrode SCi of the discharge cell in which the sustain discharge has occurred. This weak discharge is continuously generated while the voltage applied to scan electrode SC1 through scan electrode SCn increases. When the increasing voltage reaches the predetermined voltage Vers, the voltage applied to scan electrode SC1 through scan electrode SCn is decreased to 0 (V) as the base potential.

  At this time, the charged particles generated by this weak discharge are accumulated on sustain electrode SUi and scan electrode SCi so as to alleviate the voltage difference between sustain electrode SUi and scan electrode SCi. Therefore, in the discharge cell in which the sustain discharge has occurred, the wall voltage between scan electrode SC1 on scan electrode SCn and sustain electrode SU1 on sustain electrode SUn is the difference between the voltage applied to scan electrode SCi and the discharge start voltage, That is, it is weakened to the level of (voltage Vers−discharge start voltage). As a result, in the discharge cell in which the sustain discharge has occurred, part or all of the wall voltage on scan electrode SCi and sustain electrode SUi is erased while leaving the positive wall charge on data electrode Dk. That is, the discharge generated by the erasing ramp voltage L3 serves as an “erasing discharge” for erasing unnecessary wall charges accumulated in the discharge cell in which the sustain discharge has occurred (hereinafter, the discharge generated by the erasing ramp voltage L3 is “ This is called “erase discharge”).

  Thereafter, scan electrode SC1 to scan electrode SCn are returned to 0 (V), and the sustain operation in the sustain period is completed.

  In the initialization period of the second SF, a drive voltage waveform in which the first half of the initialization period of the first SF is omitted is applied to each electrode. That is, voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, and 0 (V) is applied to data electrode D1 through data electrode Dm. Scan electrode SC1 to scan electrode SCn have a voltage that is less than the discharge start voltage (for example, The down-ramp voltage L4 that gradually decreases (for example, with a gradient of about −2.5 V / μsec) from 0 (V) toward the negative voltage Vi4 that exceeds the discharge start voltage is applied.

  As a result, a weak initializing discharge is generated in the discharge cell that has caused the sustain discharge in the sustain period of the immediately preceding subfield (first SF in FIG. 3), and the wall voltage on the scan electrode SCi and the sustain electrode SUi is weakened. The wall voltage above the data electrode Dk (k = 1 to m) is also adjusted to a value suitable for the write operation. On the other hand, initializing discharge does not occur in the discharge cells that did not cause sustain discharge in the sustain period of the immediately preceding subfield. As described above, the initializing operation in the second SF is a selective initializing operation in which the initializing discharge is performed on the discharge cells in which the sustain operation has been performed in the sustain period of the immediately preceding subfield.

  In the address period of the second SF, the same drive waveform as that in the address period of the first SF is applied to scan electrode SC1 through scan electrode SCn, sustain electrode SU1 through sustain electrode SUn, and data electrode D1 through data electrode Dm. In the sustain period of the second SF, similarly to the sustain period of the first SF, a predetermined number of sustain pulses are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn.

  In the subfields after the third SF, scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm are different from each other except that the number of sustain pulses generated in the sustain period is different. A drive waveform similar to 2SF is applied.

  The above is the outline of the driving voltage waveform applied to each electrode of the panel 10.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 4 is a circuit block diagram of plasma display device 1 according to the first exemplary embodiment of the present invention. The plasma display apparatus 1 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 41 assigns gradation values expressed in one field to each discharge cell based on the inputted image signal sig, and the gradation value assigned to each discharge cell is emitted / non-emission for each subfield. Is converted into image data indicating. Further, in the three consecutive discharge cells arranged in the direction in which the display electrode pair 24 extends, it is determined whether the lighting pattern of each subfield applies to an “erroneous writing occurrence pattern” described later, and the determination result Change part of the lighting pattern. Details of this will be described later.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and each circuit block (image signal processing circuit 41, data electrode drive circuit 42, Scan electrode drive circuit 43 and sustain electrode drive circuit 44).

  The data electrode drive circuit 42 converts the data for each subfield constituting the image data into signals corresponding to the data electrodes D1 to Dm, and each data electrode based on the timing signal supplied from the timing generation circuit 45. D1 to the data electrode Dm are driven.

  Scan electrode driving circuit 43 generates an initialization waveform generating circuit for generating an initialization waveform to be applied to scan electrode SC1 to scan electrode SCn in the initialization period, and generates a sustain pulse to be applied to scan electrode SC1 to scan electrode SCn in the sustain period. And a scan pulse generating circuit that includes a plurality of scan electrode driving ICs (hereinafter abbreviated as “scan ICs”) and generates scan pulses to be applied to scan electrode SC1 through scan electrode SCn in the address period. Then, each of the scan electrodes SC1 to SCn is driven based on the timing signal supplied from the timing generation circuit 45.

  Sustain electrode drive circuit 44 includes a sustain pulse generation circuit and a circuit (not shown) that generates voltage Ve1 and voltage Ve2. Sustain electrode drive circuit 44 uses sustain signal SU1 through sustain electrode SUn based on a timing signal supplied from timing generation circuit 45. To drive.

  In the present embodiment, as described above, in each of the three consecutive discharge cells arranged in the extending direction of the display electrode pair 24 (hereinafter simply referred to as “three consecutive discharge cells”), It is determined whether the lighting pattern of the field is applicable to the “erroneous writing occurrence pattern”, and a part of the lighting pattern is changed based on the determination result.

  Specifically, among the three consecutive discharge cells, all the subfields of the central discharge cell are not lit, and two discharge cells on both sides of the central discharge cell (hereinafter simply referred to as “two discharges on both sides”). Cell ”) determines whether or not both of the predetermined subfields (in this embodiment, the first SF which is the all-cell initialization subfield) are turned on. In the present embodiment, this lighting pattern is referred to as an “erroneous writing occurrence pattern”.

  When the lighting pattern of each subfield in the three consecutive discharge cells applies to the “erroneous address generation pattern”, in a predetermined subfield (first SF which is an all-cell initializing subfield in the present embodiment), One of the two discharge cells on both sides is changed from lighting to non-lighting.

  This is because the inventor tends to cause erroneous writing in the center discharge cell in a predetermined subfield when the above-mentioned “erroneous writing occurrence pattern” occurs, and the error is corrected by taking the above-mentioned countermeasure at that time. This is because it has been experimentally confirmed that the occurrence of writing is reduced.

  This “erroneous writing occurrence pattern” will be described with reference to the drawings. FIG. 5 schematically shows discharge cells formed in panel 10 according to Embodiment 1 of the present invention. FIG. 6 schematically shows an example of the “erroneous address occurrence pattern” generated in the discharge cell (i, j−1), the discharge cell (i, j), and the discharge cell (i, j + 1) shown in FIG. It is the figure shown in.

  FIG. 5 shows a total of 15 discharge cells of 3 rows from the (i−1) th row to the (i + 1) th row and 5 columns from the (j−2) th column to the (j + 2) th column. In the following description, for example, a discharge cell in i row and j column is referred to as a discharge cell (i, j). In FIG. 6, “◯” indicates that the subfield is lit, and “x” indicates that the subfield is not lit.

  In the following description, the discharge cell (i, j−1), the discharge cell (i, j), and the discharge cell (i, j + 1) shown in FIG. In this example, the central discharge cell is the discharge cell (i, j), and the two discharge cells on both sides are the discharge cell (i, j-1) and the discharge cell (i, j + 1).

  In the example shown in FIG. 6, all the subfields of the discharge cell (i, j) are not lit, and the discharge cell (i, j−1) and the discharge cell (i, j + 1)) are in a predetermined subfield. A certain first SF is turned on. For example, in such a lighting pattern, in the discharge cell (i, j), erroneous writing is likely to occur in the first SF that is a predetermined subfield.

  This is probably due to the following reasons.

  In a discharge cell that is miniaturized as the panel becomes higher in definition, the wall charges formed in the discharge cell by the initialization discharge are easily changed by the influence of the address discharge and the sustain discharge generated in the adjacent discharge cells. .

  In addition, in a panel in which the xenon partial pressure is increased in order to increase the brightness, variation in the discharge start voltage tends to increase.

  In addition, the panel drive impedance tends to increase with an increase in the screen size and resolution. Therefore, even if the discharge cells are formed on the same display electrode pair, the voltage drop of the drive voltage is different between the discharge cells formed near the drive circuit and the discharge cells formed far from the drive circuit. The difference between is widened.

  For these reasons, in a panel with a large screen, high brightness, and high definition, the occurrence of discharge is likely to vary, and discharge cells that are more likely to cause discharge and those that are less likely to cause discharge, In other words, when the same drive voltage is applied, there may be a discharge cell in which discharge occurs earlier in time and a discharge cell in which discharge occurs later.

  In such a panel, in order to stably generate discharge in all the discharge cells, the voltage applied to the discharge cells may be increased. For example, in order to generate a stable address discharge in a discharge cell in which discharge is relatively difficult to occur, the negative scan pulse voltage Va applied to the scan electrode 22 is decreased during the address period to increase the amplitude of the scan pulse. That's fine. Alternatively, in order to perform a sufficient initialization operation in a discharge cell that is relatively difficult to generate a discharge, for example, the maximum voltage Vi2 of the up-ramp voltage L1 is increased so that the duration of the initialization discharge is sufficient. Good.

  However, in a discharge cell that is relatively easy to generate a discharge, an initializing discharge is generated earlier in time than a discharge cell that is relatively difficult to generate a discharge. For this reason, in a discharge cell in which discharge is relatively likely to occur, for example, if the maximum voltage Vi2 of the up-ramp voltage L1 is increased, the duration of the initialization discharge becomes longer because the initialization discharge is generated earlier in time. It will be initialized to.

  In an excessively initialized discharge cell, negative wall charges may accumulate excessively on the scan electrode 22. Such a discharge cell is in a state in which a discharge is relatively easily generated, and when an address operation is performed in the discharge cell, an address discharge is generated relatively strongly.

  Further, in the three consecutive discharge cells, the address operation is not performed in the central discharge cell (that is, the address pulse is not applied), and the address operation is performed in the two discharge cells on both sides as described above. When a relatively strong address discharge occurs in the two discharge cells on both sides for some reason, some of the priming particles generated by the address discharge may leak from the two discharge cells on both sides into the center discharge cell. . This phenomenon is hereinafter referred to as “crosstalk”. In addition, the movement of the priming particles due to the crosstalk is likely to occur in the discharge cell that has been miniaturized as the panel becomes higher in definition.

  At this time, if negative wall charges are excessively accumulated on the scan electrode 22 of the central discharge cell, the discharge voltage may exceed the discharge start voltage only by applying the scan pulse in the central discharge cell. In such a case, priming particles that leak into the center discharge cell from the two discharge cells on both sides due to crosstalk can be a trigger, and a discharge can be generated without applying an address pulse to the center discharge cell. is there. In this way, it is considered that erroneous writing occurs in the central discharge cell when an “erroneous writing occurrence pattern” occurs in three consecutive discharge cells.

  On the other hand, when the “wrong address occurrence pattern” occurs in three consecutive discharge cells, the present inventor turns one of the two discharge cells at both ends from lighting to non-lighting in a predetermined subfield. It was experimentally confirmed that the occurrence of erroneous writing was reduced by changing to.

  7A and 7B are diagrams schematically showing an example of changing the lighting pattern when an “erroneous write occurrence pattern” occurs in three consecutive discharge cells in the first embodiment of the present invention. FIG. 7A is a diagram showing an example of changing the lighting pattern of the discharge cell (i, j + 1) when the “erroneous address occurrence pattern” shown in FIG. 6 occurs, and FIG. It is the figure which showed the example at the time of changing the lighting pattern of discharge cell (i, j-1) when the shown "erroneous address occurrence pattern" arises.

  For example, when the “erroneous write occurrence pattern” shown in FIG. 6 occurs, as shown in FIG. 7A, the discharge cell (i, j + 1) is changed from lighting to non-lighting in the first SF which is a predetermined subfield. . Alternatively, as shown in FIG. 7B, in the first SF that is a predetermined subfield, the discharge cell (i, j-1) may be changed from lighting to non-lighting.

  Thus, when an “erroneous address occurrence pattern” occurs in three consecutive discharge cells, two discharge cells (examples shown in FIG. 6) on both sides in a predetermined subfield (first SF in the present embodiment). Then, one of the discharge cells (i, j−1) and discharge cells (i, j + 1)) is changed from lighting to non-lighting. In this way, in a predetermined subfield (first SF in the present embodiment), priming particles that leak into the central discharge cell (discharge cell (i, j in the example shown in FIG. 6)) are halved. Thus, erroneous writing in the central discharge cell can be reduced.

  Furthermore, in this embodiment, when an “erroneous address generation pattern” occurs in three consecutive discharge cells, one of the two discharge cells on both sides is turned on from non-lighting in a predetermined subfield. In addition, the discharge cell is turned on in a subfield (second SF in the present embodiment) having the next highest luminance weight after a predetermined subfield.

  For example, in the example shown in FIG. 7A, the discharge cell (i, j + 1) is changed from lighting to non-lighting in the first SF which is a predetermined subfield, and the first SF (in this embodiment, the luminance weight is “1”). Next, the same discharge cell (i, j + 1) is turned on in the subfield having the second largest luminance weight (in the present embodiment, the second SF having the luminance weight “2”). Alternatively, in the example illustrated in FIG. 7B, the discharge cell (i, j−1) is changed from lighting to non-lighting in the first SF which is a predetermined subfield, and the first SF (in this embodiment, the luminance weight “1 ”), The discharge cell (i, j−1) is turned on in the subfield having the next highest luminance weight (in the present embodiment, the second SF having the luminance weight“ 2 ”).

  Thereby, the luminance change in the discharge cell (the discharge cell (i, j + 1) in the example shown in FIG. 7A, the discharge cell (i, j−1) in the example shown in FIG. 7B) that changes the lighting pattern is reduced. The image display quality can be further improved.

  In addition, when the luminance weight is not set so that the luminance weight becomes larger in the later subfield, for example, one field is eight subfields (first SF, second SF,..., Eighth SF). In the configuration in which luminance weights of (1, 4, 16, 64, 2, 8, 32, 128) are set in each subfield, if the predetermined subfield is the first SF, the luminance is next to the first SF. The subfield having a large weight is the fifth SF having the luminance weight “2”. In this case, the first SF may be turned off and the fifth SF may be turned on.

  In the present embodiment, when lighting / non-lighting is assigned to each subfield of each discharge cell based on the image signal, three consecutive discharge cells arranged in the extending direction of the display electrode pair 24 are provided. It is assumed that the image signal processing circuit 41 determines whether the lighting pattern of each subfield is applicable to the “erroneous writing occurrence pattern”. That is, all the subfields are not lit in the central discharge cell, and the two discharge cells on both sides are both lit in a predetermined subfield (in this embodiment, the first SF which is the all-cell initializing subfield). It is assumed that the image signal processing circuit 41 determines whether or not. When an “erroneous writing occurrence pattern” occurs, in a predetermined subfield (first SF in the present embodiment), one of the two discharge cells on both sides is switched from lighting to non-lighting. In the image signal processing circuit 41, the discharge cell is turned on in a subfield (second SF in the present embodiment) having the next highest luminance weight after a predetermined subfield.

  As described above, in this embodiment, when an “erroneous address occurrence pattern” occurs in three consecutive discharge cells, one of the two discharge cells on both sides is turned on in a predetermined subfield. Shall be changed from non-lighting. At the same time, the discharge cell is turned on in a subfield having a luminance weight next to a predetermined subfield. As a result, when an "erroneous address generation pattern" occurs in three consecutive discharge cells, the discharge cell that reduces the erroneous address that easily occurs in the center discharge cell in a predetermined subfield and changes the lighting pattern It is possible to improve the image display quality by reducing the change in luminance at.

  Note that the gradation value of the center discharge cell is a gradation value that is lit in a subfield having a luminance weight larger than that of a predetermined subfield. In this embodiment, the gradation value is lit in any one of the second SF to the eighth SF. If the gradation value is such that even if erroneous writing occurs in a predetermined discharge field in the center discharge cell, it is difficult to perceive that erroneous writing has occurred. Therefore, in the present embodiment, the lighting pattern in which the central discharge cell is not lit in all subfields and the two discharge cells on both sides are lit in a predetermined subfield is referred to as an “erroneous address generation pattern”.

  Note that the wall charges formed in the all-cell initialization subfield are gradually lost over time. Therefore, even if the center discharge cell is not lit in all subfields and the two discharge cells on both sides are lit in any subfield after the all cell initialization subfield, Depending on the specifications of the plasma display device, erroneous writing may not easily occur in the central discharge cell in the subfield. Therefore, the predetermined subfield may be limited to the all-cell initializing subfield.

  In the present embodiment, the configuration in which the first SF is the all-cell initialization subfield and the first SF is the predetermined subfield has been described. However, the present invention is not limited to this configuration. For example, if the all-cell initialization subfield is the second SF, the predetermined subfield may be the second SF.

  Alternatively, depending on the characteristics of the panel and the specifications of the plasma display device (such as the waveform shape of the drive voltage waveform), negative wall charges may be excessively accumulated in the discharge cells even in subfields other than the all-cell initialization subfield. Writing may occur. In such a case, it is desirable that the predetermined subfield is not limited to the all-cell initializing subfield, and is optimally set according to the panel characteristics, the specifications of the plasma display device, and the like.

(Embodiment 2)
In the first embodiment, when an “erroneous address generation pattern” occurs in three consecutive discharge cells, one of the two discharge cells on both sides is changed from lighting to non-lighting in a predetermined subfield. Thus, the configuration for reducing erroneous writing in the central discharge cell has been described. However, depending on the characteristics of the panel, the specifications of the plasma display device, etc., even if an “erroneous writing occurrence pattern” occurs in three consecutive discharge cells, the erroneous writing may be relatively difficult to occur in the central discharge cell. .

  For example, if the central discharge cell is not lit in all subfields in the field immediately before the current field, even if an “erroneous address generation pattern” occurs in three consecutive discharge cells in the current field, It was confirmed that erroneous writing is relatively unlikely to occur in the central discharge cell in a predetermined subfield.

  FIG. 8 schematically shows an example of an “erroneous address generation pattern” generated in the discharge cell (i, j−1), the discharge cell (i, j), and the discharge cell (i, j + 1) shown in FIG. FIG. FIG. 8 shows the discharge cells (i, j-1), discharge cells (i, j), discharge cells (i, j) of two fields that are continuous in time, that is, (N-1) field and N field. FIG. 6 schematically shows lighting / non-lighting of each subfield in j + 1). In FIG. 8, “◯” indicates that the subfield is lit, “×” indicates that the subfield is not lit, and “−” indicates that the subfield is lit or not lit. It represents that. “N” represents a natural number.

  For example, in the example shown in FIG. 8, in the N field that is the current field, an “erroneous write occurrence pattern” occurs in the first SF that is the predetermined subfield. However, in the (N-1) field which is the field immediately before the current field, the discharge cell (i, j) which is the center discharge cell is not lit in all the subfields. In such a lighting pattern, erroneous writing is relatively unlikely to occur in the discharge cell (i, j) in the first SF of the N field.

  Conversely, if the center discharge cell is lit in any one or more subfields in the field immediately preceding the current field, when an “erroneous write occurrence pattern” occurs in three consecutive discharge cells in the current field, In the predetermined subfield of the field, erroneous writing is likely to occur in the central discharge cell.

  FIG. 9 is a diagram schematically showing another example of the “erroneous address generation pattern” generated in the discharge cell (i, j−1), the discharge cell (i, j), and the discharge cell (i, j + 1). . In FIG. 9, similarly to FIG. 8, the discharge cells (i, j−1) and (i, j) of two fields that are continuous in time, that is, (N−1) field and N field, are shown. FIG. 3 schematically shows lighting / non-lighting of each subfield in the discharge cell (i, j + 1).

  For example, in the example shown in FIG. 9, in the N field that is the current field, an “erroneous write occurrence pattern” occurs in the first SF that is the predetermined subfield. In the (N-1) field, which is the field immediately before the current field, the discharge cell (i, j), which is the central discharge cell, is lit in any one or more subfields. In such a lighting pattern, erroneous writing is relatively likely to occur in the discharge cell (i, j) in the first SF of the N field.

  Although not shown in FIG. 9, for example, even if the central discharge cell is not lit in all the subfields in the field immediately before the current field, the center in any one or more subfields in that field. When an erroneous address occurs in the current discharge cell, when an “erroneous address generation pattern” occurs in three consecutive discharge cells in the current field, an erroneous address occurs in the center discharge cell in a predetermined subfield of the current field. It was also confirmed that it was easy.

  This is probably due to the following reasons.

  When the central discharge cell is lit in any one or more subfields in the field immediately before the current field, priming particles generated by the lighting remain in the central discharge cell. The residual priming particles react with the priming particles that leak into the central discharge cell due to the occurrence of an “erroneous write occurrence pattern” in the current field, so that the central discharge cell in a predetermined subfield of the current field. It is considered that erroneous writing occurs in

  On the other hand, in the field immediately before the current field, if the central discharge cell is not lit in all the subfields and no erroneous writing occurs, the possibility that the above-mentioned residual priming particles are generated in the current field is low. Therefore, even if an “erroneous write occurrence pattern” occurs in the current field, there is almost no residual priming particle that reacts with the priming particles leaking into the central discharge cell. Writing is considered to be relatively difficult to occur.

  Therefore, in the present embodiment, in the field immediately before the current field, the central discharge cell is turned on in any one or more subfields of one field, and “incorrect write occurrence” occurs in the current field. When the “pattern” occurs, in one predetermined subfield of the current field, one of the two discharge cells on both sides is changed from lighting to non-lighting, and the discharge cell is changed to the next subfield. It is assumed that the sub-field with a large luminance weight is turned on.

  Even if an “erroneous writing occurrence pattern” occurs in the current field, the center discharge cell is not lit in all the subfields immediately preceding the current field, and there is no risk of erroneous writing occurring. The lighting pattern is not changed in the current field.

  FIG. 10 is a diagram schematically showing an example of changing the lighting pattern when an “erroneous address generation pattern” occurs in three consecutive discharge cells in the second embodiment of the present invention. FIG. 10 shows discharge cells (i, j), discharge cells (i, j-1) in three fields that are continuous in time, ie, (N-1) field, N field, and (N + 1) field, The lighting / non-lighting of each subfield in the discharge cell (i, j + 1) is schematically shown.

  For example, in the example shown in FIG. 10, in the N field that is the current field, an “erroneous write occurrence pattern” occurs in the first SF that is the predetermined subfield. In the (N-1) field, which is the field immediately before the current field, the discharge cell (i, j), which is the central discharge cell, is lit in any one or more subfields. In such a lighting pattern, in the first SF which is a predetermined subfield of the N field, one of the two discharge cells on both sides (discharge cell (i, j + 1) in the example shown in FIG. 10). Change from ON to OFF. This prevents erroneous writing of the first SF in the discharge cell (i, j). At the same time, in order to reduce the luminance change in the discharge cell (i, j + 1), the discharge cell (i, j + 1) is connected to the subfield (in the present embodiment, the second SF) having the next highest luminance weight. ) To light up.

  Further, in the example shown in FIG. 10, in the (N + 1) field following the current field, an “erroneous write occurrence pattern” occurs in the first SF that is a predetermined subfield. However, in the N field which is the current field, the discharge cell (i, j) which is the central discharge cell is not lit in all the subfields. Further, the lighting pattern of the discharge cell (i, j + 1) is changed in order to prevent erroneous writing in the discharge cell (i, j). For this reason, the lighting pattern is not changed in the (N + 1) field.

  As described above, in the present embodiment, in the field immediately before the current field, the central discharge cell is turned on in any one or more subfields of one field, and “wrong writing” is performed in the current field. When the `` occurrence pattern '' occurs, in the predetermined subfield of the current field, one of the two discharge cells on both sides is changed from lighting to non-lighting, and the discharge cell is changed to the predetermined subfield. Next, it is assumed that the subfield with the largest luminance weight is turned on.

  Even if an “erroneous writing occurrence pattern” occurs in the current field, the center discharge cell is not lit in all the subfields immediately preceding the current field, and there is no risk of erroneous writing occurring. The lighting pattern is not changed in the current field.

  As a result, when an “erroneous address generation pattern” occurs in three consecutive discharge cells, it is determined whether or not to change the lighting pattern in accordance with the lighting pattern in the immediately preceding field. Therefore, it is possible to change the lighting pattern only, so that it is possible to reduce erroneous writing while minimizing the luminance change occurring in the discharge cells, and to further improve the image display quality. .

  The drive voltage waveform shown in FIG. 3 is merely an example in the embodiment, and the present invention is not limited to these drive voltage waveforms.

  In the embodiment of the present invention, scan electrode SC1 to scan electrode SCn are divided into a first scan electrode group and a second scan electrode group, and an address period is a scan electrode belonging to the first scan electrode group. Of a panel by so-called two-phase driving, which includes a first address period in which a scan pulse is applied to each of the first and second address periods in which a scan pulse is applied to each of the scan electrodes belonging to the second scan electrode group. The present invention can also be applied to a driving method, and the same effect as described above can be obtained.

  In the embodiment of the present invention, the electrode structure in which the scan electrode and the scan electrode are adjacent to each other and the sustain electrode and the sustain electrode are adjacent to each other, that is, the arrangement of the electrodes provided on the front plate 21 is “. It is also effective in a panel having an electrode structure of “electrode, scan electrode, sustain electrode, sustain electrode, scan electrode, scan electrode,.

  In the present invention, the subfield configuration (number of subfields, luminance weight of each subfield, etc.) is not limited to the configuration shown in the embodiment. Moreover, the structure which changes a subfield structure based on an image signal etc. may be sufficient. Further, specific numerical values shown in the embodiment of the present invention, for example, gradients of the ramp voltages of the up-ramp voltage L1, the down-ramp voltage L2, and the erasing ramp voltage L3, are 50 inches of the display electrode pair 1080. It is set based on the characteristics of the panel and is merely an example of the embodiment. The present invention is not limited to these numerical values, and is desirably set optimally according to the characteristics of the panel, the specifications of the plasma display device, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.

  Even in a panel with a large screen, high brightness, and high definition, the present invention can suppress the occurrence of abnormal discharge in the address period, stabilize the address operation, and improve the image display quality. It is useful as a driving method and a plasma display device.

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 10 Panel 21 Front plate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 data electrode drive circuit 43 scan electrode drive circuit 44 sustain electrode drive circuit 45 timing generation circuit

Claims (4)

A plasma display panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, the number of times corresponding to an address period for generating an address discharge in the discharge cells and a luminance weight set for each subfield A plurality of subfields each having a sustain period in which sustain pulses are alternately applied to the display electrode pairs are driven in one field;
A driving method of a plasma display panel for performing gradation display by generating a sustain discharge in the sustain period and lighting the discharge cell in a subfield in which an address discharge is generated in the address period,
In three consecutive discharge cells arranged in the direction in which the display electrode pair extends,
When the center discharge cell is unlit in all subfields, and the two discharge cells on both sides of the center discharge cell are both lit in a predetermined subfield,
In the predetermined subfield, one of the two discharge cells is changed from lighting to non-lighting, and the one discharge cell is changed to a subfield having the next highest luminance weight after the predetermined subfield. A method for driving a plasma display panel, characterized in that the plasma display panel is turned on. A plurality of selected initials that generate an initializing discharge only in a discharge cell that has generated a sustaining discharge in the sustain period of the immediately preceding subfield and an all-cell initializing subfield that generates initializing discharge in all discharge cells. And having a subfield
The method of claim 1, wherein the predetermined subfield is the all-cell initializing subfield. In the current field, the central discharge cell is not lit in all subfields, the two discharge cells are both lit in a predetermined subfield,
In the field immediately before the current field, when the central discharge cell is lit in any one or more subfields of one field,
In the predetermined subfield of the current field, one of the two discharge cells is changed from lighting to non-lighting, and the one of the discharge cells has a luminance weight next to the predetermined subfield. 2. The method of driving a plasma display panel according to claim 1, wherein lighting is performed in a large subfield. In a subfield having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, and having a plurality of subfields having an address period and a sustain period in one field, and generating an address discharge in the address period, A plasma display panel that generates gradation display by generating a number of sustain discharges according to the luminance weight set for each subfield in the sustain period;
An image signal processing circuit that converts an input image signal into image data indicating light emission / non-light emission for each of the subfields in the discharge cell according to the magnitude of a gradation value expressed in one field,
The image signal processing circuit includes:
In three consecutive discharge cells arranged in the direction in which the display electrode pair extends,
When the center discharge cell is not lit in all subfields, and the two discharge cells on both sides of the center discharge cell are both lit in a predetermined subfield,
In the predetermined subfield, one of the two discharge cells is changed from lighting to non-lighting, and the one discharge cell is changed to a subfield having the next highest luminance weight after the predetermined subfield. A plasma display device characterized by being lit.

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