JP4997932B2 - Plasma display panel driving method and plasma display device - Google Patents

Description

  The present invention relates to a driving method of a plasma display panel and a plasma display device used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other.

  In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed on the front substrate in parallel with each other, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. . The back plate has a plurality of parallel data electrodes on the back substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs formed in parallel to the data electrodes on each of the dielectric layers. A phosphor layer is formed on the side surface of the partition wall.

  Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon is enclosed in the internal discharge space. Has been. Here, a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other. In the panel having such a structure, ultraviolet light is generated by gas discharge in each discharge cell, and phosphors of red, green, and blue colors are excited and emitted by this ultraviolet light to perform color display.

  As a method for driving the panel, a subfield method, that is, a method in which one field period is composed of a plurality of subfields and gray scale display is performed by a combination of subfields that turn on discharge cells.

  Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address operation are formed on each electrode. In the address period, a scan pulse is applied to the scan electrode as an address voltage and an address pulse is selectively applied to the data electrode to selectively generate an address discharge in the discharge cells to form wall charges. In the sustain period, a sustain pulse is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell in which the address discharge is generated in the address period, and the corresponding discharge cell emits light. The image is displayed by turning it on.

  Thus, lighting / non-lighting of each discharge cell is determined by the presence / absence of the address discharge, and the address discharge is generated by the application of the address voltage. However, in general, the discharge phenomenon has a discharge delay time, and the address discharge does not occur immediately even when the address voltage is applied, but the address discharge occurs after a certain time. Therefore, the time for applying the voltage for generating the address discharge (hereinafter abbreviated as “address voltage application time”) must be set to a sufficient length to generate the address discharge with certainty.

However, if the write voltage application time is set longer than necessary, the write period becomes too long, and the drive time such as the initialization period and the sustain period cannot be secured. Therefore, a method of providing a longer address voltage application time for addresses with a longer elapsed time from the end of the initialization discharge (for example, refer to Patent Document 1), or when two or more subfields for controlling non-lighting of discharge cells are continuous. Then, a method of setting the write voltage application time of the subsequent subfield longer than the write voltage application time of other subfields (for example, see Patent Document 2) is disclosed.
JP-A-8-320668 JP 2005-338217 A

  In recent years, the time required for driving has become longer due to the increase in panel size, higher definition, etc., making it difficult to secure the write voltage application time. On the other hand, the discharge delay time has become smaller, such as smaller discharge cells and increased xenon partial pressure. And factors that increase the variation are increasing. If the address discharge does not occur even if the address pulse is applied, a malfunction that the address discharge does not occur in the discharge cells to be lit (hereinafter abbreviated as “address failure”) occurs, and the image display quality There was a risk of lowering.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a panel driving method and a plasma display device capable of suppressing defective writing of discharge cells and performing high-quality image display. To do.

  The present invention relates to a method for driving a panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and an address voltage is selectively applied between the scan electrode and the data electrode. A plurality of subfields each having an address period for selectively generating an address discharge in the discharge cells and a sustain period for generating a sustain discharge in the discharge cells in which the address discharge is generated, In a field where a predetermined number or more of non-lighting subfields that do not generate an address discharge are present in the discharge cells, at least one non-lighting subfield is omitted and an address voltage application time of at least one subfield other than the non-lighting subfield It is characterized by extending. By this method, it is possible to provide a panel driving method capable of suppressing defective writing of discharge cells and performing high-quality image display.

  Further, according to the present invention, when there is a subfield other than the non-lighting subfield after the non-lighting subfield, it is preferable not to omit the non-lighting subfield. By this method, the occurrence of flicker can be suppressed.

  Further, in the present invention, when extending the write voltage application time, it is desirable to extend over a predetermined time. By this method, the address voltage application time can be extended to a time during which the address discharge can be reliably generated without giving a visual discomfort.

  In addition, the plasma display device of the present invention selectively applies an address voltage between a scan electrode and a data electrode, and a panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode. A plurality of subfields each having an address period in which address discharge is selectively generated in the discharge cells and a sustain period in which sustain discharge is generated in the discharge cells in which the address discharge is generated are arranged to form one field period And a driving circuit that drives the panel, and the driving circuit omits at least one non-lighting subfield in a field where a predetermined number or more of non-lighting subfields that do not generate address discharge in all the discharge cells exist. In addition, the write voltage application time of at least one subfield other than the non-lighting subfield is extended and driven. It is characterized in. With this configuration, it is possible to provide a plasma display device capable of suppressing defective writing of discharge cells and performing high-quality image display.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the panel drive method and plasma display apparatus which can suppress the write defect of a discharge cell and can perform high quality image display.

  Hereinafter, a panel driving method according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to Embodiment 1 of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a discharge gas containing 10% xenon in a partial pressure ratio is enclosed. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells emit light and light up to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 in accordance with the first exemplary embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed.

  Next, a driving voltage waveform for driving panel 10 and its operation will be described. The panel 10 performs gradation display by dividing the one-field period into a plurality of subfields and controlling lighting / non-lighting of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address discharge are formed on each electrode. In addition, it has a function of generating priming for reducing the discharge delay and generating the address discharge stably. The initializing operation at this time includes an initializing operation for generating an initializing discharge in all discharge cells (hereinafter abbreviated as “all-cell initializing operation”), and an initializing discharge in a discharge cell that has undergone a sustain discharge. Initialization operation (hereinafter abbreviated as “selective initialization operation”).

  In the address period, a scan pulse is applied to the scan electrode as an address voltage and an address pulse is selectively applied to the data electrode, and an address discharge is selectively generated in the discharge cells to be lit to form wall charges. In the sustain period, a number of sustain pulses proportional to the luminance weight are alternately applied to the display electrode pairs, and a sustain discharge is generated in the discharge cell that has generated the address discharge to emit light and light up. The details of the subfield configuration will be described later, and here, the driving voltage waveform and its operation in the subfield will be described.

  FIG. 3 is a drive voltage waveform diagram applied to each electrode of panel 10 in accordance with the first exemplary embodiment of the present invention. FIG. 3 shows a subfield for performing all-cell initialization operation and a subfield for performing selective initialization operation.

  First, subfields for performing the all-cell initialization operation will be described.

  In the first half of the initialization period, 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, respectively, and the scan electrodes SC1 to SCn have a voltage lower than the discharge start voltage with respect to the sustain electrodes SU1 to SUn. A ramp waveform voltage that gradually rises from Vi1 toward voltage Vi2 that exceeds the discharge start voltage is applied.

  While this ramp waveform voltage rises, a weak initializing discharge occurs between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, and scan electrodes SC1 to SCn receive a discharge start voltage from voltage Vi3 that is equal to or lower than the discharge start voltage with respect to sustain electrodes SU1 to SUn. A ramp waveform voltage that gently falls toward the exceeding voltage Vi4 is applied. During this time, weak initializing discharges occur between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm, respectively. Then, the negative wall voltage on scan electrodes SC1 to SCn and the positive wall voltage on sustain electrodes SU1 to SUn are weakened, and the positive wall voltage on data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  In the subsequent address period, voltage Ve2 is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn.

  Next, negative scan pulse voltage Va is applied to scan electrode SC1 in the first row, and data electrode Dk (k = 1 to m) of the discharge cell to be lit in the first row among data electrodes D1 to Dm. A positive address pulse voltage Vd is applied. Thus, when the write voltage is applied between the data electrode Dk and the scan electrode SC1, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 becomes the difference between the externally applied voltages (Vd−Va) and the data electrode Dk. The upper wall voltage and the difference between the wall voltage on the scan electrode SC1 are added and exceed the discharge start voltage. However, even if the discharge start voltage is exceeded, address discharge does not occur immediately, but after a certain period of time, address is written between data electrode Dk and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1. Discharging occurs, positive wall voltage is accumulated on scan electrode SC1, negative wall voltage is accumulated on sustain electrode SU1, and negative wall voltage is also accumulated on data electrode Dk. Here, the time until the address discharge occurs after exceeding the discharge start voltage is referred to as a discharge delay time. This discharge delay time varies greatly depending on the presence or absence of priming. And since address discharge does not occur if the address voltage application time, that is, the pulse width of the scan pulse and the address pulse is shorter than the discharge delay time, the address voltage application time needs to be set to a certain extent. As will be described later, it is set to 1.2 μs to 1.6 μs.

  In this way, an address operation is performed in which address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse voltage Vd is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur.

  The above address operation is performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, positive sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn, and 0 (V) is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeds the discharge start voltage.

  Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, the sustain period is applied to the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn by alternately multiplying the luminance weight by the luminance magnification, and a potential difference is applied between the electrodes of the display electrode pair, thereby writing the address period. The sustain discharge is continuously performed in the discharge cell in which the address discharge has occurred in FIG.

  Then, at the end of the sustain period, a so-called narrow pulse voltage difference is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and the positive wall voltage on data electrode Dk is left while scanning. The wall voltage on the electrode SCi and the sustain electrode SUi is erased.

  Since priming also occurs due to this sustain discharge, the discharge delay time for the subsequent subfield address discharge can be shortened. The priming generated by the sustain discharge increases as the luminance weight increases, and increases as the ratio of discharge cells to be lit in the sustain period (hereinafter referred to as “lighting rate”) increases, so the discharge delay time is shortened. The work to do is also increased.

  Next, the operation of the subfield that performs the selective initialization operation will be described.

  In the initializing period in which selective initialization is performed, voltage Ve1 is applied to sustain electrodes SU1 to SUn, 0 (V) is applied to data electrodes D1 to Dm, and voltage Vi3 ′ toward voltage Vi4 is applied to scan electrodes SC1 to SCn. A ramp waveform voltage that gently falls is applied. Then, a weak initializing discharge is generated in the discharge cell that has caused the sustain discharge in the sustain period of the previous subfield, and the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. For data electrode Dk, a sufficient positive wall voltage is accumulated on data electrode Dk by the last sustain discharge, so that an excessive portion of this wall voltage is discharged, and the wall voltage suitable for the write operation is obtained. Adjusted to

  On the other hand, the discharge cells that did not cause the sustain discharge in the previous subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained as they are. As described above, the selective initializing operation is an operation for selectively performing initializing discharge on the discharge cells that have undergone the sustain operation in the sustain period of the immediately preceding subfield.

  The operation in the subsequent address period is the same as the operation in the address period of the subfield that performs all-cell initialization, and thus description thereof is omitted. The operation in the subsequent sustain period is the same except for the number of sustain pulses.

  Next, the subfield configuration will be described. In the present embodiment, one field is composed of 10 subfields (first SF, second SF,..., 10th SF), and the luminance weight of each subfield is, for example, (1, 2, 3, 6, 11, 18, 30, 44, 60, 80), the subfields arranged at the back will be described as being configured to be larger. However, in the present embodiment, based on the image signal, a subfield having a lighting rate of “0”, that is, a non-lighting subfield that does not generate an address discharge in all discharge cells, is detected, and based on the number of non-lighting subfields. The subfield configuration is reset. Specifically, at least one non-lighting subfield is omitted in a field where a predetermined number of non-lighting subfields that do not generate an address discharge in all the discharge cells, in this embodiment, “2” or more exist. The write voltage application time of at least one subfield other than the non-lighting subfield is extended.

  FIG. 4 schematically shows a subfield configuration in the first embodiment of the present invention, and FIG. 5 shows the number of non-lighting subfields, the number of subfields, and writing of each subfield in the first embodiment of the present invention. It is a figure which shows the relationship with voltage application time. Here, FIG. 4A is a subfield configuration of a field that displays an image in which no non-lighting subfield exists, and FIG. 4B is a subfield configuration of a field that displays an image in which the 10th SF is a non-lighting subfield. FIG. 4C shows a subfield configuration of a field for displaying an image in which the ninth SF and the tenth SF are non-lighting subfields, and FIG. 4D displays an image in which the eighth SF to the tenth SF are non-lighting subfields. Each subfield structure of the field is shown.

  In an image signal in which the lighting rate of the tenth SF having the largest luminance weight is not 0%, the lighting rates of the first to ninth SFs having a luminance weight smaller than that of the tenth SF are usually not 0%. Therefore, in this case, there is no non-lighting subfield, and one field is composed of the first SF to the tenth SF without omitting the subfield. Further, as shown in FIG. 5, the write voltage application times in the first SF to the tenth SF at this time are all set to 1.2 μs.

  In the field where the 10th SF is a non-lighting subfield, the 10th SF is omitted, and one field is composed of the first to ninth SFs. However, since the number of non-lighting subfields is “2” or less, the write voltage application time does not extend and remains 1.2 μs.

  In the field where the 10th SF and the 9th SF having the next highest luminance weight are non-lighting subfields, the 10th SF and the 9th SF are omitted as shown in FIG. 4C, and one field is composed of the 1st to 8th SFs. To do. In this case, since the number of non-lighting subfields is “2”, as shown in FIG. 5, the write voltage application time in the first to eighth SFs is extended by 0.2 μs and re-set to 1.4 μs. Set. When the ninth SF and the tenth SF having a large luminance weight are in the non-lighting subfield, the priming due to the sustain discharge is not supplied, so that the discharge delay time of the address discharge may be increased. However, in this embodiment, since the write voltage application time is also extended, the write operation can be performed stably without causing a write failure.

  In the field where the tenth SF, the ninth SF, and the eighth SF are non-lighting subfields, as shown in FIG. 4D, the driving of the tenth SF, the ninth SF, and the eighth SF is omitted, and one field is the first SF to the seventh SF. Constitute. In this case, since the number of non-lighting subfields is “3” and the discharge delay time of the address discharge may be further increased, the address voltage application time in the first SF to the seventh SF is further extended. Reset to 6 μs.

  As shown in FIG. 5, for the image signal in which the lighting rate of four or more subfields is 0%, in the present embodiment, the 10th SF to the 8th SF are the same as the image signals in which the non-lighting subfield is used. However, the non-lighting subfield may be omitted, and the write voltage application time for the other subfields may be further extended.

  FIG. 4 schematically shows an outline of one field of the drive voltage waveform applied to the scan electrode, and the details thereof are as shown in FIG.

  Next, a method for changing the subfield configuration will be described. In the present embodiment, when the number of non-lighting subfields increases as the image signal changes, the corresponding non-lighting subfields are immediately omitted, and the number of subfields constituting one field is shown in FIG. Reduce to the number shown. However, the write voltage application time does not extend immediately to the value shown in FIG. 5, but extends over a predetermined time.

  FIG. 6 is a diagram showing an example of a method for extending the write voltage application time according to the first embodiment of the present invention. FIG. 6A shows the number of non-lighting subfields that change in accordance with a change in the image signal. FIG. 6B is a diagram showing a subfield configuration of a field corresponding to the image signal. FIG. 6 shows an example of a subfield configuration corresponding to the passage of time for 26 fields. The number of non-lighting subfields is “0” up to the second field, and the third to fifth fields are non-lit. The number of lighting subfields is “1”, the number of non-lighting subfields is “2” in the 6th to 19th fields, the number of nonlighting subfields is “3” in the 20th to 23rd fields, and the number 24th. The non-lighting subfield is “0” after the field.

  In FIG. 6, since there is no non-lighting subfield up to the second field, the number of subfields is “10”, and the write voltage application time is 1.2 μs in all subfields. Since the 10th SF is a non-lighting subfield in the third field, the 10th SF is omitted and the number of subfields is “9”. However, the write voltage application time remains 1.2 μs.

  Next, in the sixth field, the ninth SF is also a non-lighting subfield. Then, the ninth SF is also omitted and the number of subfields is “8”. According to FIG. 5, the write voltage application time is 1.4 μs for each subfield. However, the write voltage application time for all subfields is not extended all at once, but gradually over a predetermined time. To do. Specifically, as shown in FIG. 6B, first, in the sixth field, the write voltage application time of the eighth SF is increased by 0.1 μs to 1.3 μs. In the seventh field, the write voltage application time of the seventh SF is extended by 0.1 μs to 1.3 μs. Similarly, the write voltage application time of the subfield is sequentially extended by 0.1 μs for each field, and the write voltage application times of the first to eighth SFs are set to 1.3 μs in the thirteenth field. Further, in the 14th field, the write voltage application time of the 8th SF is further extended by 0.1 μs to 1.4 μs. Similarly, the subfield write voltage application time is sequentially extended until the first SF to eighth SF write voltage application time reaches 1.4 μs. Thus, in the present embodiment, the write voltage application time is extended over 16 field periods.

  In the example shown in FIG. 6, the 8th SF is also a non-lighting subfield in the 20th field. Then, the eighth SF is also omitted and the number of subfields is “7”. According to FIG. 5, the write voltage application time is 1.6 μs in each subfield, but the 20th field is still in the process of extending from 1.3 μs to 1.4 μs. The extension continues until the write voltage application time of the seventh SF reaches 1.6 μs.

  In the 24th field, there is no non-lighting subfield. Then, the number of subfields is immediately returned to “10”, and the write voltage application time is also immediately returned to the original 1.2 μs.

  As described above, in the present embodiment, in a field where there are two or more non-lighting subfields that do not generate an address discharge in all discharge cells, at least one non-lighting subfield is omitted and other than the non-lighting subfields. Extending the write voltage application time of at least one subfield of. Further, when extending the write voltage application time, it does not immediately extend to the value shown in FIG. 5, but gradually increases over a predetermined time, so that a visual discomfort is not given. The address voltage application time can be extended to a time during which the address discharge can be reliably generated.

  FIG. 7 is a circuit block diagram of plasma display device 100 in accordance with the first exemplary embodiment of the present invention. The plasma display device 100 includes a panel 10, an image signal processing circuit 51, a data electrode drive circuit 52, a scan electrode drive circuit 53, a sustain electrode drive circuit 54, a timing generation circuit 55, a non-lighting SF detection circuit 61, and an SF configuration setting circuit 62. And a power supply circuit (not shown) for supplying necessary power to each circuit block.

  The image signal processing circuit 51 converts the image signal into an image signal having the number of pixels and the number of gradations that can be displayed on the panel 10, and further turns on / off in each subfield “1” of each bit of the digital signal, The image data is converted to image data corresponding to “0”. The data electrode drive circuit 52 converts the image data into address pulses corresponding to the data electrodes D1 to Dm and applies them to the data electrodes D1 to Dm.

  The non-lighting SF detection circuit 61 calculates the lighting rate of the discharge cells in each subfield, that is, the ratio of the discharge cells that sustain and discharge in the subfield with respect to all the discharge cells based on the image data, and the lighting rate is “0”. Is detected as a non-lighting subfield. As shown in FIG. 6, the SF configuration setting circuit 62 is based on the number of non-lighting subfields calculated by the non-lighting SF detection circuit 61, and the number of subfields in that field and the write voltage in the write period of each subfield. Reset the application time.

  The timing generation circuit 55 controls various operations of each circuit block to realize the number of subfields and the write voltage application time reset by the SF configuration setting circuit 62 based on the horizontal synchronization signal and the vertical synchronization signal. Are generated and supplied to the respective circuit blocks. Scan electrode drive circuit 53 and sustain electrode drive circuit 54 generate drive voltage waveforms having the above-described number of subfields and write voltage application time based on the respective timing signals, and scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. Drive each one.

  In the first embodiment, one field is composed of ten subfields, and the luminance weight of each subfield is set to be larger for the subfields arranged behind. It is not limited to this. In the following, embodiments for other subfield configurations will be described.

(Embodiment 2)
In the second embodiment of the present invention, one field is composed of 12 subfields (first SF, second SF,..., Seventh SF, eighth SF,..., 12th SF), and the luminance weight of each subfield. Is described as being set to have two peaks, for example (1, 2, 4, 14, 29, 54, 121, 6, 12, 20, 32, 92). Such a subfield configuration can be used, for example, when displaying a PAL image signal. However, also in the second embodiment, as in the first embodiment, a non-lighting subfield that does not generate an address discharge in all discharge cells is detected based on the image signal, and the non-lighting subfield of the subfield constituting the field is detected. The subfield configuration is reset based on the number. Specifically, in a field where there are a predetermined number of non-lighting subfields that do not generate an address discharge in all discharge cells, and in the second embodiment, “3” or more, at least one non-lighting subfield is omitted. The write voltage application time of at least one subfield other than the non-lighting subfield is extended.

  FIG. 8 is a diagram showing the relationship between the number of non-lighting subfields, the number of subfields, and the write voltage application time in each subfield in Embodiment 2 of the present invention.

  In an image signal in which the seventh SF having the largest luminance weight is not a non-lighting subfield, other subfields having a smaller luminance weight than the seventh SF are usually not non-lighting subfields. In this case, one field is composed of the first to twelfth SFs without omitting all the subfields. In addition, the write voltage application times in the first SF to the twelfth SF at this time are all set to 1.2 μs.

  In the field where the seventh SF having the largest luminance weight is a non-lighting subfield, as shown in FIG. 8, all the subfields are executed without being omitted. The reason why the seventh SF is not omitted in the present embodiment is to avoid the fact that the seventh SF is omitted, thereby changing the sustain discharge timing in the eighth to twelfth SFs and visually recognizing it as flicker.

  In a field in which the seventh SF with the highest luminance weight and the twelfth SF with the next highest luminance weight are non-lighting subfields, the twelfth SF is omitted and one field is composed of the first SF to the eleventh SF. However, the number of non-lighting subfields is “2”, and the write voltage application time in the first to eleventh SFs at this time remains 1.2 μs.

  In fields where the seventh SF, the twelfth SF, and the sixth SF are non-lighting subfields, the twelfth SF is omitted and one field is composed of the first SF to the eleventh SF. In this case, the number of non-lighting subfields is “3”. As shown in FIG. 8, the write voltage application time in the first SF to the fifth SF and the eighth SF to the eleventh SF at this time is 1.2 μs. Also extends to 1.4 μs longer by 0.2 μs. However, the write voltage application time of the sixth SF and the seventh SF does not extend and is 1.2 μs.

  In the fields where the seventh SF, the twelfth SF, the sixth SF, and the eleventh SF are non-lighting subfields, the twelfth SF and the eleventh SF are omitted, and one field includes the first SF to the tenth SF. At this time, the write voltage application time in the first SF to the fifth SF and the eighth SF to the tenth SF is extended to 1.4 μs.

  In fields where the seventh SF, the twelfth SF, the sixth SF, the eleventh SF, and the fifth SF are non-lighting subfields, the twelfth SF and the eleventh SF are omitted, and one field is composed of the first SF to the tenth SF. At this time, the write voltage application time in the first SF to the fourth SF and the eighth SF to the tenth SF is further extended by 0.2 μs and reset to 1.6 μs.

  Also in the second embodiment, when the number of non-lighting subfields is increased due to the change of the image signal, the driving of the corresponding subfield is immediately omitted, and the number of subfields constituting one field is shown in FIG. Reduce to the number shown. The write voltage application time does not extend immediately to the value shown in FIG. 8, but gradually extends over a predetermined field period.

  For an image signal in which six or more subfields are non-lighting subfields, in this embodiment, as shown in FIG. 8, the same subfield as the image signal in which five subfields are non-lighting subfields. Although the configuration is described, the non-lighting subfield may be omitted, and the write voltage application time of other subfields may be extended. However, in order not to generate flicker, it is desirable not to omit the non-lighting subfield when there is a subfield other than the non-lighting subfield after the non-lighting subfield.

  In the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and can be similarly applied to other subfield configurations.

  Further, the specific numerical values used in the present embodiment are merely examples, and it is desirable to appropriately set the values appropriately according to the characteristics of the panel, the specifications of the plasma display device, and the like.

  INDUSTRIAL APPLICABILITY The present invention can suppress defective writing of discharge cells and perform high-quality image display, and is useful as a panel driving method and a plasma display device.

The disassembled perspective view which shows the structure of the panel in Embodiment 1 of this invention. Electrode arrangement of the panel Drive voltage waveform diagram applied to each electrode of the panel The figure which shows typically the subfield structure in Embodiment 1 of this invention. The figure which shows the relationship between the number of non-lighting subfields in Embodiment 1 of this invention, the number of subfields, and the write voltage application time of each subfield. The figure which shows an example of the extending method of the write voltage application time in Embodiment 1 of this invention Circuit block diagram of plasma display device according to Embodiment 1 of the present invention The figure which shows the relationship between the number of non-lighting subfields in Embodiment 2 of this invention, the number of subfields, and the write voltage application time of each subfield.

Explanation of symbols

10 panel 21 front substrate 22 scan electrode 23 sustain electrode 24 display electrode pair 31 back substrate 32 data electrode 51 image signal processing circuit 52 data electrode drive circuit 53 scan electrode drive circuit 54 sustain electrode drive circuit 55 timing generation circuit 61 non-lighting SF detection Circuit 62 SF configuration setting circuit 100 Plasma display device

Claims (2)

A method for driving a plasma display panel comprising a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode,
An address period in which an address voltage is selectively applied between the scan electrode and the data electrode to selectively generate an address discharge in the discharge cell, and a sustain discharge is generated in the discharge cell in which the address discharge is generated. One field period is composed of a plurality of subfields each having a sustain period,
In a field where there are a predetermined number or more of non-lighting subfields that do not generate address discharge in all discharge cells, at least one non-lighting subfield is omitted and at least one subfield other than the non-lighting subfield is written. Extend the voltage application time ,
A method for driving a plasma display panel, wherein a non-lighting subfield is not omitted when a subfield other than the nonlighting subfield exists after the nonlighting subfield . A plasma display panel comprising a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode;
An address period in which an address voltage is selectively applied between the scan electrode and the data electrode to selectively generate an address discharge in the discharge cell, and a sustain discharge is generated in the discharge cell in which the address discharge is generated. A plurality of subfields each having a sustain period and a drive circuit configured to drive the plasma display panel by configuring one field period;
The drive circuit is
In a field where there are a predetermined number or more of non-lighting subfields that do not generate address discharge in all discharge cells, at least one non-lighting subfield is omitted and at least one subfield other than the non-lighting subfield is written. A plasma display device , which is driven by extending a voltage application time, and when there is a subfield other than the non-lighting subfield after the non-lighting subfield, the non-lighting subfield is not omitted .

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