JP2009069239A - Method of driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the length of a write period with image degradation suppressed, even in the case of a plasma display panel with a large number of scan electrodes. <P>SOLUTION: A plurality of sub-fields each of which has a write period when a scan pulse is applied to scan electrodes and a write pulse is applied to data electrodes to perform a write operation by discharge cells and a sustain period when the number of sustain pulses based on a brightness weight are applied to scan electrodes and sustain electrodes alternately to cause discharge cells to emit light are arranged to constitute one field period. In the write period, a normal write operation of applying the scan pulse to scan electrodes one by one or a simultaneous write operation of simultaneously applying the scan pulse to every two scan electrodes is performed. When the APL of an image signal for display is equal to or larger than a prescribed value, the number of sub-fields where the simultaneous write operation is performed is set to be larger than that of an image signal of which the APL is smaller than the threshold. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for driving a plasma display panel.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) is formed by arranging a large number of discharge cells having scan electrodes, sustain electrodes, and data electrodes. Then, ultraviolet light is generated by gas discharge in each discharge cell, and the RGB color phosphors applied inside the discharge cell are excited and emitted by this ultraviolet light to perform color display.

  A method for driving the panel is a subfield method, that is, a plurality of subfields having an initialization period, an address period, and a sustain period are arranged to form one field period, and gradation display is performed by combining subfields that emit light. The method of performing is common. In the initializing period, initializing discharge is performed in the discharge cells, the history of wall charges for individual previous discharge cells is erased, and wall charges necessary for the subsequent address operation are formed. In addition, it has a function of generating priming (priming for discharge = excited particles) for reducing discharge delay and stably generating address discharge. In the subsequent address period, an address operation is performed in which a scan pulse is applied to the scan electrode and an address pulse corresponding to an image signal to be displayed on the data electrode is applied to form selective wall charges in the discharge cells. In the sustain period, a number of sustain pulses corresponding to the luminance weight are alternately applied to the scan electrodes and the sustain electrodes, and the discharge cells in which the wall charges are formed by the address discharge are selectively discharged to emit light. Thus, in the address period, it is necessary to sequentially apply the scan pulse to each of the scan electrodes to selectively cause the address discharge.

In recent years, higher definition of panels has progressed, and the number of scan electrodes tends to increase accordingly. When the number of scan electrodes increases, the time required for the address operation per scan electrode (hereinafter abbreviated as “address time”) is shortened, or address discharge is selectively performed on all the scan electrodes. Therefore, it is necessary to lengthen the writing period. However, if the address time is shortened, the address discharge becomes unstable, and the cells that should emit light do not emit light and the image display quality may deteriorate. In addition, when the writing period is lengthened, the initialization period or the sustain period must be shortened accordingly. However, if the initialization period is shortened, the address discharge becomes unstable and the image display quality deteriorates. If the sustain period is shortened, the number of sustain discharges decreases and the image display brightness decreases. In order to solve these problems, for example, in Patent Document 1, the conventional line-sequential method is an interlaced method, and line-sequential driving is performed by using two consecutive rows of scanning electrodes as one scanning unit. A method for halving the time required is described.
JP-A-5-216433

  According to the panel driving method described in Patent Document 1, it is possible to halve the length of the writing period. However, since the same image signal is input to two continuous scanning electrodes, as described in Patent Document 1, it is inevitable that the resolution of the displayed image is greatly reduced.

  The present invention has been made in view of these problems, and provides a panel driving method capable of reducing the length of a writing period while suppressing deterioration in image quality even in a panel having a large number of scan electrodes. With the goal.

  The present invention relates to a panel driving method in which a large number of discharge cells each having a scan electrode, a sustain electrode, and a data electrode are arranged. A scan pulse is applied to the scan electrode and an address pulse is applied to the data electrode. One field period in which a plurality of subfields having an address period for performing an address operation and a sustain period for alternately applying the number of sustain pulses corresponding to the luminance weight to the scan electrodes and the sustain electrodes to cause the discharge cells to emit light are arranged In the address period, either the normal address operation in which the scan pulse is applied to the scan electrode one scan electrode at a time or the simultaneous address operation in which the scan pulse is simultaneously applied to the scan electrode by two scan electrodes is performed. If the APL of the image signal to be displayed is equal to or greater than a predetermined threshold value, the simultaneous writing operation is performed in comparison with the image signal less than the predetermined threshold value. Characterized by being configured to set a larger number of sub-fields. According to this method, it is possible to provide a panel driving method capable of reducing the length of the writing period while suppressing deterioration in image quality even for a panel having a large number of scan electrodes.

  In the panel driving method of the present invention, when the APL of the image signal to be displayed is equal to or higher than a predetermined threshold value, the time required for the writing operation per scanning electrode is compared with the image signal lower than the predetermined threshold value. It is desirable to configure so as to be set longer.

  In the panel driving method of the present invention, it is desirable to set a subfield having a small luminance weight as a subfield for performing a simultaneous writing operation.

  According to the present invention, it is possible to provide a panel driving method capable of reducing the length of the writing period while suppressing deterioration in image quality even for a panel having a large number of scan electrodes.

  Hereinafter, a panel driving method according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing a main part of a panel according to an embodiment of the present invention. The panel 1 is configured such that a glass front substrate 2 and a rear substrate 3 are arranged to face each other and a discharge space is formed therebetween. On the front substrate 2, a plurality of scanning electrodes 4 and sustaining electrodes 5 constituting display electrodes are formed in parallel with each other. A dielectric layer 6 is formed so as to cover the scan electrode 4 and the sustain electrode 5, and a protective layer 7 is formed on the dielectric layer 6. A plurality of data electrodes 9 covered with an insulating layer 8 are formed on the back substrate 3, and a partition wall 10 is provided in parallel with the data electrodes 9 on the insulating layer 8 between the data electrodes 9. A phosphor layer 11 is provided on the surface of the insulator layer 8 and the side surfaces of the partition walls 10. The front substrate 2 and the rear substrate 3 are arranged to face each other in a direction in which the scan electrodes 4 and the sustain electrodes 5 and the data electrodes 9 intersect, and a mixed gas of, for example, neon and xenon is enclosed as a discharge gas therebetween. .

  FIG. 2 is an electrode array diagram of panel 1 according to the embodiment of the present invention. N scan electrodes SCN1 to SCNn (scan electrode 4 in FIG. 1) and n sustain electrodes SUS1 to SUSn (sustain electrode 5 in FIG. 1) are alternately arranged in the row direction, and m data electrodes in the column direction. D1 to Dm (data electrodes 9 in FIG. 1) are arranged. A discharge cell is formed at a portion where a pair of scan electrode SCNi and sustain electrode SUSi (i = 1 to n) and one data electrode Dj (j = 1 to m) intersect, and the discharge cell is in the discharge space. M × n are formed. In the following description, n is assumed to be an even number, but the present invention is of course not limited thereto.

  FIG. 3 is a circuit block diagram of the plasma display device according to the embodiment of the present invention. The plasma display device includes a panel 1, a data electrode drive circuit 12, a scan electrode drive circuit 13, a sustain electrode drive circuit 14, a timing generation circuit 15, an image signal processing circuit 18, an APL calculation circuit 30, and a power source necessary for each circuit block. A power supply circuit (not shown) for supplying is provided.

  The timing generation circuit 15 controls the operation of each circuit block based on the horizontal synchronization signal, the vertical synchronization signal, and the average luminance level of the image signal detected by the APL calculation circuit 30 (hereinafter abbreviated as “APL”). Various timing signals are generated and supplied to each circuit block. In particular, the timing generation circuit 15 selects, based on the APL, a normal write operation in which a write operation is performed for each scan electrode and a simultaneous write operation in which a write operation is performed for each two scan electrodes in an address period to be described later. Is supplied to each circuit block.

  The image signal processing circuit 18 converts the input image signal into image data indicating light emission / non-light emission for each subfield. The data electrode driving circuit 12 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm. The APL calculation circuit 30 calculates the APL of the image signal. Specifically, the APL can be calculated by using a generally known method such as accumulating the luminance value of the image signal over one field period or one frame period. Scan electrode drive circuit 13 drives each scan electrode 4 based on the timing signal, and sustain electrode drive circuit 14 drives sustain electrode 5 based on the timing signal.

  Next, a driving voltage waveform for driving the panel 1 and its operation will be described. In the present embodiment, one field period is composed of ten subfields (first SF, second SF,..., Tenth SF) having an initialization period, an address period, and a sustain period. For example, it is assumed that each has a luminance weight of (1, 2, 3, 6, 11, 18, 30, 44, 60, 80). However, in the present invention, the number of subfields and the luminance weight are not limited to the above values.

  FIG. 4 is a waveform diagram of driving voltage applied to each electrode of the panel of the plasma display device in accordance with the exemplary embodiment of the present invention. FIG. 4 shows drive voltage waveforms in two subfields, but drive voltage waveforms in other subfields are substantially the same.

  In the first half of the initialization period, sustain electrodes SUS1 to SUSn and data electrodes D1 to Dm are held at 0 (V), and discharge starts from voltage Vp (V) that is equal to or lower than the discharge start voltage with respect to scan electrodes SCN1 to SCNn. An upward ramp waveform voltage that gently rises toward the voltage Vr (V) exceeding the voltage is applied. Then, a weak initializing discharge is generated with scan electrodes SCN1 to SCNn as anodes and sustain electrodes SUS1 to SUSn and data electrodes D1 to Dm as cathodes. Thus, the first weak initializing discharge is generated in all the discharge cells, the negative wall voltage is stored on the scan electrodes SCN1 to SCNn, and the positive wall on the sustain electrodes SUS1 to SUSn and the data electrodes D1 to Dm. Stores voltage. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the phosphor layer, the protective layer, and the like.

  In the second half of the initialization period, sustain electrodes SUS1 to SUSn are maintained at positive voltage Vh (V), and the downward slope gradually decreases from voltage Vg (V) to voltage Va (V) at scan electrodes SCN1 to SCNn. Apply waveform voltage. Then, in all the discharge cells, a second weak initializing discharge is generated using scan electrodes SCN1 to SCNn as cathodes and sustain electrodes SUS1 to SUSn and data electrodes D1 to Dm as anodes. Then, the wall voltage on scan electrodes SCN1 to SCNn and the wall voltage on sustain electrodes SUS1 to SUSn are weakened, and the wall voltage on data electrodes D1 to Dm is also adjusted to a value suitable for the write operation.

  As the drive voltage waveform in the initialization period, only the voltage waveform in the latter half of the initialization period may be applied as shown in the initialization period of the second SF in FIG. Initializing discharge is selectively generated in the discharge cells that have undergone sustain discharge in the sustain period of the subfield.

  In the subsequent address period, a normal address operation in which a scan pulse is applied to scan electrodes SCN1 to SCNn one by one, and a simultaneous address operation in which a scan pulse is simultaneously applied to two adjacent scan electrodes to scan electrodes SCN1 to SCNn. When the APL of the image signal to be displayed is equal to or greater than a predetermined threshold value, the number of subfields for simultaneous writing operation is larger than that of an image signal less than the predetermined threshold value. It is set as follows. Further, when the APL of the image signal to be displayed is equal to or greater than a predetermined threshold value, the writing time is set longer than that of an image signal less than the predetermined threshold value.

  First, the normal write operation in which the write operation is performed for each scan electrode will be described in detail. FIG. 5 is a diagram for explaining a normal write operation of the plasma display device in accordance with the exemplary embodiment of the present invention, and is a drive voltage waveform diagram applied to each electrode of the panel in the write period.

  Scan electrodes SCN1 to SCNn are once held at voltage Vs (V). Next, a positive address pulse voltage Vw (V) is applied to the data electrode Dk (k = 1 to m) of the discharge cell to be displayed in the first row among the data electrodes D1 to Dm, and the first row. Scan pulse voltage Vb (V) is applied to scan electrode SCN1. At this time, the voltage at the intersection of the data electrode Dk and the scan electrode SCN1 is obtained by adding the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SCN1 to the externally applied voltage (Vw−Vb) (V). The discharge start voltage is exceeded. Then, an address discharge occurs between data electrode Dk and scan electrode SCN1 and between sustain electrode SUS1 and scan electrode SCN1, and a positive wall voltage is accumulated on scan electrode SCN1 of this discharge cell, and on sustain electrode SUS1. And a negative wall voltage is also accumulated on the data electrode Dk. In this manner, an address operation is performed in which address discharge is caused in the discharge cells to be displayed in the first row and wall voltage is accumulated on each electrode. On the other hand, since the voltage at the intersection of the data electrode to which the positive address pulse voltage Vw (V) is not applied and the scan electrode SCN1 does not exceed the discharge start voltage, the address discharge does not occur.

  The above address operation is sequentially performed on the discharge cells in the second row, the discharge cells in the third row,..., The discharge cells in the nth row, and the address period ends. As described above, in the normal address operation, scan pulses having different phases are sequentially applied to the scan electrodes SCN1 to SCNn, and address pulses based on the image signals corresponding to the respective discharge cells are applied to the data electrodes D1 to Dm. This is an address operation for selectively performing address discharge.

  Next, the simultaneous write operation in which the write operation is performed simultaneously for every two adjacent scan electrodes will be described in detail. In the present embodiment, there are two types of simultaneous write operations. FIG. 6 is a diagram for explaining a first simultaneous write operation of the plasma display device in accordance with the exemplary embodiment of the present invention, and is a drive voltage waveform diagram applied to each electrode of the panel in the write period.

  Scan electrodes SCN1 to SCNn are once held at voltage Vs (V). Next, a positive address pulse voltage Vw (V) is applied to the data electrode Dk of the discharge cell to be displayed in the first row among the data electrodes D1 to Dm, and the scan electrode SCN1 and the second row in the first row are applied. The scan pulse voltage Vb (V) is applied to the scan electrode SCN2. Then, an address discharge occurs between data electrode Dk and scan electrode SCN1 and between sustain electrode SUS1 and scan electrode SCN1, and a wall voltage is accumulated on each electrode. At the same time, an address discharge also occurs between data electrode Dk and scan electrode SCN2 and between sustain electrode SUS2 and scan electrode SCN2, and a wall voltage is accumulated on each electrode. As described above, in the first simultaneous address operation, an address operation is performed in which the address discharge is caused in the discharge cell to be displayed in the first row and the wall voltage is accumulated on each electrode. A write operation is performed. On the other hand, no address discharge occurs in the first row discharge cells and the second row discharge cells to which the positive address pulse voltage Vw (V) is not applied.

  The above addressing operation is performed with the discharge cells in the third row, the discharge cells in the fourth row, the discharge cells in the fifth row, the discharge cells in the sixth row,..., The discharge cells in the (n−1) th row and the nth row. The discharge cell is sequentially performed, and the address period ends.

  As described above, in the first simultaneous write operation, the scan pulses having the same phase are applied to two adjacent scan electrodes, and the image signals corresponding to the discharge cells in every other row are applied to each of the data electrodes D1 to Dm. This is a simultaneous address operation in which the address pulse is selectively applied and the address discharge is selectively performed. Here, the scan electrodes to which scan pulses of the same phase are applied are scan electrode SCN1 and scan electrode SCN2, scan electrode SCN3 and scan electrode SCN4,..., Scan electrode SCNn-1 and scan electrode SCNn, and data electrode D1. Address pulses based on image signals corresponding to the odd-numbered discharge cells are applied to each of .about.Dm. In the first simultaneous writing operation, the writing operation is performed at the same time for every two scan electrodes, so that the writing period can be completed in about half the writing period of the normal writing operation. On the other hand, since the same image data is input to adjacent scanning electrodes, the resolution in the vertical direction is lowered.

  Next, the second simultaneous writing operation will be described in detail. FIG. 7 is a diagram for explaining a second simultaneous write operation of the plasma display device in accordance with the exemplary embodiment of the present invention, and is a drive voltage waveform diagram applied to each electrode of the panel during the write period.

  For the discharge cells in the first row, an address operation similar to the normal address operation is performed. That is, a positive address pulse voltage Vw (V) is applied to the data electrode Dk of the discharge cell to be displayed in the first row, and a scan pulse voltage Vb (V) is applied to the scan electrode SCN1 in the first row. Perform the action.

  Next, a positive address pulse voltage Vw (V) is applied to the data electrode Dk of the discharge cell to be displayed in the second row among the data electrodes D1 to Dm, and the scan electrode SCN2 and the third row in the second row are applied. The scan pulse voltage Vb (V) is applied to the scan electrode SCN3 to perform an address operation. Subsequently, the address operation is performed with the discharge cells in the fourth row and the discharge cells in the fifth row, the discharge cells in the sixth row and the discharge cells in the seventh row,..., The discharge cells in the n-2 row and the n-1 row. This is sequentially performed on the first discharge cell and the n-th discharge cell.

  Thus, although the second simultaneous writing operation is also a simultaneous writing operation, the scan electrodes to which the scan pulses of the same phase are applied are the scan electrode SCN2 and the scan electrode SCN3, the scan electrode SCN4 and the scan electrode SCN5,. Scan electrode SCNn-2 and scan electrode SCNn-1, and address pulses based on image signals corresponding to the discharge cells in the even-numbered rows are applied to data electrodes D1 to Dm, respectively. In the second simultaneous writing operation, since the writing operation is performed simultaneously for every two scan electrodes, the writing period can be completed in about ½ of the writing period of the normal writing operation, but the resolution in the vertical direction is lowered.

  In the subsequent sustain period, first, sustain electrodes SUS1 to SUSn are returned to 0 (V), and positive sustain pulse voltage Vm (V) is applied to scan electrodes SCN1 to SCNn. At this time, in the discharge cell in which the address discharge has occurred, the voltage between scan electrode SCNi and sustain electrode SUSi is equal to sustain pulse voltage Vm (V) as the wall voltage on scan electrode SCNi and sustain electrode SUSi. The magnitude is added and exceeds the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCNi and sustain electrode SUSi, a negative wall voltage is accumulated on scan electrode SCNi, and a positive wall voltage is accumulated on sustain electrode SUSi. At this time, a positive wall voltage is also accumulated on the data electrode Dk. In the discharge cells that did not cause the address discharge in the address period, the sustain discharge does not occur, and the wall voltage state at the end of the initialization period is maintained. Subsequently, scan electrodes SCN1 to SCNn are returned to 0 (V), and positive sustain pulse voltage Vm (V) is applied to sustain electrodes SUS1 to SUSn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage between the sustain electrode SUSi and the scan electrode SCNi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUSi and the scan electrode SCNi, Negative wall voltage is accumulated on sustain electrode SUSi, and positive wall voltage is accumulated on scan electrode SCNi. Similarly, the sustain discharge continues in the discharge cells that have caused the address discharge in the address period by alternately applying the number of sustain pulses corresponding to the luminance weight to the scan electrodes SCN1 to SCNn and the sustain electrodes SUS1 to SUSn. Done.

  Next, details of the writing time and the writing operation in this embodiment will be described. FIG. 8 is a diagram showing the relationship between the write operation of each subfield and APL, and the relationship between the write time and APL in the plasma display device in accordance with the exemplary embodiment of the present invention. In this embodiment, there are two predetermined thresholds for APL, one is 50% and the other is 75%. That is, for an image signal having an APL of less than 50%, the writing operation of all subfields is a normal writing operation, and the writing time is 1.00 μs. For image signals having an APL of 50% or more and less than 75%, the first SF write operation is a simultaneous write operation, and the other subfield write operations are normal write operations. The writing time at this time is 1.05 μs. For an image signal with an APL of 75% or more, the first SF and second SF write operations are simultaneous write operations, and the other subfield write operations are normal write operations. The write time at this time is 1.10 μs.

  As described above, the subfield having a small luminance weight is set as a subfield for performing the simultaneous writing operation. In the subfield where the simultaneous writing operation is performed, the first simultaneous writing operation and the second simultaneous writing operation are alternately switched for each field. For example, the first SF write operation for an image signal having an APL of 50% or more and less than 75% is the first simultaneous write operation in the first field, the second simultaneous write operation in the next field, and the following In the field, the first simultaneous write operation is performed, and in the next field, the second simultaneous write operation is performed. The first SF and second SF write operations for an image signal having an APL of 75% or more are the first simultaneous write operation in the first field, the second simultaneous write operation in the next field, and the next field. Is the first simultaneous write operation, and in the next field is the second simultaneous write operation.

  As described above, in the present embodiment, when the APL of the image signal to be displayed is equal to or greater than the predetermined threshold value, the number of subfields for performing the simultaneous writing operation is compared with the image signal less than the predetermined threshold value. Many are set. In addition, when the APL of the image signal to be displayed is equal to or greater than a predetermined threshold, the writing time is set longer than that of an image signal less than the predetermined threshold. Further, the subfields are set so as to perform the simultaneous writing operation in order from the subfield having the smallest luminance weight.

  This shows that when an image with a large APL is displayed, the address discharge tends to become unstable, and it has been empirically revealed that it is effective to set the address time longer in order to solve this problem. Therefore, in this embodiment, when displaying an image with a large APL, the number of subfields for simultaneous writing operation is increased to shorten the writing period, and the writing time is set to be longer by using the shortened time. This stabilizes the address discharge. Further, by controlling the simultaneous writing operation in order from the subfield with the smallest luminance weight, the reduction in the resolution in the vertical direction is suppressed. Further, in the subfield where the simultaneous writing operation is performed, the vertical resolution is compensated by alternately switching the first simultaneous writing operation and the second simultaneous writing operation for each field. In this manner, in this embodiment, even in a panel having a large number of scan electrodes, the address discharge is stabilized and a high-quality image display is performed.

  It should be noted that the specific numerical values used in the present embodiment are merely examples, and it is desirable to appropriately set the optimal values according to the panel characteristics, the plasma display device specifications, and the like.

  The present invention is useful as a panel driving method because even a panel having a large number of scan electrodes can reduce the length of an address period while suppressing deterioration in image quality.

The disassembled perspective view which shows the principal part of the panel in embodiment of this invention Electrode arrangement of the panel Circuit block diagram of plasma display device in accordance with exemplary embodiment of the present invention Drive voltage waveform diagram applied to each electrode of the panel of the plasma display device The figure explaining normal write-in operation of the plasma display device The figure explaining the 1st simultaneous writing operation | movement of the plasma display apparatus The figure explaining 2nd simultaneous write-in operation | movement of the plasma display apparatus The figure which shows the relationship between writing operation of each subfield of the plasma display apparatus, and APL, and the relationship between writing time and APL.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Panel 2 Front substrate 3 Back substrate 4 Scan electrode 5 Sustain electrode 9 Data electrode 12 Data electrode drive circuit 13 Scan electrode drive circuit 14 Sustain electrode drive circuit 15 Timing generation circuit 18 Image signal processing circuit 30 APL calculation circuit

Claims (3)

A method of driving a plasma display panel in which a number of discharge cells having scan electrodes, sustain electrodes, and data electrodes are arranged,
An address period in which a scan pulse is applied to the scan electrode and an address pulse is applied to the data electrode to perform an address operation in the discharge cell, and a number of sustain pulses corresponding to a luminance weight are applied to the scan electrode and the sustain electrode A plurality of subfields having a sustain period for causing the discharge cells to emit light by alternately applying a plurality of subfields constitute one field period,
In the address period, either a normal address operation in which a scan pulse is applied to the scan electrode by one scan electrode or a simultaneous address operation in which a scan pulse is simultaneously applied to the scan electrode by two scan electrodes is performed. Configured as
In addition, when the APL of the image signal to be displayed is greater than or equal to a predetermined threshold value, the number of subfields for performing simultaneous writing operation is set to be larger than that of the image signal less than the predetermined threshold value. A method for driving a plasma display panel. When the APL of the image signal to be displayed is equal to or greater than the predetermined threshold value, the time required for the writing operation per scan electrode is set longer than the image signal less than the predetermined threshold value. The method of driving a plasma display panel according to claim 1, wherein: 2. The method of driving a plasma display panel according to claim 1, wherein the subfield having a small luminance weight is set to a subfield for performing a simultaneous writing operation.

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