KR100502924B1 - Plasma display panel and driving method thereof - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel, wherein an erroneous discharge erase period is added between a reset period and an address period. Due to the unstable reset operation in the reset period, a large amount of negative and positive charges can be formed in the scan electrode and the sustain electrode, respectively. These charges can cause a discharge between the scan electrode and the sustain electrode in the sustain period even if there is no address discharge in the address period. In the erroneous discharge erasing period, first, a voltage is applied between the scan electrode and the sustain electrode to generate a discharge, thereby forming positive and negative charges on the scan electrode and the sustain electrode, respectively. Next, an erase waveform is applied to erase the positive and negative charges formed in the scan electrode and the sustain electrode. In this way, discharge cells that are not selected in the sustain period can be prevented from being discharged when an unstable reset operation occurs.

Description

Plasma Display Panel and Driving Method {PLASMA DISPLAY PANEL AND DRIVING METHOD THEREOF}

The present invention relates to a plasma display panel (PDP) and a driving method thereof.

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. First, the structure of the plasma display panel will be described with reference to FIGS. 1 and 2.

1 is a partial perspective view of a plasma display panel, and FIG. 2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

As shown in FIG. 2, the electrode of the plasma display panel has a matrix structure of n × m. Address electrodes A ₁ -A _m are arranged in the column direction, and n rows of scan electrodes Y ₁ -Y _n and sustain electrodes X ₁ -X _n are arranged in pairs in the row direction.

In general, a plasma display panel is driven by dividing one frame into a plurality of subfields, and gray levels are expressed by a combination of subfields. Each subfield is composed of a reset period, an address period, and a sustain period as shown in FIG. The reset period serves to erase the wall charges formed by the previous sustain discharge and to set up the wall charges in order to stably perform the next address discharge. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cells.

Next, a conventional driving method of the plasma display panel will be described with reference to FIG. 3.

3 is a driving waveform diagram of a plasma display panel according to the prior art. As shown in Fig. 3, the reset period is composed of an erase period, a ramp rising period and a ramp falling period.

In the erase period, an erase ramp waveform that rises slowly from 0 V toward the V _e voltage is applied to the sustain electrode X. Then, the wall charges formed on the sustain electrode X and the scan electrode Y gradually disappear.

Next, in the ramp rising period, the address electrode A and the sustain electrode X are kept at 0 V, and a ramp waveform gradually rising from the V _s voltage to the V _set voltage is applied to the scan electrode Y. While this ramp waveform is rising, the first weak reset discharge occurs in each of the discharge cells from the scan electrode Y to the address electrode A and the sustain electrode X, respectively. As a result, negative wall charges are accumulated in the scan electrode Y, and positive wall charges are accumulated in the address electrode A and the sustain electrode X at the same time.

Subsequently, in the ramp down period, while the sustain electrode X is maintained at the V _e voltage, a ramp waveform that gently falls toward 0 V at the V _s voltage is applied to the scan electrode Y. While this ramp waveform falls, the second weak reset discharge occurs again in all the discharge cells. As a result, the negative wall charge of the scan electrode Y decreases and the positive wall charge of the sustain electrode X decreases.

When the reset period is normally operated, the wall charges of the scan electrode Y and the sustain electrode X are erased, but an unstable discharge may occur due to an unstable reset operation. In such unstable discharge, when a discharge occurs due to self-erasing during the drop of the V _set voltage of the scan electrode Y after the strong discharge occurs during the ramp up period, the strong discharge occurs during the ramp up period and the ramp down period. In this case, strong discharge may occur during the ramp down period. In this case, in the first case, the reset function is performed according to the magnetic erase.

However, in the second and third cases, positive wall charges are formed on the scan electrode Y and negative wall charges are formed on the sustain electrode X due to the strong discharge in the ramp falling period. At this time, if the wall voltage V _wxy1 formed by the wall charges formed on the scan electrode Y and the sustain electrode X satisfies Equation 1, sustain discharge may occur in the sustain period even though there is no address discharge in the address period. Can be.

Here, V _wxy1 is a wall voltage formed between the scan electrode Y and the sustain electrode X due to the strong discharge in the ramp falling period, and V _s is the scan electrode Y by the sustain pulse applied in the sustain period. And a voltage difference formed between the sustain electrode X and V _f is a discharge start voltage between the scan electrode Y and the sustain electrode X.

As described above, according to the conventional driving method, sustain discharge may occur in a discharge cell that should not be turned on due to the strong discharge in the ramp down period of the reset period.

The technical problem to be achieved by the present invention is to eliminate the erroneous discharge that may occur due to the strong discharge in the reset period.

In order to solve this problem, the present invention erases the charges formed by the unstable reset operation.

According to one aspect of the invention, it comprises a plurality of first and second electrodes formed side by side on the first substrate, and a plurality of third electrodes formed on the second substrate and intersect the first and second electrodes, The present invention provides a method of driving a plasma display panel in which discharge cells are formed by adjacent first, second and third electrodes. This driving method includes a reset step, an auxiliary reset step, an address step and a sustain step.

The auxiliary reset step applies a discharge erase pulse having discharge and erase functions to the discharge cells under a predetermined condition. At this time, the predetermined condition is when abnormal charge is formed in the reset step, and it is preferable that the abnormal charge is discharged and erased by the discharge erase pulse.

The abnormal charge includes first and second charges formed on the first electrode and the second electrode in the reset step, respectively, and the voltage formed by the first and second charges maintains the discharge cells not selected in the address step in the sustain step. The voltage that can be discharged.

According to one embodiment, the erasing step includes applying a first voltage to the first electrode during the first period, and applying a second voltage to the second electrode during the second period. At this time, it is preferable that the first voltage is within a range capable of causing a discharge between the first electrode and the second electrode together with the voltage formed by the first charge and the second charge. The first period is within a range in which charge can be formed in the first electrode and the second electrode by the discharge between the first electrode and the second electrode, and the second voltage in the second period is formed in the first period. It is preferable that it is a voltage which can erase a charge.

In the second period, the second voltage may be a voltage that gradually changes from the third voltage to the fourth voltage. Alternatively, the second voltage may be within a range capable of causing a discharge between the first electrode and the second electrode together with the voltage formed by the discharge between the first electrode and the second electrode in the first period. At this time, it is preferable that the second period is within a range in which charges formed by the discharge between the first electrode and the second electrode can be accumulated below a predetermined amount on the first electrode and the second electrode.

According to another embodiment of the present invention, in the erasing step, the second voltage is applied to the second electrode while the first voltage is applied to the first electrode.

The first voltage may be applied to the first electrode for a predetermined period of time. At this time, it is preferable that the voltage difference between the first voltage and the second voltage is within a range capable of causing a discharge between the first electrode and the second electrode together with the voltage formed by the first charge and the second charge. The predetermined period is preferably within a range in which charges formed by the discharge between the first electrode and the second electrode can be accumulated below a predetermined amount on the first electrode and the second electrode.

Alternatively, the first voltage may be a voltage that gradually changes from the third voltage to the fourth voltage.

A driving method of a plasma display panel according to another aspect of the present invention includes an erasing step that can cause discharge and erasure when a predetermined condition is formed in a reset period.

According to one embodiment of this driving method, the erasing step is a first step of applying a discharge pulse to the discharge cell, which can cause a discharge between the first electrode and the second electrode under a predetermined condition in the reset period, and the first step And a second step of applying an erase pulse to the discharge cell for erasing charges formed in the first electrode and the second electrode by the discharge of.

According to another embodiment of this driving method, the erasing step includes applying an erase pulse to the discharge cell for causing the discharge between the first electrode and the second electrode to erase the charge under a predetermined condition in the reset period. .

At this time, a certain condition is a case where abnormal charge is formed in the reset step.

The abnormal charge includes first and second charges formed on the first electrode and the second electrode in the reset step, and the voltage formed by the first and second charges causes the discharge cells not selected in the address step to be sustained. It is the voltage that can sustain discharge.

According to another feature of the invention, the first substrate, a plurality of first and second electrodes formed side by side on the first substrate, respectively, the second substrate facing the first substrate, the first substrate and the second electrode intersect The present invention provides a plasma display panel including a plurality of third electrodes formed on a second substrate, and a driving circuit for supplying driving signals to discharge cells formed by adjacent first electrodes, second electrodes, and third electrodes. The driving circuit applies a first voltage to the first electrode and a second voltage to the second electrode between the reset period and the address period. Abnormal charges are erased among the charges formed in the reset period by the first voltage and the second voltage.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

A method of driving a plasma display panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

4 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention. 5A through 5D are wall charge distribution diagrams according to the driving waveform of FIG. 4. 6A to 6C are wall charge distribution diagrams when strong discharge occurs during a ramp falling period in the driving waveform of FIG. 4. 7 and 8 are modified examples of the drive waveforms shown in FIG. 4, respectively.

As shown in FIG. 4, the driving waveform according to the first embodiment of the present invention includes a reset period 10, a misfiring erase period 20, an address period 30, and a sustain period 40. Include. The reset period 10 consists of an erase period 11, a ramp rising period 12 and a ramp falling period 13.

The erase period 11 of the reset period 10 is a period for erasing electric charges formed by sustain discharge in the sustain period 40 of the previous subfield. The ramp rising period 12 is a period during which wall charges are formed in the scan electrode Y, the sustain electrode X, and the address electrode A, and the ramp falling period 13 is a wall charge formed in the ramp rise period 12. Is a period for erasing a portion of the to facilitate address discharge.

The erroneous discharge erasing period 20 is a period for forming a charge state so as to normally emit light by assisting the reset period 10, and the scan electrode Y and the sustain electrode formed due to unstable strong discharge in the ramp falling period 13. It is the period of removing the wall charge of (X).

The address period 30 is a period for selecting a discharge cell to cause sustain discharge in the sustain period from among the plurality of discharge cells. The sustain period 40 is a period for sustain discharge of the discharge cells selected in the address period 30 by applying a sustain pulse to the scan electrode Y and the sustain electrode X in order.

In addition, the plasma display panel applies a driving voltage to the scan / hold driving circuit for applying the driving voltage to the scan electrode Y and the sustain electrode Y in each of the periods 10, 20, 30, and 40 and the address electrode A. And an address driving circuit to be applied.

First, a case in which the reset operation normally occurs by the driving waveform according to the first embodiment of the present invention will be described in detail with reference to FIGS. 5A to 5D.

In the sustain period 40 of the previous subfield, negative wall charges accumulate on the scan electrode Y by a sustain discharge between the scan electrode Y and the sustain electrode X, and a positive wall on the sustain electrode X. Electric charges will accumulate. In the erase period 11, a ramp waveform that rises slowly from the reference voltage to the V _e voltage is applied to the sustain electrode X while the scan electrode Y is maintained at the reference voltage. In the first embodiment of the present invention, it is assumed that the reference voltage is 0V. Then, the wall charges formed on the sustain electrode X and the scan electrode Y gradually disappear.

Next, ramp-up period (12) is applied to the ramp waveform gently rising from voltage V _set at V _s voltage to the scan electrode (Y) while maintaining the sustain electrode (X) at the reference voltage state. At this time, the V _s voltage is lower than the discharge start voltage Vf between the scan electrode Y and the sustain electrode X, and the V _set voltage is higher than the discharge start voltage Vf. Then, a weak reset discharge occurs from the scan electrode Y to the address electrode A and the sustain electrode X while the ramp waveform rises. As a result, as shown in Fig. 5A, negative wall charges are accumulated on the scan electrode Y, and positive wall charges are accumulated on the address electrode A and the sustain electrode X at the same time.

In the ramp falling period 13, a ramp waveform that gently falls from the V _s voltage to the reference voltage is applied to the scan electrode Y while the sustain electrode X is maintained at the V _e voltage. While this ramp waveform is falling, again weak discharge discharge occurs in all the discharge cells. As a result, as shown in Fig. 5B, the negative wall charge of the scan electrode Y decreases and the positive wall charge of the sustain electrode X decreases. In addition, the positive wall charge of the address electrode A is adjusted to a value suitable for the address operation.

In the false discharge erase period 20, a square pulse having a voltage V _s is applied to the scan electrode Y while the sustain electrode X is maintained at the reference voltage. At this time, if the charge is normally erased in the ramp falling period 13, the wall voltage formed between the scan electrode Y and the sustain electrode X is negative when the scan electrode Y is referenced (-V _wxy2). ) Then, the voltage between scan electrode Y and sustain electrode X becomes (V _s -V _wxy2 ), which does not exceed the discharge start voltage V _f , and no discharge occurs. Thus, as shown in FIG. 5C, the wall charge distribution in the discharge cell remains the same as in FIG. 5B.

Next, in the false discharge erasing period 20, an erase ramp waveform that gradually rises from the reference voltage to the V _e voltage is applied to the sustain electrode X while the scan electrode Y is maintained at the reference voltage. Since the charge distribution in the scan electrode Y and the sustain electrode X is the same as the previous period and no discharge occurs even with this erase ramp waveform, the wall charge is maintained as in FIG. 5B as shown in FIG. 5D.

In the address period 30, a scan pulse is sequentially applied to the scan electrode Y to select a discharge cell, and among the address electrodes A intersecting the scan electrode Y to which the scan pulse is applied, An address pulse is applied to A). Then, discharge occurs between the scan electrode Y and the address electrode A due to the potential difference formed by the scan pulse and the address pulse. The discharge is generated between the scan electrode Y and the sustain electrode X based on the discharge between the scan electrode Y and the address electrode A to form wall charges in the scan electrode Y and the sustain electrode X. do.

In the sustain period 40, a sustain pulse is applied to the scan electrode Y and the sustain electrode X in order. A sustain pulse is a pulse to the scan electrode (Y) and the sustain electrode (X) to a voltage difference shift voltage V _s and -V _s to the voltage. The voltage V _{s is a} voltage lower than the discharge start voltage between the scan electrode Y and the sustain electrode X. If the wall voltage V _wxy3 is formed between the scan electrode Y and the sustain electrode X by the address discharge in the address period 30, the scan electrode Y is formed by the wall voltage V _wxy3 and V _s voltage. ) And sustain electrode (X).

Next, a case in which strong discharge occurs in the ramp falling period 13 among driving waveforms according to the first embodiment of the present invention will be described in detail with reference to FIGS. 6A to 6C.

When strong discharge occurs in the ramp falling period 13 due to an unstable reset operation, as shown in FIG. 6A, positive charges are accumulated on the scan electrode Y and negative charges are accumulated on the sustain electrode. At this time, the wall voltage V _wxy1 formed by the wall charges formed on the scan electrode Y and the sustain electrode X satisfies Equation 1.

When the voltage V _s is applied to the scan electrode Y and the reference voltage is applied to the sustain electrode X in the erroneous discharge erase period 20, the wall voltage V _wxy1 between the scan electrode Y and the sustain electrode X is _applied. ) And V _s voltage cause the voltage V _wxy1 + V _s between the scan electrode Y and the sustain electrode X to _{exceed the} discharge start voltage V _f . Accordingly, discharge occurs between the scan electrode Y and the sustain electrode X. As shown in FIG. 6B, a large amount of negative charge is accumulated on the scan electrode Y, and a large amount of (+) is applied to the sustain electrode X. ) The charge builds up.

Next, in the second half of the erroneous discharge erasing period 20, an erase ramp waveform is gently applied to the sustain electrode X from the reference voltage to the V _e voltage to thereby perform the erase operation. By the ramp waveform, as shown in Fig. 6C, the wall charges formed in the scan electrode Y and the sustain electrode X are erased, so that the wall voltage between the scan electrode Y and the sustain electrode X is lowered. As a result, the sum of the wall voltage between the scan electrode Y and the sustain electrode X and the V _s voltage applied in the sustain period 30 becomes lower than the discharge start voltage. Therefore, if there is no address discharge in the address period 30, no discharge occurs in the sustain period 40.

In the first embodiment of the present invention, V _s voltage is applied to scan electrode Y and V _e voltage is applied to sustain electrode X in order to simplify the driving circuit. On the other hand, if the discharge condition in the erroneous discharge erase period 20 is satisfied, a voltage different from that applied to the scan electrode Y and the sustain electrode X may be used. In the first embodiment of the present invention, the reference voltage is assumed to be 0 V. Alternatively, the reference voltage may be -V _s / 2. Referring to FIG. 7, the driving voltages applied to the scan electrode Y and the sustain electrode X in each of the periods 10, 20, 30, and 40 are lowered by the voltage V _s / 2. In this way, the voltage level used in the driving circuit is lowered, so that a device with low breakdown voltage can be used in the driving circuit. Alternatively, the voltage used in each of the periods 10, 20, 30, and 40 may be adjusted differently.

In addition, although the erase ramp waveform is applied to the sustain electrode X in the erase period 11 in the first embodiment of the present invention, the erase ramp waveform may be applied to the scan electrode Y. Referring to FIG. 8, a ramp waveform that gently falls from the V _s voltage to the reference voltage is applied to the scan electrode Y while the sustain electrode X is maintained at the V _e voltage. In this way, the voltage difference between the scan electrode Y and the sustain electrode X in the erase period 11 is the voltage between the scan electrode Y and the sustain electrode X in the erase period 11 of FIG. 4. Since it remains the same as the difference, the erase operation is performed similarly to FIG.

In the first embodiment of the present invention, the ramp rising voltage and the ramp falling voltage are applied to the scan electrode Y in the reset period 10. In addition, another reset voltage may be used in which the wall charge distribution as shown in FIG. 5B is formed by the normal reset operation and the wall charge distribution as shown in FIG. 6A is formed by the abnormal reset operation.

These modifications described above can also be applied to embodiments to be described later.

In the first embodiment of the present invention, the discharge voltage and the erase ramp waveform are used in the erroneous discharge erase period 20, but other waveforms may be used. Hereinafter, an embodiment in which a waveform different from the first embodiment of the present invention is used in the error discharge erase period 20 will be described with reference to FIGS. 9 to 13.

9 to 13 are driving waveform diagrams of the plasma display panel according to the second to sixth embodiments, respectively.

9, the driving waveform according to the second embodiment of the present invention is the same as the first embodiment except that the round waveform is used instead of the ramp waveform in the error discharge erase period 20. A rectangular pulse having a voltage V _{s is} applied to the scan electrode Y in the first half of the erroneous discharge erase period 20. A round voltage rising in a curved form from the reference voltage to the voltage V _{e is} applied to the sustain electrode X. Then, when a strong discharge occurs in the ramp falling period 13, discharge occurs by the voltage V _s so that negative and positive charges are accumulated on the scan electrode Y and the sustain electrode X, respectively, and the voltage V _e These charges are erased by the rising round voltage.

Referring to FIG. 10, in the driving waveform according to the third embodiment of the present invention, a spherical pulse is applied to the sustain electrode X and a ramp waveform is applied to the scan electrode Y in the erroneous discharge erasing period 20, unlike the first embodiment. Is applied. If described in detail, having an erroneous discharge reference voltage to the scan electrode (Y) in the first half in a state in the sustain electrode (X) in the sustain voltage V _s in the erase period (20) applies a rectangular pulse. Then, because the voltage difference between the scan electrode (Y) and the sustain electrode (X) maintain the same V _s voltage to the first embodiment, the case in lamps falling period 13 which was a strong discharge, the scan electrode (Y) and the sustain electrode Discharge occurs between (X). In the second half of the erroneous discharge erasing period 20, a ramp waveform that drops from the V _s voltage to the reference voltage is applied to the scan electrode Y while the sustain electrode X is maintained at the V _e voltage. By the ramp waveform, the electric charges formed by the discharge of the scan electrode Y and the sustain electrode X in the first half of the erroneous discharge erase period 20 can be removed. Instead of the ramp waveform, the round waveform described with reference to FIG. 9 may be used.

Next, referring to FIG. 11, the driving waveform according to the fourth embodiment of the present invention is implemented in the first embodiment except that a narrow pulse is applied instead of the erasing ramp voltage in the second half of the erroneous discharge erasing period 20. Same as the example. In detail, a narrow pulse having a V _e voltage is applied to the sustain electrode X while the scan electrode Y is maintained at the reference voltage in the second half of the erroneous discharge erasing period 20.

If there is strong discharge in the ramp falling period 13, a discharge occurs between the scan electrode Y and the sustain electrode X in the first half of the erroneous discharge erasing period 20, so that the wall charge state is as shown in Fig. 6B. At this time, when the reference voltage is applied to the scan electrode Y and the V _e voltage is applied to the sustain electrode X, the wall voltage V _wxy4 and the scan electrode Y and the sustain formed by the wall charge distribution of FIG. 6B are maintained. the discharge occurs between the scan electrode (Y) and the sustain electrode (X) by the voltage difference (V _e) of the electrode (X). However, the width of the V _e voltage pulse applied to the sustain electrode X is short, so that the charges formed by the discharge are erased without accumulating on the scan electrode Y and the sustain electrode X, resulting in a wall charge state as shown in FIG. 6C.

In the fourth embodiment of the present invention, the same modifications as in the third embodiment can be applied. That is, a rectangular pulse that changes from V _e voltage to a reference voltage is applied to the sustain electrode X while the scan electrode Y is maintained at the V _s voltage in the first half of the erroneous discharge erasing period 20. Next, in the second half of the erroneous discharge erasing period 20, a narrow pulse that changes from the V _s voltage to the reference voltage is applied to the scan electrode Y while the sustain electrode X is maintained at the V _e voltage.

In the first to fourth embodiments of the present invention, the electric charges formed by the discharge are erased after the discharge is caused in the erroneous discharge erasing period. In contrast, in the fifth and sixth embodiments, waveforms capable of simultaneously discharging and erasing in the erroneous discharge erasing period are used.

12, in the fifth embodiment of the present invention, only a narrow pulse is applied to the scan electrode Y in the erroneous discharge erase period 20. FIG. In detail, a narrow pulse having a voltage V _s is applied to the scan electrode Y while the sustain electrode X is maintained at the reference voltage in the misdischarge erase period 20. In the case where the strong discharge occurs during the ramp falling period 13 and the charge state is as shown in FIG. 6A, the voltage difference V _s between the scan electrode Y and the sustain electrode X, the scan electrode Y, and the sustain electrode ( The discharge occurs between the scan electrode Y and the sustain electrode X by the wall voltage V _wxy1 between X. However, since the width of the pulse applied to the scan electrode Y is short, the charges generated by the discharge are erased without accumulating on the scan electrode Y and the sustain electrode X.

Referring to FIG. 13, in the sixth embodiment of the present invention, only the ramp waveform is applied to the scan electrode Y in the erroneous discharge erase period 20. That is, the holding ramp waveform gently rising from voltage V _s from the reference voltage to the scan electrode (Y) in a holding state the electrode (X) at the reference voltage is applied. Then, when charges are formed in the scan electrode Y and the sustain electrode X, as shown in FIG. 6A, a weak discharge occurs between the scan electrode Y and the sustain electrode X to erase the charges.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, when a strong discharge occurs in the reset period due to an unstable reset operation, a large amount of charges are formed in the scan electrode and the sustain electrode, these charges can be erased. Therefore, sustain discharge can be prevented from occurring in the discharge cells that are not selected.

1 is a schematic partial perspective view of a plasma display panel.

2 is an arrangement diagram of electrodes of a plasma display panel.

3 is a driving waveform diagram of a plasma display panel according to the prior art.

4 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

5A to 5D are wall charge distributions according to the driving waveforms of FIG. 4, respectively.

6A to 6C are wall charge distribution diagrams when an unstable reset operation occurs in the driving waveform of FIG. 4, respectively.

7 and 8 are modified examples of the drive waveforms shown in FIG. 4, respectively.

9 to 13 are driving waveform diagrams of the plasma display panel according to the second to sixth embodiments, respectively.

Claims (40)

A plurality of first electrodes and second electrodes, and a plurality of third electrodes crossing the first and second electrodes, wherein discharge cells are formed by the adjacent first, second and third electrodes. In the method for driving a plasma display panel, A reset step of setting the discharge cells to be addressable; An auxiliary reset step of assisting the reset step by applying a pulse to the discharge cell; An address step of selecting a discharge cell to be selected among the discharge cells, and A sustain step of sustaining and discharging the selected discharge cells Method of driving a plasma display panel comprising a. The method of claim 1, And the auxiliary reset step applies a discharge erase pulse having discharge and erase functions to the discharge cells under a predetermined condition. The method of claim 2, The predetermined condition is when abnormal charge is formed in the reset step. And the abnormal charge formed in the reset step is discharged and erased by the discharge erase pulse. The method of claim 3, The abnormal charge includes first and second charges respectively formed on the first electrode and the second electrode in the reset step, And the voltage formed by the first and second charges is a voltage that allows discharge cells not selected in the address step to be sustained discharged in the sustain step. The method of claim 4, wherein The auxiliary resetting may include applying a first voltage to the first electrode for a first period, and applying a second voltage to the second electrode for a second period. The method of claim 5, And the first voltage is within a range capable of causing a discharge between the first electrode and the second electrode together with the voltage formed by the first charge and the second charge. The method of claim 6, And the first voltage is the same level as the voltage applied to the first electrode for discharging in the sustain step. The method of claim 6, The first period is within a range in which electric charges can be formed on the first electrode and the second electrode by discharge between the first electrode and the second electrode, And the second voltage in the second period is a voltage capable of erasing charges formed in the first period. The method of claim 8, And in the second period, the second voltage is a voltage that gradually changes from a third voltage to a fourth voltage. The method of claim 8, The second voltage is within a range capable of causing a discharge between the first electrode and the second electrode together with the voltage formed by the discharge between the first electrode and the second electrode in the first period, And wherein the second period is within a range in which charges formed by discharge between the first electrode and the second electrode can be accumulated below a predetermined amount on the first electrode and the second electrode. The method of claim 4, wherein And a second voltage is applied to the second electrode while the first voltage is applied to the first electrode in the erasing step. The method of claim 11, The first voltage is applied to the first electrode for a predetermined period of time, The voltage difference between the first voltage and the second voltage is within a range capable of causing a discharge between the first electrode and the second electrode together with the voltage formed by the first charge and the second charge, And the predetermined period is within a range in which electric charges formed by the discharge between the first electrode and the second electrode can be accumulated in the first electrode and the second electrode at a predetermined amount or less. The method of claim 10 or 12, And wherein the predetermined amount is within a range such that the unselected discharge cells do not cause sustain discharge in the sustain period. The method of claim 12, And the first voltage is a voltage at the same level as a voltage applied to the first electrode for discharge in a sustain period. The method of claim 11, And the first voltage is a voltage gradually changing from a third voltage to a fourth voltage. A plurality of first electrodes and second electrodes, and a plurality of third electrodes crossing the first and second electrodes, wherein discharge cells are formed by the adjacent first, second and third electrodes. In the method for driving a plasma display panel, An erasing step that can cause discharge and erasure when a predetermined condition is formed in the reset period, The erasing step, A first step of applying a discharge pulse to the discharge cell capable of causing a discharge between the first electrode and the second electrode under the predetermined condition in the reset period, and A second step of applying an erase pulse to the discharge cell for erasing charges formed in the first electrode and the second electrode by the discharge of the first step Method of driving a plasma display panel comprising a. The method of claim 16, The predetermined condition is a case where an abnormal charge is formed in the reset step. The method of claim 17, The abnormal charge includes first and second charges respectively formed on the first electrode and the second electrode in the reset period, And the voltage formed by the first and second charges is a voltage that allows discharge cells not selected in the address period to be sustained discharged in the sustain period. The method of claim 18, In the first step, the discharge pulse having the first voltage is applied to the first electrode while the second electrode is maintained at the first voltage. The voltage difference between the first voltage and the second voltage is within a range capable of causing a discharge between the first electrode and the second electrode together with the voltage formed by the first charge and the second charge. . The method of claim 19, In the second step, the erase pulse which gradually rises from the fourth voltage to the fifth voltage is applied to the second electrode while the first electrode is maintained at the third voltage. The voltage difference between the fifth voltage and the third voltage is between the first electrode and the second electrode together with the voltage formed by the charges formed in the first electrode and the second electrode when the discharge occurs in the first step. A method of driving a plasma display panel that is within a range that can cause a discharge of the. The method of claim 19, In the second step, the erase pulse which is gradually lowered from the fourth voltage to the fifth voltage is applied to the second electrode while the first electrode is maintained at the third voltage. The voltage difference between the third voltage and the fifth voltage is between the first electrode and the second electrode together with the voltage formed by the charges formed in the first electrode and the second electrode when the discharge occurs in the first step. A method of driving a plasma display panel that is within a range that can cause a discharge of the. The method of claim 19, In the second step, the erase pulse having the fourth voltage is applied to the second electrode for a predetermined period while the first electrode is maintained at the third voltage. The voltage difference between the fourth voltage and the third voltage is between the first electrode and the second electrode together with the voltage formed by the charge formed in the first electrode and the second electrode when the discharge occurs in the first step. Is within the range to cause the discharge of And the predetermined period is within a range such that charges formed by the discharge between the first electrode and the second electrode are accumulated in the first electrode and the second electrode at a predetermined amount or less. The method of claim 22, The predetermined amount may be equal to a voltage level applied to the first electrode and the second electrode in the sustain period, respectively, when the first electrode and the second electrode are respectively applied to the first electrode and the second electrode. A method of driving a plasma display panel that is within a range in which discharge does not occur between electrodes. A plurality of first electrodes and second electrodes, and a plurality of third electrodes crossing the first and second electrodes, wherein discharge cells are formed by the adjacent first, second and third electrodes. In the method for driving a plasma display panel, An erasing step that can cause discharge and erasure when a predetermined condition is formed in the reset period, And the erasing step includes applying an erase pulse to the discharge cell to cause a discharge between the first electrode and the second electrode to erase an electric charge under the predetermined condition. The method of claim 24, The predetermined condition is a case where an abnormal charge is formed in the reset step. The method of claim 25, The abnormal charge includes first and second charges respectively formed on the first electrode and the second electrode in the reset period, And the voltage formed by the first and second charges is a voltage that allows discharge cells not selected in the address period to be sustained discharged in the sustain period. The method of claim 26, In the state where the second electrode is maintained at the first voltage, the erase pulse having the second voltage for a predetermined period of time is applied to the first electrode, The voltage difference between the second voltage and the first voltage is within a range capable of causing a discharge between the first electrode and the second electrode together with the voltage formed by the first charge and the second charge, And the predetermined period is within a range such that electric charges formed by the discharge between the first electrode and the second electrode are accumulated below the predetermined amount on the first electrode and the second electrode. The method of claim 27, The predetermined amount is equal to the voltage level applied to the first electrode and the second electrode in the sustain period, respectively, when the voltage is applied to the first electrode and the second electrode, respectively. A method of driving a plasma display panel that is within a range in which discharge does not occur between two electrodes. The method of claim 26, And the erase pulse which is gradually changed from a second voltage to a third voltage is applied to the first electrode while the second electrode is maintained at the first voltage. The method of claim 29, The voltage difference between the third voltage and the first voltage is within a range capable of causing a discharge between the first electrode and the second electrode together with the voltage formed by the first charge and the second charge. Way. A plurality of first and second electrodes formed side by side, A plurality of third electrodes formed to intersect the first and second electrodes, and A driving circuit for supplying driving signals to discharge cells formed by the adjacent first, second and third electrodes, The driving circuit applies a first voltage to the first electrode and a second voltage to the second electrode between a reset period and an address period. And an abnormal charge is erased among the charges formed in the reset period by the first voltage and the second voltage. The method of claim 31, wherein And wherein the abnormal charge is formed on the first electrode and the second electrode, respectively, and includes first and second electric charges so that a discharge can occur in a sustain period even when not selected in the address period. 33. The method of claim 32, The driving circuit applies the second voltage to the second electrode for a second period after applying the first voltage to the first electrode for a first period, In the case where the first and second charges are formed during the reset period, a discharge occurs between the first electrode and the second electrode by the first voltage during the first period, and the second period during the second period. And the electric charges formed by the discharge in the first period are erased by the voltage. The method of claim 33, wherein During the first period, the driving circuit applies the first voltage to the first electrode while maintaining the second electrode at a third voltage, And a voltage difference between the first voltage and the third voltage is within a range capable of causing a discharge between the first electrode and the second electrode together with the voltages formed by the first and second charges. The method of claim 34, wherein During the second period, the driving circuit applies the second voltage to the second electrode while maintaining the first electrode at a fourth voltage, The second voltage is a voltage gradually changing from the fifth voltage to the sixth voltage, The voltage difference between the sixth voltage and the fourth voltage is a range capable of causing a discharge between the first electrode and the second electrode together with the charge formed by the discharge between the first electrode and the second electrode in the first period. Plasma display panel. The method of claim 34, wherein During the second period, the driving circuit applies the second voltage to the second electrode while maintaining the first electrode at a fourth voltage, The voltage difference between the second voltage and the fourth voltage is a range capable of causing a discharge between the first electrode and the second electrode together with the charge formed by the discharge between the first electrode and the second electrode in the first period. Within And wherein the second period is within a range such that charges formed by the discharge between the first electrode and the second electrode are accumulated in the first electrode and the second electrode at a predetermined amount or less. 33. The method of claim 32, The driving circuit applies the first voltage to the first electrode while applying the second voltage to the second electrode, and the first and second charges are erased by the first voltage and the second voltage. Plasma display panel. The method of claim 37, The driving circuit applies the first voltage for a predetermined period, The voltage difference between the first voltage and the second voltage is within a range capable of causing a discharge between the first electrode and the second electrode together with the voltage formed by the first charge and the second charge, And wherein the predetermined period is within a range such that charges formed by the discharge between the first electrode and the second electrode are accumulated in the first electrode and the second electrode at a predetermined amount or less. The method of claim 36 or 38, The predetermined amount may be equal to a voltage level applied to the first electrode and the second electrode in the sustain period, respectively, when the first electrode and the second electrode are respectively applied to the first electrode and the second electrode. A plasma display panel within a range in which discharge does not occur between electrodes. The method of claim 37, The second voltage is a voltage gradually changing from the third voltage to the fourth voltage, And a voltage difference between the fourth voltage and the first voltage is within a range capable of causing a discharge between the first electrode and the second electrode together with the voltage formed by the first charge and the second charge.