KR100603416B1 - Method of driving plasma display panel - Google Patents

Abstract

An object of the present invention is to correct a difference in the discharge start voltage of an address discharge due to the characteristics of a panel, and to uniformly perform the address discharge and the sustain discharge in the entire panel.

In order to achieve the above object, the present invention includes a scan electrode and a sustain electrode extending in one direction, and an address electrode extending to intersect the scan and sustain electrodes, the discharge cell in the cross region For the plasma display panel in which the image is defined, a unit frame representing an image is divided into a plurality of subfields having different gradation weights, each subfield having a reset period in which all the discharge cells are initialized and the discharge cells to be turned on are selected. A driving method of a plasma display panel in which a driving signal is applied to each of the electrodes by being divided into an address period and a sustain period in which a sustain discharge is performed in a selected discharge cell.

The scan electrodes and sustain electrodes are divided into a plurality of blocks from the top to the bottom of the panel. In the reset period, rising pulses and falling pulses are applied to the scan electrodes of all blocks in the top and bottom blocks of the panel. In a block except for the uppermost and lowermost blocks, the falling pulse width of the falling pulses is larger.

Description

Method of driving plasma display panel {Method of driving plasma display panel}

1 is a diagram schematically illustrating an electrode arrangement of a three-electrode plasma display panel.

FIG. 2 is a timing diagram illustrating driving signals for driving a three-electrode plasma display panel having the electrode arrangement shown in FIG. 1.

FIG. 3 is a block diagram illustrating the blocking of the scan electrodes and the sustain electrodes in order to apply the driving method of the present invention.

4 is a timing diagram showing a driving signal according to an embodiment of the driving method of the present invention.

5 is a timing diagram illustrating in detail the reset period of FIG. 4.

6 is a timing diagram showing a driving signal according to another embodiment of the driving method of the present invention.

FIG. 7 is a timing diagram illustrating the address period of FIG. 6 in detail.

Explanation of symbols on the main parts of the drawings

Y1, ..., Yn ... scanning electrodes

X1, ..., Xn ... holding electrodes

A1, ..., Am ... address electrodes

Vs ... first voltage Vset ... second voltage

Vset + Vs ... Third Voltage Vnf ... Fourth Voltage

B1, B2, B3 ... first, second and third blocks

FB1, FB2, FB3 ... Falling width of falling pulses of the first, second and third blocks

Pb1, Pb2, Pb3 ... first, second and third block address periods

Pf1, Pf2 ... first and second block falling pulse application period

The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel in which address discharge is performed for each block by dividing the scan electrodes into a plurality of blocks.

 In recent years, plasma display panels, which are attracting attention as large-sized flat panel display devices, have a discharge voltage applied after the discharge gas is filled between two substrates on which a plurality of electrodes are formed. Phosphor formed in the pattern of is excited to obtain a desired image.

1 is a diagram schematically illustrating an electrode arrangement of a three-electrode plasma display panel. Referring to the drawings, the scan electrodes Y1, ..., Yn and the sustain electrodes X1, ..., Xn are arranged in parallel in parallel, and the address electrodes A1, ..., Am Is arranged to intersect the scan electrodes Y1, ..., Yn and the sustain electrodes X1, ..., Xn, and the intersecting area divides the discharge cell Ce.

FIG. 2 is a timing diagram showing a conventional driving signal for driving a three-electrode plasma display panel having the electrode arrangement shown in FIG. 1.

One subfield SF is divided into a reset period PR, an address period PA, and a sustain period PS, and a plurality of subfields are gathered to form a frame for representing an image. In the reset period PR, a reset pulse consisting of a rising pulse and a falling pulse is applied to the scan electrodes Y1,..., And Yn so as to perform a reset discharge for initializing all discharge cells. In the address period PA, Scan pulses are sequentially applied to the scan electrodes Y1, ..., Yn so as to perform an address discharge for selecting a discharge cell to be turned on among all the discharge cells, and the address electrodes A1, ..., The address pulse is applied to Am in accordance with the scan pulse, and in the sustain period PS, the sustain pulse is applied to the scan electrodes Y1,..., Yn and the sustain electrodes X1, so that sustain discharge is performed in the selected discharge cell. ..., Xn).

On the other hand, the discharge start voltage of the address discharge is measured at approximately 293V at the center of the panel, and at 263V at the upper and lower sides of the panel due to the characteristics of the panel. This is believed to be due to unevenness in the panel manufacturing process. Therefore, when the same drive signal is applied to the entire panel, the discharge start voltage is different, which causes a problem that the address discharge starts later in the center of the panel.

In addition, as the size of the panel increases and the number of scan electrodes increases, the number of scan electrodes increases. As a result, when the address discharge is sequentially performed from the top to the bottom of the panel, the reset discharge increases from the top to the bottom of the panel. The period from later to address discharge becomes longer. In addition, the longer the period from the top of the panel to the lower direction, the longer the period from the address discharge to the sustain discharge. As described above, since the period from the reset discharge to the address discharge and the period from the address discharge to the sustain discharge are different according to the upper and lower portions of the panel, there is a problem that the uniform discharge is not performed because the discharge conditions of the entire panel are uneven. .

SUMMARY OF THE INVENTION The present invention has been made to solve a number of problems, including the above-mentioned problems, and to correct the difference in the discharge start voltage of the address discharge due to the characteristics of the panel and to uniformly perform the address discharge and the sustain discharge in the entire panel. It is an object to provide a driving method.

In order to achieve the above object and various other objects, the present invention includes scan electrodes and sustain electrodes extending in one direction, and address electrodes extending to intersect the scan electrodes and sustain electrodes. For a plasma display panel in which discharge cells are defined in an intersecting area, a unit frame representing an image is divided into a plurality of subfields having different gradation weights, each subfield being turned on during a reset period in which all discharge cells are initialized. A driving method of a plasma display panel in which a driving signal is applied to each of the electrodes divided into an address period in which a discharge cell to be selected is selected and a sustain period in which a sustain discharge is performed in the selected discharge cell.

The scan electrodes and sustain electrodes are divided into a plurality of blocks from the top to the bottom of the panel. In the reset period, rising pulses and falling pulses are applied to the scan electrodes of all blocks in the top and bottom blocks of the panel. In a block except for the uppermost and lowermost blocks, the falling pulse width of the falling pulses is larger.

According to this other feature of the present invention, the rising pulse can be raised step by step.

According to another aspect of the present invention, the address period includes a block-specific falling pulse applying period between the block-by-block address period and the block-by-block address period where block-by-block address discharge is performed,

In the block-by-block address period, the scan high voltage for each block may be applied to the scan electrodes, and the scan low voltage for each block may be sequentially applied.

According to another aspect of the present invention, it is preferable that a bias voltage for each block is applied to the sustain electrodes during the block-by-block address period and the block-falling pulse application period.

According to another aspect of the present invention, the method for driving a plasma display panel, characterized in that the bias voltage for each block is reduced by block.

According to another aspect of the present invention, it is preferable that an address pulse is applied to the address electrodes in accordance with the scanlow voltage for each block.

According to another aspect of the present invention, the falling pulses for each block fall in stages, but in blocks except for the top and bottom blocks than the top and bottom blocks of the panel, the falling width of the falling pulses may be larger.

According to another aspect of the present invention, in the sustain period, the sustain pulse can be alternately applied to the scan electrodes and the sustain electrodes.

According to another aspect of the present invention, the rising pulse rises from the first voltage to the second voltage to finally reach the third voltage, and the falling pulse falls from the first voltage to finally reach the fourth voltage, and is maintained. The pulse may alternately have a first voltage and a ground voltage.

The present invention also provides a recording medium having recorded thereon a program for executing the above method of driving the plasma display panel on a computer in order to achieve the above object.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

The plasma display panel to which the driving method of the present invention is applied generally includes a front substrate and a rear substrate, and between the front substrate and the rear substrate, address electrodes, dielectric layers, scan electrodes, sustain electrodes, and phosphor layers. , A partition and a magnesium monoxide (MgO) protective layer are provided. According to the partition structure and the arrangement of the electrodes, plasma display panels having various structures may be manufactured. Hereinafter, sustain electrodes and scan electrodes are disposed on a front substrate, address electrodes are disposed on a rear substrate, and A plasma display panel having a matrix form is described. Of course, the structure of the plasma display panel to which the driving method of the present invention is applied is not limited to that described below.

 The address electrodes are formed in a predetermined pattern on the front side of the back substrate. The back dielectric layer is applied to the front of the address electrodes. In front of the rear dielectric layer, barrier ribs are formed in a direction parallel to the address electrodes. These partitions partition the discharge area of each discharge cell and serve to prevent optical interference between the discharge cells. The phosphor layer is applied in front of the rear dielectric layer on the address electrodes between the partition walls, and a red light emitting phosphor layer, a green light emitting phosphor layer, and a blue light emitting phosphor layer are sequentially disposed.

The sustain electrodes and the scan electrodes are formed in a predetermined pattern on the back of the front substrate so as to be orthogonal to the address electrodes. Each intersection sets a corresponding discharge cell. Each sustain electrode and each scan electrode may be formed by combining a transparent electrode made of a transparent conductive material such as indium tin oxide (ITO) and a metal electrode (bus electrode) for increasing conductivity. The front dielectric layer is formed by coating the entire surface behind the sustain electrodes and the scan electrodes. A protective layer for protecting the panel from a strong electric field, for example, a magnesium monoxide (MgO) layer is formed by applying the entire surface to the back of the front dielectric layer. The plasma forming gas is sealed in the discharge space.

FIG. 3 is a diagram illustrating blocking scan electrodes and sustain electrodes into three blocks in order to apply the driving method of the present invention.

One feature of the driving method of the present invention is to block a plurality of scan electrodes and sustain electrodes of the panel, and to block the block into three blocks as shown in FIG. 3, and various other modifications are possible.

 Referring to the drawings, the scan electrodes Y1, ..., Yn and the sustain electrodes X1, ..., Xn of the panel are divided into three blocks. That is, it is divided into a first block B1, a second block B2, and a third block B3.

4 is a timing diagram showing a driving signal according to an embodiment of the driving method of the present invention. 5 is a timing diagram illustrating in detail the reset period of FIG. 4.

In order to represent an image, a unit frame is divided into a plurality of subfields, and each subfield is divided into a reset period, an address period, and a sustain period. For example, if a unit frame is divided into eight subfields for gray scale display and 256 gray scales are expressed, gray scale weights of the first to eighth subfields are 1,2,4,8,16,32, respectively. It can be assigned as 64,128, which can be variously determined according to design specifications.

Referring to FIGS. 4 and 5, one subfield SF is divided into a reset period PR, an address period PA, and a sustain period PS.

In the reset period PR, a discharge which is an area where the scan electrodes Y1, ..., Yn and the sustain electrodes X1, ..., Xn and the address electrodes A1, ..., Am cross each other. In order to initialize the cell, a reset discharge is performed. A reset pulse consisting of a rising pulse and a falling pulse is applied to the scan electrodes Y1, ..., Yn, and a positive bias voltage is applied to the sustain electrodes X1, ..., Xn when the falling lamp pulse is applied. Vb1 is applied, and a ground voltage Vg is applied to the address electrodes A1, ..., Am.

The rising pulse rises from the first positive voltage Vs by the second voltage Vset and finally reaches the third voltage Vset + Vs, and the falling pulse falls from the positive first voltage Vs and finally. Reaches the fourth voltage Vnf. Due to the application of the rising pulse, negative wall charges are accumulated in the vicinity of the scan electrodes in the discharge cells, and positive wall charges are accumulated in the vicinity of the sustain electrodes and the address electrodes, and weak discharge is performed. In addition, due to the application of the falling pulse, the wall charges accumulated near the scan electrode, the sustain electrode, and the address electrode are erased so that a weak discharge is performed in the discharge cell, and a small amount of wall charge is applied to each electrode to facilitate the address discharge. Stack up.

The present invention is characterized in that the rising pulse and the falling pulse are applied in stages so as to be more efficient in stacking or erasing wall charges in the discharge cell. In the case of applying a rising pulse that rises in stages, wall charges are stably accumulated in comparison with rising pulses that continuously rise by repeating rising and floating, and discharge is more stably generated to prevent mis-discharge. In addition, in the case of applying a falling pulse falling in stages, the wall charges are stably erased gradually by repeatedly falling and floating, and discharges are more stably generated, thereby preventing the occurrence of false discharges. However, as the number of falling pulses falling in steps increases, the reset period is increased, which causes a problem that the address period following the reset period is shortened.

On the other hand, due to the characteristics of the panel, the discharge start voltage of the upper part (first block) and the lower part (third block) of the panel is 263V, and the discharge start voltage of the center part (second block) of the panel is 293V, so that the center part (second block) of the panel is Higher discharge start voltage is observed.

In order to simultaneously overcome the above-mentioned reset pulse rising or falling and the discharge start voltage at the center of the panel is greater than the discharge start voltages at the other top and bottom, the driving method of the present invention is provided with the scan electrodes and sustain electrodes. Divide into multiple blocks. In the drawing, for convenience, divided into three blocks, the scan electrodes of the first block are Y11, ..., Y1a, the scan electrodes of the second block are Y21, ..., Y2b, and the scan electrodes of the third block are Y31. , ..., Y3c. In addition, the driving method of the present invention applies a falling pulse that falls in stages to all the scan electrodes Y1,..., And Yn regardless of the block, but the scan electrodes Y21,..., Y2b of the second block. The falling width F _B2 of the falling pulse is applied to the other blocks, that is, the scanning electrodes Y11, ..., Y1a of the first block and the scanning electrodes Y31-Y3c of the third block. The main feature is to make it larger than the falling width (F _B1 , F _B3 ) of the falling pulse.

Since the falling width F _B2 of the falling pulse applied to the second block becomes large, discharges generated while the negative wall charges accumulated near the scan electrodes of the second block start to erase are discharged to the first block and the third block. It becomes larger than this, and also the application time of the falling pulse is shortened, and it is possible to reach the fourth voltage Vnf more quickly, and more negative polarity near the scan electrode of the second block at the end of the reset period PR. Wall charges will accumulate more. Therefore, it is possible to compensate that the discharge start voltage of the second block is higher than the discharge start voltage of the first block and the third block in the address period PA.

Meanwhile, as an example, the falling width F _B2 of the falling pulse applied to the second block is larger than the falling widths F _B1 and F _B3 of the falling pulse applied to the first block and the third block. Only the first falling width of the falling pulse applied to the block may be larger than the first falling width of the falling pulse applied to the first block and the third block.

In the address period PA, an address discharge for selecting a discharge cell to be turned on among all the discharge cells is performed. The driving method of the present invention is to compensate for the longer period between reset discharge and address discharge from the top of the panel to the bottom, and the longer period between address discharge and sustain discharge from the bottom of the panel to the top. In addition, address discharge for each block is performed. That is, the address period PA includes the first block address period Pb1, the first block falling pulse applying period Pf1, the second block address period Pb2, the second block falling pulse applying period Pf2, and the first block address period Pb1. It is divided into three block address periods Pb3. Accordingly, the address discharge is performed in the scan electrodes Y11, ..., Y1a belonging to the first block during the first block address period Pb1, and the scan electrodes Y21, ..., belonging to the second block are performed. Y2b) performs address discharge during the second block address period Pb2, and scan electrodes Y31, ..., Y3c belonging to the third block perform address discharge during the third block address period Pb3. . The first block falling pulse re-initializes the discharge cells to smoothly perform address discharge of the scan electrodes Y21,..., Y2b belonging to the second block in the second block address period Pb2. The second block falling pulse re-initializes the discharge cells to smoothly perform address discharge of the scan electrodes Y31 and... Y3c belonging to the third block in the third block address period Pb3.

In detail, the first block scan high voltage Vsch1 is applied to the scan electrodes Y1,..., And Yn during the first block address period Pb1, and the second block address period Pb2 is applied to the scan electrodes Y1,. The block scan high voltage Vsch2 is applied, and the third block scan high voltage Vsch3 is applied during the third block address period Pb3. In order to perform address discharge during the first block address period Pb1, the first block scanlow voltage Vscl1 is sequentially applied to the scan electrodes Y11,..., Y1a belonging to the first block. In order to perform address discharge during the second block address period Pb2, the second block scanlow voltage Vscl2 is sequentially applied to the scan electrodes Y21,..., Y2b belonging to the second block. In order to perform address discharge during the third block address period Pb3, the third block scanlow voltage Vscl3 is sequentially applied to the scan electrodes Y31,..., Y3c belonging to the third block.

Block bias voltages are applied to sustain electrodes X1, ..., Xn during the block-by-block address period and the block-falling pulse application period. That is, the first block bias voltage Vb1 is applied in the first block address period Pb1 and the first block falling pulse applying period Pf1, and the second block address period Pb2 and the second block falling pulse applying period are applied. The second block bias voltage Vb2 is applied to Pf2, and the third block bias voltage Vb3 is applied to the third block address period Pb3. The bias voltage per block becomes smaller per block. That is, the magnitude of the first block bias voltage Vb1 is the largest and the magnitude of the third block bias voltage Vb3 is the smallest.

An address pulse having an address voltage Va is applied to the address electrodes A1, ..., Am in accordance with the scan-low voltages Vscl1, Vscl2, and Vscl3 for each block.

The following describes the state of wall charges in the discharge cells during the address period. First, when the first block scan high voltage Vsch1 is applied to the scan electrodes Y1 and... Yn during the first block address period Pb1, the first block scan high voltage Vsch1 is located near the scan electrode. ), Negative wall charges are accumulated. At this time, the first block scan low voltage Vscl1 lower than the first block scan high voltage Vsch1 is applied to the scan electrodes Y11,..., Y1a belonging to the first block, and the address electrodes A1,. When an address pulse is applied to ... Am), address discharge is performed between the scan electrode and the address electrode. Due to the address discharge, positive wall charges are accumulated near the scan electrodes belonging to the first block, and negative wall charges are accumulated near the sustain electrodes. Since the address discharge is not performed on the scan electrodes Y21 to Y2b and Y31 to Y3C belonging to the second block and the third block except the first block, positive wall charges continue to accumulate in the vicinity of the scan electrode.

During the first block falling pulse period Pf1, the scan electrodes Y1,..., And Yn descend from the first block scanlow voltage Vscl1 and finally reach the second block scanlow voltage Vscl2. When the first block falling pulse is applied, positive wall charges are accumulated in the vicinity of the scan electrodes of the first block where the address discharge is performed, and negative charges accumulated near the scan electrodes of the second and third blocks in which the address discharge is not performed. The wall charge of polarity is erased.

During the second block address period Pb2, the second block scan high voltage Vsch2 is applied to the scan electrodes Y1, ... Yn, and then the scan electrodes Y21, ..., Y2b belonging to the second block. When the second block scan low voltage Vscl2 lower than the second block scan high voltage Vsch2 is applied, and an address pulse is applied to the address electrodes A1, ..., Am, the scan electrode and the address electrode Address discharge is performed in between. Although the discharge start voltage in the second block is observed to be 293V, which is 30V higher than the discharge start voltage of the first block and the third block, which is 263V, the fall period of the falling pulse that already falls gradually in the reset period is increased, so that the reset period Since more negative wall charges are accumulated in the vicinity of the scan electrodes, the address discharge can be performed smoothly. Due to the address discharge, positive wall charges are accumulated near the scan electrodes belonging to the second block, and negative wall charges are accumulated near the sustain electrodes. Positive wall charges are accumulated near the scan electrodes of the first block, and address discharges are not performed on the scan electrodes Y31, ..., Y3c belonging to the third block, so that negative wall charges are generated near the scan electrodes. Will accumulate.

 During the second block falling pulse period Pf2, the scan electrodes Y1,..., And Yn descend from the second block scanlow voltage Vscl2 and finally reach the third block scanlow voltage Vscl3. When the second block falling pulse is applied, positive wall charges are further accumulated near the scan electrodes of the first and second blocks where the address discharge is performed, and accumulated near the scan electrodes of the third block where the address discharge is not performed. The negative wall charges are erased.

During the third block address period Pb3, the third block scan high voltage Vsch3 is applied to the scan electrodes Y1,..., And Yn, and the scan electrodes Y31,..., Y3c belonging to the third block. When the third block scan low voltage Vscl3 lower than the third block scan high voltage Vsch3 is applied, and an address pulse is applied to the address electrodes A1, ..., Am, the scan electrode and the address electrode Address discharge is performed in between. Due to the address discharge, positive wall charges are accumulated in the vicinity of the scan electrodes belonging to the third block, and negative wall charges are accumulated in the vicinity of the sustain electrodes.

As a result, positive wall charges are accumulated near the scan electrodes of each block immediately before the sustain period PS, and negative wall charges are accumulated near the sustain electrodes.

By setting block-specific falling pulse application periods Pf1 and Pf2 between block-by-block address periods Pb1, Pb2, and Pb3 so as to perform address discharge on a block-by-block basis, the discharge cells are reset for each block immediately before the block-by-block address discharge. The imbalance in address discharge from the top to the bottom of can be eliminated.

In the sustain period PS, sustain pulses are alternately applied to the scan electrodes Y1, ..., Yn and the sustain electrodes X1, ..., Xn. The sustain pulse alternately has the first voltage Vs and the ground voltage Vg, and an application time of the sustain pulse is determined according to the gray scale weight.

When the first voltage Vs is applied to the scan electrode, the first voltage Vs applied to the scan electrode, the ground voltage Vg applied to the sustain electrode, the positive wall charge accumulated near the scan electrode, The sustain discharge is performed by the negative wall charges accumulated near the sustain electrode, the negative wall charges accumulate near the scan electrodes, and the positive wall charges accumulate near the sustain electrodes.

When the first voltage Vs is applied to the sustain electrode, the first voltage Vs applied to the sustain electrode, the ground voltage Vg applied to the scan electrode, the positive wall charge accumulated near the sustain electrode, The sustain discharge is performed by the negative wall charges accumulated near the scan electrodes, the negative wall charges are accumulated near the sustain electrodes, and the positive wall charges are accumulated near the scan electrodes. Since the sustain pulse has an application period determined according to the gray scale weight, the sustain voltage is continuously performed while the first voltage Vs is alternately applied to the scan electrode and the sustain electrode according to the gray scale weight.

On the other hand, due to the address periods Pb1, Pb2 and Pb3 of each block of the address period PA and the application periods Pf1 and Pf2 of the falling pulses of each block, the discharge cells from the top to the bottom of the panel are uniform at the end of the address period. One wall charge state can be established, so that uniform sustain discharge can be performed even during sustain discharge of the sustain period PS.

6 is a timing diagram showing a driving signal according to an embodiment of the driving method of the present invention. FIG. 7 is a timing diagram illustrating the address period of FIG. 6 in detail.

4 to 7, the driving signals applied to the electrodes in the reset period PR are as shown in FIGS. 4 and 5. In summary, once all of the scan electrodes Y1, ..., Yn are applied with a rising pulse that rises in steps and a falling pulse that falls in steps, in particular, the scan electrodes Y21,. In the Y2b), the falling widths F _B1 and F _B3 of the falling pulses of the scan electrodes Y11 to Y1a, Y31 to Y3c of the first and third blocks having different falling widths F _B2 are different. Greater than that. After the reset period PR ends, more negative wall charges are accumulated in the vicinity of the scan electrode of the second block.

In the address period PA, as shown in the driving signals shown in FIGS. 4 and 5, a block-specific falling pulse applying period Pf1, Pf2 is provided between the address periods Pb1, Pb2, and Pb3 for each block, so that address discharge is generated in the entire panel. To be performed uniformly. In addition, a uniform wall charge state is formed after the address discharge so that the sustain discharge is evenly performed. This is similar to the driving signals shown in FIGS. 4 and 5, but the difference is that in FIG. 5 and FIG. 7, the falling pulses that fall in steps are applied to the falling pulse applying periods Pf1 and Pf2 for each block. The falling pulse is divided into a falling period and a floating period, and in the drawing, falling widths of falling pulses of the first block and the third block having different falling widths F _{B2 of} the second block F _B1 , F _B3 ) is larger than the main feature. Due to the falling pulse applied to the second block having a larger falling width, more negative wall charges are accumulated in the vicinity of the scan electrodes of the first block and the third block than the scan electrodes of the second block. As a result, it is possible to compensate that the discharge start voltage in the second block is higher than the discharge start voltages of the first block and the third block.

In the sustain period PS, a sustain pulse is alternately applied to all the scan electrodes Y1, ..., Yn and the sustain electrodes X1, ..., Xn regardless of the block. The sustain discharge is performed only in the discharge cells selected in the address period PA, and the sustain discharge is not performed in the discharge cells not selected. The sustain pulse has the first voltage Vs and the ground voltage Vg alternately, and an application time of the sustain pulse is determined according to the gray scale weight.

When the first voltage Vs is applied to the scan electrode, the first voltage Vs applied to the scan electrode, the ground voltage Vg applied to the sustain electrode, the positive wall charge accumulated near the scan electrode, The sustain discharge is performed by the negative wall charges accumulated near the sustain electrode, the negative wall charges accumulate near the scan electrodes, and the positive wall charges accumulate near the sustain electrodes.

When the first voltage Vs is applied to the sustain electrode, the first voltage Vs applied to the sustain electrode, the ground voltage Vg applied to the scan electrode, the positive wall charge accumulated near the sustain electrode, The sustain discharge is performed by the negative wall charges accumulated near the scan electrodes, the negative wall charges are accumulated near the sustain electrodes, and the positive wall charges are accumulated near the scan electrodes. Since the sustain pulse is determined by the gray scale weight, the first voltage Vs is alternately applied to the scan electrode and the sustain electrode according to the gray weight so that the sustain discharge is continuously performed.

On the other hand, due to the address periods Pb1, Pb2 and Pb3 of each block of the address period PA and the application periods Pf1 and Pf2 of the falling pulses of each block, the discharge from the upper part to the lower part of the panel at the end of the address period PA. Since a uniform wall charge state may be formed in the cell, a uniform sustain discharge may be performed even during a sustain discharge of the sustain period PS.

Meanwhile, the method of driving the plasma display panel according to the present invention described above may be embodied as computer readable codes on a computer readable recording medium. Computer-readable recording media include any type of recording device that stores programs or data that can be read by a computer system. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, hard disk, floppy disk, flash memory, optical data storage, and the like. Here, the program stored in the recording medium refers to a series of instruction instructions used directly or indirectly in an apparatus having an information processing capability such as a computer to obtain a specific result. Thus, the term computer is used to mean all devices having information processing capability to perform a specific function by a program including a memory, an input / output device, and an arithmetic device regardless of the actual name. Even in the case of a device for driving a panel, its use is limited to a specific field of panel driving, and in reality, it is a kind of computer.

In particular, the driving method of the plasma display panel of the present invention to apply a rising pulse, a falling pulse and a falling pulse for each block in stages, and to vary the falling width of the falling pulse for each block, is a schematic or ultra-fast integration on a computer. It may be written by a circuit hardware description language (VHDL) or the like, and may be implemented by an integrated circuit programmable to a computer, for example, a field programmable gate array (FPGA). The recording medium includes such a programmable integrated circuit.

According to the present invention as described above, the following effects can be obtained.

First, in the case of applying the reset pulse generated by the rising pulse and the falling pulse, in particular, by applying the falling width of the falling pulse for each block, the discharge start occurs uniformly by compensating for the difference in the address discharge start voltage in the address period. You can do that.

Second, by setting a block-falling pulse application period for initializing the discharge cells between the block-by-block address period and the block-by-block address period to perform the address discharge block by block, between the reset discharge in the reset period and the address discharge in the address period. The uniform address discharge and sustain discharge are compensated by compensating that the resting period of the panel increases from the top of the panel to the bottom of the panel and that the resting period between the address discharge in the address period and the sustain discharge in the sustain period increases from the panel to the top. Can be performed.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (10)

An image is displayed for a plasma display panel including scan electrodes and sustain electrodes extending in one direction, and address electrodes extending to intersect the scan electrodes and sustain electrodes, and discharge cells defined in the crossing regions. The unit frame to be expressed is divided into a plurality of subfields having different gradation weights, and each subfield has a reset period in which all discharge cells are initialized, an address period in which discharge cells to be turned on are selected, and a sustain discharge in a selected discharge cell. A driving method of a plasma display panel in which a driving signal is applied to each of the electrodes divided by a sustain period, The scan electrodes and the sustain electrodes are divided into a plurality of blocks from the top to the bottom of the panel, and a rising pulse and a falling pulse falling in steps are applied to the scan electrodes of all blocks during the reset period. And a falling width of the falling pulse is greater in the blocks except for the top and bottom blocks than in the top and bottom blocks of the panel. The method of claim 1, wherein the rising pulse, A method of driving a plasma display panel, characterized by rising in steps. The method of claim 1, The address period has a block-by-block falling pulse application period between the block-by-block address period where block-by-block address discharge is performed and the block-by-block address period, In the block-by-block address period, a scan high voltage for each block is applied to the scan electrodes, and a scan low voltage for each block is sequentially applied. The method of claim 3, And a bias voltage for each block is applied to the sustain electrodes during the address period for each block and the falling pulse application period for each block. The method of claim 4, wherein And the bias voltage for each block decreases for each block. The method of claim 5, And an address pulse is applied to the address electrodes in accordance with the scanlow voltage of each block. The method of claim 3, wherein the falling pulse for each block, A falling method of driving a plasma display panel, wherein the falling pulse has a larger falling width in blocks except for the top and bottom blocks than the top and bottom blocks of the panel. The method of claim 1, And a sustain pulse is alternately applied to the scan electrodes and the sustain electrodes in the sustain period. The method of claim 8, The rising pulse rises from the first voltage by the second voltage to finally reach the third voltage, and the falling pulse falls from the first voltage to finally reach the fourth voltage, and the sustain pulse reaches the first voltage. And a voltage and ground voltage alternately. A recording medium having recorded thereon a program for executing the method of claim 9 on a computer.

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