KR20090050309A - Plasma display apparatus - Google Patents

Abstract

The present invention relates to a driving apparatus for supplying a driving signal to a plasma display panel and a plasma display apparatus using the same. In the first subfield of a plurality of subfields constituting one frame, a sustain signal is not supplied and a scan is performed. The first voltage is supplied to the scan electrode during the erase period after the address period in which the scan signal is supplied to the electrode, and the signal gradually falling from the second voltage to the third voltage is supplied to the sustain electrode.

According to the present invention, when driving the plasma display panel, it is possible to improve the low gradation power of the image by configuring a subfield to which the sustain signal is not supplied. In addition, by discharging the wall charges due to the address discharge by supplying a signal that gradually descends to the sustain electrode in the subfield for low gradation, the discharge cell initialization can be effectively performed, thereby reducing mis-discharge of the plasma display device. You can.

Plasma Display Panel, Discharge Cell Initialization, Low Gradation

Description

Plasma display apparatus

The present invention relates to a plasma display device, and more particularly, to a method of driving a plasma display panel.

The plasma display panel (hereinafter referred to as PDP) displays an image by excitation and emitting phosphors by vacuum ultraviolet rays (VUV) generated when the inert gas is discharged.

Such a PDP is not only large in size and thin in thickness, but also has a simple structure and is easy to manufacture, and has a high luminance and high luminous efficiency compared to other flat display devices. In particular, the AC surface-discharge type 3-electrode plasma display panel has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge to protect the electrodes from sputtering caused by the discharge.

The plasma display panel is time-division driven by a reset period for initializing all cells, an address period for selecting cells, and a sustain period for causing display discharge in the selected cells in order to realize gray levels of an image. do.

If all the electrodes are not initialized to the wall charge state for addressing during the reset period, there may be a phenomenon in which no discharge or discharge occurs in the address period, thereby degrading the image quality of the display image.

SUMMARY In order to solve the above problems in the panel driving apparatus provided in the plasma display apparatus, a plasma display apparatus capable of stably driving the panel by effectively discharging the discharge cells before addressing is provided. The purpose is to provide.

According to an aspect of the present invention, there is provided a plasma display apparatus including: a plasma display panel including a plurality of scan electrodes and sustain electrodes formed on an upper substrate, and a plurality of address electrodes formed on a lower substrate; And a driving unit supplying a driving signal to the plurality of electrodes, wherein a sustain signal is not supplied in a first subfield among a plurality of subfields constituting one frame, and a scan signal is supplied to the scan electrode. A first voltage is supplied to the scan electrode during the erase period after the address period, and a signal gradually decreasing from the second voltage to the third voltage is supplied to the sustain electrode.

According to the present invention, it is possible to improve the low gradation expression power of an image by configuring a subfield to which the sustain signal is not supplied. In addition, by discharging the wall charges due to the address discharge by supplying a signal gradually falling to the sustain electrode in the subfield for low gradation, the discharge cell initialization can be effectively performed, and thus, the mis-discharge of the plasma display device is prevented. Can be reduced.

Hereinafter, a plasma display device according to the present invention will be described in detail with reference to the accompanying drawings. 1 is a perspective view illustrating an embodiment of a structure of a plasma display panel.

As shown in FIG. 1, the plasma display panel includes a scan electrode 11, a sustain electrode 12, a sustain electrode pair formed on the upper substrate 10, and an address electrode 22 formed on the lower substrate 20. It includes.

The sustain electrode pairs 11 and 12 generally include transparent electrodes 11a and 12a and bus electrodes 11b and 12b formed of indium tin oxide (ITO), and the bus electrodes 11b and 12b. 12b) may be formed of a metal such as silver (Ag) or chromium (Cr) or a stack of chromium / copper / chromium (Cr / Cu / Cr) or a stack of chromium / aluminum / chromium (Cr / Al / Cr). . The bus electrodes 11b and 12b are formed on the transparent electrodes 11a and 12a to serve to reduce voltage drop caused by the transparent electrodes 11a and 12a having high resistance.

Meanwhile, according to the exemplary embodiment of the present invention, the sustain electrode pairs 11 and 12 may not only have a structure in which the transparent electrodes 11a 12a and the bus electrodes 11b and 12b are stacked, but also the buses without the transparent electrodes 11a and 12a. Only the electrodes 11b and 12b may be configured. This structure does not use the transparent electrodes (11a, 12a), there is an advantage that can lower the cost of manufacturing the panel. The bus electrodes 11b and 12b used in this structure may be various materials such as photosensitive materials in addition to the materials listed above.

Light between the scan electrodes 11 and the sustain electrodes 12 between the transparent electrodes 11a and 12a and the bus electrodes 11b and 11c to absorb external light generated outside the upper substrate 10 to reduce reflection. A black matrix (BM, 15) is arranged that functions to block and to improve the purity and contrast of the upper substrate 10.

The black matrix 15 according to the exemplary embodiment of the present invention is formed on the upper substrate 10, the first black matrix 15 and the transparent electrodes 11a and 12a formed at positions overlapping the partition wall 21. And the second black matrices 11c and 12c formed between the bus electrodes 11b and 12b. Here, the first black matrix 15 and the second black matrices 11c and 12c, also referred to as black layers or black electrode layers, may be simultaneously formed and physically connected in the formation process, or may not be simultaneously formed and thus not physically connected. .

In addition, when physically connected and formed, the first black matrix 15 and the second black matrix 11c and 12c may be formed of the same material, but may be formed of different materials when they are formed separately.

The upper dielectric layer 13 and the passivation layer 14 are stacked on the upper substrate 10 having the scan electrode 11 and the sustain electrode 12 side by side. Charged particles generated by the discharge are accumulated in the upper dielectric layer 13, and the protective electrode pairs 11 and 12 may be protected. The protective film 14 protects the upper dielectric layer 13 from sputtering of charged particles generated during gas discharge, and increases emission efficiency of secondary electrons.

In addition, the address electrode 22 is formed in a direction crossing the scan electrode 11 and the sustain electrode 12. In addition, a lower dielectric layer 24 and a partition wall 21 are formed on the lower substrate 20 on which the address electrode 22 is formed.

In addition, the phosphor layer 23 is formed on the surfaces of the lower dielectric layer 24 and the partition wall 21. The partition wall 21 has a vertical partition wall 21a and a horizontal partition wall 21b formed in a closed shape, and physically distinguishes discharge cells, and prevents ultraviolet rays and visible light generated by the discharge from leaking into adjacent discharge cells.

In an embodiment of the present invention, not only the structure of the partition wall 21 illustrated in FIG. 1, but also the structure of the partition wall 21 having various shapes may be possible. For example, a channel in which a channel usable as an exhaust passage is formed in at least one of the differential partition structure, the vertical partition 21a, or the horizontal partition 21b having different heights of the vertical partition 21a and the horizontal partition 21b. A grooved partition structure having a groove formed in at least one of the type partition wall structure, the vertical partition wall 21a, or the horizontal partition wall 21b may be possible.

Here, in the case of the differential partition wall structure, the height of the horizontal partition wall 21b is more preferable, and in the case of the channel partition wall structure or the groove partition wall structure, it is preferable that a channel is formed or the groove is formed in the horizontal partition wall 21b. something to do.

Meanwhile, in one embodiment of the present invention, although the R, G and B discharge cells are shown and described as being arranged on the same line, it may be arranged in other shapes. For example, a Delta type arrangement in which R, G, and B discharge cells are arranged in a triangular shape may be possible. In addition, the shape of the discharge cell may be not only rectangular, but also various polygonal shapes such as a pentagon and a hexagon.

In addition, the phosphor layer 23 emits light by ultraviolet rays generated during gas discharge to generate visible light of any one of red (R), green (G), and blue (B). Here, an inert mixed gas such as He + Xe, Ne + Xe and He + Ne + Xe for discharging is injected into the discharge space provided between the upper / lower substrates 10 and 20 and the partition wall 21.

FIG. 2 illustrates an embodiment of an electrode arrangement of a plasma display panel, and a plurality of discharge cells constituting the plasma display panel are preferably arranged in a matrix form as shown in FIG. 2. The plurality of discharge cells are provided at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn, respectively. The scan electrode lines Y1 to Ym may be driven sequentially or simultaneously, and the sustain electrode lines Z1 to Zm may be driven simultaneously. The address electrode lines X1 to Xn may be driven by being divided into odd-numbered lines and even-numbered lines, or sequentially driven.

Since the electrode arrangement shown in FIG. 2 is only an embodiment of the electrode arrangement of the plasma panel according to the present invention, the present invention is not limited to the electrode arrangement and driving method of the plasma display panel shown in FIG. 2. For example, a dual scan method in which two scan electrode lines among the scan electrode lines Y1 to Ym are simultaneously scanned is possible. In addition, the address electrode lines X1 to Xn may be driven by being divided up and down in the center portion of the panel.

3 is a timing diagram illustrating an embodiment of a time division driving method by dividing a frame into a plurality of subfields. The unit frame may be divided into a predetermined number, for example, eight subfields SF1, ..., SF8 to realize time division gray scale display. Each subfield SF1, ... SF8 is divided into a reset section (not shown), an address section A1, ..., A8 and a sustain section S1, ..., S8.

Here, according to an embodiment of the present invention, the reset period may be omitted in at least one of the plurality of subfields. For example, the reset period may exist only in the first subfield or may exist only in a subfield about halfway between the first subfield and all the subfields.

In each address section A1, ..., A8, a display data signal is applied to the address electrode X, and scan pulses corresponding to each scan electrode Y are sequentially applied.

In each of the sustain periods S1, ..., S8, a sustain pulse is alternately applied to the scan electrode Y and the sustain electrode Z to form wall charges in the address periods A1, ..., A8. Sustain discharge occurs in the discharge cells.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge periods S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gradations, each subfield in turn has different sustains at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128. The number of pulses can be assigned. In order to obtain luminance of 133 gradations, cells may be sustained by addressing the cells during the subfield 1 section, the subfield 3 section, and the subfield 8 section.

The number of sustain discharges allocated to each subfield may be variably determined according to weights of the subfields according to the APC (Automatic Power Control) step. That is, in FIG. 3, a case in which one frame is divided into eight subfields has been described as an example. However, the present invention is not limited thereto, and the number of subfields forming one frame may be variously modified according to design specifications. Do. For example, a plasma display panel may be driven by dividing one frame into eight or more subfields, such as 12 or 16 subfields.

The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34.

4 is a timing diagram illustrating an embodiment of driving signals for driving a plasma display panel with respect to the divided subfield.

The subfield is a wall formed by a pre-reset section and a pre-reset section for forming positive wall charges on the scan electrodes Y and negative wall charges on the sustain electrodes Z. A reset section for initializing the discharge cells of the entire screen using the charge distribution, an address section for selecting the discharge cells, and a sustain section for maintaining the discharge of the selected discharge cells.

The reset section includes a setup section and a setdown section. In the setup section, rising ramp waveforms (Ramp-up) are simultaneously applied to all scan electrodes to generate fine discharges in all discharge cells. Thus, wall charges are generated. In the set-down period, a falling ramp waveform (Ramp-down) falling at a positive voltage lower than the peak voltage of the rising ramp waveform (Ramp-up) is simultaneously applied to all scan electrodes (Y), thereby erasing discharge in all discharge cells. Is generated, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges.

In the address period, the negative scan signal scan is sequentially applied to the scan electrode, and at the same time, the data signal data having the positive voltage Va is applied to the address electrode X. The address discharge is generated by the voltage difference between the scan signal and the data signal and the wall voltage generated during the reset period, thereby selecting the cell. Meanwhile, a signal for maintaining a sustain voltage is applied to the sustain electrode during the set down period and the address period.

In the sustain period, a sustain pulse having a sustain voltage Vs is alternately applied to the scan electrode and the sustain electrode to generate sustain discharge in the form of surface discharge between the scan electrode and the sustain electrode.

The driving waveforms shown in FIG. 4 are exemplary embodiments of signals for driving the plasma display panel according to the present invention, and the present invention is not limited to the waveforms shown in FIG. 4. For example, the pre-reset period may be omitted, and the polarity and the voltage level of the driving signals illustrated in FIG. 4 may be changed as necessary. After the sustain discharge is completed, an erase signal for erasing wall charge may be applied to the sustain electrode. May be authorized. In addition, the single sustain driving may be performed by applying the sustain signal to only one of the scan electrode (Y) and the sustain (Z) electrode to generate a sustain discharge.

5 through 10 illustrate timing diagrams of embodiments of waveforms of a panel driving signal according to the present invention.

In the at least one subfield (hereinafter, referred to as the half-gradation subfield) of the plurality of subfields constituting one frame, no sustain signal is supplied and no sustain discharge is generated, and only a scan signal and a data signal are supplied. Only address discharge can occur.

As described above, by using the half-gradation subfield in which only the address discharge occurs, it is possible to express a low level of the gray scale smaller than the gray scales that can be represented by the sustain discharge. That is, assuming that the gray scales that can be represented by the sustain discharges are 0, 1, 2, ..., 255, the decimal point gray scales between 0 and 1 can be expressed by using the half-gray subfield in which only the address discharges occur. have.

5 is a timing diagram illustrating an embodiment of a driving signal waveform supplied from the half gray subfield.

Referring to FIG. 5, the reset signal is supplied to the scan electrode Y during the reset period to initialize the discharge cells, and the data signal and the scan signal are supplied to the address electrode X and the scan electrode Y, respectively, during the address period. Address discharge occurs. In order to stabilize the initialization discharge and the address discharge, the bias voltage Vzb may be supplied to the sustain electrode Z during the set down period and the address period during which the voltage gradually decreases during the reset period.

In addition, in the plasma display device according to the present invention, the half gray subfield preferably includes an erasing section for erasing wall charges formed in the electrodes by address discharge to initialize the discharge cells.

Referring to FIG. 5, during the erase period after the address period of the half gray subfield, the voltage V3 may be supplied to the scan electrode Y and the signal that gradually decreases to the sustain electrode Z.

As described above, the voltage V3 is supplied to the scan electrode Y and the voltage supplied to the sustain electrode Z is gradually decreased to thereby utilize the discharge between the scan electrode Y and the sustain electrode Z. The discharge cell can be initialized effectively.

More specifically, by including the erase period as shown in FIG. 5 in the half gray subfield, the discharge between the scan electrode Y and the address electrode X is prevented while the scan electrode Y and the sustain electrode Z are prevented. It is possible to generate a discharge therebetween, thereby reducing the occurrence of bright spot false discharge.

 The voltage V3 supplied to the scan electrode Y during the erase period may be a positive voltage. In addition, the voltage V3 may be a sustain voltage Vs or a reset to increase the ease of driving circuit configuration and discharge efficiency. The falling slope of the voltage supplied to the sustain electrode Z during the erase period may be the same as the first rising voltage V1 of the signal, and the falling slope of the reset signal supplied to the scan electrode Z during the setdown period of the reset period. May be the same as

In order to prevent the strong discharge between the scan electrode (Y) and the sustain electrode (Z) in the erase period, the voltage V3 supplied to the scan electrode (Y) during the erase period is applied to the sustain electrode (Z). It may be equal to the voltage V4 that is initially supplied. In addition, the voltage V4 supplied to the sustain electrode Z at the start of the erase period may be the same as the bias voltage Vzb supplied to the sustain electrode Z, and at the end of the erase period The voltage supplied to the electrode Z may be a ground voltage GND.

Further, in order to reduce the occurrence of the discharge between the scan electrode Y and the address electrode X or the sustain electrode Z and the address electrode X, the voltage supplied to the scan electrode Y during the erase period ( It is preferable that the voltage V4 supplied to the sustain electrode Z at the beginning of V3) and the erase period is lower than the maximum voltage Vst of the reset signal.

The reset signal waveform of the half gray subfield shown in FIG. 5 is only an embodiment of the present invention. Accordingly, the reset signal of the half-gradation subfield may not include a setup section that gradually rises in addition to the waveform shown in FIG. 5, and various waveforms for initializing discharge cells may be applied.

Referring to FIG. 6, a pre-reset signal gradually decreasing to the negative voltage during the pre-reset period before the reset period may be supplied to the scan electrode Y.

The positive bias voltage Vzb may be supplied to the sustain electrode Z during the preset period.

In addition, in the rising period S1 of the reset signal, the voltage supplied to the sustain electrode Z may gradually fall from the bias voltage Vzb. As shown in FIG. 6, the voltage supplied to the sustain electrode Z is gradually lowered to generate a weak discharge between the scan electrode Y and the sustain electrode Z, thereby stabilizing the initialization discharge and simultaneously resetting it. The panel driving margin can be secured by reducing the length of the section.

To facilitate the construction of the driving circuit and to prevent the occurrence of strong discharge, the falling slope of the voltage supplied to the sustain electrode Z during the erase period, the falling slope and the free fall of the reset signal supplied to the scan electrode Z during the setdown period during the reset period. The falling slopes of the preset signals supplied to the scan electrodes Z during the reset period may be the same.

As shown in FIG. 7, the rising section s1 of the reset signal may include the first rising section s11 that rapidly rises up to the first rising voltage V1, and the holding section s12 that holds the first rising voltage V1. ) And a second rising period s13 gradually rising to the highest voltage V2.

The voltage supplied to the sustain electrode Z may maintain the bias voltage Vzb during the pre-reset period, and may gradually decrease during the sustain period s12 of the reset signal. Thereafter, the bias voltage Vzb may be supplied to the sustain electrode Z at the start of the set-down period s3 of the reset signal.

8 is a timing diagram illustrating another embodiment of a drive signal waveform according to the present invention.

Referring to FIG. 8, a bias voltage supplied to the sustain electrode Z during the set down period s3 may have a value of 2 or more.

For example, at the start of the set-down period s3, a high bias voltage Vzb1 is supplied to the sustain electrode Z, and after a predetermined time elapses, a bias voltage Vzb2 lower than the Vzb1 is sustained. Can be supplied to.

In the set-down period s3 of the reset period, as the signal gradually descending to the negative voltage is supplied to the scan electrode Y, the unnecessary charge of the wall charges formed on the scan electrode Y is erased in the setup period.

More specifically, during the set-down period s3, a signal gradually falling to the scan electrode Y is supplied and a positive bias voltage is supplied to the sustain electrode Z, so that a weak discharge is generated between the electrodes. The discharge causes unwanted wall charges to be erased.

When the discharge in the setdown period s3 is unstable, unnecessary wall charges may not be sufficiently erased, and thus, bright spot discharge and address false discharge may occur.

In addition, deterioration of the MgO protective layer or the phosphor layer may occur according to the long-term use of the panel, and accordingly, discharge characteristics such as surface discharge and counter discharge of the panel may change. Accordingly, as the service life of the panel becomes longer, the likelihood of occurrence of the bright spot or the discharge of the address may be further increased.

As shown in FIG. 8, the weak discharge between the scan electrode Y and the sustain electrode Z may be stabilized by supplying the high bias voltage Vzb1 to the sustain electrode Z at the start of the set-down period s3. Therefore, the bright spot misfiring and the address misfiring can be effectively controlled.

However, when the high bias voltage Vzb1 is supplied in the whole set-down period s3, the bright spot misdischarge may occur in the set-down period s3 due to excessive discharge.

That is, the discharge may be excessively generated in the set-down period s3, and the bright spot discharge may occur, and the likelihood of the bright spot discharge may be further increased by the change in the discharge characteristics as the service life of the panel becomes longer.

Therefore, as shown in FIG. 8, after a predetermined time after the start of the set-down period s3, a discharge amount generated in the second half of the set-down period s3 by supplying a bias voltage Vzb2 lower than Vzb1 to the sustain electrode Z. It is possible to adjust, thereby preventing the occurrence of bright spot mis-discharge due to changes in the discharge characteristics.

The high bias voltage Vzb1 supplied to the sustain electrode Z for ease of driving circuit configuration and discharge stabilization in the set-down period s3 may be a voltage having the same or similar voltage level as the sustain voltage Vs. The low bias voltage Vzb2 supplied thereafter may be lower than the sustain voltage Vs to prevent occurrence of bright point mis-discharge.

In addition, the bias voltages Vzb1 and Vzb2 supplied to the sustain electrode Z are lower than the maximum voltage V2 of the reset signal, and the high bias voltage Vzb1 supplied to the sustain electrode Z is set-down period s3. The low bias voltage Vzb2, which is equal to the start voltage V1 and is supplied to the sustain electrode Z, may be lower than the start voltage V1 of the set-down period s3.

In order to maintain the voltage difference between the scan electrode (Y) and the sustain electrode (Z) at a predetermined voltage or more during the set-down period (s3), and to eliminate unnecessary charges by the surface discharge between the two electrodes, it is supplied to the sustain electrode (Z). The bias voltages Vzb1 and Vzb2 may be greater than the scan bias voltage supplied to the scan electrode Y in the address period, and more preferably, greater than the absolute value of the scan voltage Vsc.

In this case, the voltage V3 supplied to the scan electrode Y during the erase period and the voltage supplied to the sustain electrode Z at the start of the erase period in order to promote the ease of the driving circuit configuration and the stability of the initialization discharge ( V4) is greater than the low bias voltage Vzb2 and may have the same value as the high bias voltage Vzb1.

Referring to FIG. 9, the setdown period s3 includes first and second setdown periods s31 and s33 in which the voltage gradually decreases, and a predetermined voltage is provided between the first and second setdown periods s31 and s33. It may include a holding section (s32) for holding.

The ground voltage GND is supplied to the sustain electrode Z during the first set-down period s31, the high bias voltage Vzb2 is supplied at the sustain period s32, and the low bias voltage is supplied during the second set-down period s32. (Vzb2) can be supplied.

At this time, the bias voltages Vzb1 and Vzb2 supplied to the sustain electrode Z are applied to the scan electrode Y in the sustain period s32 in order to stably generate a discharge in the set-down period s3 to erase the unnecessary charges. It may be greater than the voltage supplied.

FIG. 10 illustrates another embodiment of a drive signal waveform according to the present invention, and illustrates a drive signal waveform supplied from a first subfield and a second subfield among a plurality of subfields constituting one frame.

Referring to FIG. 10, the first subfield is a half gray level subfield to which a sustain signal is not supplied, and the sustain signals are alternately supplied to the scan electrode X and the sustain electrode Z in the second subfield.

As described above, in the first subfield, which is the half-gradation subfield, the positive voltage V3 is supplied to the scan electrode X during the erasing period, and the signal gradually descending is supplied to the sustain electrode Z.

It is preferable that the width w1 of the pulse supplied to the scan electrode X during the erase period of the first subfield is greater than the width w2 of the sustain signal supplied to the scan electrode X during the sustain period of the second subfield. In addition, in order to stably perform the initialization after the address discharge of the half gray subfield, the width w1 of the pulse supplied to the scan electrode X during the erasing period of the first subfield is equal to the width w2 of the sustain signal of the second subfield. 3 times or more).

When the widths of the plurality of sustain signals supplied in the second subfield are different from each other, the width w1 of the pulse supplied to the scan electrode X during the erase period of the first subfield is the maximum width of the sustain signal supplied in the second subfield. Larger is preferred.

In addition, the time when the high bias voltage Vzb1 is supplied to the sustain electrode Z in the setdown period s3 of the first subfield is the high bias voltage Vzb1 to the sustain electrode Z in the setdown period s3 of the second subfield. ) May be shorter than the time it is supplied.

For example, as shown in FIG. 10, in the first subfield, a high bias voltage Vzb1 is supplied to the sustain electrode Z during the sustain period s32 of the setdown period s3, and in the second subfield, the setdown period ( A high bias voltage Vzb1 may be supplied to the sustain electrode Z during the first setdown period s31 and the sustain period s32 of s3.

As described above, by adjusting the time for which the high bias voltage Vzb1 is supplied to the sustain electrode Z, the occurrence of bright point discharge in the first subfield, which is a half gray subfield, can be reduced.

In addition, a pre-reset period may be included before the reset period of the first and second subfields, and a pre-reset signal falling to the negative voltage during the pre-reset period may be supplied to the scan electrode (X).

As shown in FIG. 10, in the second subfield, the first pre-reset signal gradually falling from the positive voltage to the ground voltage GND during the pre-reset period, and gradually falling from the ground voltage GND to the negative voltage. The second preset signal may be sequentially supplied to the scan electrode X.

Although not shown in FIG. 10, sustain signals may be supplied in the third and subsequent subfields.

Although a preferred embodiment of the present invention has been described in detail above, those skilled in the art to which the present invention pertains can make various changes without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made to the branches. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

1 is a perspective view illustrating an embodiment of a structure of a plasma display panel.

2 is a cross-sectional view illustrating an embodiment of an electrode arrangement of a plasma display panel.

FIG. 3 is a timing diagram illustrating an embodiment of a method of time-divisionally driving a plasma display panel by dividing one frame into a plurality of subfields.

4 is a timing diagram illustrating an embodiment of driving signals for driving a plasma display panel.

5 to 10 are timing diagrams showing embodiments of waveforms of a panel driving signal according to the present invention.

Claims (20)

A plasma display panel including a plurality of scan electrodes and sustain electrodes formed on an upper substrate, and a plurality of address electrodes formed on a lower substrate; And a driving unit supplying a driving signal to the plurality of electrodes. In the first subfield of the plurality of subfields constituting one frame, The sustain signal is not supplied, and the first voltage is supplied to the scan electrode during the erase period after the address period in which the scan signal is supplied to the scan electrode, and the sustain electrode has a signal that gradually decreases from the second voltage to the third voltage. The plasma display device, characterized in that supplied. The method of claim 1, And at least one of the first and second voltages is substantially the same as the sustain voltage. The method of claim 1, And the second voltage is substantially equal to the first voltage. The method of claim 1, And the first and second voltages are higher than the scan bias voltages supplied to the scan electrodes during the address period. The method of claim 1, And a length of the erase period is greater than a width of a sustain signal supplied from a second subfield among the plurality of subfields. The method of claim 1, The reset signal supplied to the scan electrode may include a rising period that rises from a fourth voltage to a sixth voltage, wherein the rising period includes a first rising period and a fifth voltage rising from the fourth voltage to a fifth voltage. And a second rising section that rises with a slope smaller than the first rising section to the sixth voltage. The method of claim 6, And at least one of the first and second voltages is substantially the same as the fifth voltage. The method of claim 6, The first and second voltages are lower than the sixth voltage. The method of claim 6, And the third voltage is substantially equal to the fourth voltage. The method of claim 6, And a voltage supplied to the sustain electrode gradually decreases from a seventh voltage to an eighth voltage during a sustain falling period in which at least a portion overlaps with the rising period. The method of claim 10, The reset signal may include a first sustain period that maintains the fifth voltage between the first and second rising periods, and the sustain falling period overlaps the first sustain period. The method of claim 10, And a start time point of the sustain falling section is after an end point of the first rising section. The method of claim 10, And the seventh voltage is substantially the same as the first and second voltages. The method of claim 10, And the eighth voltage is substantially the same as the third voltage. The method of claim 10, And the falling slope of the voltage supplied to the sustain electrode during the erase period is substantially the same as the falling slope of the voltage supplied to the sustain electrode during the sustain falling period. The method of claim 10, Before the reset signal is supplied to the scan electrode is supplied a pre-reset signal that gradually decreases to a negative voltage, And the seventh voltage is supplied to the sustain electrode while the pre-reset signal is supplied. The method of claim 6, And a bias voltage supplied to the sustain electrode after the rising period of the reset signal has a value of 2 or more. The method of claim 17, And a first bias voltage and a second bias voltage lower than the first bias voltage are sequentially supplied to the sustain electrode after the rising period of the reset signal. The method of claim 18, And the second bias voltage is supplied to the sustain electrode during the address period. The method of claim 18, At least one of the first and second voltages is substantially the same as the first bias voltage.

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