KR100837660B1 - Plasma display device - Google Patents

Abstract

A plasma display apparatus is provided to enhance reliability without a bright defect by applying an offset signal with a positive polarity to increase gradually after supplying a reset signal to a plasma display panel. A plasma display apparatus includes a plasma display panel and drivers. The plasma display panel includes discharge cells at sections where scan and sustain electrodes cross each other. The drivers apply a reset signal for initializing the discharge cells to the scan electrodes during a reset period. During at least one reset period of plural sub-fields, first and second reset signals including a ramp-up signal to increase gradually and a ramp-down signal to decrease gradually respectively are applied to the scan electrodes. An offset signal to increase gradually is applied between the first and second reset signals.

Description

Plasma Display Device

1 is a perspective view showing an embodiment of a plasma display panel according to the present invention.

2 is a diagram illustrating an embodiment of an electrode arrangement of a plasma display panel.

3 is a timing diagram illustrating an embodiment of a time division driving method by dividing a frame into a plurality of subfields.

4 is a timing diagram illustrating a first embodiment of driving signals for driving a plasma display panel for one divided subfield.

FIG. 5 is a timing diagram illustrating a second embodiment of driving signals for driving a plasma display panel for one divided subfield.

FIG. 6 is a timing diagram illustrating a third embodiment of driving signals for driving a plasma display panel for one divided subfield.

FIG. 7 illustrates an embodiment of a scan driving circuit for applying the reset signal shown in FIGS. 4 and 6 to the scan electrode;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, and more particularly, to a plasma display device having a driver for applying a reset signal to a plasma display panel to initialize a plurality of discharge cells. .

BACKGROUND ART In general, a plasma display panel is an apparatus that displays an image by applying a predetermined voltage to electrodes provided in a discharge space and causing a discharge, and the plasma generated during gas discharge excites a phosphor.

Such a plasma display panel is not only large in size and thin in thickness, but also has a simple structure, which makes the plasma display panel easier to manufacture and has a higher luminance and higher luminous efficiency than other flat panel display devices.

The plasma display panel is time-divisionally driven into a reset section for initializing all the discharge cells, an address section for selecting a cell in which discharge is to be generated, and a sustain section for generating sustain discharge in the selected cell. .

Also, in general, the reset period is a setup period that gradually rises from the first voltage to the second voltage, a falling period that rapidly falls from the second voltage to the third voltage, and gradually falls from the third voltage to the fourth voltage. It is divided into a set-down section.

In this case, in general, the plasma display apparatus has a problem in that strong discharge occurs in the set-down period of the reset signal, resulting in an afterimage bright spot due to supersaturated charges, thereby reducing the reliability of the plasma display panel.

SUMMARY OF THE INVENTION In order to solve the above problems in the plasma display device, a technical problem to be solved by the present invention is to solve the above problem, and after the set-down period of the first reset signal in the reset period is completed, a second period having only a gradually increasing set-up period is obtained. It is an object of the present invention to provide a plasma display device capable of canceling bright spots caused by strong discharge by applying a reset signal.

According to an aspect of the present invention, there is provided a plasma display apparatus including: a plasma display panel in which discharge cells are defined in an area where a scan electrode and a sustain electrode cross each other; And a driving unit configured to apply a reset signal to the scan electrode for initializing the plurality of discharge cells in a reset period, wherein the voltage of the driving signal is in the reset period of at least one of a plurality of subfields. The first reset signal including the gradually rising first set-up period and the gradually decreasing first set-down period and the offset signal gradually increasing the voltage of the driving signal are sequentially applied to the scan electrode. It is characterized by.

In addition, after the offset signal is applied, a second reset signal including a second set-up period in which the voltage of the driving signal gradually increases and a second set-down period in which the driving signal is gradually lowered may be sequentially applied to the scan electrode. .

The application time of the offset signal is preferably 0.1 s to 3.5 s (w) after the first reset signal is finished, and the width of the offset signal Ru is 60 s to 90 s, and the voltage of the offset signal The level is preferably 140V to 200V.

Preferably, the offset signal may be one to three.

The first reset signal, the offset signal, and the second reset signal may be sequentially applied to only the first subfield among the plurality of subfields.

Hereinafter, a plasma display device according to the present invention will be described in detail with reference to the accompanying drawings. 1 is a view showing an embodiment of a plasma display panel according to the present invention.

As shown in FIG. 1, the plasma display panel includes a scan electrode 11, a sustain electrode 12, a sustain electrode pair formed on the upper substrate 10, and an address electrode 22 formed on the lower substrate 20. It includes.

The sustain electrode pairs 11 and 12 generally include transparent electrodes 11a and 12a and bus electrodes 11b and 12b formed of indium tin oxide (ITO), and the bus electrodes 11b and 12b. 12b) may be formed of a metal such as silver (Ag) or chromium (Cr) or a stack of chromium / copper / chromium (Cr / Cu / Cr) or a stack of chromium / aluminum / chromium (Cr / Al / Cr). . The bus electrodes 11b and 12b are formed on the transparent electrodes 11a and 12a to serve to reduce voltage drop caused by the transparent electrodes 11a and 12a having high resistance.

Meanwhile, according to the exemplary embodiment of the present invention, the sustain electrode pairs 11 and 12 may not only have a structure in which the transparent electrodes 11a 12a and the bus electrodes 11b and 12b are stacked, but also the buses without the transparent electrodes 11a and 12a. Only the electrodes 11b and 12b may be configured. This structure does not use the transparent electrodes (11a, 12a), there is an advantage that can lower the cost of manufacturing the panel. The bus electrodes 11b and 12b used in this structure may be various materials such as photosensitive materials in addition to the materials listed above.

Light between the scan electrodes 11 and the sustain electrodes 12 between the transparent electrodes 11a and 12a and the bus electrodes 11b and 11c to absorb external light generated outside the upper substrate 10 to reduce reflection. A black matrix (BM, 15) is arranged that functions to block and to improve the purity and contrast of the upper substrate 10.

The black matrix 15 according to the exemplary embodiment of the present invention is formed on the upper substrate 10, the first black matrix 15 and the transparent electrodes 11a and 12a formed at positions overlapping the partition wall 21. And the second black matrices 11c and 12c formed between the bus electrodes 11b and 12b. Here, the first black matrix 15 and the second black matrices 11c and 12c, also referred to as black layers or black electrode layers, may be simultaneously formed and physically connected in the formation process, or may not be simultaneously formed and thus not physically connected. .

In addition, when physically connected and formed, the first black matrix 15 and the second black matrix 11c and 12c may be formed of the same material, but may be formed of different materials when they are formed separately.

The upper dielectric layer 13 and the passivation layer 14 are stacked on the upper substrate 10 having the scan electrode 11 and the sustain electrode 12 side by side. Charged particles generated by the discharge are accumulated in the upper dielectric layer 13, and the protective electrode pairs 11 and 12 may be protected. The protective film 14 protects the upper dielectric layer 13 from sputtering of charged particles generated during gas discharge, and increases the emission efficiency of secondary electrons.

In addition, the address electrode 22 is formed in a direction crossing the scan electrode 11 and the sustain electrode 12. In addition, the lower dielectric layer 23 and the partition wall 21 are formed on the lower substrate 20 on which the address electrode 22 is formed.

In addition, phosphor layers are formed on the surfaces of the lower dielectric layer 23 and the partition wall 21. The partition wall 21 has a vertical partition wall 21a and a horizontal partition wall 21b formed in a closed shape, and physically distinguishes discharge cells, and prevents ultraviolet rays and visible light generated by the discharge from leaking into adjacent discharge cells.

In an embodiment of the present invention, not only the structure of the partition wall 21 illustrated in FIG. 1, but also the structure of the partition wall 21 having various shapes may be possible. For example, a channel in which a channel usable as an exhaust passage is formed in at least one of the differential partition structure, the vertical partition 21a, or the horizontal partition 21b having different heights of the vertical partition 21a and the horizontal partition 21b. A grooved partition structure having a groove formed in at least one of the type partition wall structure, the vertical partition wall 21a, or the horizontal partition wall 21b may be possible.

Here, in the case of the differential partition wall structure, the height of the horizontal partition wall 21b is more preferable, and in the case of the channel partition wall structure or the groove partition wall structure, it is preferable that a channel is formed or the groove is formed in the horizontal partition wall 21b. something to do.

On the other hand, in one embodiment of the invention is shown and described that each of the R, G and B discharge cells are arranged on the same line, it may be arranged in a different shape. For example, a Delta type arrangement in which R, G, and B discharge cells are arranged in a triangular shape may be possible. In addition, the shape of the discharge cell may be not only rectangular, but also various polygonal shapes such as a pentagon and a hexagon.

In addition, the phosphor layer emits light by ultraviolet rays generated during gas discharge to generate visible light of any one of red (R), green (G), and blue (B). Here, an inert mixed gas such as He + Xe, Ne + Xe and He + Ne + Xe for discharging is injected into the discharge space provided between the upper / lower substrates 10 and 20 and the partition wall 21.

FIG. 2 illustrates an embodiment of an electrode arrangement of a plasma display panel, and a plurality of discharge cells constituting the plasma display panel are preferably arranged in a matrix form as shown in FIG. 2. The plurality of discharge cells are provided at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn, respectively. The scan electrode lines Y1 to Ym may be driven sequentially or simultaneously, and the sustain electrode lines Z1 to Zm may be driven simultaneously. The address electrode lines X1 to Xn may be driven by being divided into odd-numbered lines and even-numbered lines, or sequentially driven.

Since the electrode arrangement shown in FIG. 2 is only an embodiment of the electrode arrangement of the plasma panel according to the present invention, the present invention is not limited to the electrode arrangement and driving method of the plasma display panel shown in FIG. 2. For example, a dual scan method in which two scan electrode lines among the scan electrode lines Y1 to Ym are simultaneously scanned may be possible. In addition, the address electrode lines X1 to Xn may be driven by being divided up and down in the center portion of the panel.

3 is a timing diagram illustrating an embodiment of a time division driving method by dividing a frame into a plurality of subfields. The unit frame may be divided into a predetermined number, for example, eight subfields SF1, ..., SF8 to realize time division gray scale display. Each subfield SF1, ... SF8 is divided into a reset section (not shown), an address section A1, ..., A8 and a sustain section S1, ..., S8.

Here, according to an embodiment of the present invention, the reset period may be omitted in at least one of the plurality of subfields. For example, the reset period may exist only in the first subfield or may exist only in a subfield about halfway between the first subfield and all the subfields.

In each address section A1, ..., A8, a display data signal is applied to the address electrode X, and scan pulses corresponding to each scan electrode Y are sequentially applied.

In each of the sustain periods S1, ..., S8, a sustain pulse is alternately applied to the scan electrode Y and the sustain electrode Z to form wall charges in the address periods A1, ..., A8. Sustain discharge occurs in the discharge cells.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge periods S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gradations, each subfield in turn has different sustains at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128. The number of pulses can be assigned. In order to obtain luminance of 133 gray levels, cells may be sustained by addressing the cells during the subfield 1 section, the subfield 3 section, and the subfield 8 section.

The number of sustain discharges allocated to each subfield may be variably determined according to weights of the subfields according to the APC (Automatic Power Control) step. That is, in FIG. 3, a case in which one frame is divided into eight subfields has been described as an example. However, the present invention is not limited thereto, and the number of subfields forming one frame may be variously modified according to design specifications. . For example, a plasma display panel may be driven by dividing one frame into eight or more subfields, such as 12 or 16 subfields.

The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34.

4 through 6 illustrate timing diagrams of embodiments of driving signals for driving a plasma display panel according to an exemplary embodiment of the present invention.

One subfield includes a reset section for initializing the discharge cells of the previous screen, an address section for selecting the discharge cells, and a sustain section for maintaining the discharge of the selected discharge cells.

As shown in FIG. 4, according to the driving signal of the plasma display panel according to the present invention, two reset signals having a set-up period Su and a set-down period Sd in the reset period are scanned electrodes Y. FIG. Is applied to the scan electrode (Y).

As described above, each of the two reset signals sequentially applied includes a setup section Su1 and Su2 and a setdown section Sud1 and Sd2. In the setup section Su1 and Su2, all scan electrodes ( The setup signal of gradually increasing the voltage at Y) is simultaneously applied to generate fine discharge in all the discharge cells, thereby generating wall charges.

In the setdown periods Sd1 and Sd2, a setdown signal gradually decreasing at a positive voltage lower than the peak voltage of the setup signal is simultaneously applied to all the scan electrodes Y, thereby erasing discharge in all the discharge cells. By eliminating the unnecessary charges of the wall charges and the space charges generated by the wall charges, the wall charges necessary for the address discharge are uniformly retained in the discharge cells.

When such a reset signal is applied only once to the scan electrode Y, the wall charges of all the discharge cells may not remain suitable for the address discharge due to the imperfection of the plasma display panel. Therefore, as in the driving signal according to the present invention, by applying the reset signal twice, the wall charges of all the discharge cells can be set to the state necessary for the address discharge. Therefore, by applying the reset signal twice, the wall charges can be properly generated and retained to reduce the occurrence of false discharge in the address period.

The magnitude of the voltage at which the reset signal rises during the setup periods Su1 and Su2 is preferably 160 to 260V. In such a case, erroneous discharge can be reduced by generating wall charges necessary for the address section within a range of not increasing power consumption more than necessary, and the blinking phenomenon can be improved.

As shown in FIG. 4, according to the driving signal of the plasma display panel according to the present invention, a positive offset signal gradually increasing by V1 is applied to the scan electrode Y after the first reset signal is applied. This offset signal allows the afterimage bright point to be offset by the strong discharge caused in the set down period of the first reset signal. In detail, negative wall charges are formed in the scan electrode Y included in most of the discharge cells during the set-down period Sd1, and positive wall charges are formed in the sustain electrode Z. However, since the positive wall charge may be formed in the scan electrode Y included in some discharge cells, after the first reset signal is applied, the second reset signal is applied to all the scan electrodes Y. Negative wall charges are formed. At this time, when the negative wall charge is formed more than the negative electrode charge as the scan electrode (Y) than the positive wall charge is formed as the sustain electrode (Z), the strong discharge is caused, the afterimage bright spot is generated in the panel. Therefore, the positively rising offset signal Ru is gradually applied to the scan electrode Y, so that the positive wall charges are formed on all the scan electrodes Y so that the afterimage bright point is offset. That is, before the afterimage bright point is displayed on the panel, the positive wall charges are formed on the scan electrodes Y so that the excess negative wall charges are erased.

As such, since the offset signal Ru must be canceled before the afterimage bright point is displayed on the panel by the strong discharge caused after the first reset signal is applied, the point of application of the offset signal is after the end of the first reset signal. , 0.1 kPa to 3.5 kPa. In such a case, the afterimage bright point can be appropriately canceled within a range in which the limited reset period is not long due to the offset signal Ru.

In addition, it is preferable that the width of the offset signal is 60 Hz to 90 Hz in order to properly form the positive wall charges with the scan electrodes and to efficiently apply the reset signal and the offset signal in the limited reset period.

 In addition, the highest voltage level V1 of the offset signal is preferably 140 to 200V. When the highest voltage level V1 has such a range, positive wall charges can be formed by the scan electrodes in a range that does not significantly increase power consumption, and the afterimage bright point can be canceled.

In order to cancel the negative wall charges excessively formed on the scan electrode by the offset signal, and to prevent afterimage bright spots that may occur due to the negative wall charge remaining after one offset signal, the offset signal is 1 It will be desirable to apply three to three consecutively.

In addition, it is preferable that the number of subfields to which the offset signal SAFE of the present invention is applied is one to three among the plurality of subfields. When the number of subfields to which the safe signal is applied exceeds three, a flashing phenomenon may occur in which the discharge cells are repeatedly turned on and off. Preferably, as shown in FIG. 4, the first reset signal, the offset signal, and the second reset signal are sequentially applied to the scan electrode Y in the first subfield of the plurality of subfields for split driving one frame. It is desirable to. Further, considering the driving margin and contrast of the panel, as shown in FIG. 5, the first reset signal is omitted from the second subfield, and the first reset signal and the offset signal are omitted from the second subfield. It is preferable to apply only the first reset signal.

In addition, as shown in FIG. 6, the driving signal of the plasma display apparatus according to the present invention may be applied with the preset down signal Rd before the first reset signals Ru1 and Rd1 are applied to the reset period. . The preset down signal Rd increases the amount of charge of the wall charges remaining on the sustain electrode and the scan electrode to prepare the reset state so as to facilitate the reset discharge. In addition, a bias signal rising up to a constant voltage level is applied to the sustain electrode Z in synchronization with the set down signal of the scan electrode, and thus the scan electrode Y included in most of the discharge cells during the set down period has a negative polarity. The wall charges are formed, and the positive electrode wall charges may be formed on the sustain electrode Z more smoothly. In the present specification, although the bias signal is not applied to the sustain electrode in the set down period of the last reset signals Su2 and Sd2, the bias signal is not applied to the sustain electrode in the address period. It may overlap with the set down period.

In the address period, the negative scan signal is sequentially applied to the scan electrodes Y and the positive data signal Va is applied to the address electrodes X. An address discharge is generated in the cell to which the data signal Va is applied as the voltage difference between the scan signal Yy and the data signal Va and the wall voltage generated in the setup period are added. Wall charges are generated in the cells selected by the address discharge. Meanwhile, in the present invention, since the negative wall charges are evenly formed on the scan electrodes Y formed in all the discharge cells by the second reset signal, stable address discharge can be caused. This can prevent the bright spot mis-discharge phenomenon.

During the address period, a bias voltage Vzb is preferably applied to the sustain electrode, and the bias voltage Vzb is preferably 140 to 190V. When the bias voltage Vzb has the same value as above, no flicker occurs and luminance is improved.

The voltage Vy of the scan signal is preferably -130 to -90V, and as described above, the flickering phenomenon and the bright spot do not occur, and the black luminance of the displayed image is improved.

In the sustain period, sustain pulses are alternately applied to the scan electrode and the sustain electrode to generate sustain discharge in the form of surface discharge between the scan electrode (Y) and the sustain electrode (Z).

The driving waveforms shown in FIGS. 4 to 5 are examples of signals for driving the plasma display panel according to the present invention, and the present invention is not limited by the waveforms shown in FIGS. 4 to 5. . For example, the method may further include a pre-reset section for forming the positive wall charges on the scan electrodes Y and the negative wall charges on the sustain electrodes Z. The polarity and voltage levels of the illustrated driving signals may be changed as necessary, and an erase signal for erasing wall charge may be applied to the sustain electrode after the sustain discharge is completed. In addition, the sustain signal may be applied to only one of the scan electrode (Y) and the sustain (Z) electrode to generate a single sustain (single sustain) drive that causes sustain discharge.

FIG. 6 illustrates an embodiment of a scan driving circuit for applying the reset signal shown in FIGS. 4 and 5 to the scan electrode.

As shown in FIG. 6, the scan driving circuit according to the present invention includes an energy recovery unit 20, a sustain driver 30, a reset driver 40, and a scan IC 50.

The sustain driver 30 includes a sustain voltage power supply Vsus for supplying a high potential sustain voltage Vsus during the sustain period, and a sustain-up switch Su_up turned on so that the sustain voltage Vsus is applied to the scan electrode 10. And a sus-down switch Su_dn turned on to drop to the ground voltage applied to the scan electrode 10. That is, the sustain driver 30 is connected to the sustain voltage power supply Vsus and the sustain-up switch Su_up is connected to the sustain switch Sus_up and ground.

The energy recovery unit 20 recovers the source capacitor Cs and the capacitor Cs to recover and supply the energy supplied to the scan electrode 10 so that the energy stored in the source capacitor Cs is supplied to the scan electrode 10. An energy recovery switch ER_up which is turned on and an energy recovery switch ER_dn which are turned on to recover energy from the scan electrode 10 are included.

The reset driver 40 is connected to the set-up switch Set_up and the negative voltage -Vy, which are turned on to supply a gradually rising set-up signal to the scan electrode 10, up to the negative voltage -Vy. The set-down switch Set_dn is turned on to supply the progressively descending setdown signal to the scan electrode 10, and the pass switch Pass_sw forming a current path path with the scan electrode 10.

As shown in FIG. 6, in the set-up switch Set_up, a drain is connected to a sustain voltage power source, a source is connected to a pass switch Pass_sw, and a gate is a variable resistor. And a setup signal which gradually rises as the resistance value of the variable resistor changes.

The set-down switch Set_dn has a drain connected to the scan IC 50, a source connected to a negative voltage (-Vy), and a variable resistor (not shown) connected to the gate. As the resistance value of the variable resistor (not shown) changes, a setdown signal that gradually decreases is generated.

The scan IC 50 is connected to a scan voltage power source and turned on to apply a ground voltage to the scan electrode 10 and the scan-up switch Q1 which is turned on to apply the scan voltage Vsc to the scan electrode 10. And a scan-down switch Q2. In addition, the scan IC 50 includes a first diode D1 connected in parallel with the scan-up switch Q1 and a second diode D2 connected in parallel with the scan-down switch Q2.

As illustrated in FIG. 6, the first diode D1 has a cathode connected to the drain of the scan-up switch Q1 and an anode of the source of the scan-up switch Q1. Source is connected to the second diode (D2), the cathode (Cathode) is connected to the drain (Drain) of the scan-down switch (Q2) and the anode (Anode) source of the scan-down switch (Q2) ).

Although a preferred embodiment of the present invention has been described in detail above, those skilled in the art to which the present invention pertains can make various changes without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

According to the plasma display device according to the present invention configured as described above, after applying the reset signal to the plasma display panel, by applying a gradually rising positive offset signal, it is possible to prevent the generation of afterimage bright spots due to strong discharge It is possible to improve the reliability of the plasma display device.

Claims (7)

A plasma display panel in which discharge cells are defined in a region where the scan electrode and the sustain electrode cross each other; And a driving unit configured to apply a reset signal to the scan electrode for initializing the plurality of discharge cells in a reset period. In the reset period of at least one of a plurality of subfields, First and second reset signals including a gradually rising signal and a gradually falling signal are applied to the scan electrode, And an offset signal that gradually rises between the first and second reset signals. delete The method according to claim 1, And the time point at which the offset signal is applied is 0.1 ms to 3.5 ms after the first reset signal ends. The method according to claim 1, And a width of the offset signal is 60 Hz to 90 Hz. The method according to claim 1, The voltage level of the offset signal is a plasma display device, characterized in that 140V to 200V. The method according to claim 1, And said offset signal is one to three. delete

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