KR100790832B1 - Plasma display apparatus - Google Patents

Abstract

A plasma display device is provided to stabilize voltages at both ends of a scan voltage source by removing a sustain voltage after collecting energy from a panel and removing a scan voltage in a descending period of a reset signal. A plasma display device includes a plasma display panel having a plurality of discharge cells and a driving unit for applying a reset signal to reset the discharge cells. The reset signal includes a setup period for raising a first voltage to a second voltage, a descending period(500) for descending the second voltage to a third voltage, and a setdown period for descending gradually the third voltage to a fourth voltage. The descending period includes a first descending period for descending the second voltage to a fifth voltage. The second voltage is higher than a scan voltage and is lower than a sum of the scan voltage and a sustain voltage. The fifth voltage is larger than the scan voltage.

Description

 Plasma display apparatus

1 is a perspective view showing an embodiment of a plasma display panel according to the present invention.

2 is a diagram illustrating an embodiment of an electrode arrangement of a plasma display panel.

3 is a timing diagram illustrating an embodiment of a time division driving method by dividing a frame into a plurality of subfields.

FIG. 4 is a timing diagram illustrating an embodiment of driving signals for driving a plasma display panel with respect to the divided subfield.

5A and 5B are diagrams illustrating a first embodiment of a reset signal waveform applied to a plasma display panel.

6A to 6C are circuit diagrams showing the configuration of the scan driving circuit for applying the reset signal shown in FIGS. 5A and 5B and the current flow of the driving circuit.

7A and 7B illustrate a second embodiment of a reset signal waveform applied to a plasma display panel.

8A to 8E are circuit diagrams showing the configuration of the scan driving circuit for applying the reset signal shown in FIGS. 7A and 7B and the current flow of the driving circuit.

9A to 9C are graphs illustrating voltages across the scan voltage power source when the reset signals having the waveforms shown in FIGS. 5A and 5B are applied to the panel.

10A through 10C are graphs illustrating voltages across a scan voltage power supply when applying reset signals having a waveform shown in FIGS. 6A and 6B to a panel.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, and more particularly, to a plasma including a scan driving device for applying a reset signal to a plasma display panel to initialize a plurality of discharge cells. It relates to a display device.

BACKGROUND ART In general, a plasma display panel is an apparatus that displays an image by applying a predetermined voltage to electrodes provided in a discharge space and causing a discharge, and the plasma generated during gas discharge excites a phosphor.

Such a plasma display panel is not only large in size and thin in thickness, but also has a simple structure, which makes the plasma display panel easier to manufacture and has a higher luminance and higher luminous efficiency than other flat panel display devices.

The plasma display panel is time-divisionally driven into a reset section for initializing all the discharge cells, an address section for selecting a cell in which discharge is to be generated, and a sustain section for generating sustain discharge in the selected cell. . Also, in general, the reset section is a setup section that gradually rises from the first voltage to the second voltage, a falling section that rapidly falls from the second voltage to the third voltage, and gradually falls from the third voltage to the fourth voltage. It is divided into a set-down section.

When the driving device of the conventional plasma display panel applies the reset signal to the panel, the amount of current flowing in the opposite direction across the scan voltage power supply in the falling section becomes very large, resulting in unstable voltages between the power supply and the reliability of the scan IC. There was a problem that this was lowered and the waveform of the reset signal was distorted.

SUMMARY OF THE INVENTION In order to solve the above problems in the plasma display device, a technical problem of the present invention is to stabilize the voltages at both ends of the scan voltage power supply in the falling section of the reset signal, thereby improving the reliability of the scan IC, and It is an object of the present invention to provide a plasma display device capable of preventing distortion of a waveform.

Plasma display device according to the present invention for solving the above problems, the plasma display panel comprising a plurality of discharge cells; And a driving unit which applies a reset signal to the panel to initialize the plurality of discharge cells, wherein the reset signal comprises: a setup period in which the reset signal gradually rises from a first voltage to a second voltage; A falling period in which the voltage falls from the second voltage to a third voltage; And a set-down period that gradually descends from the third voltage to a fourth voltage, wherein the falling period includes a first falling period that descends from the second voltage to a fifth voltage having a value greater than a scan voltage. Characterized in that it comprises a.

Preferably, the second voltage is greater than the scan voltage and has a value less than the sum of the scan voltage and the sustain voltage.

The falling period may include a second falling period falling from the fifth voltage to the third voltage, wherein the second falling period is a period falling from the fifth voltage to the sixth voltage by a scan voltage and the It is preferable to include a section falling from the sixth voltage to the third voltage.

Preferably, the falling section further includes a section for maintaining the fifth voltage for a predetermined time between the first falling section and the second falling section, the predetermined time is preferably 40 kHz or less.

The falling section may include a section that rises from the fifth voltage to a seventh voltage and a section that falls from the seventh voltage to the fourth voltage, and the difference between the seventh voltage and the fourth voltage is sustain. It is preferable that it is a voltage.

Preferably, the interval from the fifth voltage to the seventh voltage is 8 to 12 mA, and the seventh voltage is preferably smaller than the second voltage.

Preferably, the setup period includes a first setup period that gradually rises from the first voltage to an eighth voltage and a second setup period that gradually rises from the ninth voltage to the second voltage. Is preferably smaller than the eighth voltage.

Another plasma display device according to the present invention for solving the above technical problem has a fifth switch turned on to supply energy stored in a source capacitor to the panel, and a sixth switch turned on to recover energy from the panel. Energy recovery unit; A sustain driver including a third switch turned on to apply a sustain voltage to the panel and a fourth switch turned on to apply a ground voltage to the panel; And a first switch that transmits outputs of the energy recovery unit and the sustain driver to the panel, a first switch turned on to apply a scan voltage to the panel, and a second switch turned on to apply a ground voltage to the panel. The second switch is turned on after the sixth switch is turned on in the falling section of the reset signal, and the fourth switch is turned on between the turn-on time of the sixth switch and the turn-on time of the second switch. The switch is characterized in that it is turned on.

Preferably, the voltage of the reset signal at the time when the sixth switch is turned on is greater than the scan voltage and has a value smaller than the sum of the scan voltage and the sustain voltage. Preferably, the fourth switch is turned on after the second switch is turned on, and the fifth switch is turned on in the state where the first switch and the second switch are floating after the sixth switch is turned on. It is desirable to be.

Preferably, the second switch is turned on after the fifth switch is turned on, and the fifth switch and the third switch are sequentially turned on after the second switch is turned on.

The scan IC may include a first diode connected in parallel with the first switch; And a second diode connected in parallel with the second switch, wherein the energy is supplied to the panel through the second diode when the fifth switch is turned on while the first and second switches are floated. desirable.

Preferably, the voltage across the second switch at the time when the second switch is turned on is substantially the same, and the time for which the first and second switches are floated is preferably 8 to 12 kW.

Hereinafter, a plasma display device according to the present invention will be described in detail with reference to the accompanying drawings. 1 is a perspective view showing an embodiment of a plasma display panel according to the present invention.

As shown in FIG. 1, the plasma display panel includes a scan electrode 11, a sustain electrode 12, a sustain electrode pair formed on the upper substrate 10, and an address electrode 22 formed on the lower substrate 20. It includes.

The sustain electrode pairs 11 and 12 generally include transparent electrodes 11a and 12a and bus electrodes 11b and 12b formed of indium tin oxide (ITO), and the bus electrodes 11b and 12b. 12b) may be formed of a metal such as silver (Ag) or chromium (Cr) or a stack of chromium / copper / chromium (Cr / Cu / Cr) or a stack of chromium / aluminum / chromium (Cr / Al / Cr). . The bus electrodes 11b and 12b are formed on the transparent electrodes 11a and 12a to serve to reduce voltage drop caused by the transparent electrodes 11a and 12a having high resistance.

Meanwhile, according to the exemplary embodiment of the present invention, the sustain electrode pairs 11 and 12 may not only have a structure in which the transparent electrodes 11a 12a and the bus electrodes 11b and 12b are stacked, but also the buses without the transparent electrodes 11a and 12a. Only the electrodes 11b and 12b may be configured. This structure does not use the transparent electrodes (11a, 12a), there is an advantage that can lower the cost of manufacturing the panel. The bus electrodes 11b and 12b used in this structure may be various materials such as photosensitive materials in addition to the materials listed above.

Light between the scan electrodes 11 and the sustain electrodes 12 between the transparent electrodes 11a and 12a and the bus electrodes 11b and 11c to absorb external light generated outside the upper substrate 10 to reduce reflection. A black matrix (BM, 15) is arranged that functions to block and to improve the purity and contrast of the upper substrate 10.

The black matrix 15 according to the exemplary embodiment of the present invention is formed on the upper substrate 10, the first black matrix 15 and the transparent electrodes 11a and 12a formed at positions overlapping the partition wall 21. And the second black matrices 11c and 12c formed between the bus electrodes 11b and 12b. Here, the first black matrix 15 and the second black matrices 11c and 12c, also referred to as black layers or black electrode layers, may be simultaneously formed and physically connected in the formation process, or may not be simultaneously formed and thus not physically connected. .

In addition, when physically connected and formed, the first black matrix 15 and the second black matrix 11c and 12c may be formed of the same material, but may be formed of different materials when they are formed separately.

The upper dielectric layer 13 and the passivation layer 14 are stacked on the upper substrate 10 having the scan electrode 11 and the sustain electrode 12 side by side. Charged particles generated by the discharge are accumulated in the upper dielectric layer 13, and the protective electrode pairs 11 and 12 may be protected. The protective film 14 protects the upper dielectric layer 13 from sputtering of charged particles generated during gas discharge, and increases emission efficiency of secondary electrons.

In addition, the address electrode 22 is formed in a direction crossing the scan electrode 11 and the sustain electrode 12. In addition, the lower dielectric layer 23 and the partition wall 21 are formed on the lower substrate 20 on which the address electrode 22 is formed.

In addition, phosphor layers are formed on the surfaces of the lower dielectric layer 23 and the partition wall 21. The partition wall 21 has a vertical partition wall 21a and a horizontal partition wall 21b formed in a closed shape, and physically distinguishes discharge cells, and prevents ultraviolet rays and visible light generated by the discharge from leaking into adjacent discharge cells.

In an embodiment of the present invention, not only the structure of the partition wall 21 illustrated in FIG. 1, but also the structure of the partition wall 21 having various shapes may be possible. For example, a channel in which a channel usable as an exhaust passage is formed in at least one of the differential partition structure, the vertical partition 21a, or the horizontal partition 21b having different heights of the vertical partition 21a and the horizontal partition 21b. A grooved partition structure having a groove formed in at least one of the type partition wall structure, the vertical partition wall 21a, or the horizontal partition wall 21b may be possible.

Here, in the case of the differential partition wall structure, the height of the horizontal partition wall 21b is more preferable, and in the case of the channel partition wall structure or the groove partition wall structure, it is preferable that a channel is formed or the groove is formed in the horizontal partition wall 21b. something to do.

On the other hand, in one embodiment of the invention is shown and described that each of the R, G and B discharge cells are arranged on the same line, it may be arranged in a different shape. For example, a Delta type arrangement in which R, G, and B discharge cells are arranged in a triangular shape may be possible. In addition, the shape of the discharge cell may be not only rectangular, but also various polygonal shapes such as a pentagon and a hexagon.

In addition, the phosphor layer emits light by ultraviolet rays generated during gas discharge to generate visible light of any one of red (R), green (G), and blue (B). Here, an inert mixed gas such as He + Xe, Ne + Xe and He + Ne + Xe for discharging is injected into the discharge space provided between the upper / lower substrates 10 and 20 and the partition wall 21.

FIG. 2 illustrates an embodiment of an electrode arrangement of a plasma display panel, and a plurality of discharge cells constituting the plasma display panel are preferably arranged in a matrix form as shown in FIG. 2. The plurality of discharge cells are provided at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn, respectively. The scan electrode lines Y1 to Ym may be driven sequentially or simultaneously, and the sustain electrode lines Z1 to Zm may be driven simultaneously. The address electrode lines X1 to Xn may be driven by being divided into odd-numbered lines and even-numbered lines, or sequentially driven.

Since the electrode arrangement shown in FIG. 2 is only an embodiment of the electrode arrangement of the plasma panel according to the present invention, the present invention is not limited to the electrode arrangement and driving method of the plasma display panel shown in FIG. 2. For example, a dual scan method in which two scan electrode lines among the scan electrode lines Y1 to Ym are simultaneously scanned is possible. In addition, the address electrode lines X1 to Xn may be driven by being divided up and down in the center portion of the panel.

3 is a timing diagram illustrating an embodiment of a time division driving method by dividing a frame into a plurality of subfields. The unit frame may be divided into a predetermined number, for example, eight subfields SF1, ..., SF8 to realize time division gray scale display. Each subfield SF1, ... SF8 is divided into a reset section (not shown), an address section A1, ..., A8 and a sustain section S1, ..., S8.

Here, according to an embodiment of the present invention, the reset period may be omitted in at least one of the plurality of subfields. For example, the reset period may exist only in the first subfield or may exist only in a subfield about halfway between the first subfield and all the subfields.

In each address section A1, ..., A8, a display data signal is applied to the address electrode X, and scan pulses corresponding to each scan electrode Y are sequentially applied.

In each of the sustain periods S1, ..., S8, a sustain pulse is alternately applied to the scan electrode Y and the sustain electrode Z to form wall charges in the address periods A1, ..., A8. Sustain discharge occurs in the discharge cells.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge periods S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gradations, each subfield in turn has different sustains at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128. The number of pulses can be assigned. In order to obtain luminance of 133 gray levels, cells may be sustained by addressing the cells during the subfield 1 section, the subfield 3 section, and the subfield 8 section.

The number of sustain discharges allocated to each subfield may be variably determined according to weights of the subfields according to the APC (Automatic Power Control) step. That is, in FIG. 3, a case in which one frame is divided into eight subfields has been described as an example. However, the present invention is not limited thereto, and the number of subfields forming one frame may be variously modified according to design specifications. . For example, a plasma display panel may be driven by dividing one frame into eight or more subfields, such as 12 or 16 subfields.

The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34.

4 is a timing diagram illustrating an embodiment of driving signals for driving a plasma display panel with respect to the divided subfield.

The subfield is a wall formed by a pre-reset section and a pre-reset section for forming positive wall charges on the scan electrodes Y and negative wall charges on the sustain electrodes Z. A reset section for initializing the discharge cells of the entire screen using the charge distribution, an address section for selecting the discharge cells, and a sustain section for maintaining the discharge of the selected discharge cells.

The reset section includes a progressively rising setup section, a rapidly descending descending section, and a progressively descending setdown section, in which the ramp ramp is applied to all scan electrodes. Simultaneously applied, fine discharge is generated in all the discharge cells, thereby generating wall charges. In the falling section, the voltage drops rapidly from the voltage at which the set-up section ends to the voltage at which the set-down section begins. In the set-down period, a falling ramp waveform (Ramp-down) falling at a positive voltage lower than the peak voltage of the rising ramp waveform (Ramp-up) is simultaneously applied to all the scan electrodes (Y), thereby eliminating discharge discharge in all the discharge cells. Generated, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges.

In the address period, a negative scan signal having a magnitude of the scan voltage Vsc is sequentially applied to the scan electrode, and at the same time, a positive data signal data is applied to the address electrode X. The address discharge is generated by the voltage difference between the scan signal and the data signal data and the wall voltage generated during the reset period, thereby selecting the cell. Meanwhile, a signal for maintaining a sustain voltage Vsus is applied to the sustain electrode during the setdown period and the address period.

In the sustain period, a sustain signal having a sustain voltage Vsus is alternately applied to the scan electrode and the sustain electrode, thereby generating sustain discharge in the form of surface discharge between the scan electrode and the sustain electrode.

The driving waveforms shown in FIG. 4 are examples of signals for driving the plasma display panel according to the present invention, and the present invention is not limited by the waveforms shown in FIG. 4. For example, the pre-reset period may be omitted, and the polarity and the voltage level of the driving signals illustrated in FIG. 4 may be changed as necessary, and an erase signal for erasing wall charge may be applied to the sustain electrode after the sustain discharge is completed. It may be. In addition, the single sustain driving may be performed by applying the sustain signal to only one of the scan electrode (Y) and the sustain (Z) electrode to generate a sustain discharge.

5A and 5B illustrate a first embodiment of a reset signal waveform applied to a plasma display panel, and FIG. 5A illustrates a reset section of the driving signals shown in FIG. 4 in more detail.

As shown in FIG. 5A, the setup section preferably includes a first setup section that gradually rises from the ground voltage and a second setup section that gradually rises to the highest voltage Vramp. The highest voltage Vramp preferably has a value smaller than the sum of the scan voltage Vsc and the sustain voltage Vsus, and preferably has a value greater than the scan voltage Vsc. That is, it is preferable to lower the voltage value of the reset signal before the reset signal reaches the sum of the scan voltage Vsc and the sustain voltage Vsus in the second setup period.

After the reset signal rises to the highest voltage Vramp, a falling period in which the reset signal rapidly falls from the highest voltage Vramp to the ground voltage is followed. In the set down period, the reset signal gradually falls from the ground voltage.

FIG. 5B illustrates in more detail the waveform of the falling section 500 in the first embodiment of the reset signal waveform shown in FIG. 5A. As shown in FIG. 5B, the falling section of the reset signal includes an energy recovery section (ER_down) in which the scan driving circuit recovers energy from the panel so that the reset signal gradually falls from the highest voltage (Vramp) to the voltage V1. The scan down section includes a scan down section (SCAN_down) and a sustain down section (SUS_down) section rapidly descending to the ground voltage.

As shown in FIG. 5B, it is preferable that the voltage V1 after all the energy is recovered from the panel in the energy recovery period ER_down is greater than the scan voltage Vsc, and is suspended after the scan down period SCAN_down. It is preferable that the (SUS_down) section is located. In addition, the energy recovery section ER_down preferably includes a section for maintaining the voltage V1 for a predetermined time t1, and the holding time t1 is preferably 40 mW or less. When the holding time t1 is 40 ms or less, a sufficient driving margin for driving the panel can be secured, and the panel can be stably driven due to a stable driving waveform.

Referring to FIGS. 6A to 6C, which illustrate a configuration of a scan driving circuit and a current flow of the driving circuit according to the present invention, the specific operation of the scan driving circuit in the falling section 500 of the reset signal illustrated in FIG. 5B. This will be described.

As shown in FIG. 6A, the scan driving circuit according to the present invention includes an energy recovery unit 20, a sustain driver 30, a reset driver 40, and a scan IC 50.

The sustain driver 30 includes a sustain voltage power supply Vsus for supplying a high potential sustain voltage Vsus during the sustain period, and a sustain-up switch Sus_up turned on such that the sustain voltage Vsus is applied to the scan electrode 10. And a sus-down switch Su_dn which is turned on to lower the voltage applied to the scan electrode 10 to the ground voltage. That is, the sustain driver 30 is connected to the sustain voltage power supply Vsus and the sustain-up switch Su_up is connected to the sustain switch Sus_up and ground.

The energy recovery unit 20 may include a source capacitor Cs for recovering and storing energy supplied to the scan electrode 10, and an energy supply switch that is turned on so that energy stored in the source capacitor Cs is supplied to the scan electrode 10 ( ER_up) and an energy recovery switch ER_dn which is turned on to recover energy from the scan electrode 10.

The reset driver 40 is connected to the set-up switch Set_up and the negative voltage -Vy, which are turned on to supply a gradually rising set-up signal to the scan electrode 10, up to the negative voltage -Vy. The set-down switch Set_dn is turned on to supply the progressively descending setdown signal to the scan electrode 10, and the pass switch Pass_sw forming a current path path with the scan electrode 10.

As shown in FIG. 6A, the set-up switch Set_up has a drain connected to a sustain voltage power supply, a source connected to a pass switch Pass_sw, and a gate connected to a variable resistor. And a setup signal which gradually rises as the resistance value of the variable resistor changes.

The set-down switch Set_dn has a drain connected to the scan IC 50, a source connected to a negative voltage (-Vy), and a variable resistor (not shown) connected to the gate. As the resistance value of the variable resistor (not shown) changes, a set down signal that gradually decreases is generated.

The scan IC 50 is turned on to apply a scan-up switch Q1 connected to a scan voltage power source that is turned on to apply the scan voltage Vsc to the scan electrode 10, and a ground voltage to the scan electrode 10. And a scan-down switch Q2. In addition, the scan IC 50 includes a first diode D1 connected in parallel with the scan-up switch Q1 and a second diode D2 connected in parallel with the scan-down switch Q2.

As shown in FIG. 6A, the first diode D1 has a cathode connected to the drain of the scan-up switch Q1 and an anode of the source of the scan-up switch Q1. Source is connected to the second diode (D2), the cathode (Cathode) is connected to the drain (Drain) of the scan-down switch Q2, the anode (Source) of the scan-down switch (Q2) Connected with

FIG. 6A illustrates a current flow in an energy recovery section ER_down section of the falling section of the reset signal illustrated in FIG. 5B. As shown in FIG. 6A, in the energy recovery period ER_down, energy is recovered from the scan electrode 10 to the source capacitor Cs of the energy recovery unit 20, and thus, the energy is recovered from the scan electrode 10 toward the source capacitor Cs. A current flow is generated, so that the voltage of the reset signal applied to the scan electrode 10 is lowered from the highest voltage Vramp to the voltage V1. In the energy recovery period ER_down, the scan-up switch Q1, the pass switch Pass_sw and the energy recovery switch ER_dn are turned on for the current flow as described above. As the sus-down switch Su_dn is not turned on and the energy recovery switch ER_dn is turned on to recover energy to the source capacitor Cs, the voltage of the reset signal drops to the scan voltage Vsc during the energy recovery period. Not.

Referring to FIG. 6B, the scan-up switch Q1 is turned off in the scan down period SCAN_down, the scan-down switch Q2, the pass switch Pass_sw and the energy recovery switch ER_dn are turned on, and the scan electrode is turned on. Current flows from the direction 10 to the source capacitor Cs, and the scan voltage Vsc is removed so that the voltage of the reset signal drops by the scan voltage Vsc.

Referring to FIG. 6C, after the scan-down switch Q2 is turned on, the sus-down switch Su_dn is turned on in the sus down section SUS_down. That is, the energy recovery switch ER_dn is turned off in the sus down period SUS_down, the scan-down switch Q2, the pass switch Pass_sw, and the sus-down switch Sus_dn are turned on from the scan electrode 10. A current flows in the ground direction connected to the sus-down switch Sus_dn, and thus the voltage of the reset signal drops to the ground voltage.

7A and 7B illustrate a second embodiment of a reset signal waveform applied to a plasma display panel, and FIG. 7A illustrates a reset section of the driving signals illustrated in FIG. 4 in more detail.

As shown in FIG. 7A, the setup section preferably includes a first setup section that gradually rises from the ground voltage and a second setup section that gradually rises to the highest voltage Vramp. The uppermost voltage Vramp preferably has a value smaller than the sum of the scan voltage Vsc and the sustain voltage Vsus, and preferably has a larger value than the scan voltage Vsc. That is, it is preferable to lower the voltage value of the reset signal before the reset signal reaches the sum of the scan voltage Vsc and the sustain voltage Vsus in the second setup period.

After the reset signal rises to the highest voltage Vramp, a falling period in which the reset signal rapidly falls from the highest voltage Vramp to the ground voltage is followed. In the set down period, the reset signal gradually falls from the ground voltage.

FIG. 7B illustrates in detail the waveform of the falling section 600 in the second embodiment of the reset signal waveform shown in FIG. 7A. As shown in FIG. 7B, the falling section of the reset signal includes an energy recovery section (ER_down) in which the scan driving circuit recovers energy from the panel so that the reset signal gradually falls from the highest voltage (Vramp) to the voltage V1. The energy supply section (ER_up) in which the reset signal rises from the voltage V1 to the predetermined voltage by supplying the voltage, the scan down section (SCAN_down) in which the scan-down switch is turned on, and the reset signal is restored to the ground voltage. It includes the energy recovery / sus down section (ER / SUS_down) to descend to.

As shown in FIG. 7B, it is preferable that the voltage V1 after all the energy is recovered from the panel in the energy recovery period ER_down is greater than the scan voltage Vsc, and after the scan down period SCAN_down, It is preferable that the (SUS_down) section is located. The energy supply period ER_up is preferably 8 to 12 kV. In the case of the above-mentioned range, the driving voltage of the panel is sufficiently secured, and the reset voltage can be increased by supplying the energy stored in the source capacitor Cs to the panel. You can get enough time. In addition, the voltage of the reset signal raised in the energy supply period ER_up is preferably the sustain voltage Vsus.

Referring to FIGS. 8A to 8E, which illustrate a configuration of a scan driving circuit and a current flow of the driving circuit according to the present invention, the specific operation of the scan driving circuit in the falling section 500 of the reset signal illustrated in FIG. 7B is illustrated. This will be described.

FIG. 8A illustrates a current flow in an energy recovery section ER_down section of the falling section of the reset signal illustrated in FIG. 7B. As shown in FIG. 8A, in the energy recovery period ER_down, energy is recovered from the scan electrode 10 to the source capacitor Cs of the energy recovery unit 20, and thus, the energy is recovered from the scan electrode 10 toward the source capacitor Cs. A current flow is generated, so that the voltage of the reset signal applied to the scan electrode 10 is lowered from the highest voltage Vramp to the voltage V1. In the energy recovery period ER_down, the scan-up switch Q1, the pass switch Pass_sw and the energy recovery switch ER_dn are turned on for the current flow as described above. As the sus-down switch Su_dn is not turned on and the energy recovery switch ER_dn is turned on to recover energy to the source capacitor Cs, the voltage of the reset signal does not drop to the scan voltage Vsc during the energy recovery period. No.

Referring to FIG. 8B, in the energy supply section ER_up, energy is supplied from the source capacitor Cs to the scan electrode 10 to generate a current flow from the source capacitor Cs toward the scan electrode 10, thereby scanning. The voltage of the reset signal applied to the electrode 10 is increased. In the energy supply period ER_up, it is preferable to increase by 20 to 50V, and accordingly, the reset signal may increase from the voltage V1 to the sustain voltage Vsus. Due to the voltage rise of the reset signal in the above range, the voltage across the scan down switch Q2 may be equal.

In the energy supply section ER_up, the scan-up switch Q1 and the scan-down switch Q2 are turned off and floating at the same time, and the pass switch Pass_sw and the energy supply switch ER-up are turned on. do. Therefore, the energy stored in the source capacitor Cs is supplied to the scan electrode 10 through the second diode D2 connected in parallel with the scan-down switch Q2. That is, in the energy supply period ER_up, a current flows through the second diode D2 connected in parallel with the scan-down switch Q2.

The time of the energy supply section ER_down is preferably 8us to 12us. The time of the energy supply section ER_down in the above range lowers the capacitance of the parasitic capacitor (not shown) present in the scan-up switch Q1 and the scan-down switch Q2, thereby reducing the scan-down switch ( This is the time required to equalize the voltage across scan-down switch Q2 before Q2) is turned on.

In the energy supply section ER_up, energy is supplied to the scan electrode 10 by the current flow as described above, so that the voltage of the reset signal increases, so that the voltages of both ends of the scan-down switch Q2 become equal. .

By having the energy supply period ER_up as described above, the switching delay of the scan-up switch Q1 is reduced, and the scan when switching from the scan-up switch Q1 to the scan-down switch Q2 is switched. It is possible to prevent shorts occurring in the -down switch Q2.

Referring to FIG. 8C, the scan-down switch Q2, the pass switch Pass_sw and the energy supply switch ER_up are turned on in the scan down period SCAN_down. As described with reference to FIG. 8B, since the voltages across the scan-down switch Q2 are the same at the end of the energy supply section ER_up, the scan-down switch Q2 is also turned on during the scan-down period SCAN_down. The voltage of the reset signal applied to the scan electrode 10 does not change.

Referring to FIG. 8D, in the energy recovery period ER_down of the energy recovery / susdown period ER / SUS, energy is recovered from the scan electrode 10 to the source capacitor Cs of the energy recovery unit 20 to scan electrode. A current flow in the direction of the source capacitor Cs is generated from (10), thereby lowering the voltage of the reset signal applied to the scan electrode 10. In the energy recovery period ER_down, the scan-down switch Q2, the pass switch Pass_sw and the energy recovery switch ER_dn are turned on for the current flow as described above.

Referring to FIG. 8E, in the sus down section SUS_down of the energy recovery / sus down section ER / SUS, a current flow in the ground direction connected to the sus-down switch Sus_dn is generated from the scan electrode 10. The voltage of the reset signal applied to the scan electrode 10 drops to the ground voltage. In the susdown section SUS_down, the scan-down switch Q2, the pass switch Pass_sw and the sus-down switch SUS_dn are turned on for the current flow as described above.

As described above, in the scan driving apparatus according to the present invention, after the scan-down switch Q2 is turned on, the sus-down switch Sus_dn is turned on. When the sus-dn switch is turned on while the scan-up switch Q1 is turned on after the energy recovery period ER_down, a reverse current is applied to the scan voltage power supply by the voltage difference between the scan electrode 10 and the ground. Flows, causing a problem that the voltage across the scan voltage power supply becomes unstable. In addition, as described above, when the highest voltage Vramp of the reset signal is smaller than the sum of the scan voltage Vsc and the sustain voltage Vsus, the energy recovered to the source capacitor Cs is small in the energy recovery period ER_down. The reverse current in the scan voltage supply is very large.

If the voltage across the scan voltage supply becomes unstable, the reliability of the scan IC is deteriorated, and the drive signal waveform may be distorted, causing errors in panel driving. Therefore, in the scan driving circuit according to the present invention, after the energy recovery period ER_down, the scan-down switch Q2 is first turned on to remove the scan voltage, and after that, the scan-down switch Su_dn is turned on to reset. The voltage of the signal is lowered to the ground voltage. Therefore, when the sus-down switch Su_dn is turned on, it is possible to prevent the reverse current from flowing in the scan voltage power supply.

In the above description, the operation of the scan driving circuit according to the present invention has been described by turning on the sus-down switch Su_dn after turning on the scan-down switch Q2, but according to another embodiment of the present invention, the scan-down switch It is possible to prevent the reverse current from flowing to the scan voltage power supply by turning on the Q2 and the sus-down switch Su_dn at the same time.

9A to 9C are graphs of voltages across the scan voltage power supply when the reset signals having the waveforms shown in FIGS. 5A and 5B are applied to the panel.

Referring to FIG. 9A, in the case of the reset signal 90a falling from the highest voltage Vramp to the scan voltage Vsc, the voltage 91a of both ends of the scan voltage power source is very unstable. In the case of the reset signal 90b falling from the highest voltage Vramp to a voltage larger than the scan voltage Vsc according to the present invention, i.e., less than 90a, the voltage 91b of both ends of the scan voltage power is stabilized. Able to know.

FIG. 9B illustrates a case in which the highest voltage Vramp of the reset signal is set smaller than that in FIG. 9A, and in the case of the reset signal 92a falling from the highest voltage Vramp to the scan voltage Vsc, the voltages of both ends of the scan voltage power supply. It can be seen that 93a is more unstable than the case of FIG. 9A. In the case of the reset signal 92b falling from the highest voltage Vramp to a voltage larger than the scan voltage Vsc, the voltage 93b of both ends of the scan voltage power source is stabilized.

FIG. 9C illustrates a case in which the highest voltage Vramp of the reset signal is set smaller than that of FIG. 9B. In the case of the reset signal 94a falling from the highest voltage Vramp to the scan voltage Vsc, the voltages of both ends of the scan voltage power supply are shown. It can be seen that 95a is more unstable than the case of FIG. 9B. The reset signal 94b according to the present invention shown in FIG. 9C is a case where little or very little energy is recovered to the source capacitor Cs in the energy recovery period ER_down, and in this case, the voltages across both ends of the scan voltage power supply 95b. ) Is stable.

10A to 10C are graphs of voltages across the scan voltage power supply when the reset signals having the waveforms shown in FIGS. 7A and 7B are applied to the panel.

Referring to FIG. 10A, in the case of the reset signal 96a falling from the highest voltage Vramp to the scan voltage Vsc, the voltage 97a at both ends of the scan voltage power source is very unstable, but the highest voltage Vramp according to the present invention. From the reset signal 96b falling down to a voltage greater than the scan voltage Vsc, it can be seen that the voltage 97b of both ends of the scan voltage power source is stabilized.

FIG. 10B illustrates a case in which the highest voltage Vramp of the reset signal is set smaller than that in FIG. 10A, and in the case of the reset signal 98a falling from the highest voltage Vramp to the scan voltage Vsc, the voltages of both ends of the scan voltage power supply. Although the 99a is more unstable than in FIG. 10a, in the case of the reset signal 98b that drops from the highest voltage Vramp to a voltage greater than the scan voltage Vsc according to the present invention, the voltage 99b of both ends of the scan voltage power supply. It can be seen that this is stable.

FIG. 10C illustrates a case in which the highest voltage Vramp of the reset signal is set smaller than that of FIG. 10B, and in the case of the reset signal 100a falling from the highest voltage Vramp to the scan voltage Vsc, the voltages of both ends of the scan voltage power supply. It can be seen that 101a is more unstable than in the case of FIG. The reset signal 100b according to the present invention illustrated in FIG. 10C is a case in which the energy recovered to the source capacitor Cs is little or very small in the energy recovery period ER_down, and in this case, the voltage across both ends of the scan voltage power supply 101b. ) Is stable.

Although a preferred embodiment of the present invention has been described in detail above, those skilled in the art to which the present invention pertains can make various changes without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

According to the plasma display device according to the present invention configured as described above, when the reset signal is applied to the plasma display panel, the scan by removing the sustain voltage after recovering energy from the panel in the falling section of the reset signal and removing the scan voltage, The voltage across the voltage power source can be stabilized, thereby improving the reliability of the plasma display device. In addition, the waveform of the signal for driving the plasma display panel may be prevented from being distorted, thereby improving the image quality of the display image.

Claims (20)

A plasma display panel including a plurality of discharge cells; And a driving unit configured to apply a reset signal to the panel to initialize the plurality of discharge cells. The reset signal gradually increases from a first voltage to a second voltage; A falling period in which the voltage falls from the second voltage to a third voltage; And a set-down period of gradually descending from the third voltage to a fourth voltage. The falling section includes a first falling section falling from the second voltage to the fifth voltage, And the second voltage is greater than the scan voltage and less than the sum of the scan voltage and the sustain voltage, and the fifth voltage is greater than the scan voltage. delete The method of claim 1, wherein the falling section And a second falling period falling from the fifth voltage to the third voltage. The method of claim 3, wherein the second falling section And a section falling from the fifth voltage to the sixth voltage by a scan voltage and a section falling from the sixth voltage to the third voltage. The method of claim 3, wherein the falling section And a section for maintaining the fifth voltage for a predetermined time between the first falling section and the second falling section. The method of claim 5, And said predetermined time is 40 ms or less. The method of claim 1, wherein the falling section And a section rising from the fifth voltage to a seventh voltage and a section falling from the seventh voltage to the fourth voltage. The method of claim 7, wherein And the difference between the seventh voltage and the fourth voltage is a sustain voltage. The method of claim 7, wherein And a section of rising from the fifth voltage to the seventh voltage is 8 to 12 kHz. The method of claim 7, wherein And the seventh voltage is smaller than the second voltage. The method of claim 1, wherein the setup interval is A first setup period gradually increasing from the first voltage to an eighth voltage and a second setup period gradually rising from the ninth voltage to the second voltage, And the ninth voltage has a smaller value than the eighth voltage. A plasma display apparatus comprising a plasma display panel including a plurality of discharge cells, and a driver for applying a reset signal for initializing the plurality of discharge cells to the panel. The driving unit includes an energy recovery unit including a fifth switch turned on to supply energy stored in a source capacitor to the panel, and a sixth switch turned on to recover energy from the panel; A sustain driver including a third switch turned on to apply a sustain voltage to the panel and a fourth switch turned on to apply a ground voltage to the panel; And A scan IC for delivering outputs of the energy recovery and sustain drivers to the panel, the scan IC including a first switch turned on to apply a scan voltage to the panel and a second switch turned on to apply a ground voltage to the panel Including, In the falling section of the reset signal, the second switch is turned on after the sixth switch is turned on, and the fourth switch is turned on between the turn-on time of the sixth switch and the turn-on time of the second switch. Plasma display device characterized in that. The method of claim 12, And the voltage of the reset signal at the time when the sixth switch is turned on is greater than the scan voltage and has a value smaller than the sum of the scan voltage and the sustain voltage. The method of claim 12, And the fourth switch is turned on after the second switch is turned on. The method of claim 12, And the fifth switch is turned on in a state in which the first switch and the second switch are floating after the sixth switch is turned on. The method of claim 15, And the second switch is turned on after the fifth switch is turned on. The method of claim 16, And the fifth switch and the third switch are sequentially turned on after the second switch is turned on. The method of claim 15, wherein the scan IC A first diode connected in parallel with the first switch; And Further comprising a second diode connected in parallel with the second switch, And when the fifth switch is turned on while the first and second switches are in a floating state, energy is supplied to the panel through the second diode. The method of claim 16, And a voltage at both ends of the second switch at the time when the second switch is turned on. The method of claim 15, The time for which the first and second switches are floated is 8 to 12 ms.

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