KR100806309B1 - Plasma display apparatus - Google Patents

Abstract

The present invention relates to a plasma display apparatus including a plasma display panel including a plurality of discharge cells, the apparatus comprising: a first display in a reset section for initializing the plurality of discharge cells; The first signal rising from the voltage to the second voltage and the second signal falling from the second voltage to the third voltage are applied to the sustain electrode and the scan electrode as the second signal is applied to the sustain electrode. Characterized in that the voltage of the reset signal is applied to fall.

According to the present invention, when a reset signal is applied to the plasma display panel, the voltages at both ends of the switch to be turned on are reduced by floating the switches included in the scan IC and then applying a falling signal to the sustain electrode. By doing so, it is possible to prevent shorts occurring when switching of the scan IC is changed, thereby improving the reliability of the plasma display apparatus. In addition, the waveform of the signal for driving the plasma display panel may be prevented from being distorted, thereby improving the image quality of the display image.

Description

 Plasma display apparatus

1 is a perspective view showing an embodiment of a plasma display panel according to the present invention.

2 is a diagram illustrating an embodiment of an electrode arrangement of a plasma display panel.

3 is a timing diagram illustrating an embodiment of a time division driving method by dividing a frame into a plurality of subfields.

FIG. 4 is a timing diagram illustrating an embodiment of driving signals for driving a plasma display panel with respect to the divided subfield.

5A and 5B illustrate an exemplary embodiment of waveforms of driving signals applied to scan electrodes and sustain electrodes of a plasma display panel in a reset period.

6A to 6E are circuit diagrams showing the configuration of the scan driving circuit for applying the reset signal shown in FIGS. 5A and 5B to the scan electrode and the current flow of the driving circuit.

7A to 7D are circuit diagrams showing the configuration of the sustain drive circuit for applying the drive signal shown in FIG. 5B to the sustain electrode and the current flow of the drive circuit.

The present invention relates to a plasma display device, and more particularly, to a plasma display device including a driving device for applying a reset signal to a plasma display panel to initialize a plurality of discharge cells. will be.

BACKGROUND ART In general, a plasma display panel is an apparatus that displays an image by applying a predetermined voltage to electrodes provided in a discharge space and causing a discharge, and the plasma generated during gas discharge excites a phosphor.

Such a plasma display panel is not only large in size and thin in thickness, but also has a simple structure, which makes the plasma display panel easier to manufacture and has a higher luminance and higher luminous efficiency than other flat panel display devices.

The plasma display panel is time-divisionally driven into a reset section for initializing all the discharge cells, an address section for selecting a cell in which discharge is to be generated, and a sustain section for generating sustain discharge in the selected cell. . Also, in general, the reset period is a setup period that gradually rises from the first voltage to the second voltage, a falling period that rapidly falls from the second voltage to the third voltage, and gradually falls from the third voltage to the fourth voltage. It is divided into a set-down section.

In general, a plasma display device includes a scan IC having a scan-up switch and a scan-down switch that alternately operate to apply a reset signal to a scan electrode. When the switching is changed between the scan-up switch and the scan-down switch in the scan IC, the switch may be shorted to generate a peaking current.

In order to solve the above problems in the plasma display device, a technical problem of the present invention is to prevent short circuits during switching changes, thereby improving the reliability of the scan IC and preventing distortion of the waveform of the reset signal. It is an object to provide a plasma display device.

According to an aspect of the present invention, there is provided a plasma display apparatus including: a plasma display panel including a plurality of discharge cells and having a scan electrode and a sustain electrode formed thereon; And a driving unit configured to apply a reset signal to the scan electrode for initializing the plurality of discharge cells in a reset period, wherein the first signal and the second signal rise from the first voltage to the second voltage in the reset period. A second signal falling from a second voltage to a third voltage is applied to the sustain electrode, and as the second signal is applied to the sustain electrode, the voltage of the reset signal applied to the scan electrode decreases.

Preferably, at least one of the first and third voltages is a ground voltage, and the second voltage is preferably 50 to 250V, more preferably 150 to 210V.

As the second signal is applied to the sustain electrode, the reset signal is preferably lowered by 25 to 125V, more preferably 75 to 105V.

Preferably, the reset signal comprises: a setup period for gradually increasing from the fourth voltage to the fifth voltage; A falling section that falls from the fifth voltage to a sixth voltage; And a set-down period that gradually decreases from the sixth voltage to the seventh voltage, wherein the first signal is applied to the sustain electrode at any point in the setup period of the reset signal, and the second electrode is connected to the sustain electrode. As the signal is applied, the reset signal may drop from the fifth voltage to the eighth voltage.

Preferably, the first signal is applied to the sustain electrode in a section in which the reset signal maintains the second voltage.

Preferably, the falling period includes a first falling period falling from the fifth voltage to the eighth voltage, a second falling period falling from the eighth voltage to a ninth voltage, and a voltage falling from the ninth voltage to the tenth voltage. The falling pulse includes a third falling period, and the reset pulse is dropped by 0 to 50V during the second falling period and is lowered by 150 to 210V during the third falling period.

Another plasma display device according to the present invention for solving the above technical problem is a scan-up switch turned on to apply a scan voltage to the scan electrode and a scan- turned on to apply a ground voltage to the scan electrode. A first driver including a scan IC having a down switch; And sustain the first signal rising from the first voltage to the second voltage and the second signal falling from the second voltage to the third voltage while the scan-up switch and the scan-down switch are floating. And a second driving part applied to the electrode.

Preferably, the second signal is lowered by 150 to 210V, and as the second signal is applied to the sustain electrode, the reset signal applied to the scan electrode is lowered by 75 to 105V.

The second driving unit includes an energy recovery unit including an energy supply switch turned on to supply energy stored in a source capacitor to the sustain electrode and an energy recovery switch turned on to recover energy from the sustain electrode; And a sustain driver including a sustain-up switch turned on to apply a sustain voltage to the sustain electrode, and a sustain-down switch turned on to apply a ground voltage to the sustain electrode.

Preferably, the energy supply switch and the sustain switch are sequentially turned on to apply the first signal to the sustain electrode, and the energy recovery switch and the sustain switch are sequentially turned on to the sustain electrode. The second signal is applied.

The first driving unit includes an energy recovery unit including an energy supply switch turned on to supply energy stored in a source capacitor to the scan electrode and an energy recovery switch turned on to recover energy from the scan electrode; And a sustain driver including a sustain-up switch turned on to apply a sustain voltage to the scan electrode, and a sustain-down switch turned on to apply a ground voltage to the scan electrode.

Preferably, the scan driver includes an energy recovery unit including an energy supply switch turned on to supply energy stored in a source capacitor to the scan electrode and an energy recovery switch turned on to recover energy from the scan electrode; And a sustain driver including a sustain-up switch turned on to apply a sustain voltage to the scan electrode, and a sustain-down switch turned on to apply a ground voltage to the scan electrode.

Preferably, the scan-up switch and the scan-down switch are floated after the sus-up switch and the scan-up switch are turned on, and the scan after the scan-up switch and the scan-down switch are floated. Preferably, the -down switch is turned on. Preferably, the energy recovery switch and the sus-down switch are sequentially turned on after the scan-down switch is turned on.

Preferably, the voltage between both ends of the scan-down switch is 40V or less when the scan-down switch is turned on.

The scan IC may include a first diode connected in parallel with the scan-up switch; And a second diode connected in parallel with the scan-down switch, wherein current flows through the first diode while the first signal is applied to the sustain electrode, and the second signal is sustained. Preferably, current flows through the second diode while being applied to the electrode.

Hereinafter, a plasma display device according to the present invention will be described in detail with reference to the accompanying drawings. 1 is a perspective view showing an embodiment of a plasma display panel according to the present invention.

As shown in FIG. 1, the plasma display panel includes a scan electrode 11, a sustain electrode 12, a sustain electrode pair formed on the upper substrate 10, and an address electrode 22 formed on the lower substrate 20. It includes.

The sustain electrode pairs 11 and 12 generally include transparent electrodes 11a and 12a and bus electrodes 11b and 12b formed of indium tin oxide (ITO), and the bus electrodes 11b and 12b. 12b) may be formed of a metal such as silver (Ag) or chromium (Cr) or a stack of chromium / copper / chromium (Cr / Cu / Cr) or a stack of chromium / aluminum / chromium (Cr / Al / Cr). . The bus electrodes 11b and 12b are formed on the transparent electrodes 11a and 12a to serve to reduce voltage drop caused by the transparent electrodes 11a and 12a having high resistance.

Meanwhile, according to the exemplary embodiment of the present invention, the sustain electrode pairs 11 and 12 may not only have a structure in which the transparent electrodes 11a 12a and the bus electrodes 11b and 12b are stacked, but also the buses without the transparent electrodes 11a and 12a. Only the electrodes 11b and 12b may be configured. This structure does not use the transparent electrodes (11a, 12a), there is an advantage that can lower the cost of manufacturing the panel. The bus electrodes 11b and 12b used in this structure may be various materials such as photosensitive materials in addition to the materials listed above.

Light between the scan electrodes 11 and the sustain electrodes 12 between the transparent electrodes 11a and 12a and the bus electrodes 11b and 11c to absorb external light generated outside the upper substrate 10 to reduce reflection. A black matrix (BM, 15) is arranged that functions to block and to improve the purity and contrast of the upper substrate 10.

The black matrix 15 according to the exemplary embodiment of the present invention is formed on the upper substrate 10, the first black matrix 15 and the transparent electrodes 11a and 12a formed at positions overlapping the partition wall 21. And the second black matrices 11c and 12c formed between the bus electrodes 11b and 12b. Here, the first black matrix 15 and the second black matrices 11c and 12c, also referred to as black layers or black electrode layers, may be simultaneously formed and physically connected in the formation process, or may not be simultaneously formed and thus not physically connected. .

In addition, when physically connected and formed, the first black matrix 15 and the second black matrix 11c and 12c may be formed of the same material, but may be formed of different materials when they are formed separately.

The upper dielectric layer 13 and the passivation layer 14 are stacked on the upper substrate 10 having the scan electrode 11 and the sustain electrode 12 side by side. Charged particles generated by the discharge are accumulated in the upper dielectric layer 13, and the protective electrode pairs 11 and 12 may be protected. The protective film 14 protects the upper dielectric layer 13 from sputtering of charged particles generated during gas discharge, and increases emission efficiency of secondary electrons.

In addition, the address electrode 22 is formed in a direction crossing the scan electrode 11 and the sustain electrode 12. In addition, the lower dielectric layer 23 and the partition wall 21 are formed on the lower substrate 20 on which the address electrode 22 is formed.

In addition, phosphor layers are formed on the surfaces of the lower dielectric layer 23 and the partition wall 21. The partition wall 21 has a vertical partition wall 21a and a horizontal partition wall 21b formed in a closed shape, and physically distinguishes discharge cells, and prevents ultraviolet rays and visible light generated by the discharge from leaking into adjacent discharge cells.

In an embodiment of the present invention, not only the structure of the partition wall 21 illustrated in FIG. 1, but also the structure of the partition wall 21 having various shapes may be possible. For example, a channel in which a channel usable as an exhaust passage is formed in at least one of the differential partition structure, the vertical partition 21a, or the horizontal partition 21b having different heights of the vertical partition 21a and the horizontal partition 21b. A grooved partition structure having a groove formed in at least one of the type partition wall structure, the vertical partition wall 21a, or the horizontal partition wall 21b may be possible.

Here, in the case of the differential partition wall structure, the height of the horizontal partition wall 21b is more preferable, and in the case of the channel partition wall structure or the groove partition wall structure, it is preferable that a channel is formed or the groove is formed in the horizontal partition wall 21b. something to do.

Meanwhile, in one embodiment of the present invention, although the R, G and B discharge cells are shown and described as being arranged on the same line, it may be arranged in other shapes. For example, a Delta type arrangement in which R, G, and B discharge cells are arranged in a triangular shape may be possible. In addition, the shape of the discharge cell may be not only rectangular, but also various polygonal shapes such as a pentagon and a hexagon.

In addition, the phosphor layer emits light by ultraviolet rays generated during gas discharge to generate visible light of any one of red (R), green (G), and blue (B). Here, an inert mixed gas such as He + Xe, Ne + Xe and He + Ne + Xe for discharging is injected into the discharge space provided between the upper and lower substrates 10 and 20 and the partition wall 21.

FIG. 2 illustrates an embodiment of an electrode arrangement of a plasma display panel, and a plurality of discharge cells constituting the plasma display panel are preferably arranged in a matrix form as shown in FIG. 2. The plurality of discharge cells are provided at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn, respectively. The scan electrode lines Y1 to Ym may be driven sequentially or simultaneously, and the sustain electrode lines Z1 to Zm may be driven simultaneously. The address electrode lines X1 to Xn may be driven by being divided into odd-numbered lines and even-numbered lines, or sequentially driven.

Since the electrode arrangement shown in FIG. 2 is only an embodiment of the electrode arrangement of the plasma panel according to the present invention, the present invention is not limited to the electrode arrangement and driving method of the plasma display panel shown in FIG. 2. For example, a dual scan method in which two scan electrode lines among the scan electrode lines Y1 to Ym are simultaneously scanned is possible. In addition, the address electrode lines X1 to Xn may be driven by being divided up and down in the center portion of the panel.

3 is a timing diagram illustrating an embodiment of a time division driving method by dividing a frame into a plurality of subfields. The unit frame may be divided into a predetermined number, for example, eight subfields SF1, ..., SF8 to realize time division gray scale display. Each subfield SF1, ... SF8 is divided into a reset section (not shown), an address section A1, ..., A8 and a sustain section S1, ..., S8.

Here, according to an embodiment of the present invention, the reset period may be omitted in at least one of the plurality of subfields. For example, the reset period may exist only in the first subfield or may exist only in a subfield about halfway between the first subfield and all the subfields.

In each address section A1, ..., A8, a display data signal is applied to the address electrode X, and scan pulses corresponding to each scan electrode Y are sequentially applied.

In each of the sustain periods S1, ..., S8, a sustain pulse is alternately applied to the scan electrode Y and the sustain electrode Z to form wall charges in the address periods A1, ..., A8. Sustain discharge occurs in the discharge cells.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge periods S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gradations, each subfield in turn has different sustains at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128. The number of pulses can be assigned. In order to obtain luminance of 133 gradations, cells may be sustained by addressing the cells during the subfield 1 section, the subfield 3 section, and the subfield 8 section.

The number of sustain discharges allocated to each subfield may be variably determined according to weights of the subfields according to the APC (Automatic Power Control) step. That is, in FIG. 3, a case in which one frame is divided into eight subfields has been described as an example. However, the present invention is not limited thereto, and the number of subfields forming one frame may be variously modified according to design specifications. . For example, a plasma display panel may be driven by dividing one frame into eight or more subfields, such as 12 or 16 subfields.

The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34.

4 is a timing diagram illustrating an embodiment of driving signals for driving a plasma display panel with respect to the divided subfield.

The subfield is a wall formed by a pre-reset section and a pre-reset section for forming positive wall charges on the scan electrodes Y and negative wall charges on the sustain electrodes Z. A reset section for initializing the discharge cells of the entire screen using the charge distribution, an address section for selecting the discharge cells, and a sustain section for maintaining the discharge of the selected discharge cells.

The reset section includes a progressively rising setup section, a rapidly descending descending section, and a progressively descending setdown section, in which the ramp ramp is applied to all scan electrodes. Simultaneously applied, fine discharge is generated in all the discharge cells, thereby generating wall charges. In the falling section, the voltage drops rapidly from the voltage at which the set-up section ends to the voltage at which the set-down section begins. In the set-down period, a falling ramp waveform (Ramp-down) falling at a positive voltage lower than the highest voltage Vramp of the rising ramp waveform Ramp-up is simultaneously applied to all scan electrodes (Y), thereby An erase discharge is generated, thereby erasing unnecessary charges during wall charges and space charges generated by the setup discharges.

As shown in FIG. 4, signals 400, 410, and 420 having a voltage of 50 to 250V are applied to the sustain electrodes Z during the reset period. Preferably, the signals 400, 410, and 420 applied to the sustain electrodes Z are 150 to 210 V, and more preferably, the signals 400, 410, and 420 are alternately applied to the scan electrode Y and the sustain electrode Z during the sustain period. It is preferable that it is the same as the sustain voltage Vsus which is the voltage of the sustain signal. The timings and voltage levels of the signals 400, 410, and 420 applied to the sustain electrodes Z will be described in detail with reference to FIGS. 5A through 7D.

In the address period, a negative scan signal having a magnitude of the scan voltage Vsc is sequentially applied to the scan electrode, and at the same time, a positive data signal data is applied to the address electrode X. The address discharge is generated by the voltage difference between the scan signal and the data signal data and the wall voltage generated during the reset period, thereby selecting the cell. Meanwhile, a signal for maintaining a sustain voltage Vsus is applied to the sustain electrode during the setdown period and the address period.

In the sustain period, a sustain signal having a sustain voltage Vsus is alternately applied to the scan electrode and the sustain electrode, thereby generating sustain discharge in the form of surface discharge between the scan electrode and the sustain electrode.

The driving waveforms shown in FIG. 4 are examples of signals for driving the plasma display panel according to the present invention, and the present invention is not limited by the waveforms shown in FIG. 4. For example, the pre-reset period may be omitted, and the polarity and the voltage level of the driving signals illustrated in FIG. 4 may be changed as necessary, and an erase signal for erasing wall charge may be applied to the sustain electrode after the sustain discharge is completed. It may be. In addition, the single sustain driving may be performed by applying the sustain signal to only one of the scan electrode (Y) and the sustain (Z) electrode to generate a sustain discharge.

5A and 5B illustrate an embodiment of waveforms of driving signals applied to scan electrodes and sustain electrodes of a plasma display panel during a reset period. FIG. 5A illustrates scans during a reset period among the driving signals shown in FIG. 4. The reset signal applied to the electrode Y is shown in more detail.

As shown in FIG. 5A, the setup section preferably includes a first setup section that gradually rises from the ground voltage and a second setup section that gradually rises to the highest voltage Vramp.

After the reset signal rises to the highest voltage Vramp, a falling period in which the reset signal rapidly falls from the highest voltage Vramp to the ground voltage is followed. In the set down period, the reset signal gradually falls from the ground voltage.

FIG. 5B illustrates in detail the waveform of the falling section 500 and the waveform of the signal applied to the sustain electrode during the reset section of the reset signal shown in FIG. 5A. As shown in FIG. 5B, the reset signal applied to the scan electrode maintains the highest voltage (Vramp) and then drops down to the floating period and sustain voltage (Vsus), which are lowered by a predetermined voltage (Vf). (SCAN_down) section, the scan driving circuit recovers energy from the scan electrode and includes a recovery section (ER_down) in which the reset signal gradually falls from the sustain voltage (Vsus) and a sustain down (SUS_down) section in which the voltage falls rapidly to the ground voltage. do.

As shown in FIG. 5B, a signal rising to the sustain voltage Vsus is applied to the sustain electrode while the reset signal applied to the scan electrode maintains the highest voltage Vramp, and the sustain voltage Vsus is applied for a predetermined time. A signal that maintains and falls to ground voltage is applied to the sustain electrode. As the voltage applied to the sustain electrode falls from the sustain voltage Vsus to the ground voltage, the voltage of the reset signal applied to the scan electrode drops by Vf.

Since the output terminal of the scan driving circuit for applying the reset signal to the scan electrode is floating, the voltage applied to the sustain electrode is lowered due to the capacitance of the panel including the scan and sustain electrodes. The output terminal voltage of the scan driving circuit applied is reduced. In this case, the magnitude of the falling voltage of the reset signal applied to the scan electrode is about 1/2 of the magnitude of the falling voltage of the signal applied to the sustain electrode. That is, when the signal applied to the sustain electrode falls 50 to 250V, the reset signal falls 25 to 125V. When the signal applied to the sustain electrode falls 150 to 210V, the reset signal falls 75 to 105V and is applied to the sustain electrode. When the signal to be lowered by the sustain voltage (Vsus), the reset signal is lowered by 1/2 of the sustain voltage.

Referring to FIGS. 6A to 6F, a circuit diagram illustrating a configuration of a scan driving circuit and a current flow of the driving circuit according to an embodiment of the present invention may be described in detail with respect to the operation of the scan driving circuit in the falling section 500 of the reset signal illustrated in FIG. 5B. This will be described.

As shown in FIG. 6A, the scan driving circuit according to the present invention includes an energy recovery unit 20, a sustain driver 30, a reset driver 40, and a scan IC 50.

The sustain driver 30 includes a sustain voltage power supply Vsus for supplying a high potential sustain voltage Vsus during the sustain period, and a sustain-up switch Su_up turned on so that the sustain voltage Vsus is applied to the scan electrode 10. And a sus-down switch Su_dn turned on to drop to the ground voltage applied to the scan electrode 10. That is, the sustain driver 30 is connected to the sustain voltage power supply Vsus and the sustain-up switch Su_up is connected to the sustain switch Sus_up and ground.

The energy recovery unit 20 recovers the source capacitor Cs and the capacitor Cs to recover and supply the energy supplied to the scan electrode 10 so that the energy stored in the source capacitor Cs is supplied to the scan electrode 10. An energy recovery switch ER_up which is turned on and an energy recovery switch ER_dn which are turned on to recover energy from the scan electrode 10 are included.

The reset driver 40 is connected to the set-up switch Set_up and the negative voltage -Vy, which are turned on to supply a gradually rising set-up signal to the scan electrode 10, up to the negative voltage -Vy. The set-down switch Set_dn is turned on to supply the progressively descending setdown signal to the scan electrode 10, and the pass switch Pass_sw forming a current path path with the scan electrode 10.

As shown in FIG. 6A, the set-up switch Set_up has a drain connected to a sustain voltage power supply, a source connected to a pass switch Pass_sw, and a gate connected to a variable resistor. And a setup signal which gradually rises as the resistance value of the variable resistor changes.

The set-down switch Set_dn has a drain connected to the scan IC 50, a source connected to a negative voltage (-Vy), and a variable resistor (not shown) connected to the gate. As the resistance value of the variable resistor (not shown) changes, a setdown signal that gradually decreases is generated.

The scan IC 50 is connected to a scan voltage power source and turned on to apply a ground voltage to the scan electrode 10 and the scan-up switch Q1 which is turned on to apply the scan voltage Vsc to the scan electrode 10. And a scan-down switch Q2. In addition, the scan IC 50 includes a first diode D1 connected in parallel with the scan-up switch Q1 and a second diode D2 connected in parallel with the scan-down switch Q2.

As shown in FIG. 6A, the first diode D1 has a cathode connected to the drain of the scan-up switch Q1 and an anode of the source of the scan-up switch Q1. Source is connected to the second diode (D2), the cathode (Cathode) is connected to the drain (Drain) of the scan-down switch (Q2) and the anode (Anode) source of the scan-down switch (Q2) ).

FIG. 6A illustrates a current flow in a floating section of the falling section of the reset signal illustrated in FIG. 5B. As shown in FIG. 6A, in the floating period, current flows from the sustain voltage source and the scan voltage source toward the scan electrode 10, and the scan-up switch Q1 and the scan-down switch Q2 are generated. Is floating, that is, turned off so that the current flows to the scan electrode 10 through a first diode D1 connected in parallel to the scan-up switch Q1. Accordingly, the voltage of the reset signal applied to the scan electrode 10 maintains the highest voltage Vramp before the floating period. In the floating period, the scan-up switch Q1 and the scan-down switch Q2 are turned off for the above operation, and the sus-up switch Sus-up and the pass switch Pass_sw are turned on. do.

While the reset signal maintains the highest voltage Vramp, a signal rising from the ground voltage to the sustain voltage Vsus is applied to the sustain electrode, in which case the voltage of the reset signal applied to the scan electrode 10 hardly changes. . After that. The voltage applied to the sustain electrode maintains the sustain voltage Vsus for a predetermined time and then falls back to the ground voltage.

FIG. 6B illustrates the current flow of the scan driving circuit when the voltage applied to the sustain electrode in the floating period falls from the sustain voltage Vsus to the ground voltage. As shown in FIG. 6B, when the voltage applied to the sustain electrode falls while the scan-up switch Q1 and the scan-down switch Q2 are floated, the first and second switches connected to the scan-down switch Q2 in parallel are connected. A current flow from the scan electrode 10 in the direction of the sustain voltage power supply is formed through the two diodes D2. Therefore, as the voltage applied to the sustain electrode drops, the voltage of the reset signal applied to the scan electrode 10 drops.

As the voltage of the reset signal applied to the scan electrode 10 drops, the voltage between the scan-down switch Q2 and both ends decreases, and preferably, the voltage between the scan-down switch Q2 and both ends is 40V or less. Decreases. When the voltage between both ends of the scan-down switch Q2 is reduced to 40V or less, it is possible to prevent the occurrence of the peaking current due to a short circuit when the scan-down switch Q2 is turned on in the next scan down period SCAN_down.

Referring to FIG. 6C, in the scan down (SCAN_down) period, the scan-down switch Q2, the pass switch Pass_sw and the energy recovery switch ER_dn are turned on so that the current flows from the scan electrode 10 toward the source capacitor Cs. Flows, and the voltage of the reset signal drops rapidly to the sustain voltage Vsus.

Referring to FIG. 6D, in the energy recovery period ER_down, energy is recovered from the scan electrode 10 to the source capacitor Cs of the energy recovery unit 20 so that the current in the direction of the source capacitor Cs from the scan electrode 10 is reduced. A flow is generated, whereby the voltage of the reset signal applied to the scan electrode 10 is lowered from the sustain voltage Vsus. In the energy recovery period ER_down, the scan-down switch Q1, the pass switch Pass_sw and the energy recovery switch ER_dn are turned on for the current flow as described above.

Referring to FIG. 6E, the energy recovery switch ER_dn is turned off, the scan-down switch Q2, the pass switch Pass_sw and the sus-down switch Sus_dn are turned on in the scan down period SUS_down, and the scan electrode is turned on. The current flows from (10) to the ground connected to the sus-down switch Su_dn, whereby the voltage of the reset signal drops to the ground voltage.

7A to 7D show a circuit diagram of a configuration of a sustain driving circuit and a current flow of the driving circuit for applying the driving signal shown in FIG. 5B to the sustain electrode. As shown in FIG. 7A, the sustain driving circuit according to the present invention includes an energy recovery unit 60 and a sustain driving unit 70.

The sustain driver 70 includes a sustain voltage power supply Vsus for supplying a high potential sustain voltage Vsus during the sustain period, and a sustain-up switch Sus_up turned on such that the sustain voltage Vsus is applied to the sustain electrode 80. And a sus-down switch Su_dn turned on so that the voltage applied to the sustain electrode 80 drops to the ground voltage. That is, in the sustain driver 70, the sus-up switch Su_up is connected to the sustain voltage power supply Vsus, and the sus-down switch Su_dn is connected to the sus-up switch Sus-up and ground.

The energy recovery unit 60 may include a source capacitor Cs for recovering and storing energy supplied to the sustain electrode 80, and an energy supply switch that is turned on so that energy stored in the source capacitor Cs is supplied to the sustain electrode 80 ( ER_up) and an energy recovery switch ER_dn which is turned on to recover energy from the sustain electrode 80.

Hereinafter, an embodiment of a method of generating the sustain electrode driving signal illustrated in FIG. 4 or 5B will be described with reference to FIGS. 7A to 7D.

Referring to FIG. 7A, the energy supply switch ER_up is turned on during the energy supply period ER_up, and current flows from the source capacitor Cs toward the sustain electrode 80. As a result, energy stored in the source capacitor Cs is supplied to the sustain electrode 80, thereby increasing the voltage of the signal applied to the sustain electrode 80.

Referring to FIG. 7B, after the supply of energy from the source capacitor Cs to the sustain electrode 80 is finished, the sustain-up switch Sus-up is turned on during the sustain period SUS-up so that the sustain voltage power supply is turned on. The current flows from the sustain electrode 80 toward the sustain electrode 80 so that the signal applied to the sustain electrode 80 rises rapidly until the sustain voltage Vsus is maintained.

Referring to FIG. 7C, the energy recovery switch ER_dn is turned on during the energy recovery period ER_down, so that a current flows from the sustain electrode 80 toward the source capacitor Cs. As a result, energy is recovered from the sustain electrode 80 to the source capacitor Cs, and a signal applied to the sustain electrode 80 is lowered from the sustain voltage Vsus.

Referring to FIG. 7D, the sus-down switch Su_dn is turned on during the sus-down period SUS_down, so that current flows from the sustain electrode 80 to the ground connected to the sus-down switch Su_dn, and thus the sustain electrode. The signal applied to 80 drops rapidly to the ground voltage.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art to which the present invention pertains should make the present invention without departing from the spirit and scope of the present invention as defined in the appended claims. It will be appreciated that various modifications or changes can be made. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

According to the plasma display device according to the present invention configured as described above, when applying a reset signal to the plasma display panel, both ends of the switch to turn on by applying a falling signal to the sustain electrode after floating the switches provided in the scan IC By reducing the voltage, it is possible to prevent a short circuit occurring when the switching of the scan IC is changed, thereby improving the reliability of the plasma display device. In addition, the waveform of the signal for driving the plasma display panel may be prevented from being distorted, thereby improving the image quality of the display image.

Claims (20)

A plasma display panel including a plurality of discharge cells and having a scan electrode and a sustain electrode formed thereon; And a driving unit configured to apply a reset signal to the scan electrode for initializing the plurality of discharge cells in a reset period. In the reset section, A setup period in which the voltage gradually rises from the fourth voltage to the fifth voltage; A holding period for maintaining the fifth voltage for a predetermined time, and a falling period for falling from the fifth voltage to the sixth voltage; And a reset signal including a set down period that gradually descends from the sixth voltage to the seventh voltage, and is applied to the scan electrode. After a first signal rising from a first voltage to a second voltage is applied to the sustain electrode at any point in the sustain period, a second signal falling from the second voltage to a third voltage is applied to the sustain electrode. Become, And the voltage of the reset signal applied to the scan electrode decreases as the second signal is applied to the sustain electrode in the falling section. The method of claim 1, At least one of the first and third voltages is a ground voltage. The method of claim 1, wherein the second voltage is Plasma display device, characterized in that 50 to 250V. The method of claim 1, wherein the second voltage is Plasma display device, characterized in that 150 to 210V. The method of claim 1, And the reset signal drops by 25 to 125V as the second signal is applied to the sustain electrode. The method of claim 1, And the reset signal drops by 75 to 105V as the second signal is applied to the sustain electrode. delete delete The method of claim 1, wherein the falling period of the reset signal applied to the scan electrode A first falling period falling from the fifth voltage to an eighth voltage, a second falling period falling from the eighth voltage to a ninth voltage, and a third falling period falling from the ninth voltage to the tenth voltage; , And the reset signal falls by 0 to 50V during the second falling period. The method of claim 9, wherein the reset signal applied to the scan electrode And descending by 150 to 210V during the third falling period. A plasma display panel including a plurality of discharge cells and having a scan electrode and a sustain electrode formed thereon; And a first driver configured to apply a reset signal to the scan electrode to initialize the plurality of discharge cells. A first driver including a scan-up switch turned on to apply a scan voltage to the scan electrode and a scan-down switch turned on to apply a ground voltage to the scan electrode; And While the scan-up switch and the scan-down switch are floating, a first signal rising from a first voltage to a second voltage and a second signal falling from the second voltage to a third voltage are sustained. And a second driving unit applied to the electrode. The method of claim 11, wherein the second signal is Plasma display device, characterized in that descending by 150 to 210V. The method of claim 11, And as the second signal is applied to the sustain electrode, the reset signal applied to the scan electrode drops by 75 to 105 volts. The method of claim 11, wherein the second drive unit An energy recovery unit including an energy supply switch turned on to supply energy stored in a source capacitor to the sustain electrode, and an energy recovery switch turned on to recover energy from the sustain electrode; And A sustain driver including a sustain-up switch turned on to apply a sustain voltage to the sustain electrode, and a sustain-down switch turned on to apply a ground voltage to the sustain electrode; The energy supply switch and the sustain switch are sequentially turned on to apply the first signal to the sustain electrode, and the energy recovery switch and the sustain switch are sequentially turned on to supply the second signal to the sustain electrode. Plasma display device characterized in that is applied. The method of claim 11, wherein the first drive unit An energy recovery unit including an energy supply switch turned on to supply energy stored in a source capacitor to the scan electrode and an energy recovery switch turned on to recover energy from the scan electrode; And And a sustain driver including a sustain-up switch turned on to apply a sustain voltage to the scan electrode, and a sustain-down switch turned on to apply a ground voltage to the scan electrode. The method of claim 15, And the scan-up switch and the scan-down switch are floated after the sus-up switch and the scan-up switch are turned on. The method of claim 15, And after the scan-up switch and the scan-down switch are floated, the scan-down switch is turned on. The method of claim 15, And the energy recovery switch and the sus-down switch are sequentially turned on after the scan-down switch is turned on. The method of claim 17, And the voltage between both ends of the scan-down switch is 40V or less when the scan-down switch is turned on. The method of claim 11, wherein the scan IC A first diode connected in parallel with the scan-up switch; And A second diode connected in parallel with the scan-down switch; A current flows through the first diode while the first signal is applied to the sustain electrode, and a current flows through the second diode while the second signal is applied to the sustain electrode. .

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