KR20060061200A - Method for driving plasma display panel - Google Patents

Abstract

A method of driving a plasma display panel of the present invention is a method of driving a plasma display panel of the present invention, in which a plurality of scan electrode lines are driven by dividing m (m is an integer of 2 or more) into blocks. Applying p (p is a natural number of at least one) first reset pulses having a first voltage to the scan electrode lines belonging to at least one of the m blocks during a frame; Q (q is one or more natural numbers) second reset pulses having a second voltage different from the first voltage are simultaneously applied to the scan electrode lines belonging to the remaining blocks except the one or more blocks during the specific frame. It is characterized by including.

In addition, the reset pulse by the driving device of the plasma display panel including a sustain pulse supply for supplying a sustain voltage, a setup supply for supplying a set-up voltage, a set-down supply for supplying a set-down voltage, a scan bias voltage supply for supplying a scan bias voltage Is formed, the method of driving the plasma display panel according to the present invention includes the step of applying the scan bias voltage to the scan electrode by the scan bias voltage supply, scanning the sustain voltage from the sustain pulse supply while having a first slope through the setup supply The step of applying to the electrode and the setup supply is characterized by applying a ramp voltage having a second slope to the scan electrode.

Description

Method for Driving Plasma Display Panel {Method for Driving Plasma Display Panel}

1 is an enlarged view of one discharge cell constituting a general AC PDP.

2 illustrates a driving waveform of a conventional plasma display panel.

3 is a circuit diagram of a scan electrode driver of a conventional plasma display panel.

4 is a waveform diagram showing a strong discharge reset pulse of the plasma display panel of the present invention.

5 is a waveform diagram showing a weak discharge reset pulse of the plasma display panel of the present invention.

6 is a waveform diagram showing a general reset pulse.

7 is a drive waveform diagram having a selective reset pulse of the plasma display panel of the present invention.

8 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

9 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention.

10 is a driving waveform diagram of a plasma display panel according to a third embodiment of the present invention.

11 is a driving waveform diagram of a plasma display panel according to a fourth embodiment of the present invention.

12 is a driving waveform diagram of a plasma display panel according to a fifth embodiment of the present invention.

FIG. 13 is a driving waveform diagram showing another application method of the strong discharge reset pulse shown in FIG. 12.

14 is a driving waveform diagram of a plasma display panel according to a sixth embodiment of the present invention.

15 is a driving waveform diagram of a plasma display panel according to a seventh embodiment of the present invention.

16 is a driving waveform diagram of a plasma display panel according to an eighth embodiment of the present invention.

The present invention relates to a plasma display panel, and more particularly, to a method of driving a plasma display panel.

Recently, a plasma display panel (Plasma Display Panel) that is easy to manufacture a large panel as a flat panel display device has attracted attention. The plasma display panel normally displays an image by adjusting the gas discharge period of each of the pixels in accordance with digital video data. As the plasma display panel, as shown in FIG. 1, an AC plasma display panel having three electrodes and driven by an AC voltage is representative.

1 is an enlarged view of one discharge cell constituting a general AC plasma display panel. The discharge cell 30 shown in FIG. 1 includes an upper substrate and a lower substrate having scan and sustain electrodes 12A and 12B, an upper dielectric layer 14, and a protective layer 16 sequentially formed on the upper substrate 10. 18, a lower plate having an address electrode 20, a lower dielectric layer 22, a partition wall 24, and a phosphor layer 26 sequentially formed on the substrate 18 is provided.

Each of the scan electrode 12A and the sustain electrode 12B is composed of a transparent electrode and a metal electrode for compensating for the high resistance of the transparent electrode. The scan electrode 12A supplies a scan signal for address discharge and a sustain signal for sustain discharge. The sustain electrode 12B mainly supplies a sustain signal. The address electrode 20 is formed to cross the scan electrode 12A and the sustain electrode 12B. The address electrode 20 supplies a data signal for address discharge.

Charges generated by discharge are accumulated in the upper dielectric layer 14 and the lower dielectric layer 22. The protective film 16 prevents damage to the upper dielectric layer 14 due to sputtering during discharge and increases the emission efficiency of secondary electrons. The dielectric layers 14 and 22 and the protective layer 16 may lower the discharge voltage applied from the outside.

The partition wall 24 provides a discharge space together with the upper and lower substrates 10 and 18. The partition wall 24 is formed in parallel with the address electrode 20 to prevent ultraviolet rays generated by the gas discharge from leaking into adjacent cells.

The phosphor layer 26 is applied to the surfaces of the lower dielectric layer 22 and the partition wall 24 to generate red, green or blue visible light. The discharge space is filled with an inert gas such as He, Ne, Ar, Xe, Kr for gas discharge, a discharge gas having a combination thereof, or an excimer gas capable of generating ultraviolet rays by discharge.

The discharge cell 30 having such a structure is selected as the counter discharge by the address electrode 20 and the scan electrode 12A, and then maintains the discharge by surface discharge by the scan electrode 12A and the sustain electrode 12B. Accordingly, in the discharge cell 30, visible light is emitted by the phosphor 26 emitting light by ultraviolet rays generated during sustain discharge.

In this case, the discharge cell 30 adjusts the sustain discharge period, that is, the number of sustain discharges according to the video data, thereby implementing gray scale required for displaying an image. In addition, a color of one pixel is realized by a combination of three discharge cells coated with red, green, and blue phosphors 26, respectively.

2 illustrates a driving waveform of a conventional plasma display panel. As shown in FIG. 2, the plasma display panel is driven by being divided into an initialization period for initializing all screens, an address period for selecting cells, and a sustain period for maintaining discharge of the selected cells.

In the initialization period, the rising ramp pulse Ramp-up is simultaneously applied to all the scan electrode lines Y in the set-up period SU. This rising ramp pulse causes dark discharge in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode line X and the sustain electrode line Z, and negative wall charges are accumulated on the scan electrode line Y.

In the set down period SD, a falling ramp pulse Ramp-down is applied. Ramp-down begins to fall from the positive voltage lower than the peak voltage of the rising ramp pulse and falls to a base voltage (GND) or a specific voltage level of negative polarity, thereby removing some of the wall charge that is excessively formed in the cells. Erase. Wall charges evenly remain in the cells so that the address discharge can be stably caused by the falling ramp pulse Ramp-down.

In the address period, the scan pulse Scan is sequentially applied to the scan electrode lines Y and the data pulse data is applied to the address electrode lines X in synchronization with the scan pulse Scan.

As the voltage difference between the scan pulse and the data pulse data and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse data is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when a sustain voltage is applied.

The bias voltage Zdc is applied to the sustain electrode line Z so as to reduce the voltage difference between the scan electrode line Y during the set-down period SD and the address period so as to prevent erroneous discharge from the scan electrode line Y.

In the sustain period, a sustain pulse Su is applied to the scan electrode lines Y and the sustain electrode lines Z alternately. In the cell selected by the address discharge, as the wall voltage and the sustain pulse in the cell are added, a sustain discharge, that is, a display discharge occurs between the scan electrode line Y and the sustain electrode line Z every time the sustain pulse is applied.

After the sustain discharge is completed, a ramp waveform (Ramp-ers) having a small pulse width and a low voltage level is supplied to the sustain electrode line Z to erase the wall charge remaining in the cells of the full screen.

3 is a circuit diagram of a conventional scan electrode driver. The scan electrode driver of the conventional plasma display panel generates a rising ramp pulse and a ramping down ramp pulse during the initialization period.

First, the setup switch Q5 and the seventh switch Q7 are turned on during the initialization period. At this time, the sustain voltage Vs is applied from the sustain pulse supply unit 40. The sustain voltage Vs is supplied to the scan electrode lines via the body diode of the sixth switch Q6, the seventh switch Q7, and the scan IC 48.

At this time, since the sustain voltage Vs is applied to the negative terminal of the second capacitor C2, the second capacitor C2 sets the sum of the sustain voltage and the setup voltage (Vs + Vsetup) to the fifth switch Q5. Supply.

The fifth switch Q5 is connected to the first node point n1 with a predetermined slope of the voltage supplied from the second capacitor C2 by the first variable resistor VR1 and the third capacitor C3 installed at the front end thereof. Supply.

The voltage applied to the first node point n1 with a predetermined slope is applied to the scan electrode line via the seventh switch Q7 and the scan IC 48. Therefore, a rising ramp pulse Ramp-up is applied to the scan electrode lines.

After the rising ramp pulse Ramp-up is applied to the scan electrode line, the fifth switch Q5 is turned off. When the fifth switch Q5 is turned off, only the voltage of Vs supplied from the sustain pulse supply unit 40 is applied to the first node point n1, and thus the voltage of the scan / sustain electrode rapidly drops to Vs. .

Thereafter, the seventh switch Q7 is turned off and the tenth switch Q10 is turned on in the set down period SD. The tenth switch Q10 lowers the voltage of the second node n2 with a predetermined slope to the write scan voltage (-Vw) while the channel width is adjusted by the second variable resistor VR2 provided at the front end thereof. . In this case, a falling ramp pulse Ramp-down is applied to the scan electrode line.

However, in the conventional driving waveform, dark discharge occurs because a high voltage reset pulse is applied in the reset period of each subfield. Ideally, no light should be emitted in the reset section, but light is emitted due to the dark discharge caused by the reset pulse.

The generation of light due to the dark discharge is a major factor that hinders the improvement of the contrast ratio of the plasma display panel, and the low contrast ratio reduces the sharpness of the plasma display panel.

The present invention is to solve the above problems, and to provide a method of driving a plasma display panel that supports a high contrast ratio.

In order to achieve the above object, a method of driving a plasma display panel of the present invention is a method of driving a plasma display panel in which a plurality of scan electrode lines are divided into m blocks (m is an integer of 2 or more). Applying p (p is a natural number of at least one) first reset pulses having a first voltage to the scan electrode lines belonging to at least one of the blocks; Q (q is one or more natural numbers) second reset pulses having a second voltage different from the first voltage are simultaneously applied to the scan electrode lines belonging to the remaining blocks except the one or more blocks during the specific frame. It is characterized by including.

The p first reset pulses and the q second reset pulses may be applied to a reset period of a subfield constituting the specific frame.

One or more reset pulses are applied to scan electrode lines belonging to at least one of the m blocks in a specific frame, a second reset pulse is applied to scan electrodes belonging to the remaining blocks, and at least one to which the first reset pulses are applied. The first reset pulse is applied to the scan electrode lines belonging to the block after one or more frames in the specific frame, and the first frame from the next frame to the scan electrode lines belonging to the block to which the second reset pulse is applied. A reset pulse is applied.

During the specific frame, applying the first reset pulses having a first voltage (p is a natural number of 1 or more) to the scan electrode lines belonging to one or more blocks of the m blocks may include first to nth operations. n is a natural number. The first reset pulses are sequentially applied to each of the blocks formed of the scan electrode lines.

During the specific frame, applying the first reset pulses having a first voltage (p is a natural number of 1 or more) to the scan electrode lines belonging to one or more blocks of the m blocks may include first to nth operations. n is a natural number. The first reset pulse applied to each of the blocks formed of the scan electrode lines is repeatedly applied in units of the nth frames.

A driving apparatus of a plasma display panel according to an exemplary embodiment of the present invention is a driving apparatus of a plasma display panel in which a plurality of scan electrode lines are divided into m blocks (m is an integer of 2 or more). Generating and supplying p (p is a natural number of 1 or more) first reset pulses having a first voltage to the scan electrode lines belonging to at least one of the blocks, and blocking the remaining blocks except for the at least one block during the specific frame And a reset driving circuit for generating and supplying q (q is a natural number of 1 or more) second reset pulses having a second voltage different from the first voltage in the scan electrode lines.

In the reset driving circuit, after the potential of the scan electrode line rapidly rises to the scan bias voltage, the reset driving circuit increases to the sum of the scan bias voltage and the sustain voltage at a first slope, and the scan bias voltage Vsc and the sustain at a second slope. The first reset pulse, which rises to the sum of the voltage Vs and the ramp voltage Vramp, is supplied to the scan electrode line, and the potential of the scan electrode line rises to the sustain voltage Vs with a third slope. And a second reset pulse that rises to the sum of the sustain voltage Vs and the ramp voltage Vramp at a fourth slope to the scan electrode line.

The second reset pulse is characterized in that the potential of the scan electrode line rises to the sustain voltage Vs at a fifth slope and is maintained for a predetermined time.

The second reset pulse is supplied to the cell in which the discharge occurred in the immediately preceding subfield.

The reset driving circuit includes: a sustain pulse supply unit configured to generate the sustain pulses included in the first and second reset pulses; A rising ramp pulse supply unit configured to generate rising ramp pulses included in the first and second reset pulses; A falling ramp pulse supply unit configured to generate the falling ramp pulses included in the first and second reset pulses; And a scan bias voltage supply unit configured to generate a scan bias voltage included in the first reset pulse.

The first voltage is greater than the second voltage.

The magnitude of the first slope and the second slope are the same.

The magnitude of the third slope and the fourth slope are the same.

The first slope, the second slope, the third slope, the fourth slope and the fifth slope are equal in magnitude.

The ramp voltage Vramp may be formed by blocking the application of the setup voltage Vsetup.

The p first reset pulses and the q second reset pulses may be applied to a reset period of a subfield constituting the specific frame.

One or more reset pulses are applied to scan electrode lines belonging to at least one of the m blocks in a specific frame, a second reset pulse is applied to scan electrodes belonging to the remaining blocks, and at least one to which the first reset pulses are applied. The first reset pulse is applied to the scan electrode lines belonging to the block after at least one frame in the specific frame, and the first reset pulse is applied to the scan electrode lines belonging to the block to which the second reset pulse is applied from the next frame. A pulse is applied.

The reset driving circuit may be configured to sequentially apply the first reset pulse to each block formed of the first to nth (where n is a natural number) scan electrode lines.

The reset driving circuit may be configured to repeatedly apply the first reset pulses applied to the blocks formed of the first to nth (where n is a natural number) scan electrode lines in units of n frames.

The reset driving circuit may apply the first reset pulse out of order to different subfields included in each of the frames, and the out of order application method may be repeated periodically.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 4 to 16.

4 to 7 illustrate strong discharge reset pulses, weak discharge reset pulses, and SR (selective reset) pulses among driving waveforms applied to the plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the strong discharge reset pulse according to an exemplary embodiment of the present invention rapidly rises to a scan bias voltage Vsc applied to scan electrode lines which have already been scanned or have not been scanned in the address period, and then The first slope is increased to the sum of the scan bias voltage Vsc and the sustain voltage Vs and then maintained, and the second slope is increased to the sum of the scan bias voltage Vsc, the sustain voltage Vs, and the ramp voltage Vramp. . At this time, since the scan bias voltage Vsc is 100V, the sustain voltage Vs is 200V, and the ramp voltage Vramp is 100V, the strong discharge reset pulse used in the driving method of the present invention is raised to 400V. Also, the magnitude of the first slope and the second slope are the same.

The weak discharge reset pulse according to the embodiment of the present invention is formed by the sustain voltage Vs and the ramp voltage Vramp without applying the scan bias voltage Vsc as shown in FIG. 5. That is, the weak discharge reset pulse is formed by increasing the potential of the scan electrode line to the sum of the sustain voltage Vs at the third slope and to the sum of the sustain voltage Vs and the ramp voltage Vram at the fourth slope. do. In this case, the third slope is equal in magnitude to the first slope, and the fourth slope is equal to the second slope. Most preferably, the first to fourth slopes are the same.

Here, the formation of the strong discharge reset pulse and the weak discharge reset pulse according to an embodiment of the present invention can be implemented using the conventional driving circuit shown in FIG. 3 instead of the new driving circuit. That is, the panel driving circuit according to the embodiment of the present invention includes a sustain pulse supply unit 40 generating and supplying a sustain pulse, a rising lamp pulse supply unit 42 generating and supplying a rising lamp pulse to the panel, and a scan bias voltage. Strong discharge through a combination of the scan bias voltage Vsc supply unit 50 generating and supplying the Vsc to the panel, and the voltage generated from the falling ramp pulse supply units 44 generating and supplying the falling ramp pulse to the panel. It generates a reset pulse and a weak discharge reset pulse.

In detail, first, the scan bias voltage Vsc is applied to the panel C by turning on the switch Q8 and the switch Q14. Therefore, the potential of the scan electrode line rapidly rises from 0V to 100V, which is the scan bias voltage Vsc. Next, the switch Q3 and the switch Q5 are turned on to apply the sustain voltage Vs to the scan electrode line. At this time, since the switch Q5 operates in the active region, the potential of the scan electrode line rises with the first slope. Therefore, the potential of the scan electrode line is the sum of the scan bias voltage Vsc and the sustain voltage Vs. At this time, since the scan bias voltage Vsc is 100V and the sustain voltage Vs is 200V, the potential of the scan electrode line rises to 300V. Subsequently, a setup voltage Vsetup for forming a conventional rising ramp pulse Ramp-up is applied to the scan electrode line through the switch Q5. Therefore, the potential of the scan electrode line is the sum of the scan bias voltage Vsc, the sustain voltage Vs, and the ramp voltage Vramp. That is, the potential of the scan electrode line rises from 300V with the second slope to 400V. At this time, the magnitude of the first slope and the second slope are the same. The ramp voltage Vramp is formed by the setup voltage Vsetup.

If the conventional reset pulse is 200V as shown in Fig. 6, it rises to 400V, which is the sum of the setup voltage Vsetup and the sustain voltage Vs. Therefore, if the setup voltage Vsetup is used as it is for the formation of the strong discharge reset pulse of the present invention, the strong discharge reset pulse rises to 500V (= Vsc + Vs + Vsetup). If the strong discharge reset pulse rises to 500V, a discharge voltage is worsened because a voltage higher than the standard is applied to the panel C. As a result, in order to form the strong discharge reset pulse according to the driving method of the present invention, the potential of the scan electrode line rises with the second slope at the sum of the scan bias voltage Vsc and the sustain voltage Vs, and then the setup voltage Vsetup. It is preferable that the supply of) rise only to the point of 400V by blocking.

On the other hand, the weak discharge reset pulse is formed by the sustain voltage (Vs) and the ramp voltage (Vramp) without applying the scan bias voltage (Vsc) in the process of forming a strong discharge reset pulse, so a description thereof will be omitted.

As shown in FIG. 7, the SR pulse according to the exemplary embodiment of the present invention is simultaneously supplied with the rising ramp waveform Ramp-up to all the scan electrodes Y in the setup period SU of the reset period. At the same time, 0 [V] is supplied to the sustain electrode Z and the address electrode X. The rising ramp waveform Ramp-up causes a setup discharge with weak discharge between the scan electrode Y and the address electrode X and between the scan electrode Y and the sustain electrode Z in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. In the set-down period SD of the reset period, a falling ramp waveform Ramp-down, which starts to fall from approximately the sustain voltage Vs and drops to a base voltage GND or 0 [V], is applied to the scan electrodes Y. Supplied at the same time. While the falling ramp waveform Ramp-down is supplied to the scan electrodes Y, a positive sustain voltage Vs is supplied to the sustain electrode Z, and 0 [V] is supplied to the address electrode X. do. When the falling ramp waveform Ramp-down is supplied, a set-down discharge occurs with a weak discharge between the scan electrode Y and the sustain electrode Z and between the scan electrode Y and the address electrode X. At this time, excess wall charges unnecessary for the address discharge are erased among the wall charges formed during the setup discharge by the set-down discharge. Looking at the wall charge change during this reset period, there is almost no wall charge change on the address electrode (X), and negative (-) wall charges on the scan electrode (Y) formed during the setup discharge are partially reduced by the setdown discharge. . On the other hand, the positive wall charges are formed on the sustain electrode Z during the set-up discharge, but the negative wall charges are accumulated on the self as much as the decrease of the negative wall charges of the scan electrode Y during the set-down discharge.

In the address period, the negative scan pulse scan is sequentially supplied to the scan electrodes Y, and the positive data pulse data is supplied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the reset period are added, an address discharge is generated in the on-cell to which the data pulse is supplied. In the on-cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is supplied. During this address period, the positive pole DC voltage Zdc is supplied to the sustain electrode Z.

In the sustain period, sustain pulses sus are alternately supplied to the scan electrodes Y and the sustain electrodes Z. FIG. On-cells selected by the address discharge are sustain discharge, that is, display discharge, between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is supplied as the wall voltage and the sustain pulse sus are added in the cell. Is generated.

After the sustain discharge is completed, the stabilization period continues. In the stabilization period, the first stabilization ramp waveform Ers1 is supplied to the scan electrode Y and the second stabilization ramp waveform Ers2 is supplied to the sustain electrode Z to stabilize the wall charge remaining in the cells of the full screen.

A plasma driving method for improving the contrast ratio using the SR pulse, the strong discharge reset pulse, and the weak discharge reset pulse will be described in detail with reference to FIGS. 8 to 16.

8 is a waveform diagram illustrating a method of driving a plasma display panel using a strong discharge reset pulse and a weak discharge reset pulse according to a first embodiment of the present invention.

Referring to FIG. 8, in the method of driving the plasma display panel according to the first embodiment of the present invention, a scan electrode line is time-divided into a plurality of subfields, for example, 10 to 12 in one frame, and m is supplied to a scan electrode line. Divide into blocks For example, when m is 2, the odd scan electrode lines Y1, Y3, Y5 ... are defined as the first block, and the even scan electrode lines Y0, Y2, Y4 ... are defined as the second block. In this case, while the driving waveform including the strong discharge reset pulse is supplied to the first block during the first subfield period, the driving waveform including the weak discharge reset pulse is supplied to the second block. Next, while the driving waveform including the strong discharge reset pulse is supplied to the second block during the second subfield period, the driving waveform including the weak discharge reset pulse is applied to the first block. In the same manner, the drive waveforms including the strong discharge reset pulse and the weak discharge reset pulse are alternately supplied to the first and second blocks every subfield. The driving method according to the first exemplary embodiment of the present invention in which such driving waveforms are supplied can achieve a high contrast ratio as compared with the conventional driving method of supplying strong discharge reset pulses in every subfield.

9 is a waveform diagram illustrating a method of driving a plasma display panel using a strong discharge reset pulse and a weak discharge reset pulse according to a second embodiment of the present invention.

Referring to FIG. 9, in the method of driving the plasma display panel according to the second embodiment of the present invention, a scan electrode line is time-divided into a plurality of subfields, for example, ten to twelve, in one frame. Divide into blocks For example, when m is three, the multiple scan electrode lines 3 including the 0 th such as the scan electrode lines Y0, Y3, Y6 ... are defined as the first block, and the scan electrode lines Y1, Y4, Y7 are defined. When ... is defined as the second block and Y2, Y5, Y8 ... are defined as the third block, a driving waveform including a strong discharge reset pulse is supplied to the first block during the first subfield period. In the meantime, a driving waveform including a weak discharge reset pulse is supplied to the second block and the third block. Next, while the driving waveform including the strong discharge reset pulse is supplied to the second block during the second subfield period, the driving waveform including the weak discharge reset pulse is applied to the first block and the third block. In addition, the driving waveform including the weak discharge reset pulse is supplied to the first and second blocks while the driving waveform including the strong discharge reset pulse is applied to the third block during the third subfield period. In the same manner, the first to third blocks are supplied with a driving waveform including one strong discharge reset pulse and two weak discharge reset pulses every three subfields. The driving method according to the second exemplary embodiment of the present invention in which the driving waveform is supplied may achieve a higher contrast ratio than the conventional driving method of supplying strong discharge reset pulses in every subfield. Here, the driving waveform including the strong discharge pulses supplied to the first and third blocks during the same subfield period may be supplied out of order, for example, in the order of the first block, the third block, and the second block. In addition, the driving method of the plasma display panel according to an exemplary embodiment of the present invention is not limited to the number of blocks. That is, blocks may be divided into 4-7 blocks.

FIG. 10 is a waveform diagram illustrating a plasma display panel driving method using strong discharge reset pulses and SR pulses according to a third exemplary embodiment of the present invention.

Referring to FIG. 10, when m = 2, a block according to the third embodiment of the present invention divides the entire panel by two adjacent scan electrode lines in block units to form a total horizontal resolution / 2 blocks. Specifically, the odd scan electrode lines Yn + 1, Yn + 3, Yn + 5 in each scan electrode line Yn, Yn + 1, Yn + 2, Yn + 3, Yn + 4, Yn + 5 ..... When ... is defined as the first block and the even-numbered scan electrode lines Yn, Yn + 2, and Yn + 4 ... are defined as the second block, initializing discharge is performed in all cells for one frame (TV-field). While a drive waveform including a strong discharge reset pulse (all reset) that can be generated is applied to the first block, the second block includes an SR (Selective Reset) pulse that causes discharge only in the cell that was turned on in the previous subfield. A driving waveform is applied. While the driving waveform including the SR pulse (Selective Reset) is applied to the first block during the next two frames (TV-field), the driving waveform including the strong discharge reset pulse (all Reset) is applied to the second block. In this manner, the first block and the second block are alternately supplied every TV-field. Here, the driving waveform including the strong discharge reset pulse (all reset) applied to the first and second blocks during each frame (TV-field) is at least one of a plurality of subfields included in one frame (TV-field) The method included in the above and supplied to the plurality of subfields may be supplied according to the driving method described above in the first and second embodiments of the present invention. For example, the driving method of the plasma display panel applied to a plurality of subfields in one frame (TV-field) according to the third embodiment of the present invention is a plurality of frames in one frame (1TV-field) in even-numbered scan lines. A strong discharge reset waveform (all reset) is applied to the first subfield among the subfields, and a weak discharge reset waveform (Selective Reset) is applied to the remaining subfields. A weak discharge reset waveform (Selective Reset) is applied to the odd scan lines as a whole. In the next frame (2TV-field), the strong discharge reset waveform (all reset) is applied to any one of the remaining subfields except the first subfield among the plurality of subfields in the frame among the driving waveforms applied to the odd scan line. The weak discharge reset waveform (Selective Reset) is applied to the remaining subfields. In this case, a weak discharge reset waveform (Selective Reset) is applied to the even-numbered scan lines as a whole. In this manner, the time when the strong discharge reset waveform (all reset) is applied in units of TV-field is alternately applied to even and odd scan lines, and in each subfield in units of TV-field. The applied strong discharge reset waveform (all reset) is applied out of order in one or more of the plurality of subfields. As a result, the driving method of the plasma display panel according to the third embodiment of the present invention can achieve a high contrast ratio by reducing the supply of the strong discharge reset waveforms, and the strong discharge reset waveforms applied to the plurality of subfields. By controlling the timing of (all reset) out of order, it is possible to prevent image quality errors such as ripples that may occur when applied sequentially.

In the driving waveform of the plasma display panel according to the third exemplary embodiment of the present invention, the SR waveform is applied to initialize the wall charge of the on-cell, while controlling the off-cell is difficult due to the surrounding conditions of the plasma display panel. Done. Accordingly, in the fourth embodiment of the present invention, a driving waveform using weak discharge pulses capable of achieving both high contrast ratio and controlling both on and off cells will be proposed.

FIG. 11 is a waveform diagram illustrating a method of driving a plasma display panel using strong discharge reset pulses (all reset) and weak discharge reset pulses (small reset) according to a fourth embodiment of the present invention.

Referring to FIG. 11, when m = 2, the block according to the fourth embodiment of the present invention divides the entire panel into block units of two adjacent scan electrode lines to form a total horizontal resolution / 2 blocks. Specifically, the odd scan electrode lines Yn + 1, Yn + 3, Yn + 5 in each scan electrode line Yn, Yn + 1, Yn + 2, Yn + 3, Yn + 4, Yn + 5 ..... When ... is defined as the first block, and even-numbered scan electrode lines Yn, Yn + 2, Yn + 4 ... are defined as the second block, initializing discharge is performed in all cells for one frame (TV-field). While the driving waveform including the strong discharge reset pulse (all reset) to be generated is applied to the first block, the driving waveform including the above-described small discharge reset pulse (small reset) is applied to the second block. During the next two frames (TV-field), the driving waveform including the SR pulse (Selective Reset) is applied to the first block, while the driving waveform including the strong discharge reset pulse (all Reset) is applied to the second block. In this manner, the first block and the second block are alternately supplied every TV-field. Here, the driving waveform including the strong discharge reset pulse (all reset) applied to the first and second blocks during each frame (TV-field) is at least one of a plurality of subfields included in one frame (TV-field) The method included in the above and supplied to the plurality of subfields may be supplied according to the driving method described above in the first and second embodiments of the present invention. In the driving method of the plasma display panel according to the third embodiment of the present invention driven in this manner, a higher contrast ratio is improved by applying fewer strong discharge reset pulses (all reset) than the first embodiment of the present invention. Will be achieved.

12 is a waveform diagram illustrating a method of driving a plasma display panel using strong discharge reset pulses (all reset) and selective reset (SR) pulses according to a fifth embodiment of the present invention. In this case, the SR pulse according to the fifth embodiment of the present invention may be replaced with the above-described weak discharge reset pulse.

In the plasma display panel according to the fifth embodiment of the present invention, the Yn, Yn + 4, Yn + 8 ... th scan electrode lines are the first block, and the Yn + 1, Yn + 5, Yn + 9 ... th Scan electrode lines to the second block, Yn + 2, Yn + 6, Yn + 10 ... th scan electrode lines to the third block, Yn + 3, Yn + 7, Yn + 11 ... th scan The electrode lines are defined as fourth blocks. As described above, the driving method of the plasma display panel according to the fifth embodiment of the present invention having the first to fourth blocks includes a strong discharge reset pulse (all reset) in the first block in one frame (1TV-field) period. While the driving waveform is applied, the driving waveform including the SR pulse is applied to the remaining second to fourth blocks instead of the all-discharge reset pulse. In the two frame (2TV-field) period, while the driving waveform including the strong discharge reset pulse (all reset) is applied to the second block, the first block except for the second block, and the SR instead of the third and fourth blocks. A drive waveform including a (Selective reset) pulse is applied. In this way, the driving waveform including the strong discharge reset pulse (all reset) is applied to the third block in the three frame (TV-field) period, and the strong discharge reset in the fourth block in the four frame (4TV-fied) period. A drive waveform including a pulse (all reset) is applied. Thereafter, a driving waveform including a strong discharge reset pulse (all reset) is applied to the first to fourth blocks every four frames (TV-field).

The strong discharge reset pulse (all reset) applying method of the plasma display panel according to the fifth embodiment applied in this manner is similarly applied to the scan electrode lines divided into the first to third blocks as shown in FIG. 13. can do. Specifically, a strong discharge reset pulse (all reset) is sequentially applied to one frame (TV-field) and three frames (TV-field) to the first block and the third block formed of Yn to Yn + 2 horizontal lines. The method of applying the strong discharge reset pulse (all reset) may be applied every three frames (TV-field) and each block formed of three horizontal lines.

In the driving method of the plasma display panel according to the fifth embodiment of the present invention, a driving waveform including a strong discharge reset pulse (all reset) is sequentially performed for each frame (TV-field) in units of m blocks (m is a natural number). Is applied. In this driving method, since a driving waveform including a strong discharge reset pulse (all reset) is repeatedly applied to m blocks, streaks generally occur.

14 is a waveform diagram illustrating a method of driving a plasma display panel using strong discharge reset pulses (all reset) and selective reset (SR) pulses according to a sixth embodiment of the present invention. Here, the SR pulse according to the sixth embodiment of the present invention may be replaced with the weak discharge reset pulse described above.

Here, the driving method of the plasma display panel according to the sixth embodiment of the present invention is a driving waveform including a strong discharge reset pulse (all reset) compared to the driving method of the plasma display panel according to the fifth embodiment of the present invention. Since the application point is the same except that the application point is different, only the application point of the driving waveform will be described.

Referring to FIG. 14, the plasma display panel according to the sixth embodiment of the present invention is supplied with a driving waveform including a strong discharge reset pulse (all reset) to the first block during one frame (TV-field) period. A driving waveform including an SR (selective rest) pulse is applied to the second to fourth blocks except for one block. During the next two frames (TV-field), the driving waveform including the strong discharge reset pulse (all reset) is supplied to the third block, and SRs are provided to the first block, the second block, and the fourth block except the third block. A selective waveform is applied to the driving waveform. During the next three frames (TV-field), the drive waveform including the strong discharge reset pulse (all reset) is supplied to the second block, and SRs are provided to the first block, the third block, and the fourth block except the second block. The drive waveform including the selective rest pulse is applied. During the next four frames (TV-field) period, the driving waveform including the strong discharge reset pulse (all reset) is supplied to the fourth block, and SR (selective rest) is applied to the first to third blocks except for the fourth block. A driving waveform is included. In this manner, a driving waveform including a strong discharge reset pulse is sequentially applied to the first block and the fourth block every four frames (TV-field).

15 is a waveform diagram illustrating a method of driving a plasma display panel using strong discharge reset pulses (all reset) and selective reset (SR) pulses according to a seventh embodiment of the present invention. In this case, the SR pulse according to the seventh embodiment of the present invention may be replaced with the aforementioned weak discharge reset pulse.

Here, the driving method of the plasma display panel according to the seventh embodiment of the present invention is a driving waveform including a strong discharge reset pulse (all reset) compared to the driving method of the plasma display panel according to the sixth embodiment of the present invention. Since the application point is the same except that the application point is different, only the application point of the driving waveform will be described.

According to a seventh embodiment of the present invention, a plasma display panel includes a first vertical block including Yn to Yn + 3 scan electrode lines of first to fourth blocks, and Yn + 4 to Yn + of first to fourth blocks. A second vertical block consisting of seven scan electrode lines and a third vertical block consisting of Yn + 8 to Yn + 11 scan electrode lines of the first to fourth blocks with the same numbering. Here, the odd-numbered vertical blocks, that is, the first vertical block, the third vertical block ... are driven in the same manner as the driving method of the plasma display panel according to the sixth embodiment of the present invention, and description thereof will be omitted. . The driving method of the plasma display panel in the even-numbered vertical block, that is, the second vertical block, the fourth vertical block ... is the fourth block in the first block for the period of one frame (1TV-field) to four frames (4TV-field). The driving waveform including a strong discharge reset pulse (all reset) is sequentially applied to the block, and the fourth to first blocks are applied during the period of 5 frames (TV-field) to 8 frames (5TV-field to 8TV-field). Drive waveforms including a strong discharge reset pulse (all reset) are sequentially applied. Here, the supply time of the driving waveform including the strong discharge reset pulse (all reset) supplied to the even-numbered vertical block is different from the supply time of the driving waveform including the strong discharge reset pulse (all reset) supplied to the odd-numbered vertical block. Is set.

In the driving method of the plasma display panel according to the seventh embodiment of the present invention driven in this manner, one strong discharge reset pulse (all reset) is applied to every four frames (TV-field) in each horizontal line. It is possible to minimize the dark discharge by. Accordingly, the driving method of the plasma display panel according to the seventh exemplary embodiment of the present invention can achieve a higher contrast ratio than the first exemplary embodiment of the present invention.

In the driving method of the plasma display panel implemented in the embodiments of the present invention, the time when the driving waveform including the strong discharge reset pulse (all reset) is applied, the method of dividing the scan electrode line, and the strong discharge reset pulse applied (all reset) It can be set in various ways according to the number of driving waveforms including) and the number of subfields included in one frame (TV-field). Among the various settings, the block division of the most preferable plasma display panel which can substantially prevent streaks and reduce miss discharge is divided into five blocks and seven blocks not shown, as shown in FIG. 16. to be.

Referring to FIG. 16, a plasma display panel according to an eighth embodiment of the present invention uses Yn, Yn + 4 ... scan electrode lines as a first block, and Yn + 1, Yn + 5 ... scan electrode lines. Yn + 2, Yn + 6 ... scan electrode lines to third block, Yn + 3, Yn + 7 ... scan electrode lines to fourth block, Yn + 4, Yn + 8 The scan electrode lines are defined as fifth blocks, and the second to fifth blocks are applied while the driving waveform including the strong discharge reset pulse (all reset) is applied to the first block during one frame (TV-field). The drive waveform including the SR (Selective reset) pulse is applied to the block. Here, in the method of driving the plasma display panel according to the eighth embodiment of the present invention, the weak discharge reset pulse may be used instead of the selective reset (SR) pulse. While the driving waveform including the strong discharge reset pulse (all reset) is applied to the second block during two frames (TV-field), the first block, and the third to fifth blocks include a selective reset (SR) pulse The drive waveform is applied. In the same manner, the driving waveform including the strong discharge reset pulse (all reset) is applied to the third to fifth blocks, and at the same time, the driving waveform including the selective reset (SR) pulse is applied to the blocks except the block. . Here, the order in which the driving waveform including the strong discharge reset pulse (all reset) is applied to the first to fifth blocks is preferably supplied out of order, and experimentally in the order of 1-3-5-2-4. It is preferred to be supplied.

In addition, when the plasma display panel according to the embodiment of the present invention is divided into the first to seventh blocks in the same manner as the eighth embodiment of the present invention, the driving waveform including the strong discharge reset pulse (all reset) is The order of application is applied in a non-sequential order and preferably supplied in the order of 1-3-5-7-2-4-6.

In summary, a plurality of scan electrode lines are driven by dividing m (m is an integer greater than or equal to 2) blocks, and the scan electrode lines belonging to one or more blocks of m groups during a specific frame in which 10 or 12 subfields exist. During the subfield, p (p is a natural number of 1 or more) strong discharge reset pulses having a first voltage are applied, and scan electrode lines belonging to the remaining groups except for one or more blocks to which a strong discharge reset pulse is applied during the specific frame. Q weak discharge reset pulses having a second voltage different from the first voltage (q is a natural number of 1 or more) are simultaneously applied.

In addition, in a TV-field splitting scheme using a plurality of frames (for example, 60 Hz frequency), the driving apparatus includes p strong discharge reset pulses in one or more blocks during 60 frames (TV-field). The waveform is applied and the driving waveform including q weak discharge reset pulses is applied to the remaining blocks except for the block to which the driving waveform including the strong discharge reset pulse is applied during the same frame (TV-field). Here, p strong discharge reset pulses supplied to the plurality of blocks are sequentially applied.

As described above, the driving method according to the present invention can support the high contrast ratio of the plasma display panel by alternately applying the strong discharge reset pulse and the weak discharge reset pulse without changing the driving circuit.

On the other hand, to summarize the block classification method according to each embodiment of the present invention, a plurality of scan lines, that is, Y0, Y1, Y2, Y3, Y4, Y5 ..... Yn-5, Yn-4, Yn-3 In Yn-2, Yn-1, and Yn, the first block division method divides blocks into two, and each block includes an even scan line and an odd scan line. The second block division method divides the block into three, the first block includes the scan lines Y0, Y3, Y6 ... Y (3 · n), and the second block is Y1, Y4, Y7 ... Y A scan line of (3 · n + 1) is included, and the third block includes a scan line of Y2, Y5, Y8 ... Y (3 · n + 2). The third block division method is divided into five blocks,

As described above, the driving method of the plasma display panel according to the present invention can support the high contrast ratio of the plasma display panel by alternately applying the strong discharge reset pulse and the weak discharge reset pulse without changing the driving circuit.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive.

The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

Claims (20)

In the driving method of the plasma display panel in which a plurality of scan electrode lines are driven divided into m (m is an integer of 2 or more) blocks, Applying (p is a natural number of at least one) first reset pulses having a first voltage to the scan electrode lines belonging to at least one of the m blocks during a specific frame; Q (q is one or more natural numbers) second reset pulses having a second voltage different from the first voltage are simultaneously applied to the scan electrode lines belonging to the remaining blocks except the one or more blocks during the specific frame. And a plasma display panel driving method. The method of claim 1, And the p first reset pulses and the q second reset pulses are applied to a reset period of a subfield constituting the specific frame. The method of claim 1, In a particular frame, a first reset pulse is applied to scan electrode lines belonging to at least one of the m blocks, and a second reset pulse is applied to scan electrodes belonging to the remaining blocks. The first reset pulse is applied to the scan electrode line belonging to at least one block to which the first reset pulse is applied, after at least one frame in the specific frame, And the first reset pulse is applied to a scan electrode line belonging to the block to which the second reset pulse is applied, starting from a frame following the specific frame. The method of claim 1, During the specific frame, the step of applying p (p is a natural number of 1 or more) first reset pulses having a first voltage to the scan electrode lines belonging to at least one of the m blocks And the first reset pulses are sequentially applied to each of the blocks formed of the first to nth (n is natural numbers) scan electrode lines. The method of claim 1, During the specific frame, the step of applying p (p is a natural number of 1 or more) first reset pulses having a first voltage to the scan electrode lines belonging to at least one of the m blocks Wherein the first reset pulse applied to each block formed of the first to nth (where n is a natural number) scan electrode lines is repeatedly applied in units of nth frames. . In the driving apparatus of the plasma display panel in which a plurality of scan electrode lines are driven divided into m (m is an integer of 2 or more) blocks, Generate and supply p (p is a natural number of 1 or more) first reset pulses having a first voltage to the scan electrode lines belonging to one or more of the m blocks during a specific frame, and supplying the one or more first reset pulses during the specific frame. And a reset driving circuit for generating and supplying q (q is a natural number of 1 or more) second reset pulses having a second voltage different from the first voltage to the scan electrode lines that block except for the block. A driving device of the plasma display panel. The method of claim 6, The reset driving circuit After the potential of the scan electrode line rapidly rises to the scan bias voltage, the first slope increases to the sum of the scan bias voltage and the sustain voltage, and the second slope increases the scan bias voltage Vsc, the sustain voltage Vs, and The first reset pulse which rises to the sum of the ramp voltage Vramp is supplied to the scan electrode line. The scan of the second reset pulse in which the potential of the scan electrode line rises to a sustain voltage Vs at a third slope and rises to a sum of the sustain voltage Vs and a ramp voltage Vramp at a fourth slope A drive device for a plasma display panel, characterized in that it is supplied to an electrode line. The method of claim 6, And the second reset pulse is maintained at a predetermined time while the potential of the scan electrode line rises to a sustain voltage (Vs) at a fifth slope. The method of claim 8, And the second reset pulse is supplied to a cell in which a discharge is generated in the immediately preceding subfield. The method according to any one of claims 7 and 8, The reset driving circuit A sustain pulse supply unit configured to generate the sustain pulses included in the first and second reset pulses; A rising ramp pulse supply unit configured to generate rising ramp pulses included in the first and second reset pulses; A falling ramp pulse supply unit configured to generate the falling ramp pulses included in the first and second reset pulses; And a scan bias voltage supply unit configured to generate a scan bias voltage included in the first reset pulse. The method according to any one of claims 7 and 8, And the first voltage is greater than the second voltage. The method of claim 7, wherein And the first inclination and the second inclination have the same magnitude. The method of claim 7, wherein And the third inclination and the fourth inclination have the same magnitude. The method according to any one of claims 7 and 8, And the first inclination, the second inclination, the third inclination, the fourth inclination and the fifth inclination have the same magnitude. The method of claim 7, wherein The ramp voltage Vramp is formed by blocking the application of the setup voltage Vsetup. The method of claim 6, And the p first reset pulses and the q second reset pulses are applied to a reset period of a subfield constituting the specific frame. The method of claim 6, In a specific frame, a first reset pulse is applied to scan electrode lines belonging to at least one of the m blocks, and a second reset pulse is applied to scan electrodes belonging to the remaining blocks. The first reset pulse is applied to the scan electrode line belonging to at least one block to which the first reset pulse is applied, after at least one frame in the specific frame, And the first reset pulse is applied to a scan electrode line belonging to the block to which the second reset pulse is applied, starting from a frame following the specific frame. The method of claim 6, The reset driving circuit And the first reset pulses are sequentially applied to each of the blocks formed of the first to nth (n is natural numbers) scan electrode lines. The method of claim 6, The reset driving circuit And a first reset pulse applied to each of the blocks formed of the first to nth (where n is a natural number) scan electrode lines repeatedly applied to the nth frame units. The method of claim 6, The reset driving circuit And applying said first reset pulse out of order to different subfields included in each of said frames, and said out of order application method being repeated periodically.

Images