KR100784522B1 - Driving Apparatus and Method for Plasma Display Panel - Google Patents

Abstract

The present invention relates to a driving apparatus and a driving method of a plasma display panel. In a method of driving a plasma display panel according to an embodiment of the present invention, in the method of driving a plasma display panel in which a plurality of frames display an image, a method of driving a plasma display panel includes a first frame and a second frame consecutive to the first frame. And a number of rising ramp pulses applied in the setup period of the reset period of the plurality of subfields of the second frame than the number of the rising ramp pulses applied in the setup period of the reset period of the plurality of subfields of the first frame. Is less, and a bias voltage is applied during the setup period of the reset period of the subfield to which the rising ramp pulse is not applied among the subfields of the second frame.

Dark Image, Plasma Display Panel, Reset Pulse, Bias Voltage

Description

Driving apparatus and driving method of plasma display panel {Driving Apparatus and Method for Plasma Display Panel}

1 is a diagram showing the structure of a typical plasma display panel.

2 is a diagram illustrating a method of expressing image gradation of a conventional plasma display panel.

3 is a view illustrating a driving waveform according to a driving method of a conventional plasma display panel.

4 is a diagram for explaining generation of local afterimages generated in a conventional plasma display panel.

5 is a diagram showing the degree of dark afterimage according to the number of reset pulses.

6 is a view illustrating a driving waveform according to a method of driving a plasma display panel according to an embodiment of the present invention.

FIG. 7 is a diagram for explaining region A of FIG. 6 in more detail.

8 is a view for explaining a driving apparatus of a plasma display panel for implementing a driving waveform according to a driving method of a plasma display panel according to an embodiment of the present invention;

9 is a view showing a driving waveform according to the method of driving a plasma display panel according to an embodiment of the present invention.

FIG. 10 is a diagram for explaining region B of FIG. 9 in more detail.

11 is a view showing that the reset pulse according to the driving method of the plasma display panel of the present invention is sequentially applied according to a predetermined time.

12 is a view showing a driving waveform in accordance with a method for driving a plasma display panel according to an embodiment of the present invention.

FIG. 13 is a diagram for explaining regions C and D of FIG. 12 in more detail.

14 is a view for explaining a driving apparatus of a plasma display panel for implementing a driving waveform in accordance with a method of driving a plasma display panel according to an embodiment of the present invention;

(Explanation of symbols for the main parts of the drawing)

101: front substrate 102: scan electrode

103: sustain electrode 104: upper dielectric layer

111: rear substrate 112: bulkhead

113: address electrode 114: phosphor

115: lower dielectric layer

The present invention relates to a method of removing an afterimage of a plasma display panel, and more particularly, to a method of driving a plasma display panel to reduce a dark afterimage by improving a reset pulse waveform applied to a reset section.

In general, a plasma display panel is a partition wall formed between a front panel and a rear panel to form one unit cell, and each cell includes neon (Ne), helium (He), or a mixture of neon and helium (Ne + He) and An inert gas containing the same main discharge gas and a small amount of xenon is filled. When discharged by a high frequency voltage, the inert gas emits vacuum ultraviolet rays to emit phosphors formed between the partition walls, thereby realizing an image. Such a plasma display panel has a spotlight as a next generation display device because of its thin and light configuration.

1 illustrates a structure of a general plasma display panel.

As illustrated in FIG. 1, a plasma display panel includes a front panel in which a plurality of sustain electrode pairs formed by pairing a scan electrode 102 and a sustain electrode 103 are arranged on a front substrate 101 that is a display surface on which an image is displayed. 100 and the rear panel 110 on which the plurality of address electrodes 113 are arranged so as to intersect the plurality of storage electrode pairs described above on the rear substrate 111 forming the rear surface are coupled in parallel with a predetermined distance therebetween.

The front panel 100 is made of a scan electrode 102 and a sustain electrode 103, that is, a transparent electrode (a) formed of a transparent ITO material and a metal material to mutually discharge and maintain light emission of the cells in one discharge cell. The scan electrode 102 and the sustain electrode 103 provided as the bus electrode b are included in pairs. Scan electrode 102 and sustain electrode 103 are covered by one or more upper dielectric layers 104 that limit discharge current and insulate between electrode pairs, and facilitate discharge conditions on top of upper dielectric layer 104. For this purpose, a protective layer 105 on which magnesium oxide (MgO) is deposited is formed.

The rear panel 110 is arranged in such a manner that a plurality of discharge spaces, that is, barrier ribs 112 of a stripe type (or well type) for forming discharge cells are maintained in parallel. In addition, a plurality of address electrodes 113 are arranged in parallel with the partition wall 112 to perform address discharge so that the inert gas in the discharge cell generates vacuum ultraviolet rays. On the upper side of the rear panel 110, red (R), green (G), and blue (B) phosphors 114 which emit visible light for image display during sustain discharge are coated. A lower dielectric layer 115 is formed between the address electrode 113 and the phosphor 114 to protect the address electrode 113.

The plasma display panel having the above-described structure is provided with a plurality of discharge cells in a matrix structure, and a driving unit including a driving circuit for supplying a predetermined pulse to the discharge cells is attached and driven.

A method of expressing image gradation of a conventional plasma display panel having such a structure will be described with reference to FIG. 2.

2 is a diagram illustrating a method of expressing image gray scale of a conventional plasma display panel. As shown, the image gradation of the plasma display panel is driven by dividing one frame into several subfields having different emission counts. Each subfield is divided into a reset section for uniformly generating a discharge, an address section for selecting a discharge cell, and a sustain section for implementing gray levels according to the number of discharges. For example, when displaying an image with 256 gray levels, a frame section (16.67 ms) corresponding to 1/60 second is divided into eight subfields. In addition, each of the eight subfields is divided into an address period and a sustain period. Here, the reset section and the address section of each subfield are the same for each subfield, while the sustain section increases at a rate of 2n (n = 0,1,2,3,4,5,6,7) in each subfield. do. Referring to the driving waveform according to the driving method of the plasma display panel as shown in FIG.

3 is a view illustrating a driving waveform according to a driving method of a conventional plasma display panel. As shown, the plasma display panel includes a reset section for initializing the entire screen, an address section for selecting a cell to be discharged, a sustain section for maintaining the discharge of the selected cell, and an erasing section for erasing wall charges in the discharged cell. Driven by dividing into.

In the reset section, the rising ramp waveform Ramp-up is simultaneously applied to all the Y electrodes (scan electrodes) in the setup section. This rising ramp waveform causes discharge to occur in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the X electrode (address electrode) and Z electrode (sustain electrode), and negative wall charges are accumulated on the Y electrode. During the set-down period, after the rising ramp waveform is supplied, the ramp ramp starts to fall from the positive voltage lower than the peak voltage of the rising ramp waveform and falls to a specific voltage level below the ground (GND) level voltage. By causing a weak erase discharge in the cells, the overcharged wall charge is sufficiently erased. By this set-down discharge, wall charges evenly remain in the cells so that the address discharge can be stably generated.

In the address period, the negative scan pulse Scan is sequentially applied to the Y electrodes, and the positive data pulse data is applied to the X electrode in synchronization with the scan pulse. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges such that discharge can occur when the sustain voltage Vs is applied are formed. The positive electrode voltage Vz is supplied to the Z electrode so as to reduce the voltage difference between the Y electrode during the set-down period and the address period so as to prevent erroneous discharge from the Y electrode.

In the sustain period, a sustain pulse Su is alternately applied to the Y electrode and the Z electrodes. In the cell selected by the address discharge, as the wall voltage and the sustain pulse in the cell are added, a sustain discharge, that is, a display discharge occurs between the Y electrode and the Z electrode every time the sustain pulse is applied.

After the sustain discharge is completed, a voltage of an erase ramp waveform (Ramp-ers) having a small pulse width and a low voltage level is supplied to the Z electrode in the erase section to erase the wall charge remaining in the cells of the full screen.

The PDP driven as described above generates an afterimage when a predetermined pattern appears in view of driving characteristics.

4 is a view for explaining the generation of local afterimage occurring in the conventional PDP.

As shown in FIG. 4, when a predetermined window pattern is displayed at the center portion of the screen, the window pattern intensively discharges a portion 400a of the panel display surface 400. Subsequently, when the entire panel 400b becomes an off cell, the window pattern displayed on the portion 400a of the panel display surface 400 appears as an afterimage 400c. The afterimage 400c is worsened due to deterioration of the phosphor, surface property change of the protective film, or misdischarge due to unsafe driving of the PDP, and deepens as the gas ratio of xenon (Xe) increases.

In particular, the residual image level is severely displayed according to a signal applied when driving the PDP, that is, a reset pulse as shown in FIG. 5.

5 is a diagram illustrating the degree of dark afterimage according to the number of reset pulses. As shown in the figure, the dark residual level is very good when the number of reset pulses is one in one frame, whereas the dark residual level is intensified as the number of reset pulses in one frame increases.

However, if the number of reset pulses is reduced within an indefinite frame, there is a problem that inadvertently reducing the number of reset pulses depending on the panel and the waveform has a dependency in that misdischarge may occur.

Accordingly, an object of the present invention is to provide a method of driving a plasma display panel which reduces an afterimage by improving a reset pulse waveform applied to a reset period.

Another object of the present invention is to provide a driving device of a plasma display panel.

Technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned above will be clearly understood by those skilled in the art from the following description. Could be.

According to an aspect of the present invention, there is provided a method of driving a plasma display panel, the method comprising: a method of driving a plasma display panel in which a plurality of frames display an image, the first frame and the first frame among the plurality of frames; A setup of reset intervals of the plurality of subfields of the second frame, including a second frame continuous to one frame, and a number of rising ramp pulses applied to the setup period of the reset intervals of the plurality of subfields of the first frame; The number of rising ramp pulses applied to the period is smaller, and the bias voltage is applied during the setup period of the reset period of the subfield to which the rising ramp pulse is not applied among the subfields of the second frame.

The second frame may be a plurality of frames.

The number of reset pulses having the rising ramp pulse applied to the subfield of the second frame may be sequentially reduced in the second frame.

The bias voltage value may be a voltage value Vs of a sustain pulse.

When the number of reset pulses having the rising ramp pulses applied to the subfield of the second frame is 1 to 3, the peak voltage of the rising ramp pulses may be adjusted.

The discharge loads of the first frame and the second frame may be the number of data pulses applied to the address period of the second frame.

The number of data pulses applied to the address period of the second frame may be determined by the data most applied to any one of the R, G, and B cells.

In another aspect, a driving apparatus of a plasma display panel includes a panel including a scan electrode, a first frame among a plurality of frames, and a second frame continuous to the first frame. The number of rising ramp pulses applied in the setup period of the reset period of the plurality of subfields of the second frame is greater than the number of the rising ramp pulses applied in the setup period of the reset period of the plurality of subfields of the first frame. The scan driver may further include a scan driver configured to apply a bias voltage during a setup period of the reset period of the subfield to which the rising ramp pulse is not applied among the subfields of the second frame.

The second frame may be a plurality of frames.

The scan driver may adjust the number of reset pulses having the rising ramp pulse applied to the subfield of the second frame by sequentially decreasing the number of reset pulses in the second frame.

The bias voltage value may be a voltage value Vs of a sustain pulse.

When the number of reset pulses having the rising ramp pulses applied to the subfield of the second frame is 1 to 3, the scan driver may adjust the lowering peak voltage of the rising ramp pulses.

The discharge loads of the first frame and the second frame may be the number of data pulses applied to the address period of the second frame.

The number of data pulses applied to the address period of the second frame may be determined by the data most applied to any one of the R, G, and B cells.

Specific details of other embodiments are included in the detailed description and the drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. Like reference numerals refer to like elements throughout.

6 to 7, a plasma display driving method according to an embodiment of the present invention will be described.

6 is a diagram illustrating a driving waveform according to a method of driving a plasma display panel according to an embodiment of the present invention. As shown in FIG. 6, in the method of driving a plasma display panel according to the present invention, an image is represented by a plurality of frames, and each frame is divided into several subfields having different emission counts. In other words, each frame may be composed of ten or twelve subfields having different number of emission times.

In addition, the plasma display panel is divided into a reset section for initializing the entire screen, an address section for selecting a cell to be discharged, a sustain section for maintaining the discharge of the selected cell, and an erasing section for erasing wall charges in the discharged cell. Driven. Here, the driving method of the plasma display panel according to the present invention is to the discharge rod of the second frame, the first frame (not shown) and the second frame continuous to the first frame (not shown) and the first frame (not shown). Accordingly, when an afterimage occurs, a reset pulse applied to the remaining subfields except for one of the second frames is adjusted.

Here, the unregulated reset pulse applied to one subfield of the second frame does not necessarily have to be forwarded, and may be applied to any one of the plurality of subfields. In FIG. 6, an unadjusted reset pulse is applied to the fourth subfield, but it is clear that the present invention is not limited thereto and is arbitrarily written to facilitate the description of the present invention. Here, the discharge load (load) refers to the entire screen is composed of a number of cells, which refers to the ratio of the cells selected to emit light.

FIG. 7 is a diagram for describing region A of FIG. 6 in more detail. As shown in FIG. 7, the waveform of the reset pulse applied to the remaining subfields except for one subfield of the second frame according to the exemplary embodiment of the present invention is shown.

The reset pulse applied to the remaining subfields except for the subfield of the second frame adjusts the setup pulse applied to the setup period of the reset period. Here, the setup pulse applied to the setup period of the reset period among the reset pulses applied to the remaining subfields except for one subfield of the second frame may be a bias voltage. Further, more preferably, the above-described bias voltage value may be a voltage value Vs of the sustain pulse.

In other words, when an afterimage pattern occurs according to the discharge load of the first frame (not shown) and the second frame, the setup pulse of the ramp-up in the reset period is set in the remaining subfields except for one of the second frames. Is not applied, but a setup pulse is maintained to maintain the sustain voltage (Vs).

Here, the point where the pulse of the rising ramp starts is the sustain voltage Vs. As such, maintaining the voltage at the point at which the rising ramp pulse starts is relatively easy in terms of control of the driving circuit.

In addition, generating the pulse of the rising ramp described above is, for example, a voltage source that is different from the voltage source supplying the sustain voltage Vs described above, thus switching the voltage source from one voltage source to another. The control of the drive is further complicated because additional switching is required for the operation. However, as in the present invention, supplying and maintaining the sustain voltage Vs in the setup period is easier to control because it does not require changing the voltage source.

In addition, since the rising ramp is removed in the setup period of the reset period in the remaining subfields except for one of the second frames, there is no influence on driving during driving to implement an image of the plasma display panel.

In addition, by applying a sustain voltage Vs to the scan electrode (not shown) in the setup period of the reset period in the remaining subfields except for one of the second frames, another subfield, that is, one of the second frames Since the pulse of the rising lamp having a relatively large voltage applied in the setup period of the subfield applied to the field is not applied, the power consumption of the rising lamp described above is prevented to reduce the overall power consumption of the plasma display panel. Accordingly, the driving efficiency of the plasma display panel is increased.

Here, the discharge loads of the first frame and the second frame described above are the number of data pulses applied in the address period of the second frame. Here, preferably, the number of data pulses applied to the address period of the second frame is determined by the data most applied to any one of the R, G, and B cells. For example, the discharge loads of the first frame and the second frame are divided into R, G, and B cells, respectively. If the number of data pulses applied to the address period of the second frame is 1024, the data pulses of 1024/3 are divided. Discharge rod classification is performed by selecting the maximum number of loads. In addition, when the number of data pulses applied to the R, G, B cells is differently applied, the discharge load is classified by selecting the maximum number of data pulses applied to the most applied cell among the R, G, B cells as the maximum load. You can proceed.

Looking at the driving device for implementing the drive waveform of the present invention as shown in FIG.

8 is a diagram for describing a driving apparatus of a plasma display panel for implementing driving waveforms according to a driving method of a plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 8, the driving apparatus of the plasma display panel according to the present invention includes a combination of at least one subfield in which a predetermined pulse is applied to an address electrode, a scan electrode, and a sustain electrode in a reset period, an address period, and a sustain period. By this, a predetermined number of frames are used to represent an image.

Here, the driving apparatus of the plasma display panel according to the present invention includes a panel 805 including a scan electrode, a subfield mapping unit 800, a timing controller 801, a data driver 802, a scan driver 803, and a sustain. The drive unit 804 is included.

The subfield mapping unit 800 maps the image data processed through a predetermined image processing process to subfields and outputs the image data. For example, motion processing, average power level (APL) processing, and halftone processing of image data input from an external predetermined signal processing means (not shown), for example, a VSC (Video Signal Controller) chip (not shown). After image processing through a process such as (Half Tone) correction, subfield mapping data is generated by mapping for each subfield, and the subfield mapping data is output.

The data driver 802 samples and latches a data pulse in response to the timing control signal CTRX from the timing controller 801, and then supplies the data pulse to the address electrodes X ₁ to Xm. .

The scan driver 803 adjusts the setup pulses applied to the scan electrodes Y ₁ to Yn during the setup period of the reset period under the control of the timing controller 801. Here, when the afterimage pattern is generated according to the discharge rods of the first frame and the second frame, the reset pulse applied to the remaining subfields except for one of the second frames is adjusted and applied to the scan electrode Y. . That is, a setup pulse applied to the setup period of the reset pulse applied to the remaining subfields other than one subfield of the second frame is adjusted and applied. Here, the setup pulse is preferably a bias voltage. In addition, the above-mentioned bias voltage value is preferably the voltage value Vs of the sustain pulse.

At this time, the two frames a sub-field scanning the rising lamp waveform (Ramp-Up), also falling ramp waveform (Ramp-Down) in the set-down period in the setup period of the reset pulse electrode of the (Y ₁ ~ Yn) To feed.

In addition, under the control of the timing controller 801, the scan pulse Sp of the scan voltage (-Vy) is sequentially supplied to the scan electrodes Y ₁ to Yn during the address period.

The sustain driver 804 supplies the bias voltage of the sustain voltage Vs to the sustain electrodes Z during the set down period and the address period of the reset period under the control of the timing controller 801, and the scan driver 803 during the sustain period. It alternately operates to supply the sustain pulse SUS to the sustain electrodes Z. Further, the sustain driver 804 may supply when the last sustain discharge end in a subfield erase ramp waveform (V _{(ramp- ers))} to the sustain electrode (Z).

The timing controller 801 receives the vertical and horizontal synchronizing signals and a predetermined clock signal and generates timing control signals CTRX, CTRY, and CTRZ for controlling the respective driving units 802, 803, and 804, and controls the timing. By supplying the signals CTRX, CTRY, and CTRZ to the corresponding driving units 802, 803, and 804, the operation of the driving units 802, 803, and 804 is controlled.

Here, the discharge loads of the first frame and the second frame described above are the number of data pulses applied to the address period of the second frame. Here, preferably, the number of data pulses applied to the address period of the second frame is determined by the data most applied to any one of the R, G, and B cells. For example, the discharge loads of the first frame and the second frame are divided into R, G, and B cells, respectively. If the number of data pulses applied to the address period of the second frame is 1024, the data pulses of 1024/3 are divided. Discharge rod classification is performed by selecting the maximum number of loads. In addition, when the number of data pulses applied to the R, G, B cells is differently applied, the discharge load is classified by selecting the maximum number of data pulses applied to the most applied cell among the R, G, B cells as the maximum load. You can proceed.

As described above, by setting the setup pulse applied to the setup period of the reset pulse applied to the remaining subfields other than one subfield of the second frame as the sustain voltage Vs, the rising ramp of a relatively high voltage ( The driving efficiency of the entire plasma display panel is improved by reducing the power consumption by ramp-up). In addition, the reset pulse of the present invention has a luminance difference of approximately 0 cd / m ² per pulse and the luminance difference is changed to an off cell compared to a reset pulse having a ramp-up of approximately 0.1 cd / m ² or more per pulse. This can reduce the level of afterimages that occur.

9 to 13, a plasma display driving method according to an exemplary embodiment of the present invention will be described.

9 is a diagram illustrating a driving waveform in accordance with a method of driving a plasma display panel according to an embodiment of the present invention. As shown in FIG. 9, the method for driving a plasma display panel according to the present invention represents an image in a plurality of frames, and each frame is divided into several subfields having different number of emission times. In other words, each frame may be composed of ten or twelve subfields having different number of emission times.

In addition, the plasma display panel is divided into a reset section for initializing the entire screen, an address section for selecting a cell to be discharged, a sustain section for maintaining the discharge of the selected cell, and an erasing section for erasing wall charges in the discharged cell. Driven. Here, the driving method of the plasma display panel according to the present invention is to the discharge rod of the second frame, the first frame (not shown) and the second frame continuous to the first frame (not shown) and the first frame (not shown). Accordingly, when the afterimage pattern is generated, the reset pulse is adjusted according to the number of reset pulses having the rising ramp pulse applied to the subfield of the second frame. Here, the second frame may be a plurality of frames.

In addition, the reset pulse having the rising ramp pulse applied to the subfield of the second frame may be adjusted while decreasing the setup pulse applied to the setup period of the reset period.

For example, when the number of reset pulses having the rising ramp pulses applied to the subfield of the second frame is 12 and the black luminance is high, the reset pulses having the rising ramp pulses are sequentially adjusted one by one from the next frame.

In FIG. 9, although the reset pulse having the rising ramp pulse is adjusted from the last subfield in one frame, that is, the twelfth subfield, the rising ramp pulse of one of the plurality of subfields is not necessarily adjusted from the last subfield. It is also possible to adjust the reset pulse having a. It is to be understood that this is not limited to this arbitrarily written to facilitate the description of the present invention.

11 is a view showing that the reset pulse is sequentially applied according to a predetermined time according to the driving method of the plasma display panel of the present invention. As shown in FIG. 11, the reset pulse having the rising ramp is sequentially adjusted according to a predetermined time. That is, it is necessary to adjust the reset pulse having the rising ramp by one increment every time one frame is crossed, and it is not necessary to adjust the reset pulse having the rising ramp in the subfield order or the reverse order. As described above, the embodiment shown in Figure 11 is made arbitrarily in order to facilitate the description of the present invention is not limited to this.

FIG. 10 is a diagram for describing region B of FIG. 9 in more detail. As shown in FIG. 10, a waveform of an adjusted reset pulse applied to a subfield of a second frame according to an embodiment of the present invention is shown.

The reset pulse having the rising ramp pulse applied to the subfield of the second frame described above adjusts the setup pulse applied to the setup section of the reset section. Here, the adjusted setup pulse is preferably a bias voltage. In addition, the above-mentioned bias voltage value is preferably the voltage value Vs of the sustain pulse.

In other words, the adjusted setup pulse is not applied with the setup pulse of the ramp-up in the reset period, but with the setup pulse for maintaining the sustain voltage Vs.

Here, the point where the pulse of the rising ramp starts is the sustain voltage Vs. As such, maintaining the voltage at the point at which the rising ramp pulse starts is relatively easy in terms of control of the driving circuit.

In addition, generating the pulse of the rising ramp described above is, for example, another voltage source different from the voltage source supplying the sustain voltage Vs described above, and thus the voltage source from one voltage source to another voltage source. The control of the drive is further complicated because additional switching is required for the operation of switching. However, as in the present invention, supplying and maintaining the sustain voltage Vs in the setup period is easier to control because it does not require changing the voltage source.

In contrast, when the number of reset pulses having the rising ramp pulses applied to the subfield of the second frame is 1 to 3 and the black luminance is low, the reset pulses are applied differently from the above-described driving waveforms. Looking at in detail with reference to Figure 13 as follows.

FIG. 12A illustrates a case where the number of reset pulses having the rising ramp pulses applied to the subfield of the second frame is 1 to 3, and FIG. 12B illustrates the rising ramp pulse described above. It is a diagram for explaining that the reset pulse having the control. As illustrated in FIG. 12, when the number of reset pulses having the rising ramp pulses applied to the subfield of the second frame is 1 to 3, the peak voltage of the rising ramp pulses is adjusted.

FIG. 13 is a diagram for describing regions C and D of FIG. 12 in more detail. , The control to lower when the number of the reset pulse having a rising ramp pulse personal 1-3 has a peak voltage (V _peak1) of the rising ramp pulse to the peak voltage (V _peak2) of the rising ramp of the present invention as shown in Figure 13 It is.

This is a reset pulse, if adjusted to the waveform may cause erroneous discharge peak voltage of the reset pulse having a rising ramp pulse (V _peak1) shown in Figure 10 when the number of reset pulses 1-3 dogs lower black luminance having a rising ramp pulse Lowering the value prevents mis-discharge and prevents sudden changes in black brightness.

Here, the discharge loads of the first frame and the second frame described above are the number of data pulses applied to the address period of the second frame. Here, preferably, the number of data pulses applied to the address period of the second frame is determined by the data most applied to any one of the R, G, and B cells. For example, the discharge loads of the first frame and the second frame are divided into R, G, and B cells, respectively. If the number of data pulses applied to the address period of the second frame is 1024, the data pulses of 1024/3 are divided. Discharge rod classification is performed by selecting the maximum number of loads. In addition, when the number of data pulses applied to the R, G, B cells is differently applied, the discharge load is classified by selecting the maximum number of data pulses applied to the most applied cell among the R, G, B cells as the maximum load. You can proceed.

Looking at the driving device for implementing the driving waveform of the present invention as shown in FIG.

FIG. 14 is a diagram for describing a driving apparatus of a plasma display panel for implementing driving waveforms according to a driving method of a plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 14, the driving apparatus of the plasma display panel according to the present invention includes a combination of at least one subfield in which a predetermined pulse is applied to an address electrode, a scan electrode, and a sustain electrode in a reset period, an address period, and a sustain period. By this, a predetermined number of frames are used to represent an image.

Here, the driving apparatus of the plasma display panel according to the present invention includes a panel 1405 including a scan electrode, a subfield mapping unit 1400, a timing controller 1401, a data driver 1402, a scan driver 1403, and a sustain driver. 1404.

The subfield mapping unit 1400 maps image data processed through a predetermined image processing process to subfields and outputs the image data. For example, motion processing, average power level (APL) processing, and halftone processing of image data input from an external predetermined signal processing means (not shown), for example, a VSC (Video Signal Controller) chip (not shown). After image processing through a process such as (Half Tone) correction, subfield mapping data is generated by mapping for each subfield, and the subfield mapping data is output.

The data driver 1402 samples and latches a data pulse in response to the timing control signal CTRX from the timing controller 1401, and then supplies the data pulse to the address electrodes X ₁ to Xm. .

The scan driver 1403 adjusts the setup pulses applied to the scan electrodes Y ₁ to Yn during the setup period of the reset period under the control of the timing controller 1401. Here, when the afterimage pattern is generated in the scan electrode (Y) according to the discharge load of the first frame and the second frame, the reset according to the number of reset pulses having the rising ramp pulse applied to the subfield of the second frame Adjust the pulse to apply. Here, the second frame is preferably a plurality of frames.

In addition, the scan driver 1403 sequentially adjusts and applies a setup pulse applied to the setup section of the reset section among the reset pulses having the rising ramp pulse applied to the subfield of the second frame. Here, the adjusted setup pulse is preferably a bias voltage. In addition, the above-mentioned bias voltage value is preferably the voltage value Vs of the sustain pulse.

In addition, the scan driver 1403 may apply the voltage value of the ground level GND to the voltage value of the setup pulse applied to the setup section of the reset section among the reset pulses having the rising ramp pulse applied to the subfield of the second frame. Be sure to

In addition, when the number of reset pulses having the rising ramp pulses applied to the subfield of the second frame is 1 to 3, the scan driver 1403 adjusts and applies them to lower the peak voltage of the rising ramp pulses.

Further, under the control of the timing controller 1401, the scan pulse Sp of the scan voltage (-Vy) is sequentially supplied to the scan electrodes Y ₁ to Yn during the address period.

The sustain driver 1404 supplies the bias voltage of the sustain voltage Vs to the sustain electrodes Z during the set down period and the address period of the reset period under the control of the timing controller 1401, and the scan driver 1403 during the sustain period. It alternately operates to supply the sustain pulse SUS to the sustain electrodes Z. Further, the sustain driving unit 1404 may supply when the last sustain discharge end in a subfield erase ramp waveform (V _{(ramp- ers))} to the sustain electrode (Z).

The timing controller 1401 receives the vertical and horizontal synchronization signals and a predetermined clock signal, and generates timing control signals CTRX, CTRY, and CTRZ for controlling the driving units 1402, 1403, and 1404, and control the timing. By supplying the signals CTRX, CTRY, and CTRZ to the corresponding driving units 1402, 1403, and 1404, the operation of each of the driving units 1402, 1403, and 1404 is controlled.

Here, the discharge loads of the first frame and the second frame described above are the number of data pulses applied to the address period of the second frame. Here, preferably, the number of data pulses applied to the address period of the second frame is determined by the data most applied to any one of the R, G, and B cells. For example, the discharge loads of the first frame and the second frame are divided into R, G, and B cells, respectively. If the number of data pulses applied to the address period of the second frame is 1024, the data pulses of 1024/3 are divided. Discharge rod classification is performed by selecting the maximum number of loads. In addition, when the number of data pulses applied to the R, G, B cells is differently applied, the discharge load is classified by selecting the maximum number of data pulses applied to the most applied cell among the R, G, B cells as the maximum load. You can proceed.

As described above, by sequentially adjusting the setup pulses applied to the setup period of the reset pulse according to the number of reset pulses having the rise ramp pulses applied to the subfield of the second frame, The driving efficiency of the entire plasma display panel is improved by reducing the power consumption by ramp-up). In addition, by adjusting the reset pulse having the rising ramp pulse in accordance with the discharge load change, it is possible to prevent the occurrence of the erroneous discharge and a sudden change in the black brightness, it is possible to reduce the level of the afterimage.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains can understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. will be. Therefore, the above-described embodiments are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

The method and apparatus for driving a plasma display panel according to an exemplary embodiment of the present invention as described above can reduce the afterimage and improve the jitter characteristic by improving the reset pulse waveform applied to the reset section according to the discharge load. There is an effect that can prevent the discharge.

Claims (14)

A driving method of a plasma display panel in which a plurality of frames display an image, A first frame of the plurality of frames and a second frame continuous to the first frame, The number of rising ramp pulses applied in the setup period of the reset period of the plurality of subfields of the second frame is smaller than the number of the rising ramp pulses applied in the setup period of the reset period of the plurality of subfields of the first frame. And applying a bias voltage during a setup period of a reset period of a subfield to which the rising ramp pulse is not applied among the subfields of the second frame. The method of claim 1, And the second frame is a plurality of frames. The method according to claim 1 or 2, And the number of reset pulses having rising ramp pulses applied to the subfields of the second frame is sequentially reduced in the second frame. The method of claim 1, And the bias voltage value is a voltage value (Vs) of a sustain pulse. The method of claim 1, And when the number of reset pulses having the rising ramp pulses applied to the subfields of the second frame is one to three, adjusting the peak voltage of the rising ramp pulses to lower the peak voltage. The method of claim 1, And the discharge loads of the first frame and the second frame are the number of data pulses applied to the address period of the second frame. The method of claim 6, The number of data pulses applied to the address period of the second frame is determined by the data most applied to any one of the R, G, B cells. A panel comprising a scan electrode; The second frame includes a first frame of the plurality of frames and a second frame continuous to the first frame, and the number of the rising ramp pulses applied to the setup period of the reset period of the plurality of subfields of the first frame. The number of rising ramp pulses applied in the setup period of the reset period of the plurality of subfields is smaller, and in the setup period of the reset period of the subfield in which the rising ramp pulse is not applied among the subfields of the second frame. And a scan driver for applying a bias voltage. The method of claim 8, And the second frame is a plurality of frames. The method according to claim 8 or 9, And the scan driver controls the number of reset pulses having the rising ramp pulses applied to the subfields of the second frame by sequentially decreasing the number of reset pulses in the second frame. The method of claim 8, The bias voltage value is a driving device of the plasma display panel, characterized in that the voltage value (Vs) of the sustain pulse. The method of claim 8, And the scan driver adjusts the peak voltage of the rising ramp pulse to reduce the peak voltage when the number of reset pulses having the rising ramp pulse is applied to the subfield of the second frame is 1 to 3. Drive of the panel. The method of claim 8, And the discharge loads of the first frame and the second frame are the number of data pulses applied to the address period of the second frame. The method of claim 13, And the number of data pulses applied to the address period of the second frame is determined by the data most applied to any one of the R, G, and B cells.

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