KR100645792B1 - Driving Apparatus of Plasma Display Panel - Google Patents

Abstract

The present invention relates to a driving apparatus of a plasma display panel. The driving apparatus of the plasma display panel of the present invention includes a reset period including a setup period in which rising ramp waveforms are applied and a set-down period in which falling ramp waveforms are applied, and predetermined address electrodes, scan electrodes, and sustain electrodes in the address period and the sustain period. An apparatus for driving a plasma display panel which expresses an image by a combination of at least one subfield to which a pulse is applied, the subfield mapping for mapping and outputting image data processed through a predetermined image processing process into subfields part; A scan driver for applying a predetermined driving pulse to the scan electrode; And controlling the scan driver to apply a predetermined positive voltage to the scan electrode during the setup period of the reset period of the subfield in which the data pulse is not applied to the address electrode in the address period according to the subfield mapping data output by the subfield mapping unit. It includes a timing controller. According to the present invention, it is possible to improve the driving efficiency of the plasma display panel by reducing the power consumption by improving the reset pulse applied in the reset period in the subfield where no data pulse is applied in the address period.

Plasma Display Panel, Data Pulse, Frame, Subfield, Reset Period, Setup Period, Set Down Period

Description

Driving device for plasma display panel {Driving Apparatus of Plasma Display Panel}

1 is a diagram showing the structure of a typical plasma display panel.

2 is a diagram illustrating a method of implementing image gradation of a conventional plasma display panel.

3 is a view illustrating a driving waveform according to a driving method of a conventional plasma display panel.

4 is a view for explaining a driving waveform in one frame according to a conventional method for driving a plasma display panel.

5 is a view showing a driving waveform of the plasma display panel according to the first embodiment of the present invention;

FIG. 6 is a view for explaining region A in detail in the driving waveform shown in FIG. 5; FIG.

FIG. 7 is a view for explaining a driving apparatus of a plasma display panel for implementing the first embodiment of the present invention shown in FIG.

8 illustrates driving waveforms of a plasma display panel according to a second exemplary embodiment of the present invention.

FIG. 9 is a view for explaining region B in detail in the driving waveform shown in FIG. 8; FIG.

FIG. 10 is a view for explaining a driving apparatus of a plasma display panel for implementing a second embodiment of the present invention shown in FIG.

<Explanation of symbols for main parts of the drawings>

100: front panel 101: front glass

102 scan electrode 103 sustain electrode

104: upper dielectric layer 105: protective layer

110: rear panel 111: rear glass

112: partition 113: address electrode

114 phosphor layer 115 lower dielectric layer

a: transparent electrode b: bus electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a driving apparatus of a plasma display panel which improves driving efficiency by improving a reset pulse according to the presence or absence of a data pulse applied in a reset period.

In general, a plasma display panel is a partition wall formed between a front panel and a rear panel to form a unit cell, and each cell includes neon (Ne), helium (He), or a mixture of neon and helium (Ne + He) and An inert gas containing the same main discharge gas and a small amount of xenon is filled. When discharged by a high frequency voltage, the inert gas generates vacuum ultraviolet rays and emits phosphors formed between the partition walls to realize an image. Such a plasma display panel has a spotlight as a next generation display device because of its thin and light configuration.

1 illustrates a structure of a general plasma display panel.

As shown in FIG. 1, a plasma display panel includes a front panel in which a plurality of sustain electrode pairs formed by pairing a scan electrode 102 and a sustain electrode 103 are arranged on a front glass 101 that is a display surface on which an image is displayed. The rear panel 110 on which the plurality of address electrodes 113 are arranged so as to intersect the plurality of sustain electrode pairs on the back glass 111 forming the back surface 100 and the rear surface is coupled in parallel with a predetermined distance therebetween. .

The front panel 100 is made of a scan electrode 102 and a sustain electrode 103, that is, a transparent electrode (a) formed of a transparent ITO material and a metal material to mutually discharge and maintain light emission of the cells in one discharge cell. The scan electrode 102 and the sustain electrode 103 provided as the bus electrode b are included in pairs. The scan electrode 102 and the sustain electrode 103 are covered by one or more upper dielectric layers 104 that limit the discharge current and insulate the electrode pairs, and to facilitate the discharge conditions on the upper dielectric layer 104 top surface. A protective layer 105 on which magnesium oxide (MgO) is deposited is formed.

The rear panel 110 is arranged in such a manner that a plurality of discharge spaces, that is, strips 112 of a stripe type (or well type) for forming discharge cells are maintained in parallel. In addition, a plurality of address electrodes 113 which perform address discharge to generate vacuum ultraviolet rays are arranged in parallel with the partition wall 112. On the upper side of the rear substrate 110, R, G, and B phosphors 114 which emit visible light for image display during address discharge are coated. A lower dielectric layer 115 is formed between the address electrode 113 and the phosphor 114 to protect the address electrode 113.

A method of implementing image gradation in such a plasma display panel is shown in FIG. 2.

2 is a diagram illustrating a method of implementing image grayscale of a conventional plasma display panel.

As shown in FIG. 2, in the conventional method of expressing a gray level of a plasma display panel, a frame is divided into several subfields having different number of emission times, and each subfield is a reset period (RPD) for initializing all cells again. ) Is divided into an address period APD for selecting a cell to be discharged and a sustain period SPD for implementing gradation according to the number of discharges. For example, when displaying an image with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. 2, and eight subfields. Each of the SFs SF1 to SF8 is divided into a reset period, an address period, and a sustain period.

The reset period and the address period of each subfield are the same for each subfield. The address discharge for selecting the cell to be discharged is caused by the voltage difference between the address electrode and the transparent electrode which is the scan electrode. The sustain period is increased at a rate of 2 ⁿ ( ^where n = 0, 1, 2, 3, 4, 5, 6, 7) in each subfield. In this way, since the sustain period is different in each subfield, the gray scale of the image is expressed by adjusting the sustain period of each subfield, that is, the number of sustain discharges. The driving waveforms according to the driving method of the plasma display panel are shown in FIG. 3.

3 is a view illustrating a driving waveform according to a driving method of a conventional plasma display panel.

As shown in Fig. 3, the plasma display panel erases the reset period for initializing all the cells, the address period for selecting the cells to be discharged, the sustain period for maintaining the discharge of the selected cells, and the wall charges in the discharged cells. It is divided into an erase period for driving.

In the reset period, the rising ramp waveform Ramp-up is applied to all the scan electrodes at the same time in the setup period. This rising ramp waveform causes weak dark discharge within the full discharge cells. By this setup discharge, positive wall charges are accumulated on the address electrode and the sustain electrode, and negative wall charges are accumulated on the scan electrode.

In the set-down period, after the rising ramp waveform is supplied, the falling ramp waveform (Ramp-down) begins to fall from the positive voltage lower than the peak voltage of the rising ramp waveform and falls to a specific voltage level below the ground (GND) level voltage. By generating a weak erase discharge in the inside, the wall charges excessively formed in the scan electrode are sufficiently erased. By this set-down discharge, wall charges such that the address discharge can stably occur remain uniformly in the cells.

In the address period, the negative scan pulses are sequentially applied to the scan electrodes, and the positive data pulses are applied to the address electrodes in synchronization with the scan pulses. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the reset period are added, address discharge is generated in the discharge cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is applied. The sustain electrode is supplied with a positive polarity voltage Vz during the set down period and the address period so as to reduce the voltage difference with the scan electrode so as to prevent mis-discharge with the scan electrode.

In the sustain period, a sustain pulse Su is applied to the scan electrode and the sustain electrodes alternately. In the cell selected by the address discharge, as the wall voltage and the sustain pulse in the cell are added, a sustain discharge, that is, a display discharge, occurs between the scan electrode and the sustain electrode every time the sustain pulse is applied.

After the sustain discharge is completed, in the erase period, a voltage of an erase ramp waveform Ramp-ers having a small pulse width and a low voltage level is supplied to the sustain electrode to erase the wall charge remaining in the cells of the full screen.

Conventionally, these driving waveforms are applied to each subfield to form one frame. That is, driving waveforms as shown in FIG. 3 are applied to all subfields of one frame. Referring to the driving waveform in one frame as shown in FIG.

4 is a view for explaining a driving waveform in one frame according to a conventional method of driving a plasma display panel.

As shown in FIG. 4, the driving waveforms of FIG. 3 are conventionally applied to all subfields in one frame. For example, even when the sustain discharge is generated only in the fourth subfield SF4 and the fifth subfield SF5 as shown in FIG. 4B, other subfields, that is, the first, second, third, sixth, seventh and eighth subfields, are generated. All other pulses except data pulses are also applied to the fields SF1, SF2, SF3, SF6, SF7, SF8.

In other words, when a data pulse is applied to the address electrode X only in the fourth subfield SF4 having a weight of 8 and the fifth subfield SF5 having a weight of 16 in order to implement a gray scale of 24, The subfields to which the data pulses are not applied to the above-described address electrode X, that is, the first, second, third, sixth, seventh and eighth subfields SF1, SF2, SF3, SF6, SF7, SF8, are excluded from the data pulse. Other pulses, that is, pulses such as reset pulses, scan pulses, and sustain pulses, are applied to the scan electrode Y or the sustain electrode Z.

As a result, a predetermined driving pulse is supplied even in an unused subfield, that is, a subfield in which no data pulse is applied to the address electrode X, thereby reducing driving efficiency when the entire plasma display panel is driven.

In order to solve this problem, the present invention adjusts a driving pulse applied in an unused subfield, that is, a subfield in which no data pulse is applied to the address electrode X, to increase the driving efficiency of the plasma display panel. The purpose is to provide a drive device.

The driving apparatus of the plasma display panel according to the present invention for achieving the above object includes a reset period including a setup period in which a rising ramp waveform is applied and a setdown period in which a falling ramp waveform is applied, and an address electrode and a scan electrode in an address period and a sustain period. And a driving apparatus of a plasma display panel which expresses an image by a combination of at least one subfield in which a predetermined pulse is applied to the sustain electrode, wherein the image data processed through a predetermined image processing process is mapped to a subfield. An output subfield mapping unit; A scan driver for applying a predetermined driving pulse to the scan electrode; And apply a predetermined positive voltage to the scan electrode in a setup period of a reset period of a subfield in which a data pulse is not applied to the address electrode in the address period according to the subfield mapping data output by the subfield mapping unit. And a timing controller for controlling the scan driver.

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In addition, the driving apparatus of the plasma display panel of the present invention includes a reset period including a setup period in which a rising ramp waveform is applied and a setdown period in which a falling ramp waveform is applied, and an address electrode, a scan electrode, and a sustain electrode in an address period and a sustain period. A driving apparatus of a plasma display panel which expresses an image by a combination of at least one subfield to which a predetermined pulse is applied, the sub display which maps and outputs image data processed through a predetermined image processing process into subfields. A field mapping unit; A scan driver for applying a predetermined driving pulse to the scan electrode; And the scan driver to apply a predetermined positive voltage to the scan electrode in a reset period of a subfield in which a data pulse is not applied to the address electrode in the address period according to the subfield mapping data output by the subfield mapping unit. And a timing controller for controlling.

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The positive voltage is characterized in that the square wave.

The positive voltage is characterized in that the voltage level is the same as the voltage (Vs) level of the sustain pulse.

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Hereinafter, exemplary embodiments of a driving apparatus of a plasma display panel of the present invention will be described in detail with reference to the accompanying drawings.

<First Embodiment>

5 illustrates a driving waveform of the plasma display panel according to the first embodiment of the present invention.

As shown in Fig. 5, the first embodiment of the driving waveform of the plasma display panel of the present invention is applied to the address electrode X, the scan electrode Y and the sustain electrode Z in the reset period, the address period and the sustain period. In a plasma display panel which expresses an image composed of a predetermined number of frames by a combination of at least one subfield to which a predetermined pulse is applied, data pulses are applied to the address electrode X in the address period among the above-mentioned frames. In the unapplied subfield, the setup pulse applied to the scan electrode Y is adjusted in the setup period of the reset period. Here, in FIG. 5, the magnitudes of the scan pulses applied to the scan electrode Y and the data pulses applied to the address electrode X in the address period are shown to be larger than the sustain pulses applied in the sustain period. It is to be understood that the present invention is not limited thereto and is arbitrarily written to facilitate the description of the invention.

Here, the adjustment of the setup pulse is compared with FIG. 4, but the driving waveform of FIG. 4 has the same driving waveform applied to all the subfields within one frame. However, in the first embodiment of the present invention, the address period of one frame is In a subfield in which no data pulse is applied to the address electrode X, a predetermined positive voltage is applied to the scan electrode Y as a setup pulse in the setup period of the reset period. Preferably, the above-mentioned positive voltage is a square wave. That is, the setup pulse of the ramp-up is applied in FIG. 4, but the setup pulse of the square wave is applied in FIG. 5.

More preferably, the positive voltage applied to the scan electrode Y in the setup period in the subfield to which the data pulse as described above is not applied is the sustain voltage Vs. That is, in the subfield in which the data pulse is not applied to the address electrode X in the address period, the sustain voltage Vs, which is a predetermined positive voltage, is applied to the scan electrode Y in the setup period of the reset period and is maintained in the setup period. do. In other words, in the subfield in which the data pulse is not applied to the address electrode X in the address period, the setup pulse of the ramp-up is not applied in the reset period, and the setup pulse which maintains the sustain voltage Vs. Is applied.

For example, when sustain discharge is generated only in the fourth subfield SF4 and the fifth subfield SF5 as shown in FIG. 5B, the other subfields, that is, the first, the second, the third, the sixth, the seventh In the 8 subfields SF1, SF2, SF3, SF6, SF7, SF8, the sustain voltage Vs is applied to the scan electrode Y in the setup period of the reset period and held in the setup period.

In other words, in order to implement the gray level having the weight 24, the data pulse is applied to the address electrode X only in the fourth subfield SF4 having a weight of 8 and the fifth subfield SF5 having a weight of 16. In the case where sustain discharge is generated only in the sustain periods of the fourth subfield SF4 and the fifth subfield SF5, the subfields to which the data pulses are not applied to the above-described address electrode X, that is, the first, second, third, In the 6, 7, 8 subfields SF1, SF2, SF3, SF6, SF7, SF8, the sustain voltage Vs, which is a positive voltage, is applied to the scan electrode Y in the setup period of the reset period and is maintained in the setup period. . The sustain voltage Vs applied to the scan electrode Y in the setup period of the reset period in the subfield to which the data pulse is not applied will be described in more detail with reference to FIG. 6 as follows.

FIG. 6 is a diagram for describing region A in detail in the driving waveform shown in FIG. 5.

Referring to FIG. 6, in the subfield to which the data pulse is not applied, the sustain voltage Vs is applied and maintained to the scan electrode Y in the setup period of the reset period. As described above, the reason why the setup pulse applied to the scan electrode Y is set to the sustain voltage Vs in the setup period is as follows.

In the fourth subfield SF4 and the fifth subfield SF5 in FIG. 5B, that is, the subfield in which the data pulse is applied in the address period, the ramp ramps up to the scan electrode Y in the setup period of the reset period. A setup pulse of (Ramp-Up) is applied. Here, the point at which the above-mentioned setup pulse of the rising ramp starts to rise is the sustain voltage Vs. As such, maintaining the voltage at the point at which the rising ramp pulse starts is relatively easy in terms of control of the driving circuit.

In addition, generating the pulse of the rising ramp described above is, for example, a voltage source that is different from the voltage source supplying the aforementioned sustain voltage Vs, thus switching the voltage source from one voltage source to another. The control of the drive is further complicated because additional switching is required for the operation. However, as in the present invention, supplying and maintaining the sustain voltage Vs in the setup period is easier to control because it does not require changing the voltage source.

In addition, since the first embodiment of the present invention removes the rising ramp in the setup period of the reset period in the subfield in which no data pulse is applied in the address period and no discharge occurs, the image of the plasma display panel is implemented. It doesn't affect driving.

Further, by applying the sustain voltage Vs to the scan electrode Y in the setup period of the reset period in the subfield where no data pulse is applied, it is applied in the setup period of another subfield, that is, the subfield to which the data pulse is applied. Since the pulse of the rising lamp having a relatively large voltage is not applied, power consumption due to the above-mentioned rising lamp is prevented to reduce the overall power consumption of the plasma display panel. Accordingly, the driving efficiency of the plasma display panel is increased.

In the subfield in which no data pulse is applied to the address electrode X in the address period in the subfield, the voltage value of the setup pulse applied to the scan electrode in the setup period of the reset period maintains the voltage value of the ground level GND. It is also possible. That is, in the above, the sustain voltage, which is a positive square wave, is applied as the setup pulse in the setup period, but the voltage of the ground level GND is applied as the setup pulse in the setup period to further reduce power consumption and more easily control.

Looking at the driving device for implementing the first embodiment of the present invention as shown in FIG.

FIG. 7 is a diagram for describing a driving apparatus of a plasma display panel for implementing a first embodiment of the present invention illustrated in FIG. 5.

As shown in FIG. 7, the driving apparatus of the plasma display panel according to the present invention includes a combination of at least one subfield in which a predetermined pulse is applied to an address electrode, a scan electrode, and a sustain electrode in a reset period, an address period, and a sustain period. The subfield mapping unit 700, the timing controller 701, the data driver 702, the scan driver 703 and the sustain driver 704 in the apparatus for driving a plasma display panel expressing an image composed of a predetermined number of frames. ).

The subfield mapping unit 700 maps image data processed through a predetermined image processing process into subfields and outputs the image data. For example, motion processing, average power level (APL) processing, and halftone processing of image data input from an external predetermined signal processing means (not shown), for example, a VSC (Video Signal Controller) chip (not shown). After image processing through a process such as (Half Tone) correction, subfield mapping data is generated for each subfield, and the subfield mapping data is output.

The data driver 702 samples and latches a data pulse in response to the timing control signal CTRX from the timing controller 701 described above, and then supplies the data pulse to the address electrodes X ₁ to X _m . do.

The scan driver 703 adjusts the setup pulses applied to the scan electrodes Y ₁ to Y _n during the setup period of the reset period under the control of the timing controller 701. Here, in a subfield in which no data pulse is applied to the address electrode X in the address period in one frame, a predetermined positive voltage is applied to the scan electrode Y in the setup period of the reset period. That is, the setup pulse applied to the scan electrode Y is set to a predetermined positive voltage. This positive voltage is preferably a square wave.

In a subfield in which a data pulse is applied to the address electrode X in the address period in one frame, the ramp ramp up during the setup period of the reset period and the ramp ramp down during the set-down period. ) Is supplied to the scan electrodes Y ₁ to Y _n .

In addition, under the control of the timing controller 701, the scan pulse Sp of the scan voltage −Vy is sequentially supplied to the scan electrodes Y ₁ to Y _n during the address period.

The sustain driver 704 supplies the bias voltage of the sustain voltage Vs to the sustain electrodes Z during the set down period and the address period of the reset period under the control of the timing controller 701, and the scan driver 703 during the sustain period. It alternately operates to supply the sustain pulse SUS to the sustain electrodes Z. In addition, the sustain driver 704 may supply the erase lamp waveform V _(Ramp-ers ) to the sustain electrodes Z when the last sustain discharge is completed in one subfield.

The timing controller 701 receives the vertical and horizontal synchronizing signals and a predetermined clock signal and generates timing control signals CTRX, CTRY, and CTRZ for controlling the driving units 702, 703, and 704, and control the timing. The operation of the driving units 702, 703, 704 is controlled by supplying the signals CTRX, CTRY, CTRZ to the corresponding driving units 702, 703, 704.

In addition, the timing controller 701 uses the data mapped to each subfield in the above-described subfield mapping unit 700, and the subfield and data to which the data pulse is applied to the address electrode X in the address period in one frame. The subfield to which no pulse is applied is determined. According to the result determined in this way, the above-described scan driver 703 is controlled to adjust the setup pulse applied to the scan electrode in the setup period of the reset period in the subfield in which the data pulse is not applied to the address electrode X in the address period. .

As described above, the timing controller 701 is set to the scan electrode Y in the setup period of the reset period in the subfield in which the scan driver 703 does not apply the data pulse to the address electrode X in the address period. It is controlled to apply a positive voltage of, wherein the above-mentioned positive voltage is more preferably the sustain voltage (Vs). In addition, as described above, it is possible to set the positive voltage to the sustain voltage Vs, but it is also possible to set the above-mentioned positive voltage to the voltage of the ground level GND in order to further increase easier control and driving efficiency. Do.

As described in detail above, the setup pulse applied to the scan electrode in the setup period of the reset period in the subfield in which the data pulse is not applied to the address electrode X in the address period is set to the sustain voltage Vs as the positive voltage. By setting the power consumption by a relatively high voltage ramp-up, the driving efficiency of the entire plasma display panel is increased.

In the first embodiment of the present invention, the setup pulse applied to the scan electrode is set to the sustain voltage Vs in the setup period of the reset period in the subfield in which the data pulse is not applied to the address electrode X in the address period. However, the driving efficiency of the plasma display panel may be improved by adjusting the reset pulse applied in the reset period. The driving waveforms are described in the following second embodiment.

Second Embodiment

8 is a view showing a driving waveform of the plasma display panel according to the second embodiment of the present invention.

As shown in Fig. 8, the second embodiment of the driving waveform of the plasma display panel of the present invention is applied to the address electrode X, the scan electrode Y and the sustain electrode Z in the reset period, the address period and the sustain period. In a plasma display panel which expresses an image composed of a predetermined number of frames by a combination of at least one subfield to which a predetermined pulse is applied, data pulses are applied to the address electrode X in the address period among the above-mentioned frames. In the remaining subfields other than the subfield to be applied, that is, the subfield to which the data pulse is not applied, the reset pulse applied to the scan electrode Y is adjusted in the reset period.

Here, the adjustment of the reset pulse is compared with FIG. 4, and the driving waveform of FIG. 4 is the same driving waveform applied to all the subfields in one frame, respectively, and compared with the first embodiment of the present invention of FIG. 5. In the first embodiment of the present invention, in a subfield in which data pulses are not applied to the address electrode X in the address period in one frame, a predetermined positive voltage is applied as the setup pulse to the scan electrode Y in the setup period of the reset period. In the second embodiment of the present invention, in the subfield in which data pulses are not applied to the address electrode X in the address period in one frame, the predetermined positive voltage is applied to the scan electrode Y in the reset period. It is adjusted to be applied with this reset pulse. Here, it is preferable that the above-mentioned reset pulse of the positive voltage is a square wave. That is, in FIG. 4, the reset pulses of the ramp-up and ramp-down are applied in the reset period, but the reset pulse of the square wave is applied in FIG. 8.

More preferably, the positive voltage applied to the scan electrode Y in the reset period of the subfield to which the data pulse as described above is not applied is the voltage of the sustain voltage Vs or the ground level GND. For example, in the case of the voltage of the ground level GND, in the subfield in which the data pulse is not applied to the address electrode X in the address period, the ground level GND of the predetermined positive voltage to the scan electrode Y in the reset period. ) Is applied and maintained in the reset period. In other words, in the subfield in which the data pulse is not applied to the address electrode X in the address period, the setup pulse of the ramp-up and the setdown pulse of the ramp-down are not applied in the reset period. A reset pulse is applied to maintain the voltage at ground level GND. The same applies to the case of the sustain voltage Vs described above.

For example, when sustain discharge is generated only in the fourth subfield SF4 and the fifth subfield SF5, as shown in FIG. In the 8 subfields SF1, SF2, SF3, SF6, SF7, SF8, the ground level GND is applied to the scan electrode Y in the reset period and maintained in the reset period.

In other words, in order to implement the gray level having the weight 24, the data pulse is applied to the address electrode X only in the fourth subfield SF4 having a weight of 8 and the fifth subfield SF5 having a weight of 16. In the case where sustain discharge is generated only in the sustain periods of the fourth subfield SF4 and the fifth subfield SF5, the subfields to which the data pulses are not applied to the above-described address electrode X, that is, the first, second, third, In the 6, 7, 8 subfields SF1, SF2, SF3, SF6, SF7, SF8, the voltage of the ground level GND, which is a positive voltage, is applied to the scan electrode Y in the reset period and maintained in the reset period. As described above, the reset pulse applied to the scan electrode Y in the reset period in the subfield to which the data pulse is not applied will be described in detail with reference to FIG. 9.

FIG. 9 is a diagram for describing region B in detail in the driving waveform shown in FIG. 8.

Referring to FIG. 9, in the subfield to which the data pulse is not applied, the voltage of the ground level GND is applied and maintained to the scan electrode Y in the reset period. As described above, the reason why the reset pulse applied to the scan electrode Y is set to the voltage of the ground level GND in the reset period is as follows.

In the fourth subfield SF4 and the fifth subfield SF5 in FIG. 8B, that is, the subfield in which the data pulse is applied in the address period, the ramp ramps up to the scan electrode Y in the setup period of the reset period. A setup pulse of (Ramp-Up) is applied. Here, the voltage at the point where the reset period starts before the setup pulse of the rising ramp starts to rise is the voltage of the ground level GND. Thus, maintaining the voltage at the point at which the reset period starts is relatively easy in terms of control of the drive circuit.

In addition, generating the pulse of the rising ramp described above is, for example, switching for the operation of switching the voltage source for supplying the voltage of the rising ramp, unlike supplying and maintaining the voltage of the ground level GND described above. The control of the drive is further complicated because it is additionally necessary.

Further, a set down pulse of a ramp ramp down in the set down period is applied after the setup period of the above-described reset period. The set-down pulse of the falling ramp is similar to the setup pulse of the rising ramp described above, unlike the supply and maintenance of the voltage at the ground level GND, and additionally, switching for an operation of switching the voltage source for supplying the voltage of the falling ramp is additional. The control of the drive is more complicated because it is necessary.

However, as in the present invention, supplying and maintaining the voltage at the level of the ground level GND in the reset period is easier to control of the drive device because no control of the voltage source is required.

Further, by applying the voltage of the ground level GND to the scan electrode Y in the reset period in the subfield where no data pulse is applied, the relative voltage applied in the setup period of another subfield, that is, the subfield to which the data pulse is applied, is applied. Since the setup pulse of the rising lamp and the down lamp of the falling lamp having a large voltage are not applied, the power consumption of the rising lamp and the falling lamp is prevented, thereby reducing the overall power consumption of the plasma display panel. Accordingly, the driving efficiency of the plasma display panel is increased. In FIG. 8, the reset pulse applied in the reset period is illustrated and described as being the voltage of the ground level GND. However, as described above, the reset pulse may be set to the sustain voltage Vs, which is a square wave having a positive polarity.

Looking at the driving device for implementing the second embodiment of the present invention as shown in FIG.

FIG. 10 is a diagram for describing a driving apparatus of a plasma display panel for implementing a second embodiment of the present invention illustrated in FIG. 8.

As shown in FIG. 10, the driving apparatus of the plasma display panel according to the present invention is a combination of at least one subfield in which a predetermined pulse is applied to an address electrode, a scan electrode, and a sustain electrode in a reset period, an address period, and a sustain period. In the driving apparatus of the plasma display panel expressing an image composed of a predetermined number of frames, the subfield mapping unit 1000, the timing controller 1001, the data driver 1002, the scan driver 1003, and the sustain driver 1004. ).

The subfield mapping unit 1000 maps the image data processed through a predetermined image processing process into subfields and outputs the image data. For example, motion processing, average power level (APL) processing, and halftone processing of image data input from an external predetermined signal processing means (not shown), for example, a VSC (Video Signal Controller) chip (not shown). After image processing through a process such as (Half Tone) correction, subfield mapping data is generated for each subfield, and the subfield mapping data is output.

The data driver 1002 samples and latches a data pulse in response to the timing control signal CTRX from the timing controller 1001 described above, and then supplies the data pulse to the address electrodes X ₁ to X _m . do.

The scan driver 1003 adjusts reset pulses applied to the scan electrodes Y ₁ to Y _n during the reset period under the control of the timing controller 1001. Here, in a subfield in which data pulses are not applied to the address electrode X in the address period in one frame, a predetermined positive voltage is applied to the scan electrode Y in the reset period. That is, the reset pulse applied to the scan electrode Y is set to a predetermined positive voltage.

In the subfield in which the data pulse is applied to the address electrode X in the address period in one frame, the rising ramp waveform Ramp-up and the falling ramp waveform Ramp-down are scanned in the reset period Y _1. To Y _n ).

Further, under the control of the timing controller 1001, the scan pulse Sp of the scan voltage −Vy is sequentially supplied to the scan electrodes Y ₁ to Y _n during the address period.

The sustain driver 1004 supplies a bias voltage of the sustain voltage Vs to the sustain electrodes Z during the set down period and the address period of the reset period under the control of the timing controller 1001, and the scan driver 1003 during the sustain period. It alternately operates to supply the sustain pulse SUS to the sustain electrodes Z. In addition, the sustain driver 1004 may supply the erase lamp waveform V _(Ramp-ers ) to the sustain electrodes Z when the last sustain discharge is completed in one subfield.

The timing controller 1001 receives the vertical and horizontal synchronizing signals and a predetermined clock signal and generates timing control signals CTRX, CTRY, and CTRZ for controlling the driving units 1002, 1003, and 1004, and control the timing. The operation of each of the driving units 1002, 1003, and 1004 is controlled by supplying signals CTRX, CTRY, and CTRZ to the corresponding driving units 1002, 1003, and 1004.

In addition, the timing controller 1001 uses the data mapped for each subfield in the above-described subfield mapping unit 1000, and the subfield and data to which a data pulse is applied to the address electrode X in an address period in one frame. The subfield to which no pulse is applied is determined. The scan driver 1003 described above is controlled to adjust the reset pulse applied to the scan electrode in the reset period in the subfield in which the data pulse is not applied to the address electrode X in the address period according to the determination result.

As described above, the timing controller 1001 applies the predetermined positive voltage to the scan electrode in the reset period in the subfield in which the data driver is not applied to the address electrode X in the address period in the scan driver 1003. The above-mentioned positive voltage is more preferably a voltage of the ground level GND. In addition, it is preferable that the above-mentioned positive voltage is a square waveform sustain voltage vs.

As described above in detail, the reset pulse applied to the scan electrode in the reset period in the subfield in which the data pulse is not applied to the address electrode X in the address period is a voltage of the ground level GND or the positive voltage. By setting it as an adult square wave, that is, the sustain voltage Vs, the power consumption of the ramp-up and the ramp-down of a relatively high voltage is reduced, thereby driving the entire plasma display panel. Increase the efficiency

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the following claims rather than the foregoing description, and the meaning and scope of the claims. And all changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described in detail above, the driving apparatus of the plasma display panel of the present invention improves the driving efficiency of the plasma display panel by reducing the power consumption by improving the reset pulse applied in the reset period in the subfield where no data pulse is applied in the address period. The height is effective.

Claims (20)

delete delete delete delete delete A reset period including a setup period in which a rising ramp waveform is applied and a set-down period in which a falling ramp waveform is applied, and at least one subfield in which a predetermined pulse is applied to the address electrode, the scan electrode, and the sustain electrode in the address period and the sustain period. A driving apparatus for a plasma display panel which expresses an image by a combination of A subfield mapping unit for mapping and outputting image data processed through a predetermined image processing process into subfields; A scan driver for applying a predetermined driving pulse to the scan electrode; And The scan such that a predetermined positive voltage is applied to the scan electrode in a setup period of a reset period of a subfield in which a data pulse is not applied to the address electrode in the address period according to the subfield mapping data output by the subfield mapping unit. And a timing controller for controlling the driver. delete The method of claim 6, And wherein the positive voltage is a square wave. The method of claim 6, And wherein the positive voltage is equal to the voltage (Vs) level of the sustain pulse. delete delete delete delete delete delete A reset period including a setup period in which a rising ramp waveform is applied and a set-down period in which a falling ramp waveform is applied, and at least one subfield in which a predetermined pulse is applied to the address electrode, the scan electrode, and the sustain electrode in the address period and the sustain period. A driving apparatus for a plasma display panel which expresses an image by a combination of A subfield mapping unit for mapping and outputting image data processed through a predetermined image processing process into subfields; A scan driver for applying a predetermined driving pulse to the scan electrode; And The scan driver is controlled such that a predetermined positive voltage is applied to the scan electrode in the reset period of the subfield in which the data pulse is not applied to the address electrode in the address period according to the subfield mapping data output by the subfield mapping unit. And a timing controller for driving the plasma display panel. delete The method of claim 16, And wherein the positive voltage is a square wave. The method of claim 16, And wherein the positive voltage is equal to the voltage (Vs) level of the sustain pulse. delete

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