JP2002351396A - Driving device of plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To greatly reduce changes of making erroneous discharge in a maintaining period and no lighting and to realize a stable driving by improving the discharging probability of discharging during a maintaining period with an optimum maintaining time and optimum power consumption. SOLUTION: The plasma display panel is provided with a plurality of opposing first and second display electrodes located between a pair of parallel substrates and data electrodes that are arranged orthogonal to the first display electrodes. The panel has at least an initializing period, a writing period, a maintaining period and an erasing period. In the plasma display panel, the pulse width of the voltage and the magnitude of the voltage in the maintaining period are varied between subfields or within a subfield.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method of a plasma display panel, particularly, a facing three-electrode surface discharge type AC plasma display panel, which has an optimal sustaining time, an optimal power consumption, and a discharge probability during a sustaining period discharge. And a driving method for remarkably improving erroneous discharge and no light during the sustain period and realizing stable driving.

[0002]

2. Description of the Related Art A plasma display panel is a display that excites and emits a phosphor by ultraviolet rays generated by gas discharge to display an image. The discharge can be classified into an alternating current (AC) type and a direct current (DC) type based on the method of forming the discharge. The AC type is characterized by being superior to the DC type in luminance, luminous efficiency, and life. Furthermore, among the AC types, the reflection type surface discharge type is the most common because it is particularly outstanding in terms of luminance and luminous efficiency.

FIG. 2 is a perspective view schematically showing an AC type plasma display panel (hereinafter, referred to as a PDP) as an example of the related art. Thus, the PDP has R (red), G
A large number of cells that emit light of each color (green) and B (blue) are arranged.

[0004] The structure and operation will be described below. First, the description will be made from the front panel FP side. A plurality of transparent electrodes 34 (ITO or SnO ₂ is used) are formed on the front panel glass 21 (most commonly, a glass plate is used). However, this transparent electrode 3
No. 4 has a high sheet resistance and cannot supply sufficient power to all the pixels in a large panel. Therefore, a silver thick film, an aluminum thin film, chromium / copper / chromium (Cr / Cu / Cr) 3) Bus electrode 3 with laminated thin film
5 are formed. The bus electrode 35 apparently lowers the sheet resistance of the transparent electrode 34. A transparent dielectric layer 24 (low melting glass is used) on these electrodes
And protection layer 25 made of magnesium oxide (MgO)
Are formed. The dielectric layer 24 has a current limiting function peculiar to the AC type plasma display, and is a factor that can make the life longer than that of the DC type. Protective layer 25
Is used to protect the dielectric layer 24 from being sputtered by electric discharge so that the dielectric layer 24 has excellent sputter resistance, has a high secondary electron emission coefficient (γ), and reduces the discharge starting voltage. With.

The other back panel BP will be described. On the back panel glass 26, a data electrode 27 for writing image data, a base dielectric layer 33, a partition wall 28, and phosphor layers 30 (R), 31 (G), 32 (B) are formed. Here, the data electrode 27 and the partition 28
Are disposed so as to be orthogonal to the transparent electrode 34, and form a discharge space 29 by a space surrounded by two partition walls 28. In the discharge space 29, neon (Ne) is used as a discharge gas. And a mixed gas of xenon (Xe) at a pressure of about 66.5 kPa (500 Torr). Further, the partition wall 28 partitions the adjacent discharge cells to prevent erroneous discharge and optical crosstalk.

An AC voltage of several tens of kHz to several hundreds of kHz is applied between the transparent electrodes 34 to generate a discharge in the discharge space 29, and the fluorescent layers 30, 31, 32 are excited by ultraviolet rays from the excited Xe atoms. To generate visible light to perform a display operation.

Next, FIG. 3 shows an electrode arrangement diagram of this panel. The electrodes have an m × n matrix configuration, m columns of data electrodes D1 to Dm are arranged in the column direction, and n rows of scan electrodes SCN1 to SCNn and sustain electrodes SUS1 to SUSn are arranged in the row direction. ing.

FIG. 4 shows an operation drive timing chart of a driving method for driving this panel.

As shown in FIG. 4, one field period is
It is composed of first to n-th subfields having at least a writing period and a sustaining period. In each subfield, the number of sustaining pulses is different, and gradation is displayed by a combination of the subfields. It is assumed that one field includes at least one subfield having an initialization period or an erasing period. As an example, FIG. 4 shows a subfield having both the initialization period and the erasing period as an example.

Next, each period will be described.

First, an initialization pulse is applied to the scan electrodes SCN1 to SCNn in FIG. 3 to initialize wall charges in the discharge cells of the panel. Next, in the writing period, in order to perform display on the first row, a scan pulse voltage is applied to the scan electrodes SCN1 on the first row, and the data electrode groups D1 to D1 corresponding to the discharge cells are applied.
Dm, a write pulse voltage is applied to the data electrode group D1.
A write discharge (address discharge) is caused between .about.Dm and the scan electrode SCN1 in the first row, a wall charge is accumulated on the surface of the dielectric layer, and a write operation (address operation) in the first row is performed. The above operations are sequentially performed, and the writing operation of the Nth row is completed, and a latent image for one screen is written. Next, in the sustain period, the data electrode groups D1 to Dm are grounded, a sustain pulse voltage is first applied to all the sustain electrode groups SUS1 to SUSn, and then all the scan electrode groups SCN1 to SCN
By applying the sustain pulse voltage to n and subsequently applying the sustain pulse voltage alternately, the sustain discharge is continuously emitted in the discharge cells where the write operation has been performed in the write period. Is displayed on the screen. Thereafter, in the erasing period, a discharge is generated by applying a narrow erasing pulse, and the wall charges disappear, so that an erasing operation is performed.

As described above, image display is performed by a series of driving methods of the initialization period, the writing period, the sustaining period, and the erasing period.

[0013]

In the conventional driving method,
Between all subfields, within the subfield, the write pulse voltage and the pulse width of the voltage applied in the sustain period were fixed, so that the discharge cells with a low discharge probability or the same discharge cells in the period with a low discharge probability, There has been a problem that image quality is deteriorated such as flickering or non-lighting of an image.

As a method for solving this problem, it has been attempted to lengthen all the pulse widths or set all the pulse application voltages to be high. However, there is a problem that the occupation time becomes longer and the gradation display is restricted. Further, when the pulse application voltage is increased, there is a problem that erroneous discharge such as self-erasure occurs in a cell having a low discharge start voltage.

The present invention solves the above-mentioned conventional problems, and provides a method capable of shortening the occupation time of the sustain period as much as possible, reducing power consumption as much as possible, and obtaining stable driving.

[0016]

In order to achieve the above object,
In the driving method of the plasma display panel according to the first aspect of the present invention, a plurality of first and second display electrodes facing each other are disposed between a pair of parallel substrates, and are arranged so as to be orthogonal to the first display electrodes. In a plasma display panel including a data electrode and at least an initialization period, a writing period, a sustaining period, and an erasing period, a pulse width of a voltage in the sustaining period is changed in a subfield. In a period in which the discharge probability is low, by increasing the pulse width, the formation of wall charges during that period is completed, the discharge probability is increased, and a stable maintenance operation is obtained. Further, in a period in which the probability of discharge is high, by shortening the pulse width, the time of the sustain period can be shortened.

According to a second aspect of the present invention, there is provided a driving method of a plasma display panel, wherein a plurality of first and second display electrodes opposed to each other between a pair of parallel substrates are orthogonal to the first display electrodes. In a plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, the pulse width of the voltage during the sustaining period is set between a subfield with initialization and a subfield without initialization. It is characterized by changing.

According to a third aspect of the present invention, there is provided a driving method of a plasma display panel, wherein a plurality of opposed first and second display electrodes are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. In the plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, the pulse width of the voltage in the sustaining period has an erasing period in the immediately preceding subfield. It is characterized by changing between subfields and non-subfields.

According to a fourth aspect of the present invention, there is provided a driving method of a plasma display panel, wherein a plurality of first and second display electrodes facing each other are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. In the plasma display panel provided with the arranged data electrodes and including at least an initializing period, a writing period, a sustaining period, and an erasing period, the pulse width of the voltage in the sustaining period was turned on by the immediately preceding subfield. It is characterized in that it is changed between a subfield and a subfield that is not lit.

According to a fifth aspect of the present invention, there is provided a driving method for a plasma display panel, wherein a plurality of opposed first and second display electrodes are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. In a plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, the pulse width of the voltage during the sustaining period is set to a subfield having a low discharge probability and a subfield having a high discharge probability. It is characterized by changing.

According to a sixth aspect of the present invention, in the method for driving a plasma display panel, a plurality of first and second display electrodes facing each other between a pair of parallel substrates so as to be orthogonal to the first display electrodes. In the plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, the pulse width of the voltage in the sustaining period is changed by the number of pulses.

According to a seventh aspect of the present invention, in the driving method of the plasma display panel, the pulse width of the voltage during the sustain period is 500.
ns to 10 μs.

According to an eighth aspect of the present invention, there is provided a driving method of a plasma display panel, wherein a plurality of opposed first and second display electrodes are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. In the plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, the pulse width of the voltage during the sustaining period is changed within a subfield.

A driving method of a plasma display panel according to a ninth aspect of the present invention is characterized in that the pulse width of the voltage in the sustain period is made shorter as the pulse is later.

According to a tenth aspect of the present invention, in the driving method of the plasma display panel, the voltage pulse width of the sustain period is 5
00 ns to 10 μs.

In a driving method of a plasma display panel according to an eleventh aspect of the present invention, a plurality of opposed first and second display electrodes are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. In the plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, a voltage in the sustaining period is changed in a subfield. In a period where the discharge probability is low, the discharge probability is increased by increasing the applied voltage, and a stable maintenance operation can be obtained. In a cell having a high discharge probability, erroneous discharge such as self-erasing and power consumption can be reduced by lowering the applied voltage.

According to a twelfth aspect of the present invention, in the method of driving a plasma display panel, a plurality of first and second display electrodes opposed to each other between a pair of parallel substrates so as to be orthogonal to the first display electrodes. Provided in the plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, wherein the voltage of the sustaining period is changed between a subfield with initialization and a subfield without initialization. Features.

According to a thirteenth aspect of the present invention, there is provided a driving method for a plasma display panel, wherein a plurality of opposed first and second display electrodes are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. In the plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, the voltage of the sustaining period is set to a subfield having an erasing period in the immediately preceding subfield. It is characterized in that it is changed with no subfield.

According to a fourteenth aspect of the present invention, in the method of driving a plasma display panel, a plurality of opposed first and second display electrodes are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. In the plasma display panel comprising an arranged data electrode and at least an initialization period, a writing period, a sustaining period, and an erasing period, the voltage of the sustaining period is set to the subfield in which the immediately preceding subfield was lit. It is characterized in that it is changed in a subfield that is not lit.

According to a fifteenth aspect of the present invention, there is provided a driving method of a plasma display panel, wherein a plurality of first and second display electrodes opposed to each other between a pair of parallel substrates are orthogonal to the first display electrodes. Provided in the plasma display panel comprising at least an initializing period, a writing period, a sustaining period, and an erasing period, wherein the voltage of the sustaining period is changed between a subfield having a low discharge probability and a subfield having a high discharge probability. Features.

According to a sixteenth aspect of the present invention, in the method of driving a plasma display panel, a plurality of opposed first and second display electrodes are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. In the plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, the voltage in the sustaining period is changed by the number of pulses.

According to a seventeenth aspect of the present invention, in the driving method of the plasma display panel, the voltage during the sustain period is 130 V to 3 V.
It is characterized by being 00V.

In the driving method of a plasma display panel according to the present invention, a plurality of opposed first and second display electrodes are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. In the plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, the voltage of the sustaining period is changed within a subfield.

A driving method of a plasma display panel according to a nineteenth aspect of the present invention is characterized in that the voltage during the sustain period is made lower as the pulse is later.

According to a twentieth aspect of the present invention, in the driving method of the plasma display panel, the voltage during the sustain period is 130 V to 3 V.
It is characterized by being 00V.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to the accompanying drawings.

(Embodiment 1) The basic structure of a PDP panel used in the present invention is the same as that of a conventional PDP panel. The manufacturing method will be described below with reference to FIG.

(Overall Manufacturing Method of PDP) (Preparation of Front Panel) The front panel FP is made of ITO or tin oxide (Sn) on the front panel glass 21.
O ₂ ) or other transparent conductive material, and a silver (Ag) thick film (thickness: 2 μm to 10 μm), an aluminum (Al) thin film (thickness: 0.1 μm to 1 μm) or a Cr / Cu / Cr laminate Thin film (thickness: 0.1 μm-1 μm)
m) are sequentially laminated, and further, lead oxide (PbO), bismuth oxide (Bi ₂ O ₃ ), or phosphorus oxide (PO ₄ ) is used as a main component (for example, lead oxide (Pb
O) 70 wt%, 15 wt% boron oxide (B ₂ O _3), silicon oxide (SiO ₂₎ dielectric layer 24 screen printing composed of 15 wt%) and to a low melting point glass (thickness 20Myuemu～50myuemu) (die coating It can also be formed by printing or a film laminating method). For example, in the case of a silver electrode, an ink for a silver electrode containing an ultraviolet-sensitive resin is uniformly applied onto the front glass panel 21 by a screen printing method, dried, and then formed by patterning and baking by exposure and development. Next, a protective layer 25 made of MgO for protecting the dielectric layer 24 from damage by plasma.
(Thickness: 100 nm to 1000 nm) are formed and stacked by an electron beam evaporation method or a sputtering method.

(Preparation of Back Panel) On the back panel BP side, a silver (Ag) thick film (thickness: 2 μm to 10 μm) and an aluminum (Al) thin film (thickness: 0.1 μm to 1 μm) are formed on the back panel glass 26. ) Or Cr / Cu / C
The data electrode 27 made of a laminated thin film (thickness: 0.1 μm to 1 μm), lead oxide (PbO) or bismuth oxide (B
A base dielectric layer 33 made of low-melting glass (thickness: 5 μm to 20 μm) containing i ₂ O ₃ ) or phosphorus oxide (PO ₄ ) as a main component is formed. Further, partition walls 2 mainly composed of glass
8 are formed at a predetermined pitch, and phosphor layers 30, 31, and 32 made of a red phosphor, a green phosphor, and a blue phosphor are formed in each space sandwiched by the partition walls 28, thereby forming the back panel BP side. Have been. Here, the base dielectric layer 33 is for improving the adhesion to the partition wall 28, and does not mean that the plasma display panel does not operate without it. The phosphor is a red phosphor,
The phosphor layers 30, 31, and 32 are formed by applying a green phosphor and a blue phosphor, respectively, by an ink ejection method. As the phosphor of each color, phosphor materials generally used for a plasma display panel are shown below. Here, these phosphors are used.

Red phosphor: (Y _X Gd _{1 -X} ) BO ₃ : Eu
³⁺ or YBO ₃ : Eu ³⁺ green phosphor: BaAl ₁₂ O ₁₉ : Mn or Zn ₂ Si
O ₄ : Mn Blue phosphor: BaMgAl ₁₀ O ₁₇ : Eu ²⁺ Each color phosphor is produced as follows.

The blue phosphor is prepared by first using barium carbonate (BaCO ₃ ), magnesium carbonate (MgCO ₃ ),
Aluminum oxide (α-Al ₂ O ₃ ) is mixed at a molar ratio of 1: 1 to 5: 1. Next, a predetermined amount of europium oxide (Eu ₂ O ₃ ) is added to the mixture. Then, the mixture is mixed with an appropriate amount of flux (AlF ₂ , BaCl ₂ ) in a ball mill, and calcined at 1000 ° C. to 1200 ° C. for a predetermined time (for example, 5 hours) in a weak reducing atmosphere (in H ₂ , N ₂ ). To obtain.

The red phosphor is prepared by mixing yttrium oxide (Y ₂ O ₃ ) and boric acid (H ₃ BO ₃ ) in a molar ratio of 0.5 to 1 as raw materials. Next, a predetermined amount of europium oxide (Eu ₂ O ₃ ) was added to the mixture, and the mixture was mixed with a proper amount of a flux by a ball mill.
After firing at 0 ° C. for a predetermined time (for example, 5 hours), this is sieved to obtain the powder.

The green phosphor is made of zinc oxide (Zn) as a raw material.
O), silicon oxide (SiO_Two) In a molar ratio of 2: 1
You. Next, a predetermined amount of manganese oxide is added to the mixture.
(Mn _TwoO_Three) Was added and mixed in a ball mill.
Firing at 50 ° C to 1200 ° C for a predetermined time (for example, 5 hours)
And sifting this to get it. After that, the ink ejection method
Red, green and blue phosphors (30, 3
1, 32) are formed.

(Preparation of PDP by Panel Lamination)
Next, the front panel and the back panel thus manufactured are attached to each other using sealing glass,
A high vacuum (1 × 1)
After exhausting to 0 ^-4 Pa), a plasma display panel is manufactured by filling a discharge gas having a predetermined composition at a predetermined pressure. As an example, the mixed gas of neon gas and xenon gas is 95% and 5% by volume, respectively, and the pressure is 66.5 kPa (500 Torr).

(Driving Method of PDP) The driving method of the plasma display panel according to the embodiment of the present invention has the same set values as those of the conventional driving method except for the sustain pulse width and the sustain voltage. Also, the sustain pulse width and the sustain voltage were 2.5 μs and 180 V in the case of VGA, and 2.5 μs and 160 V in the case of XGA.

The thickness of the dielectric layer 24 is 30 to 42 μm, and the thickness of the MgO protective layer 25 is 0.5
μm to 0.8 μm, the gap between the scanning electrode 22 and the sustain electrode 23 is 40 μm to 120 μm, and the height of the partition wall 28 is 80 μm.
The experiment was performed under the conditions of m to 120 μm.

In a panel for VGA display (853 × 480 pixels), as an example, the pitch between partition walls is 360 μm, the thickness of the dielectric layer 24 is 42 μm, the thickness of the MgO protective layer 25 is 0.8 μm, and the scanning electrode 22 is formed. In a panel having a structure in which the gap between the electrode and the sustain electrode 23 is 80 μm and the height of the partition 28 is 120 μm, the voltage setting values in FIG.
-100V, Vc = -20V, Vd = 140V, Ve =
150 V, Vs = 180 V, and Vdat = 67 V.

In a panel of a 42 inch class XGA display (1024 × 768 pixels), as an example, the pitch between partition walls is 300 μm, the thickness of the dielectric layer 24 is 35 μm, and
The thickness of the MgO protective layer 25 is 0.8 μm,
In a panel having a gap of 80 μm between the electrode and the sustain electrode 23 and a height of the partition wall of 120 μm, the voltage setting values in FIG. 4 are set to Va = 400V, Vb = −90V, Vc = −10V, V
d = 140V, Ve = 150V, Vs = 160V, Vd
At is set to 67V.

(Measurement of Discharge Probability) The probability of generation of a discharge during the time when a voltage pulse is applied was determined as follows. This includes the time until a discharge is formed (hereinafter, referred to as tf) and the statistical delay time of the discharge (hereinafter, tf).
s) and the voltage pulse width. For example, the technical report of the Institute of Television Engineers of Japan vol.19, No.6
6, 1955, the P55～66, probability N (t _pw) / N ₀ of occurrence of discharge the pulse width t _{pw is, N (t pw) / N} 0 = 1-exp (- (t pw −tf) / ts) (1) The discharge probability can be obtained by measuring tf and ts from equation (1). The criteria for the pulse width are 2.
Calculated as 5 μs.

A shown in claims 8 to 10 of the present invention
A driving method of the C-type plasma display panel will be described. FIG. 1 shows an operation drive timing chart. One field period includes first to n-th subfields having an initialization period, a writing period, a sustaining period, and an erasing period.

An experiment was conducted by lighting only 7SF on a VGA panel and changing each pulse width of the sustain period based on the conventional pulse width (2.5 μs).

The discharge probability of the reference pulse width of the first pulse in the sustain period is about 30 to 60%, the discharge probability becomes 95% or more by setting the pulse width to 3 μs, and the discharge probability by setting the pulse width to 5 μs. Was 99% or more, and a stable discharge was obtained.

Also, 95% from the first pulse to the ninth pulse
When the pulse width is changed after the tenth pulse in the state where the lamp is turned on with the above probability, the discharge probability is maintained at 95% even if the pulse width is reduced to 1 μs, and 90% when the pulse width is reduced to 500 ns.
%, And below that, the probability of discharge decreased. Second
Regarding the ninth pulse, the discharge probability is reduced by reducing the pulse width, and the discharge probability is 95% in the range of 2 μs or more.
, And 90% when 1 μs is set.

By increasing the pulse width, the formation of wall charges during that period is completed, the probability of discharge increases, and a stable maintenance operation can be obtained. Further, in a period in which the discharge probability is high, the time of the sustain period can be shortened by shortening the pulse width. In the period where the discharge probability is high (95% or more), the pulse width is 500 ns to 3 μs, and the discharge probability is low (70% or less).
In the period, the pulse width is set to 3 μs to 10 μs, and in the intermediate period, the pulse width is set to 1 μs to 5 μs, whereby a stable maintenance operation is realized. In order to secure a discharge probability of 95% or more and shorten the time, it is more preferable that the pulse width be 1 μs to 2.5 μs during the period of high discharge probability and 5 μs to 8 μs during the period of low discharge probability. In the intermediate period, 2 μs to 4 μs is desirable.

The time can be shortened by increasing the pulse width of the sustain period in a period having a low discharge probability or shortening the pulse width in a period having a high discharge probability within one subfield. Also, the number of pulses can be increased by the amount of time reduction, which leads to an increase in luminance. In particular, the SF having the sustain pulse number of 100 or more has an effect that the luminance is 1.4 to 2 times. The same effect was obtained with the XGA panel.

(Embodiment 2) Claims 18 to 2 of the present invention
A method of driving the AC type plasma display panel shown in FIG. FIG. 5 shows an operation drive timing chart. In the first embodiment, the configuration other than the sustain pulse width and the voltage setting and the panel structure are the same, and the description is omitted.

In the VGA panel, the conventional pulse voltage (2.
The experiment was performed by changing each pulse voltage during the sustain period with reference to 5 μs, 180 V).

The discharge probability of the reference pulse voltage of the first pulse in the sustain period was about 30 to 60%, and the discharge probability was 95% or more by setting the pulse voltage to 190 V, and a stable discharge was obtained. When the voltage was set to 300 V, erroneous discharge of other cells was generated.

Also, 95% from the first pulse to the ninth pulse
When the pulse voltage after the 10th pulse is changed in the state where the lamp is turned on with the above probability, a discharge probability of 95% is secured even when the pulse voltage is reduced to 150V, and 90% when the pulse voltage is reduced to 130V. Below, the discharge probability decreased. With respect to the second to ninth pulses, the discharge probability was reduced by lowering the pulse voltage, and the discharge probability was secured at 95% in the range of 165 V or more, and was reduced to 90% or less at 160 V or less.

By increasing the applied voltage, the probability of discharge increases, and a stable maintenance operation can be obtained. In a cell having a high discharge probability, erroneous discharge such as self-erasing and power consumption can be reduced by lowering the applied voltage. During a period in which the discharge probability is high (95% or more), the applied voltage is 130 V to 180 V.
V, the applied voltage is 190 V to 300 V during a period in which the discharge probability is low (70% or less), and the applied voltage is 160 V to 190 V during an intermediate period, whereby a stable maintenance operation is realized. In order to secure a discharge probability of 95% or more and reduce power consumption, it is more preferable that the applied voltage is 150 V to 175 V during the period of high discharge probability, and 190 V to 250 V during the period of low discharge probability. In the intermediate period, the applied voltage is desirably 165 V to 185 V.

By setting the applied voltage in the sustain period to be high in a period having a low discharge probability or low in a period having a high discharge probability in one subfield, a low power consumption and stable maintenance operation can be achieved. can get. The same effect was obtained with the XGA panel.

In the subfield, the first embodiment
The same effect can be obtained by combining with a pulse width as shown in FIG.

(Embodiment 3) A method of driving an AC type plasma display panel according to claims 1 to 7 of the present invention will be described. FIG. 6 shows an operation drive timing chart. Since the panel structure is the same as in the first and second embodiments, the description is omitted. The operation drive waveform is Vb = 0, V
The other settings are the same as in the first embodiment except for d = 0.

In the VGA panel, the conventional pulse voltage (2.
The experiment was performed by changing each pulse voltage during the sustain period with reference to 5 μs, 180 V).

As an example of a subfield in which the previous subfield is lit and a subfield which is not lit, the subfield is shown as (m) subfield and (m + 1) subfield, respectively. The lit cell has a shorter pulse width because the discharge probability increases due to the influence of priming and the like, and the unlit cell has a longer pulse width. In the figure,
The applied voltage and the pulse width in the subfield are all the same, but the pulse width may be changed in the subfield as in the first embodiment, or the applied voltage and the pulse width may be changed in the subfield as in the second embodiment. Changing has the same effect.

As an example of a subfield having an initialization period and a subfield having no initialization period, (m + 1)
The subfield is shown as (m + 2) subfield. Here, the pulse width of the applied voltage in the subfield without initialization is long, but the potential of the falling part of the initialization voltage determines the amount of wall charge accumulated on the electrode, and thereby the cell Since the voltage inside is determined and the discharge probability can be adjusted, for the subfield with initialization,
It can be relatively short. This is also effective in combination with the first and second embodiments, similarly to the above.

Further, as an example of a subfield having an erasing period and a subfield having no erasing period in the immediately preceding subfield, (m + 1) subfield and (m + 3) subfield are shown, respectively. Since the discharge probability changes depending on the pulse width of the erasing period, the presence or absence of the subsequent initialization period, and the potential of the falling portion of the applied voltage in the initialization period, the pulse width of the applied voltage is set longer according to the setting. It can be as short as possible. This is also effective in combination with the first and second embodiments, similarly to the above.

(Embodiment 4) Claims 11 to 1 of the present invention
The method for driving the AC plasma display panel shown in FIG. 7 will be described. FIG. 7 shows an operation drive timing chart. Since the panel structure is the same as in the first and second embodiments, the description is omitted. The operation drive waveform is Vb =
0, Vd = 0 and the other settings are the same as those in the first embodiment.

As an example of a subfield in which the previous subfield was lit and a subfield which was not lit, the subfield is shown as (m) subfield and (m + 1) subfield, respectively. The applied voltage of the lit cell is low because the probability of discharge increases due to the influence of priming and the like, and the unlit cell is high. In the figure,
The applied voltage and the pulse width in the subfield are all the same, but the pulse width may be changed in the subfield as in the first embodiment, or the applied voltage and the pulse width may be changed in the subfield as in the second embodiment. And the combination with the third embodiment has the same effect.

As an example of a subfield with an initialization period and a subfield without an initialization period, (m + 1)
The subfield is shown as (m + 2) subfield. Here, the applied voltage of the subfield without initialization is set high, but the potential of the falling portion of the initialization voltage determines the amount of wall charges accumulated on the electrode, and thereby the voltage in the cell. Is determined, and the discharge probability can be adjusted. Therefore, it is possible to set a relatively low value for a subfield having initialization. This is also effective in combination with the first, second, and third embodiments similarly to the above.

Further, (m + 1) subfield and (m + 3) subfield are respectively shown as examples of a subfield having an erasing period and a subfield having no erasing period in the immediately preceding subfield. In the (m + 3) subfield, an example in combination with the first embodiment is described. Since the discharge probability changes depending on the pulse width of the erase period, the presence or absence of the subsequent initialization period, and the potential of the falling portion of the applied voltage in the initialization period, the applied voltage in the sustain period is
Depending on the setting, it can be set higher or lower. This is also effective in combination with the first, second, and third embodiments similarly to the above.

[0072]

As described above, according to the present invention, the discharge probability at the time of discharge during the sustain period is improved with the optimum sustain time and the optimum power consumption, and the erroneous discharge and no light during the sustain period are remarkably improved. Stable driving can be realized.

[Brief description of the drawings]

FIG. 1 is an operation drive timing chart showing a method for driving an AC plasma display panel according to a first embodiment of the present invention;

FIG. 2 is a perspective view schematically showing an AC type plasma display panel.

FIG. 3 is an electrode arrangement diagram

FIG. 4 is a timing chart of a conventional drive waveform.

FIG. 5 is an operation drive timing chart showing a method for driving an AC plasma display panel according to a second embodiment of the present invention;

FIG. 6 is an operation drive timing chart showing a method for driving an AC plasma display panel according to a third embodiment of the present invention;

FIG. 7 is an operation drive timing chart showing a method of driving an AC plasma display panel according to a fourth embodiment of the present invention.

[Explanation of symbols]

 FP front panel BP back panel 21 front panel glass 22 scan electrode 23 sustain electrode 24 dielectric layer 25 protective layer 26 back panel glass 27 data electrode 28 partition wall 29 discharge space 30 phosphor (R) 31 phosphor (G) 32 phosphor (B) 33 dielectric layer

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Ryuji Kurata 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Yusuke Takada 1006 Kadoma Kadoma Kadoma City, Osaka Prefecture 72) Ryuichi Murai 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture F-term (reference) 5C058 AA11 BA02 BA04 5C080 AA05 BB05 DD09 HH05 JJ02 JJ04 JJ06

Claims (20)

[Claims] 1. A plurality of first and second display electrodes facing each other between a pair of parallel substrates, and a data electrode arranged to be orthogonal to the first display electrodes, and at least initialization is performed. A plasma display panel comprising a period, a write period, a sustain period, and an erase period, wherein the pulse width of the voltage in the sustain period is changed in a subfield. 2. A plurality of first and second display electrodes facing each other between a pair of parallel substrates, and data electrodes arranged to be orthogonal to the first display electrodes, and at least initialization is performed. A plasma display panel comprising a period, a writing period, a sustaining period, and an erasing period, wherein the pulse width of the voltage in the sustaining period is changed between a subfield with initialization and a subfield without initialization. . 3. A plurality of first and second display electrodes facing each other between a pair of parallel substrates and a data electrode arranged so as to be orthogonal to the first display electrodes, and at least initialization is performed. Period, a write period, a sustain period, and an erase period, wherein the pulse width of the voltage of the sustain period is changed between a subfield having an erase period and a subfield without an erase period in the immediately preceding subfield. Of driving a plasma display panel. 4. A plurality of first and second display electrodes facing each other between a pair of parallel substrates and a data electrode arranged to be orthogonal to the first display electrodes, and at least initialization is performed. In a plasma display panel including a period, a writing period, a sustaining period, and an erasing period, the pulse width of the voltage in the sustaining period is changed between a subfield in which the previous subfield was lit and a subfield which was not lit. A method for driving a plasma display panel, comprising: 5. A plurality of first and second display electrodes facing each other between a pair of parallel substrates and a data electrode arranged to be orthogonal to the first display electrodes, and at least initialization is performed. A plasma display panel comprising a period, a writing period, a sustaining period, and an erasing period, wherein the pulse width of the voltage during the sustaining period is changed between a subfield having a low discharge probability and a subfield having a high discharge probability. . 6. A plurality of first and second display electrodes opposed to each other between a pair of parallel substrates, and a data electrode arranged to be orthogonal to the first display electrodes, and at least initialization is performed. In a plasma display panel including a period, a writing period, a sustaining period, and an erasing period, a driving method of the plasma display panel, wherein the pulse width of the voltage in the sustaining period is changed by the number of pulses. 7. A pulse width of a sustain period voltage is 500 ns.
The driving method of a plasma display panel according to claim 1, wherein the driving time is 10 to 10 μs. 8. A plurality of first and second display electrodes facing each other between a pair of parallel substrates, and a data electrode arranged to be orthogonal to the first display electrodes, and at least initialization is performed. In a plasma display panel including a period, a writing period, a sustaining period, and an erasing period, a driving method of the plasma display panel, wherein a pulse width of a voltage in the sustaining period is changed within a subfield. 9. The driving method for a plasma display panel according to claim 8, wherein the pulse width of the voltage during the sustain period is made shorter as the pulse is later. 10. The pulse width of the sustain period voltage is 500
The driving method of a plasma display panel according to claim 8, wherein the driving time is ns to 10 μs. 11. A plurality of first and second display electrodes facing each other between a pair of parallel substrates, and a data electrode arranged to be orthogonal to the first display electrode, and at least initialization is performed. In a plasma display panel including a period, a writing period, a sustaining period, and an erasing period, a voltage of the sustaining period is changed in a subfield, and a driving method of the plasma display panel. 12. A plurality of first and second display electrodes facing each other between a pair of parallel substrates, and a data electrode arranged to be orthogonal to the first display electrode, and at least initialization is performed. In a plasma display panel including a period, a write period, a sustain period, and an erase period, a voltage of the sustain period is changed between a subfield with initialization and a subfield without initialization. 13. A plurality of first and second display electrodes facing each other between a pair of parallel substrates, and a data electrode arranged to be orthogonal to the first display electrode, and at least initialization is performed. A plasma display panel comprising a period, a writing period, a sustaining period, and an erasing period, wherein the voltage of the sustaining period is changed between a subfield having an erasing period and a subfield having no erasing period in the immediately preceding subfield. Panel driving method. 14. A plurality of first and second display electrodes facing each other between a pair of parallel substrates, and a data electrode arranged so as to be orthogonal to the first display electrodes, and at least initialization is performed. Period, a writing period, a sustaining period, and an erasing period, wherein the voltage of the sustaining period is changed between a subfield where the previous subfield was lit and a subfield which was not lit. Of driving a plasma display panel. 15. A plurality of first and second display electrodes facing each other between a pair of parallel substrates, and a data electrode arranged to be orthogonal to the first display electrode, and at least initialization is performed. A plasma display panel comprising a period, a writing period, a sustaining period, and an erasing period, wherein the voltage of the sustaining period is changed between a subfield having a low discharge probability and a subfield having a high discharge probability. 16. A plurality of first and second display electrodes facing each other between a pair of parallel substrates and a data electrode arranged so as to be orthogonal to the first display electrode, and at least initialization is performed. A method for driving a plasma display panel, comprising: changing a voltage of the sustain period by the number of pulses in a plasma display panel including a period, a write period, a sustain period, and an erase period. 17. The voltage of the sustain period is 130 V to 300 V.
17. The method of driving a plasma display panel according to claim 11, wherein V is V. 18. A plurality of first and second display electrodes opposed to each other between a pair of parallel substrates, and data electrodes arranged to be orthogonal to the first display electrodes, and at least initialization is performed. In a plasma display panel including a period, a writing period, a sustaining period, and an erasing period, a voltage of the sustaining period is changed within a subfield. 19. The method of driving a plasma display panel according to claim 18, wherein the voltage during the sustain period is made lower as the pulse is later. 20. A voltage during a sustain period is 130 V to 300 V.
20. The method of driving a plasma display panel according to claim 18, wherein V is V.