JP2002366089A - Method for driving plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve stable drive by reducing write failure due to the erase failure of barrier electric charges in an erase period. SOLUTION: In this method of driving a plasma display panel in which a frame is time-divided into a plurality of sub-fields and each subfield consists of at least a write period, a sustaining period and an erase period, a small-width pulse having a positive potential is applied to a scanning electrode and a data electrode simultaneously in the cycle of once in every 1 to 30 frames in the erase period or in fields having high gradation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for driving a plasma display panel, and more particularly to a method for driving a plasma display panel for high definition.

[0002]

2. Description of the Related Art In recent years, expectations for high-definition and large-screen televisions such as high-definition televisions have been increasing.
CRT, liquid crystal display (hereinafter, referred to as LCD), plasma display panel (Plasma D)
In the field of each display such as display panel (hereinafter referred to as PDP), a display suitable for this is being developed.

Conventionally, CRTs, which have been widely used as television displays, are excellent in resolution and image quality, but have a large screen of 40 inches or more in that the depth and weight increase with the screen size. Is not suitable. In addition, LCDs have excellent performances of low power consumption and low driving voltage, but have technical difficulties in producing a large screen, and have a limited viewing angle.

On the other hand, a PDP can realize a large screen even with a small depth, and a 50-inch class product has already been developed.

[0005] PDPs are roughly classified into a direct current type (DC type) and an alternating current type (AC type). At present, the AC type suitable for enlargement is mainly used.

FIG. 1 is a partial perspective view of a conventional AC plasma display panel (hereinafter referred to as a panel).

(Overall Configuration and Manufacturing Method of PDP) As shown in a schematic perspective view of FIG. 1, the opposed AC discharge type PDP according to the embodiment of the present invention has R (red), G (green), and B (green). Blue)
A large number of cells emitting the respective colors are arranged.

[0008] This PDP has a front panel glass 21.
A front panel on which discharge electrodes (scanning electrodes) 22, (sustain electrodes) 23, a dielectric film 24 and an MgO protective film 25 are disposed, and a data electrode 2 on a back panel glass 26
7, a discharge gas is sealed in a discharge space 29 formed between the back panel on which the partition walls 28 and the phosphor layers 30, 31, 32 are arranged, and is manufactured as described below. .

(Fabrication of Front Panel) The front panel comprises a front panel glass substrate 21 and discharge electrodes 22 and
23 is formed, and is covered with a lead-based dielectric glass layer 24, and an MgO protective layer 25 is further formed on the surface thereof.

In this embodiment, a discharge electrode (display electrode)
Reference numerals 22 and 23 denote silver electrodes, which are formed by uniformly applying an ink for a silver electrode containing an ultraviolet-sensitive resin on the front glass panel 21 by screen printing and drying, and then performing patterning and baking by exposure and development.

The composition of the dielectric glass 24 is 70% by weight of lead oxide [PbO], 15% by weight of boron oxide [B ₂ O ₃ ], and 15% by weight of silicon oxide [SiO ₂ ]. And baking.

The MgO protective layer 25 is made of magnesium oxide [MgO] and is formed by a sputtering method.

(Preparation of Back Panel) In the back panel, a data electrode 27 is formed on a back panel glass 26, glass partitions 28 are formed on the data electrodes 27 at a predetermined pitch, and each is sandwiched between the partitions 28. It is manufactured by forming phosphor layers 30, 31, and 32 of a red phosphor, a green phosphor, and a blue phosphor in a space.

In this embodiment, the data electrode 27 is a silver electrode, and a silver electrode ink containing an ultraviolet-sensitive resin is uniformly applied on the back panel glass 26 by a screen printing method. After drying, patterning by exposure and development and baking are performed.

The partition 28 is formed by repeatedly printing several times by a screen printing method.

Further, a red phosphor, a green phosphor, and a blue phosphor are respectively applied to the spaces sandwiched by the partition walls 28 by an ink discharge method, so that the phosphor layer 30,
31 and 32 are formed. As the phosphor of each color, a phosphor generally used for a plasma display panel can be used. Here, the following phosphor is used.

Red phosphor: (Y _X Gd _{1 -X} ) BO ₃ : Eu
³⁺ or YBO ₃ : Eu ³⁺ green phosphor: BaAl ₁₂ O ₁₉ : Mn or Zn ₂ Si
O ₄ : Mn Blue phosphor: BaMgAl ₁₀ O ₁₇ : Eu ²⁺ (Preparation of PDP by panel bonding) Next, the front panel and the back panel thus prepared are bonded together using sealing glass. A high vacuum (8 × 10 ⁻⁷ Torr) is formed in the discharge space 29 partitioned by the partition wall 28.
(1064 × 10 ⁻⁷ Pa)), and then a discharge gas having a predetermined composition is sealed at a predetermined pressure to manufacture a plasma display panel.

Next, FIG. 2 shows an electrode arrangement diagram of this panel. As shown in FIG. 2, the electrode arrangement of this panel is m × n
And m columns of data electrodes D1 to Dm are arranged in the column direction, and n rows of scan electrodes SCN1 to SCNn and sustain electrodes SUS1 to SU in the row direction.
Sn is arranged. Further, the discharge cell shown in FIG. 1 is configured as shown in FIG.

FIG. 3 shows an operation drive timing chart of a conventional drive method for driving this panel.

As shown in FIG. 3, one field period is
The first to n-th subfields having an initialization period, a writing period, a sustaining period, and an erasing period,
Thus, gradation display is performed.

First, an initialization pulse is applied to the scan electrodes SCN1 to SCNn shown in FIG. 2 to initialize wall charges in the discharge cells of the panel.

Next, in order to perform the display of the first row in the writing period, a scan pulse voltage is applied to the scan electrodes SCN1 of the first row, and the data electrode groups D1 to D1 corresponding to the discharge cells are applied.
Dm, a write pulse voltage is applied to the data electrode group D1.
A write discharge is caused between .about.Dm and the scan electrode SCN1 in the first row, wall charges are accumulated on the surface of the dielectric layer, and a write operation in the first row is performed.

The above-described operations are sequentially performed, and the writing operation on the Nth row is completed, and a latent image for one screen is written.

Next, in the sustain period, the data electrode group D1
To Dm are grounded, and all the sustain electrode groups SUS1 to SU
By applying a sustain pulse voltage to Sn, subsequently applying a sustain pulse voltage to all of the scan electrode groups SCN1 to SCNn, and subsequently alternately applying the sustain pulse voltage, writing is performed in the write period. In the discharge cell where the operation has been performed, the light emission of the sustain discharge is continuously performed, and the screen is displayed.

Thereafter, in the erasing period, a discharge is generated by applying a narrow erasing pulse, and the wall charges disappear, so that an erasing operation is performed.

As described above, in the conventional PDP driving method,
Image display is performed by a series of driving methods including an initialization period, a writing period, a sustaining period, and an erasing period.

[0027]

In the above-described conventional structure, wall charges are accumulated without being completely erased during the erasing period, and writing errors occur in the subsequent writing period, causing problems such as erroneous discharge and no lighting. Was.

An object of the present invention is to solve the above-mentioned conventional problems, reduce writing defects due to wall charge erasure failure during the erasing period, and realize stable driving.

[0029]

According to a method for driving a plasma display panel, a frame is time-divided into a plurality of subfields, and the subfield includes at least a writing period, a sustaining period, and an erasing period. The scanning electrode, the data electrode, and the means for simultaneously inputting a narrow pulse of a positive potential are used once every 30 frames or in a field having a high gradation.

Still further, in the method for driving a plasma display panel, wherein one frame is time-divided into a plurality of subfields, and the subfields include at least a writing period, a sustaining period, and an erasing period.
The same effect can be obtained by simultaneously applying a narrow pulse having a negative potential to the sustain electrode and a positive potential to the scan electrode at a cycle of once every 30 frames or in a high-gradation field.

Further, in a method of driving a plasma display panel in which one frame is time-divided into a plurality of sub-fields, and the sub-field includes at least a writing period, a sustaining period, and an erasing period,
The same effect can be obtained by simultaneously applying a narrow pulse having a negative potential to the sustain electrode and a positive potential to the data electrode in a cycle of once every 30 frames or in a field having a high gradation.

[0032]

Embodiments of the present invention will be described below. The driving waveform of the AC type plasma display panel used in the present invention will be described with reference to FIGS. FIG. 4 shows a conventional driving waveform.

(Embodiment 1) FIG. 6A shows a driving waveform for measuring the amount of remaining wall charges. In the sustain period, sustain pulse voltages (Vs respectively) applied to the scan electrode and the sustain electrode
(Scn), Vs (sus)), a positive pulse voltage is applied to the data electrode, and the W of one cell is changed.
VIO (Wall Voltage Input Ou)
put) measurements were taken. Here, the pulse width of the sustain period: 5 μs, the reference voltage: 300 V, the narrow pulse width: 2 μ
s, the rest period after the sustain period was 200 μs, and the Vdat pulse width was 100 μs. FIG. 6 (b) shows the remaining wall charge obtained therefrom. It can be seen that wall charges remain even when the Vs (sus) voltage is increased to 330 V. As described above, since the data voltage largely depends on the Vs (sus) voltage at the time of erasing, the negative wall charge on the sustain electrode or the positive wall charge on the data electrode located below the sustain electrode is erased. I understand that there is no. The remaining wall charges continue to accumulate in each lighting subfield, causing erroneous discharge in the non-lighting subfield.

Next, FIG. 6C shows the result of applying a narrow pulse to the data electrode simultaneously with the narrow pulse applied to the scanning electrode and changing the voltage. The narrow pulse width at this time is 1 μs. From this result, it can be seen that a discharge was generated between the sustain electrode and the data electrode, and these wall charges could be erased. Applying a voltage to the data electrodes at the same time lowers the firing voltage between the scan electrodes and the sustain electrodes and increases the scale of the SCN-SUS discharge, so that wall charges near the bus electrodes are easily erased.

Based on this result, a narrow pulse (Vdat (reset)) was applied to the data electrode simultaneously with the narrow pulse applied to the scanning electrode as shown in FIG. At the start of the address period of the actual drive (FIG. 4), the wall charges on the data electrodes located below the scan electrodes are about 0 V to 70 V.
V (here, as an example, V
a = 220V, Vb = 100V, Vc = 80V, Vd =
140V, Ve = 150V, Vs = 180V, Vdat
= 67V). Therefore, in order to suppress erroneous discharge,
It is necessary to keep the voltage between the sustain electrode and the data electrode below the voltage between the scan electrode and the data electrode, and Vdat (res
et) By setting the voltage to 40 V to 80 V, erroneous discharge could be suppressed. Further, the narrow pulse width is desirably 0.6 μs to 2 μs from the relationship between the discharge delay and the wall charge formation time.

However, applying a voltage to the data electrode to discharge it leads to an increase in the power consumption of the data driver. Therefore, it is necessary to perform the operation once every 1 to 30 frames or in a high gradation field. desirable.

(Embodiment 2) Claims 5 to 8 will be described with reference to FIG.

Simultaneously with the narrow pulse applied to the scanning electrode,
A negative potential narrow pulse (Vsus (rese
By applying t)), similarly to the first embodiment, wall charges on the data electrodes located below the sustain electrodes or wall charges on the sustain electrodes could be erased. This means that a discharge is generated between the sustain electrode and the data electrode, and the SCN-SUS
It can be seen that the wall charges near the bus electrode far from the inter-discharge gap are easily erased. Further, it can be seen that applying a negative potential voltage to the sustain electrode makes it easier to discharge at a lower voltage than when the MgO side is the cathode and the phosphor side is the cathode.

The Vsus (reset) voltage is -150
By setting the voltage to V to -100 V, erroneous discharge could be suppressed. Further, the narrow pulse width is desirably 0.6 μs to 2 μs from the relationship between the discharge delay and the wall charge formation time.

However, since the generation of the discharge between the data electrode and the sustain electrode leads to an increase in the power consumption of the data driver, the discharge occurs once every 1 to 30 frames or when the gradation is high. It is desirable to do it in the field.

(Embodiment 3) Claims 9 to 12 will be described with reference to FIG.

By applying a narrow pulse of a positive potential (Vdat (reset)) to a data electrode simultaneously with a narrow pulse of a negative potential (Vsus (reset)) applied to a sustain electrode, Similarly, the wall charge on the data electrode located below the sustain electrode or the wall charge on the sustain electrode could be erased.

The Vdat (reset) voltage is from 40 V
By setting the voltage to 80 V, erroneous discharge could be suppressed. Further, the narrow pulse width is desirably 0.6 μs to 2 μs from the relationship between the discharge delay and the wall charge formation time.

However, applying a voltage to the data electrode to discharge it leads to an increase in power consumption of the data driver. Therefore, it is necessary to perform the operation once every 1 to 30 frames or in a field having a high gradation. desirable.

[0045]

According to the present invention, it is possible to reduce writing defects due to wall charge erasure failure during the erasure period, and realize stable driving.

[Brief description of the drawings]

FIG. 1 is a perspective view schematically showing an AC type plasma display panel.

FIG. 2 is an electrode arrangement diagram

FIG. 3 is a drive waveform timing chart.

FIG. 4 is a diagram showing a driving waveform of a conventional AC plasma display panel.

FIG. 5 is a view showing a driving waveform of the plasma display panel according to the first embodiment of the present invention;

6A is a diagram showing a drive waveform for measuring the amount of remaining wall charges, FIG. 6B is a diagram showing the amount of remaining wall charges when Vs (scn) or Vs (sus) is changed, and FIG. 6C is a diagram showing Vdat (reset). Figure showing the amount of residual wall charge when) is applied

FIG. 7 is a diagram showing driving waveforms of a plasma display panel according to a second embodiment of the present invention.

FIG. 8 is a diagram showing driving waveforms of a plasma display panel according to a third embodiment of the present invention.

[Explanation of symbols]

 FP front panel BP back panel 21 front panel glass 22 scan electrode 23 sustain electrode 24 dielectric film 25 protective film 26 back panel glass 27 data electrode 28 partition wall 29 discharge space 30 phosphor (R) 31 phosphor (G) 32 phosphor (B) 33 dielectric film

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Ryuji Kurata 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F-term (reference) 5C058 AA11 BA02 BA35 5C080 AA05 BB05 DD09 FF12 HH07 JJ04 JJ05 JJ06

Claims (12)

[Claims] 1. A method of driving a plasma display panel in which one frame is divided into a plurality of subfields, wherein the subfield includes at least a writing period, a sustaining period, and an erasing period. A method for driving a plasma display panel, characterized in that a narrow pulse of a positive potential is simultaneously applied to a scanning electrode and a data electrode in each cycle. 2. A method for driving a plasma display panel, wherein one frame is divided into a plurality of subfields, wherein the subfields include at least a writing period, a sustaining period, and an erasing period. , A scanning electrode, a data electrode, and a narrow pulse of a positive potential applied simultaneously. 3. The method of driving a plasma display panel according to claim 2, wherein a narrow pulse width applied to the scan electrode and the data electrode is set to 0.6 μs to 2 μs. 4. The method according to claim 3, wherein the voltage of the narrow pulse applied to the data electrode ranges from 40V to 80V. 5. A method for driving a plasma display panel, wherein one frame is divided into a plurality of subfields, wherein the subfield includes at least a writing period, a sustain period, and an erasing period. A method for driving a plasma display panel, characterized in that a narrow pulse of a negative potential is applied to a sustain electrode and a narrow pulse of a positive potential is applied to a scan electrode at the same time. 6. A method of driving a plasma display panel, wherein one frame is divided into a plurality of subfields, and the subfields include at least a writing period, a sustain period, and an erasing period. A driving method for a plasma display panel, wherein a narrow pulse of a negative potential is applied to a sustain electrode and a narrow pulse of a positive potential is applied to a scanning electrode at the same time. 7. The method of driving a plasma display panel according to claim 5, wherein a narrow pulse width applied to the sustain electrode and the scan electrode is set to 0.6 μs to 2 μs. 8. The method according to claim 7, wherein the voltage of the narrow pulse applied to the sustain electrode ranges from −150V to −100V. 9. A method of driving a plasma display panel, wherein one frame is divided into a plurality of subfields, and the subfield includes at least a writing period, a sustaining period, and an erasing period. A driving method for a plasma display panel, characterized in that a narrow pulse of a negative potential is applied to a sustain electrode and a narrow pulse of a positive potential is applied to a data electrode at the same time. 10. A method of driving a plasma display panel in which one frame is time-divided into a plurality of subfields, and the subfields include at least a writing period, a sustaining period, and an erasing period. A driving method for driving a plasma display panel, wherein a narrow pulse having a negative potential is applied to a sustain electrode and a narrow pulse having a positive potential is applied to a data electrode at the same time. 11. The method according to claim 9, wherein a narrow pulse width applied to the sustain electrode and the data electrode is set to 0.6 μs to 2 μs. 12. The method according to claim 1, wherein the voltage of the narrow pulse applied to the data electrode ranges from 40V to 80V.
2. The method for driving a plasma display panel according to item 1.