JP2000267625A - Gas discharge panel display device and gas discharge panel driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gas discharge panel display device and a gas discharge panel driving method capable of realizing a precise structure and a high luminance. SOLUTION: In the gas discharge panel driving method, a voltage waveform to apply to a group of scanning electrodes at the time of set up at the time of driving a PDP by an intra-field time division intensity level assigning display system is boosted to a voltage which is not lower than 100 V but lower than a discharge starting voltage in a section A2 in a period not longer than 10 μsec and after then, boosted to voltage which is not lower than the discharge starting voltage by inclination which is not larger than 9 V/μsec in a section A3. After then, it is lowered to voltage which is not lower than 50 V but lower than the discharge starting voltage in a period not longer than 10 μsec in a section A5 and after then, is lowered between 100 to 250 μsec by inclination not larger than 9 V/μsec in a section A6. Then, a period in which this set up voltage is applied is set to be not longer than 360 μsec.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a gas discharge panel display device such as a PDP display device used for a computer, a television and the like, and a method of driving the gas discharge panel.

[0002]

2. Description of the Related Art In recent years, expectations for high-definition and large-screen televisions such as high-definition televisions have been increasing.
In the field of displays such as CRTs, liquid crystal displays (LCDs), and plasma display panels (PDPs), the development of displays suitable for them is underway.

Conventionally, CRTs, which have been widely used as television displays, are excellent in resolution and image quality, but have a large screen of 40 inches or more in that the depth and weight increase with the screen size. Is not suitable. In addition, LCDs have excellent performance such as low power consumption and low driving voltage, but have technical difficulties in producing a large screen and have a limited viewing angle.

Further, since the projection type display uses a complicated optical system and requires precise optical axis adjustment, the production cost is increased, and the image quality is greatly deteriorated due to the influence of optical distortion. However, the resolution characteristic of the image is also deteriorated, and is not suitable for high-precision image display. On the other hand, the PDP can realize a large screen even with a small depth, and a 50-inch class product has already been developed.

[0005] PDPs are roughly classified into a direct current type (DC type) and an alternating current type (AC type). At present, the AC type suitable for enlargement is mainly used. In a general AC surface discharge type PDP, a front cover plate and a back plate are arranged in parallel with a partition wall therebetween, and a discharge gas is sealed in a discharge space partitioned by the partition wall. Scan electrodes and sustain electrodes are arranged in parallel on the front cover plate, and the scan electrodes and the sustain electrodes are covered with a dielectric layer made of lead glass. On the back plate, address electrodes and partition walls, and red, green, or blue are provided. And a phosphor layer made of an ultraviolet-excited phosphor.

[0006] In such a PDP, when a discharge is generated by applying a pulse to each electrode by a driving circuit at the time of driving, ultraviolet rays are emitted from the discharge gas along with the discharge, and the phosphor particles of the phosphor layer ( (Red, green, and blue) are excited by the ultraviolet rays to emit light. by the way,
Since each discharge cell can originally express only two gradations of lighting or extinguishing, for each color of red (R), green (G), and blue (B), one field is divided into a plurality of subfields, and the lighting time is divided. (Time-division in-field display method in a field) is used in which intermediate gradations are expressed by a combination thereof.

In each subfield, a setup period in which a pulse voltage is applied to the entire scan electrode for setup, and a pulse voltage is sequentially applied to the scan electrode and a pulse voltage is applied to a selected electrode among the address electrodes. An address period in which wall charges are accumulated in a cell to be turned on, and a discharge sustain period in which a pulse voltage is applied between a scan electrode and a sustain electrode to sustain a discharge. Accordingly, an image is displayed on the PDP only for a predetermined discharge maintaining period.

[0008] In an NTSC system television image, since an image is composed of 60 fields per second, the time of one field is set to 16.7 ms.

[0009]

In the current 40- to 42-inch television PDP for televisions, the NTSC pixel level (640 × 480 pixels, cell pitch 0.43 mm ×
1.29 mm, 0.55 mm ² )
Although a panel efficiency of 1.2 lm / w and a screen luminance of about 400 cd / m ² are obtained (for example, FLAT-P
ANEL DISPLAY1997 Part5-1
P198), further higher luminance is desired.

In a high-definition television that is being put into practical use in recent years, the number of pixels is 1920 × 10
80, which is high definition, but like other display panels, such a high definition display is desired in PDP. However, in a PDP, the higher the definition, the greater the number of scanning electrodes, and therefore the longer the time required for addressing. Here, assuming that the time of one field is constant and the time required for setup is constant, the ratio of the discharge sustaining period in one field must be set small because the address period becomes long.

Therefore, the higher the definition, the smaller the ratio of the sustaining period in one field. Since the panel luminance of the PDP is proportional to the ratio of the time occupied by the discharge sustaining period, the panel luminance decreases as the definition becomes higher. Therefore, in order to realize a high-definition PDP, the necessity of improving the panel luminance is further increased.

In order to solve such a problem, for example, a technique for increasing the luminous efficiency of the cell by improving the luminous efficiency of the phosphor layer and improving the panel luminance, or a double (dual) scan method at the time of addressing is adopted. By performing scanning, the address time is reduced by one even though the number of scanning lines is the same.
There is also known a technology for shortening to about / 2. Although these techniques are effective to some extent for the above-mentioned problems, they cannot be said to be sufficient to meet the demand for high-definition and high-brightness PDPs by themselves, and solutions from other fields can be used together. desired.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a gas discharge panel display device having a fine structure and capable of realizing high luminance and a method of driving the gas discharge panel.

[0014]

In order to achieve the above object, according to the present invention, when a gas discharge panel is driven by an ADS system, a voltage is applied between a scan electrode group and an address electrode group to set up the gas discharge panel. 100V
Above and shortly to the first voltage lower than the discharge starting voltage (10
μsec or less) and a second interval after the first interval that rises to a second voltage equal to or higher than the discharge starting voltage with a slope (9 V / μsec or less) smaller than the slope of the voltage rise in the first interval. After the second section, a short time (10 μs) from the second voltage to the third voltage lower than the discharge starting voltage.
ec), and a fourth section after the third section, further falling (for 100 to 250 μsec) from the third voltage with a slope smaller than the slope of the voltage drop in the third section. And the entire voltage waveform period is 360 μs
ec or less.

If such a voltage waveform is used at the time of setup, wall charges are efficiently accumulated during a period in which the voltage rises and falls slowly (that is, a period in which the slope of the voltage change is 9 V μsed or less). Sometimes it is possible to apply a wall voltage close to the firing voltage. By applying a wall voltage close to the discharge starting voltage in this way, even if the time width of the pulse applied at the time of addressing is set to be short (1.5 μsec or less), the wall charges are reliably accumulated and the addressing is performed. It can be carried out.

In the first and third sections, since the voltage is changed in a short time (10 μsec or less), the entire period in which the setup voltage is applied is 360 μsec.
c or less, so that the setup time ratio (1
Setup time in the field) can be made relatively small.

As a result, the total time of the setup period and the address period is shortened as compared with the related art, and
It is possible to set a longer discharge sustaining period.
Further, while the total time of the setup period and the address period is the same as that of the related art, the number of the scanning electrode branches is made larger than that of the related art, so that the gas discharge panel can have higher definition. In particular, in a gas discharge panel in which the height of the partition wall group is in the range of 80 to 110 μm, it is effective to drive using the above-described voltage waveform at the time of set-up, in order to realize good display.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Overall Description of PDP Configuration, Manufacturing Method and Driving Method] FIG. 1 is a perspective view showing a schematic configuration of an AC surface discharge type PDP according to an embodiment of the present invention. The PDP includes a scan electrode group 12a, a sustain electrode group 12b, a dielectric layer 13, a protective layer 1 on a front glass substrate 11.
Front panel 10 on which rear panel 4 is disposed, and rear glass substrate 2
A rear panel 20 on which an address electrode group 22 and a dielectric layer 23 are disposed on the first electrode group 1 is arranged in parallel with each other at intervals with the electrode groups 12a, 12b and the address electrode group 22 facing each other. Have been. The gap between the front panel 10 and the rear panel 20 is partitioned by a stripe-shaped partition wall 30 to form a discharge space 40, and a discharge gas is sealed in the discharge space 40.

In the discharge space 40, a phosphor layer 31 is provided on the back panel 20 side. The phosphor layers 31 are repeatedly arranged in the order of red, green, and blue. The scan electrode group 12a, the sustain electrode group 12b, and the address electrode group 22 are all stripe-shaped, and the scan electrode branch 12a and the sustain electrode branch 12b are in a direction orthogonal to the partition 30, and the address electrode branch 22 is parallel to the partition 30. It is arranged in.

The scanning electrode group 12a, sustain electrode group 12b, and address electrode group 22 are made of silver, gold, copper, chromium, nickel,
Although it may be made of a metal such as platinum alone, the scanning electrode group 12
a, about sustain electrode group 12b, ITO, SnO ₂ ,
It is preferable to use a combination electrode in which a thin silver electrode is laminated on a wide transparent electrode made of a conductive metal oxide such as ZnO in order to secure a wide discharge area in the cell.

A panel structure is formed in which cells emitting red, green and blue light are formed at the intersections of the electrode branches 12a and 12b and the address electrode branches 22. The dielectric layer 13 is formed of the electrode groups 12a, 12a of the front glass substrate 11.
b is a layer made of a dielectric substance disposed over the entire surface on which b is disposed. Generally, lead-based low-melting glass is used, but bismuth-based low-melting glass or lead-based low-melting glass is used. It may be formed of a laminate of a melting point glass and a bismuth-based low melting point glass.

The protective layer 14 is made of magnesium oxide (Mg).
O) and covers the entire surface of the dielectric layer 13. The partition 30 is formed of the dielectric layer 2 of the back panel 20.
3 projecting from the surface. PDP with such a configuration
Is produced as follows. Fabrication of front panel: Front panel 10 has electrode groups 12a and 12b formed on front glass substrate 11, and a lead-based glass is applied and baked thereon to form dielectric layer 13, and dielectric layer 13 is formed. It is manufactured by forming a protective layer 14 on the surface of the layer 13.

The electrode groups 12a and 12b may be formed by a general method of forming a film of ITO by a sputtering method, etching portions other than necessary portions, then screen-printing a paste for a silver electrode, and then firing. However, a high-definition electrode can be formed relatively easily by a method of scanning while discharging ink containing an electrode material from a nozzle. The composition of the lead-based dielectric layer 13 is, for example, lead oxide [P
bO] 70% by weight, boron oxide [B ₂ O ₃ ] 15% by weight, silicon oxide [SiO ₂ ] 15% by weight, and can be formed by screen printing and firing. More specifically, a composition obtained by mixing with an organic binder [α-terpineol in which 10% of ethylcellulose is dissolved] is applied by a screen printing method, and then applied at 580 ° C.
It can be formed by baking for minutes.

The protective layer 14 is made of an alkaline earth oxide (here, magnesium oxide [MgO]).
It is a film having a dense crystal structure with (0) plane orientation or (110) plane orientation. Such a protective layer can be formed using, for example, an evaporation method. Fabrication of rear panel: Address electrode group 22 is formed on rear glass substrate 21 by screen printing a paste for silver electrodes and then firing, and then screen printing and firing are performed thereon in the same manner as front panel 10. Thus, a dielectric layer 23 made of lead-based glass is formed. Next, partition walls 30 made of glass are fixed at a predetermined pitch. Then, a phosphor layer 31 is formed by applying and firing one of a red phosphor, a green phosphor, and a blue phosphor in each space between the partition walls 30. As the phosphor of each color,
Phosphors generally used in PDPs can be used, and specific examples thereof include the following phosphors.

Red phosphor: (Y _x Gd _1-x ) BO ₃ : Eu ³⁺ Green phosphor: BaAl ₁₂ O 19: Mn Blue phosphor: BaMgAl ₁₄ O ₂₃ : Eu ²⁺ Production of PDP by panel bonding: The front panel and the rear panel thus manufactured are bonded together using sealing glass, and the inside of the discharge space 40 partitioned by the partition wall 30 is evacuated to a high vacuum (about 1 × 10 ⁻⁴ Pa). (For example, neon-xenon or helium-xenon) at a predetermined pressure to produce a PDP.

The pressure of the discharge gas is generally lower than the atmospheric pressure, and is usually 1 × 10 ^{4 to} 7 × 10 ⁴ Pa.
In many cases, the panel brightness is set in the range of about, but by setting the pressure in a range higher than the atmospheric pressure (a pressure of 8 × 10 ⁴ Pa or more), panel luminance and luminous efficiency can be improved. FIG. 2 is a diagram showing an electrode matrix of the PDP. Each of the electrode branches 12a and 12b and each of the address electrode branches 22 are arranged orthogonally to each other. In a space between the front glass substrate 11 and the rear glass substrate 21, a discharge cell is formed where the electrode branches intersect. Is formed. Adjacent discharge cells are separated by partition walls 30 to prevent discharge diffusion to adjacent discharge cells, so that high-resolution display can be performed.

This PDP is driven using an in-field time division gray scale display system. FIG. 3 is a diagram showing a method of dividing one field when expressing 256 gradations, where the horizontal direction indicates time and the shaded portion indicates the discharge sustaining period. For example, in the example of the division method shown in FIG. 3, one field is composed of eight subfields, and the ratio of the sustaining period of each subfield is 1, 2, 4, 8, 1
6, 32, 64, and 128, and 256 gradations can be expressed by a combination of these 8-bit binaries. In addition, in the NTSC system television video, since the video is composed of 60 field images per second, the time of one field is set to 16.7 ms.

Each subfield has a setup period,
It is composed of a series of sequences of an address period and a discharge sustaining period, and an image of one field is displayed by repeating the operation for one subfield eight times.
FIG. 4 is a timing chart when a pulse is applied to each electrode in one subfield in the present embodiment.

The operation in each period will be described later in detail. In the address period, a pulse is sequentially applied to a plurality of scan electrode branches, and a pulse is applied to a selected one of the plurality of address electrode branches. For convenience, FIG. Only one of the address electrode branches is described. [Detailed Description of Driving Device and Driving Method] FIG.
FIG. 2 is a block diagram showing a configuration of the driving device 100.

The driving apparatus 100 includes a preprocessor 101 for processing video data input from an external video output device, a frame memory 102 for storing processed video data, and generating a synchronization pulse for each field and each subfield. And a scan driver 104 for applying a pulse to the scan electrode group 12a, a sustain driver 105 for applying a pulse to the sustain electrode group 12b, and a data driver 106 for applying a pulse to the address electrode group 22. .

The preprocessor 101 extracts video data (field video data) for each field from the input video data, and creates video data of each subfield (subfield video data) from the extracted field video data. The data is stored in the frame memory 102. Also, data is output to the data driver 106 line by line from the current subfield video data stored in the frame memory 102, or a synchronization signal such as a horizontal synchronization signal or a vertical synchronization signal is detected from the input video data, It also sends a synchronization signal to the synchronization pulse generator 103 for each field and each subfield.

The frame memory 102 is capable of dividing and storing each subfield video data for each field. Specifically, the frame memory 102 stores 1
A two-port frame memory having two memory areas for field (stores eight sub-field images), wherein field image data is written to one memory area while being written to the other memory area. The operation of reading the stored field video data can be performed alternately.

The synchronizing pulse generator 103 refers to the synchronizing signal transmitted from the preprocessor 101 for each field and for each subfield, and instructs a timing for causing a setup pulse, a scan pulse, a sustain pulse, and an erase pulse to rise. A signal is generated and sent to each of the drivers 104-106. Scan driver 104
Generates and applies a setup pulse, a scan pulse, and a sustain pulse in response to a trigger signal sent from the synchronization pulse generator 103.

FIG. 6 is a block diagram showing the configuration of the scan driver 104. The setup pulse and the sustain pulse are applied in common to all the scan electrode branches 12a. Therefore, as shown in FIG. 6, the scan driver 104 includes a setup pulse generator 111 and a sustain pulse generator 112a for generating each pulse. These pulse generators are connected in series by a floating ground method, and operate in response to a trigger signal from the synchronization pulse generation unit 103, so that a setup pulse or a sustain pulse is selectively provided.
The voltage is applied to the scanning electrode group 12a.

The scan driver 104 applies a scan pulse to the scan electrode branches 12a1, 12a2,... 12aN in order, as shown in FIG. 6, here, a scan pulse generator 114 and a multiplexer 115 connected thereto.
In accordance with the trigger signal from the synchronizing pulse generator 103, the scanning pulse generator 114 generates a pulse and the multiplexer 115 switches and outputs the pulse. It is also possible to adopt a configuration in which a scanning pulse generation circuit is provided in the first embodiment.

Then, the pulse generators 111 and 112 are used.
The switches SW1 and SW2 are provided to selectively apply the output from the scan pulse generator 114 and the output from the scan pulse generator 114 to the scan electrode group 12a. The sustain driver 105 includes a sustain pulse generator 112b and an erase pulse generator 113. In response to a trigger signal from the synchronization pulse generator 103, the sustain driver 105 generates a sustain pulse and an erase pulse and applies them to the sustain electrode group 12b.

The data driver 106 outputs data pulses in parallel to the address electrode groups 221 to 22M based on subfield information corresponding to one line that is serially input. FIG. 7 shows the data driver 1
It is a block diagram which shows the structure of 06. Data driver 1
Reference numeral 06 denotes a first latch circuit 121 for taking in sub-field image data for one scan line, and a second latch circuit 121 for storing the same.
It comprises a latch circuit 122, a data pulse generator 123 for generating data pulses, and AND gates 1241 to 124M provided at the entrances of the address electrode branches 221 to 22M.

In the first latch circuit 121, the subfield video data sequentially sent from the preprocessor 101 is fetched in order of several bits in synchronization with the CLK signal.
When the subfield image data for one scan line (information indicating whether or not a data pulse is applied to each of the address electrode branches 221 to 22M) is latched, the data is transferred to the second line.
It moves to the latch circuit 122 collectively. The second latch circuit 122 opens one of the AND gates 1241 to 124M corresponding to the address electrode to which the data pulse is applied, in response to the trigger signal sent from the synchronization pulse generator 103. Then, the data pulse generator 123 generates a data pulse in synchronization with this. by this,
A data pulse is applied to the address electrode corresponding to the one whose AND gate is opened.

In such a driving device, a voltage is applied to each electrode in each of the setup period, the address period, and the sustain period as described below. [Explanation of Operation in Each Period] Setup period: In the setup period, the switch SW1 of the scan driver 104 is ON, and the switch SW2 is O.
The setup pulse generator 111 applies a setup pulse to all the scan electrode groups 12a collectively by the setup pulse generator 111, thereby performing a setup discharge in all the discharge cells.

The setup discharge occurs between the three electrodes, that is, between the scan electrode and the address electrode and between the scan electrode and the sustain electrode. The setup discharge initializes the state in each discharge cell, accumulates wall charges in each discharge cell, and applies a wall voltage. This makes it possible to hasten the rise of the address discharge in the next address period.

The waveform of the setup pulse has a waveform characteristic suitable for applying a wall voltage close to the discharge starting voltage in a relatively short time of one pulse of 360 μsec or less. Details of this feature will be described later.
A positive voltage is applied to sustain electrode group 12b from the latter half of the setup period until the end of the address period. This makes it easier to accumulate wall charges on the surface of the dielectric layer during the address period.

Address period: In the address period,
Switch SW2 of scan driver 104 is ON, SW1
Is turned off, and a negative-voltage scanning pulse generated by the scanning pulse generator 114 is sequentially applied to the scanning electrode branches 12a1 in the first row to the scanning electrode branches 12aN in the last row. Then, at the same time, the data driver 10
Numeral 6 performs address discharge by applying a positive voltage data pulse to one of the address electrode branches 221 to 22M corresponding to a discharge cell to be turned on, and accumulates wall charges in the discharge cell. In this way, by accumulating wall charges on the surface of the dielectric layer of the discharge cell to be lighted, a latent image for one screen is written.

It is desirable to set the time width (address pulse width) of the scanning pulse and the data pulse as short as possible in order to increase the driving speed. However, if the address pulse width is too short, a writing failure (address discharge failure) occurs. ) Is more likely to occur. In addition, the pulse width usually needs to be set to about 1.25 μsec or more due to circuit restrictions.

When addressing is performed by the double scan method, each address electrode group 22 shown in FIG. 2 is divided into upper and lower portions so that each address electrode branch 22 can be separately applied to the upper and lower portions by the driving device 100. Keep it. And
Addressing is performed in parallel with each of the upper half and the lower half of the panel in the same manner as described above. Discharge sustaining period: In the sustaining period, the switch SW1 of the scan driver 104 is turned on and the switch SW2 is turned off, and the sustaining pulse generator 112a collectively discharges the scan electrode group 12a with a fixed length (for example, 1 to 5 μsec). The operation of applying a pulse and the operation of applying a discharge pulse of a fixed length to the sustain electrode group 12b collectively by the sustain pulse generator 112b of the sustain driver 105 are alternately repeated.

As a result, in the discharge cells in which the wall charges are accumulated during the address period, a discharge occurs when the potential on the surface of the dielectric layer exceeds the discharge starting voltage, and in the discharge cells, ultraviolet rays are generated along with the sustain discharge. Is emitted, and is converted into visible light by the phosphor layer 31 to emit visible light corresponding to the color of the phosphor layer. At the end of the sustain period, the sustain driver 1 is used to erase the charge remaining in the lit discharge cells.
The erase pulse generator 113 of FIG.
A voltage equivalent to a sustain pulse having a slope of about 9 V / μsec is applied to sustain electrode group 12b for a short time (20 to 50 μsec).
c) is applied.

[Regarding Voltage Waveform Applied During Setup Period] FIG. 8 is a diagram for explaining the waveform of the setup pulse. This pulse waveform is divided into sections A1 to A7. In the present embodiment, a setup pulse having such a waveform is applied to the scan electrode group 12a during the setup period.

While the setup pulse is applied to the scan electrode group 12a, as shown in FIG.
Since 2 is kept at 0 potential, the potential difference between the scan electrode group 12a and the address electrode group 22 also has a waveform as shown in FIG. In addition, since the sustain electrode group 12b is also kept at the potential 0 during the section A1 to A5, in this section, the potential difference between the scan electrode group 12a and the sustain electrode group 12b also has a waveform as shown in FIG. .

The setup pulse waveform is set as follows in consideration of accumulating wall charges corresponding to the wall voltage close to the discharge starting voltage in the dielectric layer in the shortest possible time. Section A1 is a period for adjusting timing. In the section A2, the voltage V1 at a level close to the discharge starting voltage Vf is as short as possible (10 μsec).
Below). Here, the voltage V1 is 100 ≦ V1 <
Set within the range of Vf. Here, Vf is a discharge starting voltage as viewed from the outside (drive device side).

The discharge starting voltage Vf is a unique value determined by the configuration of the PDP, and can be measured, for example, as follows. While visually observing the gas discharge panel, a scanning electrode group 1 of the gas discharge panel was obtained from the panel driving device.
The voltage applied between 2a and sustain electrode group 12b is gradually increased. Then, the applied voltage when one or a predetermined number (for example, three) or more of the discharge cells of the gas discharge panel starts to be lit, and this is recorded as the discharge start voltage.

Next, in the section A3, the voltage is gradually increased to the voltage V2, and is maintained at the voltage V2 in the section A4. Here, the voltage V2 is higher than the discharge start voltage Vf. However, if the voltage V2 is too high, a self-erasing discharge may occur when the voltage falls. Set (about 450-480V).

The gradient of the voltage rise in the section A3 is 9 V
/ Μsec or less, and preferably 1.7 to 7 V / μsec. By slowly increasing the voltage in this manner, a weak discharge occurs in the IV positive characteristic region, and the discharge is almost performed in the low voltage mode, and the inside of the cell is near a value Vf * slightly lower than the discharge voltage Vf. , Negative wall charges are accumulated on the surface of the dielectric layer on the scanning electrode group 12a in accordance with the potential difference (V2−Vf *).

The standard of the time allocated to this section A3 is 100 to 250 μsec, preferably 10 to 250 μsec.
It is about 0 to 150 μsec. It is preferable to set the time of the section A4 corresponding to the top of the waveform as short as possible, but actually, several μsec is required in the circuit of the panel driving device. Next, in the section A5, a voltage V3 not less than 50 V and not more than the discharge start voltage Vf is set as short as possible (10
(μsec or less).

Then, in the section A6, the voltage is slowly decreased. The slope of the voltage drop in this section A6 is 9
V / μsec or less, and preferably 0.6 to 3 V / μsec. By slowly lowering the voltage in this manner, when the potential of the surface of the dielectric layer on the scan electrode group 12a exceeds the true discharge start voltage inside the cell, a weak discharge occurs in the positive characteristic region. However, since the inside of the cell is kept at a value Vf * slightly lower than the discharge starting voltage Vf,
The state where the negative wall charges corresponding to the firing voltage Vf * are accumulated on the surface of the dielectric layer on the scan electrode group 12a is maintained.

The section A7 is a period for adjusting the timing. By setting the voltage waveform of the setup pulse as described above, a wall voltage close to the discharge start voltage can be efficiently applied inside each discharge cell within a relatively short pulse application time of 360 μsec or less. Even if the pulse width applied during the address period is set to a short time of 1.5 μsec or less, wall charges required for addressing can be accumulated without causing a discharge delay.

As a result, even a high-definition image having 1080 scanning lines can be displayed with the same discharge maintaining period as a VGA pixel level PDP having approximately 480 scanning lines. Here, the case where the setup waveform of the present embodiment as shown in FIG. 8 is used and the case where some conventional setup waveforms are used are compared.

First, in the setup waveform of FIG. 8, in section A3 and section A6, a large amount of wall charges is accumulated by gradually increasing and decreasing the voltage so as not to generate a strong discharge. At the same time, in the sections A2 and A5, even if the voltage is rapidly increased / decreased, the accumulation of the wall charges may be performed. Therefore, the required time is suppressed by setting the slope of the voltage to be large. Thereby, the time width of the entire setup pulse is 360 μs.
ec or less and sufficient wall charges are accumulated.

On the other hand, during setup,
When a simple rectangular wave as shown in FIG. 9A is used, or when an exponential / logarithmic function waveform is used as shown in FIG. 9B, an abrupt voltage change occurs in sections A3 and A6. As a result, a strong discharge occurs, so that wall charges cannot be accumulated as in the present embodiment.

When the wall charge is not accumulated very much during the setup as described above, if the time width of the address pulse is set to about 1.5 μsec, the address discharge becomes uncertain due to the discharge delay, and the screen flickers. Become. In this case, it is necessary to set the width of the address pulse to about 2.5 μsec or more in order to reliably perform the address discharge. Therefore, if the number of scanning lines is 1080, the time required for addressing is 2.7 msec.
That is all.

On the other hand, as a setup waveform, FIG.
When a trapezoidal waveform (see US Pat. No. 5,745,086) in which the voltage gradually rises and falls as shown in (c) is used,
Although it is possible to accumulate wall charges and apply a wall voltage close to the firing voltage, the setup itself takes time,
It is impossible to suppress it to about 360 μsec. On the other hand, in the setup waveform of FIG. 8, since a wall voltage close to the discharge start voltage can be applied, stable addressing can be performed even if the pulse width of the address is considerably small and 1.25 μsec or less. Therefore, if the number of scanning lines is 1080, the addressing is 13
Since it can be performed in 50 μsec or less and the entire setup waveform time is 360 μsec or less, the total time of setup and addressing can be suppressed to 1710 μsec or less.

Thus, even if the number of subfields is 8, the total discharge sustaining time in one field is 1
6.7− (1.71 × 8) = 3.0 msec or more remains, and it can be sufficiently applied to the discharge maintaining period.
From the above considerations, it can be seen that by using the setup waveform as in the present embodiment, the total time of the setup and the address can be suppressed to be shorter than before.

In other words, even if the number of scanning electrodes is increased, the total time of the setup and the address is suppressed to the same level as in the conventional case, whereby the ratio of the discharge sustaining time to the conventional state can be secured. become. Therefore, it is effective to realize a PDP with high detail and excellent panel luminance. Further, when the addressing is performed by the double scan method, the ratio of the discharge maintaining time can be further increased as compared with the case of performing the addressing by the single scan method.

For example, when the number of scanning lines is 1080 and the pulse width at the time of address is 1.25 μsec, when the double scanning method is used, 8 subfields can be realized in the 6 × mode. 12 subfields and 15 subfields can be realized in the 1 × mode. Here, the n-times mode is a method in which a sustain pulse is applied n times the number of times in the 1-time mode during the discharge sustain period, and the brightness of the panel increases according to the mode magnification.

[Circuit for Forming Setup Pulse Waveform] In order to apply a waveform having the above-described characteristics to the scan electrode group 12a as a setup pulse, the setup pulse generator 111 shown in FIG. A pulse generation circuit as shown in FIG. FIG.
The pulse generating circuit indicated by 0 is configured by connecting a pulse generating circuit U1 for generating a first pulse rising at a gentle slope and a pulse generating circuit U2 for generating a second pulse falling at a gentle slope in a floating ground system. Have been.

The pulse generation circuit U1 and the pulse generation circuit U
2 generates a first pulse and a second pulse in response to a trigger signal sent from the synchronization pulse generator 103. Here, as shown in FIG.
Then, a trapezoidal first pulse with a gentle rise is generated, and the pulse generation circuit U2 generates a trapezoidal second pulse with a gentle fall so as to overlap with this temporally. The start of the first pulse is set so as to substantially coincide with the rise of the second pulse, and the start of the fall of the second pulse is set so as to substantially coincide with the rise of the first pulse. Then, by adding the voltages of the two pulses to form an output pulse, a pulse waveform having the same characteristics as in FIG. 8 is formed.

FIGS. 12A and 13A are block diagrams showing the configurations of the pulse generation circuit U1 and the pulse generation circuit U2. The pulse generation circuit U1 and the pulse generation circuit U2 have the following configurations. As shown in FIG. 12A, the pulse generation circuit U1 includes a pull-up FET (Q
1) and a pull-down FET (Q2) connected to the push-pull circuit, and a three-phase bridge driver IC1
(For example, IR-211 manufactured by International Recifier
3) is connected, a capacitor C1 is inserted between the gate and the drain of the pull-up FET (Q1), and the Ho of IC1 is connected.
The current limiting element R1 is interposed between the terminal and the gate of the pull-up FET (Q1). A constant voltage Vset1 is applied to this pull-up circuit. The voltage Vset1 is a voltage value corresponding to the voltage V2−the voltage V1 described with reference to FIG.

In the pulse generating circuit U1, a Miller integrating circuit is formed by the pull-up FET (Q1), the capacitor C1, and the current limiting element R1, whereby a waveform having a gentle rising gradient is formed. ing. FIG. 12B shows a pulse generation circuit U1.
FIG. 3 is a diagram showing a state in which a first pulse is formed by the above.

In the above-mentioned pulse generating circuit U1, FIG.
As shown in (b), when the pulse signal VHin1 is input to the Hin terminal of IC1 and the pulse signal VLin1 of the opposite polarity is input to the Lin terminal, the push-pull circuit operates under the control of IC1. Then, a trapezoidal first pulse rising to the voltage Vset1 with a gentle slope is output from the output terminal OUT1.

Here, the rise time of the gentle slope in the first pulse is the re-time length t 1, the capacitance C 1 of the capacitor C 1 and the voltage V 1
set1, potential difference V between terminal Ho and terminal Vs in IC1
H and the resistance value R1 of the current limiting element R1 have the following relationship. t1 = (C1 · Vset1) / [(Vset1−VH) / R1] = C1 · R1 · Vset1 / (Vset1−VH) Therefore, by changing the capacitance C1 of the capacitor C1 or the resistance value R1 of the current limiting element R1, The rise time can adjust the re-time length t1.

On the other hand, as shown in FIG. 13 (a), the pulse generation circuit U2 includes a push-pull circuit including a pull-up FET (Q3) and a pull-down FET (Q4), and a three-phase bridge driver IC2 (for example, , Internationala
l Recifier IR-2113) is connected, a capacitor C2 is inserted between the gate and drain of the pull-down FET (Q4), and the Ho terminal of IC2 and the pull-down FET
The current limiting element R2 is interposed between the gate of (Q4). A constant voltage Vset2 is applied to this push-pull circuit. This voltage V
set2 is a voltage value corresponding to the voltage V1 described in FIG.

In the pulse generation circuit U2, a Miller integrating circuit is formed by the pull-down FET (Q4), the capacitor C2 and the current limiting element R2, whereby a waveform having a gentle falling slope is formed. ing. FIG. 13B shows a pulse generation circuit U2.
FIG. 6 is a diagram showing a state in which a second pulse is formed by the above.

In the above pulse generating circuit U2, FIG.
As shown in (b), when the pulse signal VHin2 is input to the Hin terminal of the IC2 and the pulse signal VLin2 of the opposite polarity is input to the Lin terminal, the push-pull circuit operates under the control of the IC2. Then, a trapezoidal second pulse falling at a gentle slope from the voltage Vset2 is output from the output terminal OUT2.

Here, the falling time length t2 of the gentle slope in the second pulse is determined by the capacitance C2 of the capacitor C2 and the voltage V2.
The following relationship exists between set2, the potential VL of the terminal Lo in IC2, and the resistance value R2 of the current limiting element R2. t2 = (C2 · Vset2) / [(Vset2−VL) / R2] = C2 · R2 · Vset2 / (Vset2−VL) Therefore, by changing the capacitance C2 of the capacitor C2 or the resistance R2 of the current limiting element R2, It is possible to adjust the fall time length t2.

[Consideration on Partition Height, Partition Pitch, etc.] In a high-detail PDP having about 1080 scanning lines on a panel, when driving using the above-described pulse waveform at the time of setup, addressing is stable. In order to drive the PDP satisfactorily, it is desirable to design each component of the panel as follows.

* The height of the partition wall 30 is preferably set within a range of 80 to 110 μm. This is because when the height of the partition 30 is set to a low value of 110 μm or less, stable addressing can be performed even if the addressing pulse width is set to 1.5 μsec or less as described above.
If it is less than μm, the discharge space is too narrow and the addressing becomes unstable.

The height of the partition 30 is 80 to 110 μm.
It has been confirmed that, when it is set within the range of m, stable addressing can be performed even if the width of the address pulse is considerably reduced to about 1.25 μsec. * The pitch of the partition walls 30 is suitably in the range of 100 to 200 μm (particularly, in the range of 140 to 200 μm).

This is because when the pitch exceeds 200 μm,
As the panel size increases and the line resistance of each electrode increases, it becomes difficult to perform highly uniform discharge,
If the pitch is less than 140 μm (especially less than 100 μm),
This is because the discharge space is narrowed and the addressing discharge is likely to be unstable. * The gap between the scan electrode branch 12a and the sustain electrode branch 12b is 50
A range of -90 µm is appropriate.

This is because if this gap is set to less than 50 μm, a short circuit is likely to occur due to the manufacturing technique, and if this gap exceeds 90 μm, it becomes difficult to discharge at high speed. * It is preferable that the bottom of the phosphor layer 31 has a thickness in the range of 15 to 30 μm (particularly, in the range of 15 to 25 μm).

When the bottom thickness is less than 15 μm, the conversion efficiency of ultraviolet light into visible light decreases, while
If the thickness exceeds 5 μm (especially, if it exceeds 30 μm), the discharge space becomes narrow and the amount of generated ultraviolet rays decreases. * The width of the address electrode branch 22 is 40 times the pitch of the partition 30.
It is preferably set in the range of ６０60% (especially in the range of 30-60%).

If the ratio is less than 40% (especially less than 30%), the width is too small to cause stable address discharge, while if it exceeds 60%, crosstalk tends to occur between adjacent cells. It is because it becomes. * The thickness of the dielectric layer 13 is preferably set in the range of 35 to 45 μm. This is because the thickness of the dielectric layer 13 is 35
When the thickness is less than μm, the charge is easily released and it is difficult to perform stable addressing. On the other hand, when the thickness exceeds 45 μm, the driving voltage increases.

* The thickness of the dielectric layer 23 is preferably set in the range of 5 to 15 μm (particularly in the range of 5 to 10 μm). This is also because if the film thickness of the dielectric layer 23 is less than 5 μm, the charge easily escapes and stable addressing becomes difficult, while if it exceeds 10 μm (especially if it exceeds 15 μm), the driving voltage increases.

In this embodiment, as shown in FIG. 4, a pulse waveform having the above-described characteristics is applied to the scan electrode 12a during the setup period, and the address electrode group 22 is applied. No voltage is applied (the potential of the address electrode 22 during the setup period is 0), and no voltage is applied to the sustain electrode group 12b in the sections A1 to A5. If the potential difference waveform between the electrode group 22 and the potential difference waveform between the scan electrode group 12a and the sustain electrode group 12b have the same characteristics as described above,
A similar effect is achieved.

For example, during the setup period, FIG.
As shown in FIG. 4, a trapezoidal voltage pulse having a positive voltage value V1 is applied to the scanning electrode group 12a, and a negative voltage value (V1-V2) is applied to the address electrode group 22 at the same time. A trapezoidal pulse is applied. Here, the voltage values V1 and V2 have the same meaning as described in the embodiment. Also in this case, since the potential difference waveform applied between the scan electrode group 12a and the sustain electrode group 12b has the same characteristics as those described in FIG. 8, the same effects as those of the present embodiment can be obtained. .

In this embodiment, the scanning electrode group 12a
Potential difference waveform in the setup period between the scan electrode group 12a and the sustain electrode group 1
2b during the setup period between
Although both examples have the features described with reference to FIG. 8, the potential difference waveform during the setup period between the scan electrode group 12a and the address electrode group 22 has the feature described with reference to FIG. In this case, a voltage waveform having characteristics similar to this voltage waveform is applied to each discharge cell, so that substantially the same effect can be obtained.

For example, scan electrode group 12a and sustain electrode group 1
2b, a voltage waveform having the characteristics described with reference to FIG. 8 is applied to scan electrode group 12a and address electrode group 2a.
2 and between the sustain electrode group 12 b and the address electrode group 22, it is considered that substantially the same effect can be obtained. The present invention is not limited to the case of driving a PDP of the type described in the above embodiment, but can be widely applied to a gas discharge panel display device driven by a pulse memory method,
When driving the gas discharge panel in a series of a sequence of an address period and a discharge sustaining period, a voltage waveform having the same characteristics as described with reference to FIG. 8 is applied to each discharge cell during the setup period. It is considered that the same effects as those of the present embodiment can be obtained.

[0085]

[Example] (Example)

[0086]

[Table 1]

Material No. in Table 1 1 to 11 (Document No. 2)
) Are the “number of scan lines”, “address method”, “number of subfields”, “number of modes”,
When the “address pulse width” and the “setup pulse width” are set to various values, they indicate the “discharge maintenance period” and the “remaining time” that can be assigned. The “address method” shown in Table 1 indicates whether a single scan or a double scan. In Nos. 1 to 4, the single scan method, material No. For 5 to 11, the double scan method is used.

“Number of scanning lines” indicates the number of address pulses applied in one address period. The total number of scanning lines provided on the panel of the PDP is shown in Material No. 1
No. 480, Reference No. In the case of the material No. 2 driven by the double scan method as shown in Table 1, For 5-11, the “number of scan lines” is half of 1
080/2 = 540 lines.

The value of the “setup period” (μsec) described in Table 1 is one field (16.7 m).
This is the total time of the setup period occupied in sec), and is a value obtained by multiplying the pulse width at setup by the number of subfields. "Address period" in Table 1 (μsec)
Is the total time of the address period occupying in one field, and is the pulse width at the time of address × the number of scanning lines ×
This is a value corresponding to the number of subfields. However, the value of the address period in Table 1 includes a period in which the erase pulse is applied immediately after the application of the sustaining pulse.

The numerical value of “discharge sustaining period” (μsec) in Table 1 is the total time of the discharge sustaining period allocated in one field. The remaining period (μs) described in Table 1
The value of ec) is the time of one field (16.7 mse).
This is obtained by subtracting the setup period, the address period, and the discharge sustaining period from c).

Note that the material No. In 2, the address period is larger than the time of one field time,
The remaining period is a negative value. Therefore, in this document No. Under the condition (2), actual driving cannot be performed. Based on the above-described embodiment, the material No. No. 2 except for No. 2 The PDP was driven under the following conditions to display an image. As a result, the above document No. All of the devices driven under the conditions of 3 to 11 provided good image display.

(Comparative Example) As a comparative example, an example in which a conventional rectangular wave is used as a setup pulse will be described. In this comparative example, the number of scan lines in the PDP is 480, the double scan method is used, and one field (16.7 msec) is used.
The number of subfields in c) is 12, and the total setup period per field is 4.54 msec.

The pulse width at the time of addressing is 2.5 μs.
ec. In this case, the total of the address period per field is 2.5 μsec × 12 (subfield)
× 240 (line) = 7.2 msec. In this case, the discharge maintaining period in one field is the same as that of the above document No. 10
3.825 msec, the same as above, and the remaining period is 1
135 μsec.

Material No. of the above embodiment. Comparing Comparative Example No. 10 with this comparative example, the ratio of the discharge maintaining period in one field is the same. 10 indicates that the number of scanning lines is about twice as high as that of high definition. That is, from this example, it can be seen that even with a high-definition PDP having a large number of scanning lines, by applying the present invention, luminance equivalent to that of a conventional PDP having a small number of scanning lines can be obtained.

Here, the effect of the present invention when applied to a PDP having a large number of scanning lines has been mainly described. However, when the present invention is applied to a PDP having a small panel size and a small number of scanning lines, the present invention is not limited thereto. Since the sustain discharge period can be made longer, the panel luminance can be improved as compared with the conventional PDP, or the panel luminance can be sufficiently ensured even when the driving method is single scan. It can be said that such an effect is achieved.

[0096]

As described above, according to the PDP apparatus and the PDP driving method of the present invention, when driving the gas discharge panel by the ADS memory system, a voltage is applied between the scanning electrode group and the address electrode group. As a voltage waveform at the time of setup, a first voltage of 100 V or more and less than the discharge start voltage
A first section in which the voltage rises to the voltage in a short time (10 μsec or less); A second section in which the voltage rises, a third section in which the voltage drops from the second voltage to a third voltage lower than the discharge start voltage in a short time (10 μsec or less) after the second section, and a third section in which the third section From the third voltage at a slope smaller than the slope of the voltage drop (100 to 250 μsec)
(4) A fourth section that falls and a period in which the entire voltage waveform is set to 360 μsec or less is used to shorten the time width of the pulse applied at the time of addressing (to 1.5 μsec or less). Even if it is set, addressing can be performed reliably, so that it is possible to improve the panel brightness by setting the discharge sustaining period longer than before, or to achieve higher definition with the same panel brightness. Become.

The present invention also relates to a gas discharge panel,
Since it can be applied in combination with a technique such as a phosphor improvement for improving luminance or a technique such as a double scan method, it is extremely useful for realizing a high-detail gas discharge panel.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a schematic configuration of an AC surface discharge type PDP according to an embodiment.

FIG. 2 is a view showing an electrode matrix of the PDP.

FIG. 3 is a diagram illustrating a method of dividing one field when 256 gradations are expressed by an in-field time division gradation display method.

FIG. 4 is a timing chart when a pulse is applied to each electrode in one subfield in the embodiment.

FIG. 5 is a block diagram illustrating a configuration of a driving device that drives the PDP.

FIG. 6 is a block diagram illustrating a configuration of a scan driver in FIG. 5;

FIG. 7 is a block diagram illustrating a configuration of a data driver in FIG. 5;

FIG. 8 is a diagram for explaining a setup pulse waveform according to the embodiment;

FIG. 9 is a comparison diagram of pulse waveforms applied during setup.

FIG. 10 is a block diagram of a pulse synthesis circuit that forms a setup pulse according to the embodiment;

FIG. 11 is a diagram showing a manner in which a first pulse and a second pulse are combined in the pulse combining circuit.

FIG. 12 is a block diagram showing a configuration of a pulse generation circuit U1 and a diagram showing how a first pulse is formed by the circuit.

FIG. 13 is a block diagram showing a configuration of a pulse generation circuit U2 and a diagram showing how a second pulse is formed by the circuit.

FIG. 14 is a diagram showing a modification of the PDP driving method according to the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Front panel 11 Front glass substrate 12a Scan electrode group 12b Sustain electrode group 13 Dielectric layer 14 Protective layer 20 Back panel 21 Back glass substrate 22 Address electrode group 23 Dielectric layer 30 Partition wall 31 Phosphor layer 40 Discharge space 100 Driving device 104 ~ 106 Driver 111 Setup pulse generator 112a, 112b Sustain pulse generator 113 Erase pulse generator 114 Scanning pulse generator

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G09G 3/28 BH (72) Inventor Nobuaki Nagao 1006 Ojidoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. (72) Inventor Taku Sekizawa 1006 Kadoma, Kazuma, Kazuma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. 1006 Oaza Kadoma Matsushita Electric Industrial Co., Ltd.

Claims (18)

[Claims] 1. A gas discharge panel in which a plurality of discharge cells formed by partitioning a phosphor group and arranged in a matrix between a pair of substrates are formed in a matrix, and a voltage is applied to the plurality of discharge cells. A setup unit for setting up, an address unit for writing an image by applying an address pulse to the plurality of discharge cells,
A drive circuit comprising a discharge sustaining unit for sustaining a discharge by applying a sustaining voltage to the plurality of discharge cells, wherein the discharge panel displays an image during a sustain period. The voltage waveform applied to the plurality of discharge cells by the unit is: a first section in which the voltage rises to a first voltage equal to or higher than 100 V and less than a discharge start voltage; and after the first section, a slope of a voltage increase in the first section. A second section in which the second voltage rises to a second voltage equal to or higher than the discharge start voltage at a small slope; a third section in which the second voltage decreases to a third voltage lower than the discharge start voltage after the second section; A gas discharge panel table comprising, after three sections, a fourth section further decreasing from the third voltage with a slope smaller than a slope of a voltage drop in the third section. Apparatus. 2. The first panel substrate and the second panel substrate,
A first electrode group consisting of a plurality of electrode branches and a plurality of electrode branches covered with a dielectric layer are provided on a surface of the first panel substrate which is disposed in parallel with each other with a gap therebetween and faces the second panel substrate. A second electrode group consisting of the first electrode substrate and the second electrode substrate is disposed in a state where the electrode branches are adjacent to each other in parallel, and the surface of the second panel substrate facing the first panel substrate is covered with a dielectric layer to cover the first electrode group. A gas discharge panel in which a third electrode group including a plurality of electrode branches orthogonal to the group is provided, the gap is partitioned by partition groups, and a phosphor is provided between the partition walls; A setup section for applying a voltage between the first electrode group and the third electrode group to set up the voltage; and applying a voltage to the first electrode group while sequentially applying a voltage to the selected electrode branch in the third electrode group. And an address unit for writing an image by applying a voltage between the first electrode group and the second electrode. And a drive circuit comprising a discharge sustaining unit for sustaining a discharge by applying a voltage between the first electrode group and the third electrode group. The voltage waveform that rises to a first voltage that is equal to or higher than 100 V and lower than the discharge start voltage; and a slope smaller than the slope of the voltage rise in the first section after the first section, and A second section that rises to a second voltage; a third section that falls from the second voltage to a third voltage lower than a firing voltage after the second section; and a third section that follows the third section. And a fourth section further falling from the third voltage at a slope smaller than the slope of the voltage drop in the gas discharge panel display device. 3. The gas discharge panel display according to claim 2, wherein a gap between the electrode branch of the first electrode group and the electrode branch of the second electrode group is 50 to 90 μm. 4. The electrode branch of at least one of the first electrode group and the second electrode group is formed by laminating a transparent conductive film and a non-transparent conductive film. Item 3. A gas discharge panel display device according to item 2. 5. The partition group includes a plurality of partitions arranged at equal pitches, each electrode branch of the third electrode group is disposed in a gap between adjacent partitions, and the width of the electrode branches is equal to the rib pitch. 3. The gas discharge panel display device according to claim 2, wherein the ratio is 30% to 60%. 6. The gas discharge panel display device according to claim 2, wherein the dielectric layer covering the electrode branches of the first electrode group and the second electrode group has a thickness of 20 to 45 μm. 7. The gas discharge panel display device according to claim 2, wherein the dielectric covering the electrode branches of the third electrode group has a thickness of 5 to 15 μm. 8. A voltage waveform applied by the set-up unit, wherein a slope of a voltage rise in the second section and a slope of a voltage drop in the fourth section are both 9 V / μsec or less, and the first section And the time of the third section is 10 μsec.
The gas discharge panel display according to any one of claims 1 to 7, wherein the time of the fourth section is set to 100 to 250 µsec, and the total time of the first to fourth sections is set to 360 µsec or less. apparatus. 9. The gas discharge panel display device according to claim 8, wherein a time width per one voltage pulse applied by the address unit is 1.5 μsec or less. 10. The gas discharge panel display device according to claim 8, wherein the height of the partition wall group is 110 μm or less. 11. The gas discharge panel display device according to claim 10, wherein the height of the partition group is 80 μm or more. 12. The gas discharge panel display device according to claim 11, wherein the partition group has a stripe shape and a rib pitch is 200 μm or less. 13. The rib pitch of the partition group is 100 μm.
13. The gas discharge panel display device according to claim 12, wherein: 14. The rib pitch of said partition group is 140 μm.
13. The gas discharge panel display device according to claim 12, wherein: 15. At least a part of the phosphor is provided as a phosphor layer on a surface of a second panel substrate facing the first panel substrate, and the thickness of the phosphor layer is 15 to 30 μm. The gas discharge panel display device according to claim 8, wherein: 16. A gas discharge panel in which a plurality of discharge cells formed by partitioning a phosphor group and arranged in a matrix between a pair of substrates is formed by applying a voltage to the plurality of discharge cells. A setup step of setting up the plurality of discharge cells, an address step of writing an image by applying an address pulse to the plurality of discharge cells, and a discharge maintaining step of maintaining a discharge by applying a sustain voltage to the plurality of discharge cells. A drive method for displaying an image by repeating a series of operations, wherein a voltage waveform applied to the plurality of discharge cells in the set-up step is a first section in which the voltage rises to a first voltage of 100 V or more and less than a discharge start voltage. After the first section, the second voltage equal to or higher than the discharge starting voltage with a slope smaller than the slope of the voltage rise in the first section. A second section that rises from the second voltage to a third voltage that is lower than a discharge start voltage after the second section; and a voltage drop in the third section after the third section. And a fourth section further falling from the third voltage at an inclination smaller than the inclination of the third voltage. 17. The voltage waveform applied in the set-up step, wherein a slope of a voltage rise in the second section and a slope of a voltage drop in the fourth section are both 9 V / μsec or less, and the first section And the time of the third section is 10 μsec.
17. The method of claim 16, wherein the time of the fourth section is set to 100 to 250 μsec, and the total time of the first to fourth sections is set to 360 μsec or less. 18. 18. The gas discharge panel display device according to claim 17, wherein a time width per one voltage pulse applied in the addressing step is 1.5 μsec or less.