JPH11296136A - Driving method of plasma display panel - Google Patents

Driving method of plasma display panel

Info

Publication number
JPH11296136A
JPH11296136A JP10105986A JP10598698A JPH11296136A JP H11296136 A JPH11296136 A JP H11296136A JP 10105986 A JP10105986 A JP 10105986A JP 10598698 A JP10598698 A JP 10598698A JP H11296136 A JPH11296136 A JP H11296136A
Authority
JP
Japan
Prior art keywords
data
voltage
discharge
electrode
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10105986A
Other languages
Japanese (ja)
Inventor
Hidetaka Tono
秀隆 東野
Nobuaki Nagao
宣明 長尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10105986A priority Critical patent/JPH11296136A/en
Publication of JPH11296136A publication Critical patent/JPH11296136A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/293Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296Driving circuits for producing the waveforms applied to the driving electrodes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/04Structural and physical details of display devices
    • G09G2300/0404Matrix technologies
    • G09G2300/0408Integration of the drivers onto the display substrate
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0247Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide the plasma display panel, which has a high picture quality and a low cost by stabilizing the discharge during a writing interval. SOLUTION: Bias voltage pulses are applied to data electrodes 141 to 14M and writing pulses are superimposed to realize a stable writing and a high quality picture display. To realize the above, the data electrode driving circuit is constituted of a data electrode selection driving circuit 31 and a bias voltage pulse applying circuit 32. Thus, the high picture quality plasma display panel is realized at a low cost while the discharging delay during a writing discharge is improved, the malfunction in writing is greatly reduced and the deterioration in contrast is prevented.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、コンピュータおよ
びテレビ等の画像表示に用いるプラズマディスプレイパ
ネルの駆動方法及びその駆動回路に関し、特に、データ
書き込みを容易にし、パネルの高品位化を実現するプラ
ズマディスプレイパネルの駆動方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a circuit for driving a plasma display panel used for displaying images on computers and televisions, and more particularly, to a plasma display which facilitates data writing and realizes high quality panels. The present invention relates to a panel driving method.

【0002】[0002]

【従来の技術】近年、ハイビジョンをはじめとする高品
位で大画面のテレビに対する期待が高まっている中で、
CRT,液晶ディスプレイ(以下、LCDと記載す
る),プラズマディスプレイパネル(Plasma Display P
anel, 以下PDPと記載する)といった各ディスプレイ
の分野において、これに適したディスプレイの開発が進
められている。
2. Description of the Related Art In recent years, expectations for high-definition and large-screen televisions such as high-definition televisions have been increasing.
CRT, liquid crystal display (hereinafter abbreviated as LCD), plasma display panel (Plasma Display P)
In the field of each display such as anel (hereinafter referred to as PDP), a display suitable for this is being developed.

【0003】従来からテレビのディスプレイとして広く
用いられているCRTは、解像度・画質の点で優れてい
るが、画面の大きさに伴って奥行き及び重量が大きくな
る点で40インチ以上の大画面には不向きである。ま
た、LCDは、消費電力が少なく、駆動電圧も低いとい
う優れた性能を有しているが、大画面を作製するのに技
術上の困難性があり、視野角にも限界がある。
Conventionally, CRTs, which have been widely used as television displays, are excellent in resolution and image quality, but have a large screen of 40 inches or more in that the depth and weight increase with the screen size. Is not suitable. In addition, LCDs have excellent performance such as low power consumption and low driving voltage, but have technical difficulties in producing a large screen and have a limited viewing angle.

【0004】これに対して、PDPは、小さい奥行きで
も大画面を実現することが可能であって、既に40イン
チクラスの製品も開発されている。PDPは、大別して
直流型(DC型)と交流型(AC型)とに分けられる
が、現在では大型化に適したAC型が主流となってい
る。また、高精細画面表示にも向いている。
On the other hand, a PDP can realize a large screen even with a small depth, and a 40-inch class product has already been developed. PDPs are roughly classified into a direct current type (DC type) and an alternating current type (AC type). At present, the AC type suitable for upsizing is mainly used. It is also suitable for high-definition screen display.

【0005】従来のPDPは、図7に示すような構成の
ものが一般的である。図7において、前面基板11上に
は帯状の第1の表示電極群19aと、帯状の第2の表示
電極群19bが形成され、表示電極群19a、19bは
鉛ガラスなどからなる誘電体ガラス層17で覆われてお
り、誘電体ガラス層17の表面はMgO蒸着膜などから
なる保護層18で覆われている。
A conventional PDP generally has a configuration as shown in FIG. In FIG. 7, a band-shaped first display electrode group 19a and a band-shaped second display electrode group 19b are formed on a front substrate 11, and the display electrode groups 19a and 19b are made of a dielectric glass layer made of lead glass or the like. The surface of the dielectric glass layer 17 is covered with a protective layer 18 made of a MgO vapor-deposited film or the like.

【0006】背面基板12上には帯状のデータ電極群1
4と表面を覆う鉛ガラスなどからなる絶縁体層13が設
けられ、その上に隔壁15が配設されている。前面基板
11と背面基板12とは、それぞれの電極群が互いに直
交するように組み合わされている。隔壁15は、背面基
板12と接着しており、前面基板11とは接触してい
る。隔壁15によって通常は100から200ミクロン
程度の間隔で前面基板11と背面基板12が互いに平行
に対峙し封止されている。
On the back substrate 12, a band-like data electrode group 1 is provided.
4 and an insulator layer 13 made of lead glass or the like that covers the surface, and a partition 15 is provided thereon. The front substrate 11 and the rear substrate 12 are combined so that respective electrode groups are orthogonal to each other. The partition 15 is adhered to the rear substrate 12 and is in contact with the front substrate 11. Normally, the front substrate 11 and the rear substrate 12 face each other and are sealed by the partition walls 15 at intervals of about 100 to 200 microns.

【0007】前面基板11上の表示電極群19a、19
bと背面基板12上のデータ電極群14のそれぞれの誘
電体表面上に初期化放電による壁電荷を形成させた後、
第1の表示電極群19aとデータ電極群14との間に選
択的に、零と或値の2値のデータ電圧を印加することに
よって、選択された電極の交点でガス放電によって生じ
た電荷を誘電体ガラス絶縁膜17上に蓄積し、第1の表
示電極群19aを走査することにより1画面分の画素の
潜像を蓄積する書き込み動作の後に、前面基板11上の
第1の表示電極群19aと第2の表示電極群19bとの
間に交流パルス電圧を印加する維持放電動作によって、
書き込み動作において選択された放電セルが一斉に発光
することによって画像を表示する。
The display electrode groups 19a, 19 on the front substrate 11
After forming wall charges by the initializing discharge on the respective dielectric surfaces of the data electrode group 14 on the rear substrate 12 and the data electrode group 14b,
By selectively applying a binary data voltage of zero and a certain value between the first display electrode group 19a and the data electrode group 14, the charge generated by the gas discharge at the intersection of the selected electrodes is reduced. After a writing operation of accumulating on the dielectric glass insulating film 17 and accumulating a latent image of a pixel for one screen by scanning the first display electrode group 19a, the first display electrode group on the front substrate 11 is formed. By the sustain discharge operation of applying an AC pulse voltage between the first display electrode group 19a and the second display electrode group 19b,
An image is displayed when the discharge cells selected in the writing operation emit light simultaneously.

【0008】放電は前面基板11、背面基板12、なら
びに隔壁15で隔離された空間で起こるため、発光は拡
散しない。つまり、隔壁15は、前面基板11と背面基
板12との間隔を規定する目的と、解像度の高い表示が
行う目的を有している。
Since the discharge occurs in the space separated by the front substrate 11, the rear substrate 12, and the partition 15, the light emission does not diffuse. That is, the partition 15 has the purpose of defining the distance between the front substrate 11 and the rear substrate 12 and the purpose of performing high-resolution display.

【0009】さらにカラー表示を行う場合は、隔壁で遮
断されている放電空間の周辺部に蛍光体16を塗布して
おく。蛍光体は、放電によって生じた紫外線を可視光に
変換することにより行われるので、三原色である赤
(R)、緑(G)、青(B)の蛍光体を使用し、それぞ
れによる発光強度を適当に調整することにより、カラー
表示が可能になる。
Further, when performing color display, the phosphor 16 is applied to the periphery of the discharge space which is blocked by the partition. Since the phosphor is formed by converting ultraviolet light generated by the discharge into visible light, three primary colors of red (R), green (G), and blue (B) are used, and the emission intensity of each is reduced. By appropriate adjustment, color display becomes possible.

【0010】放電ガスとしては、単色表示の場合は、放
電の際に可視域での発光が見られるネオンを中心とした
混合ガスが、またカラー表示の場合は、放電の際の発光
が紫外域にあるキセノンを中心とした混合ガスが選択さ
れる。ガス圧は、大気圧下でのPDPの使用を想定し、
基板内部が外圧に対して減圧になるように、通常は、2
00Torrから500Torr程度の範囲に設定され
る。図8に従来のPDPの電極マトリックス図を示す。
As the discharge gas, in the case of a single color display, a mixed gas mainly composed of neon, which emits light in the visible region at the time of discharge, and in the case of a color display, the emission of light during the discharge is in an ultraviolet region. A mixed gas centered on xenon is selected. The gas pressure assumes the use of PDP under atmospheric pressure,
Usually, the pressure inside the substrate is reduced to 2
It is set in a range from about 00 Torr to about 500 Torr. FIG. 8 shows an electrode matrix diagram of a conventional PDP.

【0011】図9に、従来の駆動回路のブロック図を示
す。図9に於いて、第1の表示電極駆動回路は線順次走
査を行うスキャン回路と維持放電回路とから構成され、
第2の表示電極駆動回路は維持放電回路から構成され
る。データ電極駆動回路は入力信号のシリアル−パラレ
ル変換回路と出力ドライバー回路とから構成される。ス
キャン回路及びデータ電極駆動回路は、駆動電極数が非
常に多くなる為、通常は高耐圧CMOSIC等が用いら
れる。また、これらのICの数も多くなり、PDPのコ
スト高の要因となっていた。
FIG. 9 shows a block diagram of a conventional drive circuit. In FIG. 9, the first display electrode driving circuit includes a scan circuit for performing line-sequential scanning and a sustain discharge circuit.
The second display electrode drive circuit includes a sustain discharge circuit. The data electrode drive circuit includes a serial-parallel conversion circuit for input signals and an output driver circuit. Since the scan circuit and the data electrode drive circuit have a very large number of drive electrodes, a high voltage CMOS IC or the like is usually used. Also, the number of these ICs has increased, which has been a factor in increasing the cost of PDPs.

【0012】次に、従来のPDPの駆動方法について図
10を用いて説明する。図10において、まず電極群1
9b1〜19bNに初期化パルスを印加し、パネルの放電
セル内の壁電荷を初期化する。次に第1の表示電極群1
9aの一番目の電極19a1に走査パルスを、データ電
極群14の表示を行う放電セルに対応するライン141
〜14Mに書き込みパルスを同時に印加して書き込み放
電を行い誘電体層表面に壁電荷を蓄積する。
Next, a conventional PDP driving method will be described with reference to FIG. In FIG. 10, first, electrode group 1
9b initialization pulse is applied to the 1 through 19b N, initializing a wall charge in the discharge cells of the panel. Next, the first display electrode group 1
A scanning pulse is applied to the first electrode 19a 1 of the electrode 9a and a line 14 1 corresponding to a discharge cell for displaying the data electrode group 14.
A write pulse is simultaneously applied to .about.14 M to perform a write discharge to accumulate wall charges on the surface of the dielectric layer.

【0013】次に,電極群19aの二番目のライン電極
19a2に走査パルスを、データ電極群14の表示を行
う放電セルに対応するライン141〜14Mに零と80V
程度の2値の電圧の書き込みパルスを同時に印加して書
き込み放電を行い、誘電体層表面に壁電荷を蓄積する。
続いて同様に継続する走査で表示を行うセルに対応する
壁電荷を誘電体層表面に順次蓄積することによって1画
面分の潜像を書き込む。
[0013] Next, zero and 80V the second scan pulse to the line electrodes 19a 2 of the electrode group 19a, the line 14 1 to 14 M corresponding to the discharge cells for displaying data electrode groups 14
A write pulse of approximately two values is simultaneously applied to perform a write discharge, thereby accumulating wall charges on the surface of the dielectric layer.
Subsequently, similarly, a latent image for one screen is written by sequentially accumulating wall charges corresponding to cells to be displayed by continuous scanning on the surface of the dielectric layer.

【0014】次に維持放電を行うために、データ電極群
14を接地し、第1の電極群19aと第2の電極群19
bに交互に維持パルスを印加することによって、誘電体
層表面に壁電荷が蓄積されたセルでは、誘電体表面の電
位差が放電開始電圧を上回ることによって放電が発生
し、維持パルスが印加されている期間、書き込みパルス
によって選択された表示セルの主放電が維持される。こ
の際、維持期間中に印加される維持パルスの数に重み付
けを行うことによって階調表現が可能となる。
Next, in order to perform sustain discharge, the data electrode group 14 is grounded, and the first electrode group 19a and the second electrode group 19
In the cell in which wall charges are accumulated on the surface of the dielectric layer by alternately applying the sustain pulse to b, a discharge occurs when the potential difference on the dielectric surface exceeds the discharge starting voltage, and the sustain pulse is applied. During this period, the main discharge of the display cell selected by the write pulse is maintained. At this time, gradation can be expressed by weighting the number of sustain pulses applied during the sustain period.

【0015】その後、幅の狭い消去パルスを印加するこ
とによって弱い放電が発生し、壁電荷が消滅する為、消
去動作が行われる。
Thereafter, a weak discharge is generated by applying an erase pulse having a small width, and the wall charges disappear, so that an erase operation is performed.

【0016】この様に、従来のPDPの駆動方法では、
初期化期間、書き込み期間、維持期間、消去期間という
一連の駆動方法により画像表示を行っている。
As described above, in the conventional PDP driving method,
Image display is performed by a series of driving methods including an initialization period, a writing period, a sustaining period, and an erasing period.

【0017】[0017]

【発明が解決しようとする課題】しかしながら、上記の
従来の駆動方法では、書き込み期間において印加される
書き込みパルス電圧がデータ電極駆動回路の出力ドライ
バーICの耐圧制限を受け、書き込みパルス電圧が十分
に高くとれず、放電開始電圧の高いパネルでは安定した
データ書き込みが行われず、画像のちらつきや不点灯等
といった画質劣化を起こすという課題があった。
However, in the above-mentioned conventional driving method, the write pulse voltage applied during the write period is limited by the withstand voltage of the output driver IC of the data electrode drive circuit, and the write pulse voltage is sufficiently high. There is a problem that stable data writing is not performed on a panel having a high discharge starting voltage, and image quality is deteriorated such as flickering or non-lighting of an image.

【0018】特に、高精細パネルの駆動では、短い書き
込みパルス時間内に放電を終わらせることが必要であ
り、その為には、データ電極駆動電圧はVGA画面表示
の場合に比べて高くなるという課題があった。
In particular, in driving a high-definition panel, it is necessary to end the discharge within a short write pulse time, and for that purpose, the data electrode drive voltage is higher than in the case of VGA screen display. was there.

【0019】また、この課題を解決する方法として、初
期化期間に高い電圧で初期化放電を行い、絶対値の高い
壁電圧を第1の表示電極群とデータ電極群上の誘電体表
面に形成する方法が有るが、高電圧初期化放電による発
光強度が増加して黒レベルが上昇しコントラスト低下を
招くという課題が有った。
As a method for solving this problem, an initializing discharge is performed at a high voltage during the initializing period, and a wall voltage having a high absolute value is formed on the dielectric surface on the first display electrode group and the data electrode group. However, there is a problem that the light emission intensity due to the high-voltage reset discharge increases, the black level increases, and the contrast decreases.

【0020】また、前記課題を解決する他の方法とし
て、出力ドライバーICにより高耐圧のICを使用する
ことが考えられるが、一般的にはこのようなドライバー
ICは大きな駆動回路のコストアップをもたらすという
課題を有していた。
As another method for solving the above-mentioned problem, it is conceivable to use an IC having a high withstand voltage as the output driver IC. However, such a driver IC generally increases the cost of a large driving circuit. There was a problem that.

【0021】本発明は上記従来の課題を解決し、書き込
み期間における放電を安定化させることによって、高画
質で低コストなPDPを提供することを目的とする。
An object of the present invention is to solve the above-mentioned conventional problems and to provide a high-quality and low-cost PDP by stabilizing discharge during a writing period.

【0022】[0022]

【課題を解決するための手段】上記目的を達成するため
に本発明は、平行な1対の基板間に誘電体に覆われた複
数の対向する第1及び第2の表示電極と、前記第1の表
示電極と直交するように配置されたデータ電極とを設
け、前記2枚の基板間に少なくとも1枚の前記基板上に
接して設けられた隔壁とにより放電空間が形成されて放
電ガスにより充填され、第1の表示電極とデータ電極間
で選択される放電セルに書き込みパルス電圧を印加して
データを書き込み潜像を形成させるプラズマディスプレ
イパネルの駆動方法に於いて、データ書き込み期間中に
データ電極に一定のバイアス電圧パルスを印加し、これ
にデータパルスを重畳して潜像を形成させる方法を用い
る。
In order to achieve the above object, the present invention comprises a plurality of opposed first and second display electrodes covered by a dielectric between a pair of parallel substrates; A data electrode disposed so as to be orthogonal to one display electrode, and a discharge space is formed by at least one partition provided between and in contact with at least one of the two substrates. In a method of driving a plasma display panel in which a writing pulse voltage is applied to a discharge cell that is filled and selected between a first display electrode and a data electrode to write data and form a latent image, data is written during a data writing period. A method is used in which a constant bias voltage pulse is applied to the electrodes, and a data pulse is superimposed on the pulse to form a latent image.

【0023】尚、表示、非表示の選択を行うべきデータ
パルスの電圧差が、プラズマディスプレイパネルのデー
タ電極電圧の完全選択放電電圧と完全非選択放電電圧と
の電圧差以上であることが望ましい。
It is desirable that the voltage difference between the data pulses for selecting display or non-display be equal to or larger than the voltage difference between the completely selected discharge voltage of the data electrode voltage of the plasma display panel and the completely unselected discharge voltage.

【0024】また、上記目的を達成するために本発明
は、平行な1対の基板間に誘電体に覆われた複数の対向
する第1及び第2の表示電極と、前記第1の表示電極と
直交するように配置されたデータ電極とを設け、前記2
枚の基板間に少なくとも1枚の前記基板上に接して設け
られた隔壁とにより放電空間が形成され、前記放電空間
が放電ガスにより充填され、第1の表示電極とデータ電
極間で選択される放電セルに書き込みパルス電圧を印加
してデータを書き込み潜像を形成させるプラズマディス
プレイパネルの駆動回路に於いて、第1の表示電極駆動
回路と、第2の表示電極駆動回路と、データ電極駆動回
路とを具備し、データ電極駆動回路が、2値のデータ電
圧を出力するデータ選択駆動回路と、データ書き込み期
間中に一定のバイアス電圧パルスを印加するバイアス電
圧パルス印加回路とからなる構成を用いる。
According to another aspect of the present invention, there is provided a display device comprising: a plurality of opposed first and second display electrodes covered by a dielectric between a pair of parallel substrates; And a data electrode disposed so as to be orthogonal to
A discharge space is formed between at least one substrate and at least one partition provided in contact with the substrate, and the discharge space is filled with a discharge gas and is selected between the first display electrode and the data electrode. A first display electrode drive circuit, a second display electrode drive circuit, and a data electrode drive circuit, in a plasma display panel drive circuit for applying a write pulse voltage to a discharge cell and writing data to form a latent image. The data electrode driving circuit has a configuration including a data selection driving circuit for outputting a binary data voltage and a bias voltage pulse applying circuit for applying a constant bias voltage pulse during a data writing period.

【0025】更には、望ましい実施態様としては、デー
タ選択駆動回路の接地線を、バイアス電圧パルス印加回
路の出力端子に接続し、データ選択駆動回路の信号入力
線を電気的に絶縁し、かつ、その信号入力線に入力パル
ス信号を伝達する絶縁信号伝達部とを具備する構成があ
る。
Further, as a preferred embodiment, a ground line of the data selection drive circuit is connected to an output terminal of the bias voltage pulse application circuit, a signal input line of the data selection drive circuit is electrically insulated, and There is a configuration including an insulating signal transmitting unit that transmits an input pulse signal to the signal input line.

【0026】ここで、絶縁信号伝達の望ましい実施態様
としては、電気的に絶縁された対向して配置された発光
素子及び受光素子との組み合わせからなるフォトカプラ
により構成されることである。また、他の望ましい実施
態様としては、絶縁信号伝達部が、電気的に絶縁された
パルストランスにより構成されることである。もしく
は、絶縁信号伝達部がコンデンサにより構成されるもの
であっても好ましい。
In a preferred embodiment of the present invention, the insulated signal is transmitted by a photocoupler composed of a combination of a light emitting element and a light receiving element which are electrically insulated from each other. In another preferred embodiment, the insulation signal transmission unit is constituted by an electrically insulated pulse transformer. Alternatively, it is preferable that the insulation signal transmission unit is constituted by a capacitor.

【0027】[0027]

【発明の実施の形態】本発明で用いたPDPパネルの構
造は、従来のものと基本的な構造は同様である。以下、
本発明の実施の形態について図1から図3を用いて説明
する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a PDP panel used in the present invention is basically the same as that of a conventional PDP panel. Less than,
An embodiment of the present invention will be described with reference to FIGS.

【0028】(実施の形態1)図1は、本発明の実施の
形態1の駆動方法を示すタイムチャートである。図10
の従来の駆動方法との相違は、書き込み期間に印加する
書き込みパルスが、従来の駆動方法では、零又は一定の
電圧の2値パルス電圧であったのに対して、本発明の書
き込みパルスは、一定のバイアス電圧パルスを書き込み
データパルスに重畳したものを用い、これをデータ電極
に印加して、第1の表示電極とで選択される放電セルに
選択的に放電させて潜像を形成させる。従って、書き込
みパルスは3値をとることになる。
(Embodiment 1) FIG. 1 is a time chart showing a driving method according to Embodiment 1 of the present invention. FIG.
The difference from the conventional driving method is that the writing pulse applied during the writing period is a binary pulse voltage of zero or a constant voltage in the conventional driving method, whereas the writing pulse of the present invention is A constant bias voltage pulse superimposed on the write data pulse is used and applied to the data electrode to selectively discharge a discharge cell selected by the first display electrode and form a latent image. Therefore, the write pulse takes three values.

【0029】また、データ電極電位は、表示、非表示の
データに応じた書き込みデータパルス電圧に従って上下
に変化するが、これらの値は、初期化期間中のデータ電
極電位よりも、書き込みパルスに重畳されたバイアスパ
ルス電圧分だけ(符号を含めて)電位を高くしてある。
これにより、初期化期間に蓄積された第1の表示電極及
びデータ電極の壁電圧が、従来の駆動方法と同じ値のま
まで書き込み期間に利用することが可能となるので、書
き込み電圧の低電圧化には有効である。
The data electrode potential changes up and down in accordance with a write data pulse voltage corresponding to display and non-display data, and these values are superimposed on the write pulse more than the data electrode potential during the initialization period. The potential (including the sign) is increased by the amount of the applied bias pulse voltage.
Thus, the wall voltage of the first display electrode and the data electrode accumulated during the initialization period can be used in the writing period while maintaining the same value as in the conventional driving method. It is effective for conversion.

【0030】もし、全駆動期間内に一定の振幅のバイア
ス電圧を印加する場合には、初期化期間においてデータ
電極と第1の表示電極間に蓄積される壁電圧は、バイア
ス電圧分だけ低くなるので有効な方法ではない。この点
が本発明の要点である。
If a bias voltage having a constant amplitude is applied during the entire driving period, the wall voltage accumulated between the data electrode and the first display electrode during the initialization period becomes lower by the amount of the bias voltage. So it is not a valid method. This is the gist of the present invention.

【0031】加えて、書き込みパルス電位をバイアスパ
ルス電圧分だけ嵩上げすることが可能となるので、同じ
データパルス電圧でも、バイアスパルス電圧分だけ高い
データ電極電位を印加することが可能となり、さらに、
表示選択データに対しては確実にセルの選択放電が可能
となり、初期化期間のコントラストを劣化させることな
く、画質向上が可能となる。
In addition, since the write pulse potential can be raised by the bias pulse voltage, a data electrode potential higher by the bias pulse voltage can be applied even with the same data pulse voltage.
For the display selection data, the selective discharge of the cell can be reliably performed, and the image quality can be improved without deteriorating the contrast during the initialization period.

【0032】また、非表示選択データに対しては、同様
にバイアスパルス電圧分だけデータ電極電位が高くなる
が、非放電電圧以下であれば、データ電極と第1の表示
電極間に放電は起こらず、蓄積された壁電圧はそのまま
維持されるが、その後の維持放電に於いて第1の表示電
極に印加される電圧とは逆極性の壁電圧となるので、維
持放電は起こらず、非表示状態が実現される。
Similarly, for the non-display selection data, the data electrode potential increases by the amount of the bias pulse voltage. However, the accumulated wall voltage is maintained as it is, but in the subsequent sustain discharge, the wall voltage has a polarity opposite to that of the voltage applied to the first display electrode. The state is realized.

【0033】本発明者等は、プラズマディスプレイパネ
ルのデータ書き込み状態を壁電圧を詳細に測定、検討す
ることにより本発明に想到したものである。以下にそれ
を図を用いて詳細に説明する。
The present inventors have arrived at the present invention by measuring and examining the wall voltage in detail in the data writing state of the plasma display panel. This will be described below in detail with reference to the drawings.

【0034】図2には、データ書き込み電圧をパラメー
タとしたときの第1表示電極に形成される壁電圧の一例
を示す。セル構造は140μmトリオピッチで、420
μmセルピッチ、リブ高さは100μmである。第1表
示電極に印加する初期化電圧は約400V、第2表示電
極に印加する走査電圧は70V、走査パルス及び書き込
みパルス幅は1.5μsとした。
FIG. 2 shows an example of the wall voltage formed on the first display electrode when the data write voltage is used as a parameter. Cell structure is 140μm trio pitch, 420μm
The cell pitch and the rib height are 100 μm. The initialization voltage applied to the first display electrode was about 400 V, the scanning voltage applied to the second display electrode was 70 V, and the width of the scanning pulse and the writing pulse was 1.5 μs.

【0035】この様に有る閾値電圧Vdmax(この場合、
Vdmax=約100V)以上では表示選択放電が生起し、
第1及び第2表示電極間の主放電を、第1電極走査パル
ス期間内に完全に完結させることが判った。この閾電圧
値以上で壁電圧が緩やかに上昇しているのは、データ電
圧上昇に伴うデータ電極第1表示電極間放電による壁電
圧増加分であると考えられる。また、Vdmin(この場
合、Vdmin=約40V)電圧以下のデータ電圧では壁電
圧変化は起らず放電が起こらないことを示している。
The threshold voltage Vdmax (in this case,
(Vdmax = approximately 100 V), display selection discharge occurs,
It has been found that the main discharge between the first and second display electrodes is completely completed within the first electrode scanning pulse period. It is considered that the reason why the wall voltage gradually rises above the threshold voltage value is an increase in the wall voltage due to the discharge between the data electrode and the first display electrode accompanying the increase in the data voltage. Further, at a data voltage equal to or lower than the voltage Vdmin (Vdmin = about 40 V in this case), no wall voltage change occurs and no discharge occurs.

【0036】両者の間の電圧では、パルス電圧印加時に
放電遅れが発生しパルス印加時間内に放電が終了しない
為に、形成されかけた壁電荷がパルス印加後のアフター
グロー放電により一部分消去される為に起こる現象であ
ると考えられる。データ電極印加電圧が高い程、放電遅
れ時間が短くなりデータ書き込みがやり易く、完全にな
る。勿論、この曲線は、初期化パルス電圧や第2表示電
極に印加される電圧に依存することはいうまでもない。
With a voltage between the two, a discharge delay occurs when a pulse voltage is applied, and the discharge does not end within the pulse application time. Therefore, the formed wall charges are partially erased by the after-glow discharge after the pulse application. It is considered to be a phenomenon that occurs for a reason. The higher the voltage applied to the data electrode, the shorter the discharge delay time and the easier the data writing is, and the more complete the data writing becomes. Needless to say, this curve depends on the initialization pulse voltage and the voltage applied to the second display electrode.

【0037】この様に、図1に於けるデータ電極電位に
於いて、表示選択時と非表示選択時の値を、それぞれV
dmax以上、Vdmin電圧以下とすることにより完全選択放
電及び完全非選択放電が可能となる。即ち、書き込みデ
ータパルス電圧は(Vdmax−Vdmin)以上の値を設定す
ることが好ましい。また、バイアスパルス電圧にはVdm
in以下の値を設定することが好ましい。図2の例では、
バイアスパルス電圧を約40V程度の電圧とすればよ
い。
As described above, in the data electrode potential shown in FIG.
By setting the voltage between dmax and Vdmin, the complete selective discharge and the complete non-selective discharge are possible. That is, it is preferable that the write data pulse voltage be set to a value equal to or more than (Vdmax-Vdmin). The bias pulse voltage is Vdm
It is preferable to set a value of in or less. In the example of FIG.
The bias pulse voltage may be set to a voltage of about 40V.

【0038】この様な構成とすることにより、従来では
Vdmaxの(100V以上の)電圧出力を駆動できるデー
タ電極駆動回路のドライバーICが必要となり、高いV
dmax値を呈するPDPを駆動する場合には、ドライバー
ICが高価なものとなり、コストアップにつながってい
た。本発明では、比較的低電圧な(Vdmax−Vdmin)以
上の値(この例の場合、約60V以上)を駆動できるド
ライバーICが利用でき、低コスト化が可能となる。
With such a configuration, a driver IC of a data electrode driving circuit capable of driving a voltage output of Vdmax (100 V or more) is conventionally required, and a high V
When driving a PDP exhibiting a dmax value, the driver IC becomes expensive, leading to an increase in cost. In the present invention, a driver IC that can drive a relatively low voltage (Vdmax-Vdmin) or more (about 60 V or more in this example) can be used, and cost can be reduced.

【0039】尚、図1、図2に於いて、説明の簡単の
為、接地電位を基準とした電圧波形を示したが、何もこ
れに拘束されることはなく、各電極が誘電体で覆われ絶
縁されているので、基準電位が零以外でも良く、極性も
図示とは異なっていても良いのはいうまでもない。各電
極電位の相対電位差のシーケンスが同様で有ればこれに
限るもので無いのはいうまでもない。
In FIGS. 1 and 2, voltage waveforms based on the ground potential are shown for the sake of simplicity, but the present invention is not limited to this and each electrode is made of a dielectric material. Since it is covered and insulated, it goes without saying that the reference potential may be other than zero and the polarity may be different from that shown. It is needless to say that the present invention is not limited to this as long as the sequence of the relative potential difference between the electrode potentials is the same.

【0040】(実施の形態2)図3は、本発明の実施の
形態2のプラズマディスプレイパネルの駆動回路のブロ
ック図である。従来の駆動回路との違いは、データ電極
駆動回路が2値のデータ電圧を出力するように構成され
ているのに対して、本実施の形態では、データ電極駆動
回路が、2値のデータ電圧を出力するデータ電極選択駆
動回路31と、データ書き込み期間中に一定のバイアス
電圧パルスを印加するバイアス電圧パルス印加回路32
とから構成される点である。データ電極駆動電圧は、デ
ータ電極選択駆動回路31の出力とバイアス電圧パルス
印加回路32の出力との和である。
(Embodiment 2) FIG. 3 is a block diagram of a driving circuit of a plasma display panel according to Embodiment 2 of the present invention. The difference from the conventional drive circuit is that the data electrode drive circuit is configured to output a binary data voltage, whereas in the present embodiment, the data electrode drive circuit is configured to output a binary data voltage. And a bias voltage pulse applying circuit 32 for applying a constant bias voltage pulse during a data writing period.
This is a point composed of The data electrode drive voltage is the sum of the output of the data electrode selection drive circuit 31 and the output of the bias voltage pulse application circuit 32.

【0041】このような構成とする為の具体的な構成
は、図3に示すように、データ電極選択駆動回路31と
その駆動電源33の接地電極をバイアス電圧パルス印加
回路32の出力端子に接続して全体を浮かせる構成とす
るのが好ましい。この構成にすれば、バイアス電圧パル
ス印加回路32の数が少なくてすむという利点がある。
併せて、データ電極選択駆動回路31に入力すべき信号
は、電気的に絶縁し、かつ、絶縁信号伝達部34を介し
て伝達される。
As shown in FIG. 3, a specific configuration for achieving such a configuration is to connect the ground electrode of the data electrode selection drive circuit 31 and its drive power supply 33 to the output terminal of the bias voltage pulse application circuit 32. It is preferable that the entire structure is floated. With this configuration, there is an advantage that the number of bias voltage pulse application circuits 32 can be reduced.
At the same time, the signal to be input to the data electrode selection drive circuit 31 is electrically insulated and transmitted through the insulation signal transmission unit 34.

【0042】この様な構成のプラズマディスプレイパネ
ルの駆動回路に於いて、表示、非表示の選択を行うべき
データパルスの電圧差が、プラズマディスプレイパネル
のデータ電極電圧の完全選択放電電圧と完全非選択放電
電圧との電圧差以上とすることが好ましい。
In the driving circuit of the plasma display panel having such a configuration, the voltage difference between the data pulses for selecting the display and the non-display depends on the completely selected discharge voltage of the data electrode voltage of the plasma display panel and the completely unselected voltage. It is preferable that the difference be equal to or more than the voltage difference from the discharge voltage.

【0043】ここで、絶縁信号伝達部34の具体的な実
施態様の一例としては、図4に示すように、電気的に絶
縁されて対向して配置された発光素子及び受光素子との
組み合わせからなるフォトカプラにより構成することが
ある。
Here, as an example of a specific embodiment of the insulating signal transmitting section 34, as shown in FIG. 4, a combination of a light emitting element and a light receiving element which are electrically insulated and opposed to each other is used. It may be constituted by a photocoupler.

【0044】また、絶縁信号伝達部の他の具体的な実施
態様の例としては、図5に示すように、電気的に絶縁さ
れたパルストランスにより構成することである。
Another specific embodiment of the insulated signal transmitting section is, as shown in FIG. 5, constituted by an electrically insulated pulse transformer.

【0045】更には、絶縁信号伝達部の他の具体的な実
施態様の例としては、図6に示すように、コンデンサに
より構成する事も好ましい。
Further, as another specific example of the embodiment of the insulating signal transmitting section, as shown in FIG. 6, it is preferable that the insulating signal transmitting section is constituted by a capacitor.

【0046】この様な構成とすることにより、(実施の
形態1)に開示するような駆動方法が可能となり、コン
トラストの劣化を押さえながら高速書き込みが可能とな
り、チラツキのない完全に書き込みの行われた高画質の
画面表示が可能となる。
By adopting such a configuration, the driving method disclosed in (Embodiment 1) becomes possible, and high-speed writing can be performed while suppressing deterioration of contrast, and complete writing without flicker can be performed. This enables a high-quality screen display.

【0047】また、データ選択駆動回路の出力電圧範囲
が、書き込みの為にデータ電極が必要とする最高電圧よ
りもバイアス電圧パルス分だけ低い値のドライバーIC
でよいので、駆動回路の低コスト化が可能である。特
に、放電開始電圧の高くなる高精細プラズマディスプレ
イパネルの駆動には有効である。
A driver IC in which the output voltage range of the data selection drive circuit is lower than the maximum voltage required by the data electrode for writing by a bias voltage pulse.
Therefore, the cost of the drive circuit can be reduced. In particular, it is effective for driving a high-definition plasma display panel having a high discharge starting voltage.

【0048】[0048]

【発明の効果】以上のように本発明によれば、書き込み
放電時の放電遅れを改善し、書き込み不良を著しく改善
し、かつ、コントラスト劣化を抑制し、高画質なPDP
を、低コストで実現するという顕著な効果が得られる。
As described above, according to the present invention, a discharge delay at the time of writing discharge is improved, a writing defect is remarkably improved, and a contrast deterioration is suppressed.
Can be realized at low cost.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態1のプラズマディスプレイ
パネルの駆動方法を示すタイミングチャート
FIG. 1 is a timing chart showing a driving method of a plasma display panel according to a first embodiment of the present invention.

【図2】本発明の実施の形態1に於けるVdataに対する
第1表示電極の壁電圧Vwの依存性を示す図
FIG. 2 is a diagram showing the dependence of a wall voltage Vw of a first display electrode on Vdata in the first embodiment of the present invention.

【図3】本発明の実施の形態2のプラズマディスプレイ
パネルの駆動回路のブロック図
FIG. 3 is a block diagram of a driving circuit of the plasma display panel according to the second embodiment of the present invention;

【図4】本発明の実施の形態2における絶縁信号伝達部
をフォトカプラにより構成した具体的な実施態様の例を
示す図
FIG. 4 is a diagram illustrating an example of a specific embodiment in which an insulating signal transmission unit according to a second embodiment of the present invention is configured by a photocoupler;

【図5】本発明の実施の形態2における絶縁信号伝達部
をパルストランスにより構成した具体的な実施態様の例
を示す図
FIG. 5 is a diagram showing an example of a specific embodiment in which an insulating signal transmission unit according to the second embodiment of the present invention is configured by a pulse transformer;

【図6】本発明の実施の形態2における絶縁信号伝達部
をコンデンサにより構成した具体的な実施態様の例を示
す図
FIG. 6 is a diagram showing an example of a specific embodiment in which an insulating signal transmission unit according to a second embodiment of the present invention is configured by a capacitor.

【図7】従来のプラズマディスプレイパネルの構成図FIG. 7 is a configuration diagram of a conventional plasma display panel.

【図8】従来のプラズマディスプレイパネルの電極マト
リックス図
FIG. 8 is an electrode matrix diagram of a conventional plasma display panel.

【図9】従来のプラズマディスプレイパネルの駆動回路
のブロック図
FIG. 9 is a block diagram of a driving circuit of a conventional plasma display panel.

【図10】従来のプラズマディスプレイパネルの駆動方
法のタイミングチャート
FIG. 10 is a timing chart of a conventional plasma display panel driving method.

【符号の説明】[Explanation of symbols]

11 前面基板 12 背面基板 13 絶縁体層 14 データ電極群 15 隔壁 16 蛍光体 17 誘電体ガラス層 18 保護膜 19a 電極群 19b 電極群 31 データ電極選択駆動回路 32 バイアス電圧パルス印加回路 33 駆動電源 34 絶縁信号伝達部 DESCRIPTION OF SYMBOLS 11 Front substrate 12 Back substrate 13 Insulator layer 14 Data electrode group 15 Partition wall 16 Phosphor 17 Dielectric glass layer 18 Protective film 19a Electrode group 19b Electrode group 31 Data electrode selection drive circuit 32 Bias voltage pulse application circuit 33 Drive power supply 34 Insulation Signal transmission section

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】平行な1対の基板間に誘電体に覆われた複
数の対向する第1及び第2の表示電極と、前記第1の表
示電極と直交するように配置されたデータ電極とを設
け、前記2枚の基板間に少なくとも1枚の前記基板上に
接して設けられた隔壁とにより放電空間が形成され、前
記放電空間が放電ガスにより充填され、前記第1の表示
電極とデータ電極間で選択される放電セルに書き込みパ
ルス電圧を印加してデータを書き込み潜像を形成させる
プラズマディスプレイパネルの駆動方法であって、前記
データ書き込み期間中にデータ電極に一定のバイアス電
圧パルスを印加し、これにデータパルスを重畳して潜像
を形成させることを特徴とするプラズマディスプレイパ
ネルの駆動方法。
A plurality of opposing first and second display electrodes covered with a dielectric material between a pair of parallel substrates; and a data electrode disposed orthogonal to the first display electrodes. A discharge space is formed between the two substrates by a partition wall provided in contact with at least one of the substrates, the discharge space is filled with a discharge gas, and the first display electrode and the data are formed. A method for driving a plasma display panel in which a write pulse voltage is applied to discharge cells selected between electrodes to write data and form a latent image, wherein a constant bias voltage pulse is applied to a data electrode during the data write period. And driving a plasma display panel by superimposing a data pulse thereon to form a latent image.
【請求項2】表示、非表示の選択を行うべきデータパル
スの電圧差が、プラズマディスプレイパネルのデータ電
極電圧の完全選択放電電圧と完全非選択放電電圧との電
圧差以上であることを特徴とする請求項1記載のプラズ
マディスプレイパネルの駆動方法。
2. The method according to claim 1, wherein a voltage difference between data pulses for selecting display or non-display is equal to or greater than a voltage difference between a completely selected discharge voltage and a completely unselected discharge voltage of data electrode voltages of the plasma display panel. The method for driving a plasma display panel according to claim 1.
【請求項3】平行な1対の基板間に誘電体に覆われた複
数の対向する第1及び第2の表示電極と、前記第1の表
示電極と直交するように配置されたデータ電極とを設
け、前記2枚の基板間に少なくとも1枚の前記基板上に
接して設けられた隔壁とにより放電空間が形成され、前
記放電空間が放電ガスにより充填され、前記第1の表示
電極とデータ電極間で選択される放電セルに書き込みパ
ルス電圧を印加してデータを書き込み潜像を形成させる
プラズマディスプレイパネルの駆動回路であって、前記
第1の表示電極を駆動する駆動回路と、前記第2の表示
電極を駆動する駆動回路と、データ電極駆動回路とを具
備し、前記データ電極駆動回路が、2値のデータ電圧を
出力するデータ選択駆動回路と、データ書き込み期間中
に一定のバイアス電圧パルスを印加するバイアス電圧パ
ルス印加回路とからなることを特徴とするプラズマディ
スプレイパネルの駆動回路。
3. A plurality of opposing first and second display electrodes covered with a dielectric between a pair of parallel substrates, and a data electrode disposed so as to be orthogonal to the first display electrode. A discharge space is formed between the two substrates by a partition wall provided in contact with at least one of the substrates, the discharge space is filled with a discharge gas, and the first display electrode and the data are formed. A driving circuit for driving a first display electrode, wherein the driving circuit drives a first display electrode, the driving circuit applying a write pulse voltage to a discharge cell selected between the electrodes to write data and form a latent image; And a data electrode drive circuit, the data electrode drive circuit outputting a binary data voltage, and a constant bias voltage during a data write period. Driving circuit of a plasma display panel, comprising the bias voltage pulse applying circuit for applying a pulse.
【請求項4】データ選択駆動回路の接地線を、バイアス
電圧パルス印加回路の出力端子に接続し、前記データ選
択駆動回路の信号入力線を電気的に絶縁し、かつ、前記
信号入力線に入力パルス信号を伝達する絶縁信号伝達部
とを具備したことを特徴とする請求項3記載のプラズマ
ディスプレイパネルの駆動回路。
4. A ground line of a data selection drive circuit is connected to an output terminal of a bias voltage pulse application circuit, a signal input line of the data selection drive circuit is electrically insulated, and an input to the signal input line is provided. 4. The driving circuit for a plasma display panel according to claim 3, further comprising an insulating signal transmitting unit that transmits a pulse signal.
【請求項5】絶縁信号伝達部が、電気的に絶縁された対
向する発光素子及び受光素子との組み合わせからなるフ
ォトカプラにより構成されることを特徴とする請求項3
または4記載のプラズマディスプレイパネルの駆動回
路。
5. The apparatus according to claim 3, wherein the insulated signal transmitting section is constituted by a photocoupler comprising a combination of a light emitting element and a light receiving element which are electrically insulated from each other.
Or the driving circuit of the plasma display panel according to 4.
【請求項6】絶縁信号伝達部が、電気的に絶縁されたパ
ルストランスにより構成されることを特徴とする請求項
3または4記載のプラズマディスプレイパネルの駆動回
路。
6. The driving circuit for a plasma display panel according to claim 3, wherein the insulation signal transmission unit is constituted by an electrically insulated pulse transformer.
【請求項7】絶縁信号伝達部が、コンデンサにより構成
されることを特徴とする請求項3または4記載のプラズ
マディスプレイパネルの駆動回路。
7. The driving circuit for a plasma display panel according to claim 3, wherein the insulation signal transmission section is constituted by a capacitor.
【請求項8】1対の基板間に誘電体に覆われた複数の対
向する第1及び第2の表示電極と、前記第1の表示電極
と交差するように配置されたデータ電極とを設け、前記
2枚の基板間の隔壁により放電セル群が形成され、前記
放電セル群が放電ガスにより充填され、前記第1の表示
電極と前記データ電極間で選択される放電セルに書き込
みパルス電圧を印加してデータを書き込み、潜像を形成
させる画像表示装置であって、前記書き込みパルスを3
値としたことを特徴とする画像表示装置。
8. A plurality of opposing first and second display electrodes covered with a dielectric and a data electrode arranged to intersect with the first display electrode between a pair of substrates. A discharge cell group is formed by a partition wall between the two substrates, the discharge cell group is filled with a discharge gas, and a write pulse voltage is applied to a discharge cell selected between the first display electrode and the data electrode. An image display device for writing data by applying the data and forming a latent image, wherein
An image display device characterized by using a value.
JP10105986A 1998-04-16 1998-04-16 Driving method of plasma display panel Pending JPH11296136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10105986A JPH11296136A (en) 1998-04-16 1998-04-16 Driving method of plasma display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10105986A JPH11296136A (en) 1998-04-16 1998-04-16 Driving method of plasma display panel

Publications (1)

Publication Number Publication Date
JPH11296136A true JPH11296136A (en) 1999-10-29

Family

ID=14422066

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10105986A Pending JPH11296136A (en) 1998-04-16 1998-04-16 Driving method of plasma display panel

Country Status (1)

Country Link
JP (1) JPH11296136A (en)

Cited By (6)

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Publication number Priority date Publication date Assignee Title
JP2002006799A (en) * 2000-06-19 2002-01-11 Matsushita Electric Ind Co Ltd Method for driving plasma display panel
EP1227463A2 (en) * 2001-01-19 2002-07-31 Fujitsu Hitachi Plasma Display Limited Plasma display device and method for controlling the same
JP2005301282A (en) * 2004-04-12 2005-10-27 Lg Electronics Inc Drive device for plasma display panel and its driving method
JP2006337397A (en) * 2005-05-31 2006-12-14 Hitachi Ltd Plasma display driving circuit and display device using the same
WO2007018691A1 (en) * 2005-07-20 2007-02-15 Vladimir Nagorny Method of addressing a plasma display panel
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JP2002006799A (en) * 2000-06-19 2002-01-11 Matsushita Electric Ind Co Ltd Method for driving plasma display panel
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