JP2006337397A - Plasma display driving circuit and display device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display device capable of a reducing withstand voltage of an address driving circuit and reducing its power loss. <P>SOLUTION: A load of an addressing IC is alleviated by applying an addressing voltage for a variation portion by a different power source, when the addressing voltage is increased. On the other hand, regarding transmission of an address data, the number of signal lines and generation of noise are simultaneously reduced by current transmission of the data as a series data by an ultra-high speed transmission system such as a current transfer logic (CTL) system. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a plasma display display device using a plasma display panel, and more particularly to a driving technique of an address driving circuit for driving address electrodes.

  In a plasma display device using PDP (hereinafter abbreviated as “PDP display device”), signal transmission is generally performed between an image processor LSI for controlling the subfield configuration and the like and an address driving circuit (usually composed of a plurality of ICs). In addition, TTL level and CMOS signal level voltages are used. Furthermore, since the speed of the signal is high, a part of the signal is rearranged in parallel, and the parallel voltage signal is sent from the image processor to the address IC. In order to increase efficiency, the signal transmission is changed to a differential current transmission form, the voltage amplitude is reduced, and the speed is increased, thereby reducing the number of signal lines “LVDS (low amplitude differential signal: A technology that applies a high-speed current differential transmission method called “Low Voltage Differential Signaling” to convert the received serial signal into a parallel signal by the serial / parallel converter circuit on the address driver circuit side and developed it into the address driver circuit has been developed. (For example, FIG. 12 of patent document 1 etc.).

  In recent years, a CTL (Current Transfer Logic) transmission method that is more efficient than the LVDS transmission method has been studied (Non-Patent Document 1).

Japanese Patent Laying-Open No. 2005-17725 (FIG. 12) Nikkei Electronics 2004 11-22

  In general, the PDP has a very large number of cells (number of pixels). For example, even in a panel called VGA with a small number of pixels, there are 640 × 3 × 480 = 921,600 cells, and in a full high-vision with a large number of pixels, 1920 × 3 × 1080 = 6, 220,800 cells. Therefore, a variation in discharge characteristics (discharge start voltage characteristics) in each cell becomes a serious problem. In order to reduce the variation in the discharge characteristics between the cells, reset discharge is performed. Actually, however, the variation in the discharge characteristics appears as a voltage difference between the cells.

  FIG. 6 schematically shows the discharge characteristics of the cell. The bar-shaped marks with dots on the top and bottom of FIG. 6 indicate the operating voltage range in which stable discharge is performed in each cell. However, as can be seen from FIG. 6, when many cells are controlled, the common voltage range indicated by reference numeral 22 is a controllable stable operating voltage range (hereinafter, indicated by reference numeral 22). .

  Conventionally, as shown in the address signal waveform 23, GND (abbreviation of Ground, meaning ground. Also referred to as ground or ground. In the case of signal ground, when an electrical signal is exchanged between two points. The address electrode is driven by the address voltage Va, which is a drive voltage that always falls within the stable operation voltage range 22 from the reference potential (0 V).

On the other hand, there is a method of increasing the partial pressure ratio of xenon (Xe), which is one component of the discharge gas, as an effective means for improving the efficiency of the panel, which is becoming a recent trend. This is due to the following reasons. That is, by increasing the Xe partial pressure, the wavelength of ultraviolet light generated by discharge becomes longer, the conversion efficiency to visible light in the phosphor increases, and (self) absorption of the generated ultraviolet light decreases. This is because improvement in panel efficiency can be realized by improving the utilization efficiency of ultraviolet rays.
However, it is known that increasing the Xe partial pressure also increases the discharge start voltage and requires a high drive voltage, which places a heavy burden on the drive semiconductor (especially IC). In particular, in an address (data) electrode driving IC that handles high-speed signals (hereinafter simply referred to as “address IC”), the entire address driving voltage including the above-described variation in discharge characteristics increases. The actual situation is that the burden of the IC is heavy, and the design is made in consideration of the balance between improvement of panel efficiency and problems such as an increase in breakdown voltage and an increase in power loss due to an increase in driving voltage.
By the way, in order to reduce the cost, it is essential to make the address drive circuit with a large number of circuits into an IC, and recently, there is a tendency to increase the degree of integration with the aim of further reducing the cost. The obstacle at this time is an increase in the breakdown voltage of the address IC and power loss.

  In the address IC, not only the driving voltage increases but also the processing speed tends to increase as the data amount increases, for example, from VGA to XGA, and further to full high-definition (full HD).

  Furthermore, if the number of subfields is increased in order to improve the image quality, it is necessary to shorten the time required for the address operation, and the address IC is required to further increase the speed.

For the address IC, even if the address discharge current is very small, the charge / discharge current to the electrode capacitance C of the address electrode is large, and the loss is expressed by the following equation (1).
(Equation 1) P = CVa ² f
However, P is a power loss, Va is an address voltage, and f is an operating frequency.
From Equation 1, it can be seen that the power loss P increases significantly even when the electrode capacitance C is constant due to the increase in the address voltage Va and the increase in the operating frequency f.

  In Equation 1, the electrode capacitance C is determined by the panel structure, and is greatly influenced by the dielectric constant, the electrode area of the glass material, the electrode area, and the electrode shape. Even if improvements in panels to reduce capacity are promoted, large improvements cannot be expected immediately.

  On the other hand, the amount of information is increasing as the operating frequency f is VGA, XGA, full HD, and the like. Furthermore, in order to improve image quality, there is a tendency to increase the number of subfields, and although it is likely to increase as a future trend, it is unlikely to decrease.

  Further, other than the problem of the chip of the address IC, countermeasures for heat dissipation are an important issue against the increase in loss. For this reason, a cost increase becomes a big subject. Considering the widespread use of PDP display devices in the future, reducing the cost of address ICs and their peripheral parts that are used in large quantities is a major issue in the future.

  A technique for reducing the withstand voltage of the driving IC is conventionally used for the driving unit of the Y sustain electrode. That is, as shown in FIG. 27 of Patent Document 1, in the scan circuit and the Y sustain drive circuit constituting the drive unit of the Y sustain electrode, the reference potential (virtual GND) of the scan circuit is connected to the output of the Y sustain drive circuit. When the Y sustain electrode is driven by the Y sustain drive circuit during the sustain discharge, the voltage (withstand voltage) applied to the scan circuit is reduced.

  However, as shown in FIG. 29 of Patent Document 1, during the address operation in which the scan circuit operates, the scan circuit is grounded via the Y sustain drive circuit (the output potential of the Y sustain drive circuit is almost the ground potential). Therefore, the power consumption (power loss) of the scan circuit cannot be reduced.

  In addition, as shown in FIG. 27 of Patent Document 1, there are at most several control signals connected to the scan circuit via a photocoupler that performs insulation separation, and the scan circuit can be easily floated. This is due to the following reason. That is, the scan circuit has a shift register for generating a signal for sequentially specifying the Y sustain electrodes to be scanned in synchronization with the address cycle during the address operation, and “1” is input only in the first address cycle. Are shifted in synchronization with the address cycle, and the Y sustain electrodes are sequentially scanned through the output circuit. As a result, only a few lines are input to the scan circuit. On the other hand, since display data is input to the address drive circuit, the number of connections is very large.

  In addition to the above, the floating technique is also used for generating a ramp waveform in the reset period as described in Patent Document 2, but it is not for reducing the withstand voltage or power loss.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a plasma display device capable of reducing the withstand voltage of an address driving circuit and reducing the power loss thereof.

  In order to solve the above-mentioned problem, it is converted to a current transmission system with a small voltage amplitude, and a high-speed serial signal is used in order to reduce the number of parallel signals. Naturally, the number of coupling elements required for insulation corresponding to the reduced signal lines is also reduced.

  Further, the entire coupling circuit can be floated by the coupling element for insulation, and the voltage applied to the address driving IC itself can be greatly reduced.

  Between the insulating coupling element and the address drive IC, it is necessary to reduce the signal converted into the serial signal to a speed that can be processed by the address drive IC. Insert parallel (serial) conversion circuit.

  That is, the said subject can be solved by the invention described in the claim.

  ADVANTAGE OF THE INVENTION According to this invention, while reducing the withstand voltage of an address drive circuit, the plasma display display apparatus which can reduce the power loss can be provided.

  Hereinafter, the best mode of the present invention will be described with reference to the drawings. In each figure, elements having common functions are denoted by the same reference numerals, and redundant description of elements once described is omitted.

  The present embodiment is based on the fact that the breakdown voltage and loss burden of the address IC can be reduced if the AC voltage for driving the address electrode can be reduced from the characteristics of the discharge characteristics of FIG. This will be described with reference to FIG.

  FIG. 5 is a diagram schematically showing the address electrode driving method according to this embodiment. In FIG. 5, bar-shaped marks having dots on the upper and lower sides indicate the operating voltage range in which stable discharge is performed in each cell, as in FIG. Here, a stable operating voltage range in which all the cells can perform a stable discharge is indicated by reference numeral 22. If an address voltage within the stable operation voltage range 22 is always applied to the address electrode, it means that each cell reliably performs an address operation. Therefore, the output voltage output value Va of the address voltage must always be within the stable operating voltage range 22.

  As shown in FIG. 5, the address voltage Va is decomposed into a voltage Vaoff that is slightly lower than the lowest discharge start voltage among all the cells by a predetermined amount and a voltage Vsa that is a difference voltage between the voltage Va and the voltage Vaoff. can do. Since the voltage Vaoff is lower than the lowest discharge start voltage among all the cells, even if the voltage is applied to the address electrode, no discharge is caused. Therefore, by superimposing 0V and the voltage Vsa on the voltage Vaoff, the discharge is not caused at 0V, but if the voltage Vsa is superimposed, a discharge is caused. That is, address control can be performed by using the voltage Vaoff as an offset voltage and superimposing a signal having 0 V and a peak voltage Vsa thereon. Hereinafter, a signal having 0 V and a peak voltage Vsa is referred to as an “effective address signal 24” for convenience in order to avoid confusion, and the peak voltage Vsa is referred to as an “effective address voltage” to be distinguished from the address voltage Va. . The address signal waveform 25 indicates the driving method of the present embodiment described above.

  Therefore, an effective address signal having 0 V and a peak voltage Vsa is generated by the address driving circuit, and an offset voltage of voltage Vaoff is superimposed on the address signal, and an address electrode having two voltage values of voltage Vaoff and voltage Va = Vaoff + Vsa. Can be driven to perform an address operation.

  In this way, the address IC that constitutes the address drive circuit can set the voltage value of the power supply to Vsa if circuit loss is ignored, and the power supply voltage can be significantly reduced from the voltage (Va) of the conventional power supply. Can do. Accordingly, the withstand voltage and power loss of the address IC can be reduced, and further, the loss caused by charging / discharging of the electrode capacitance C can also be reduced. Therefore, the chip area of the address IC can be reduced, downsizing and cost reduction can be expected. Further, high integration is facilitated.

Further, since the loss of the address IC group can be reduced, the heat dissipation structure is simplified, and not only mounting is easy, but also cost reduction as a part is facilitated.
In this embodiment, in order to realize the address driving method described above, an effective address signal is generated by an address driving circuit and an offset voltage of voltage Vaoff is superimposed on the address driving circuit to float the entire address circuit portion. The circuit configuration is such that That is, the circuit configuration is such that the ground of the entire address circuit section (hereinafter referred to as “GND”) is floated from the GND of the display device.

  However, if the entire circuit system of the address drive circuit is to be floated, it is necessary to insulate and isolate the parallel address data with a large number of signal speeds (insulating the GND of the circuit on the floating side from the GND of the main circuit). To occur.

  Therefore, as a signal transmission mode (interface) between the image processor LSI and the address IC, for example, a high-speed current differential transmission method with a small voltage amplitude such as LVDS, TMDS (Transition Minimized Differential Signaling), and CTL is adopted, and the operation is performed. By increasing the speed, the signals processed in parallel are serialized to reduce the number of signal lines, supplied to the floating address circuit system via an isolation coupler, and the received serial signal is serial / parallel on the address circuit side. The signal is converted into a parallel signal by the conversion circuit and added to the address driving circuit (details will be described later). In other words, if the high-speed current differential transmission system interface and the serial / parallel conversion circuit provided on the address circuit side are combined, the floating of the address circuit section can be easily realized, and noise characteristics and signal routing can be achieved. It is also possible to improve the complexity.

  Hereinafter, an embodiment of the present embodiment will be specifically described with reference to FIG. FIG. 1 is a diagram showing an embodiment.

  In FIG. 1, a PDP 1 is the same as a conventional one, and includes a front plate 2F and a back plate 2R that are arranged to face each other. The front plate 2 </ b> F includes a Y sustain (scan) electrode 3 and an X sustain electrode 4. As a PDP display device, light emitted through the front plate 2F is seen. The X and Y sustain electrodes are formed by laminating a metal electrode such as silver or copper and a transparent electrode such as ITO on the inner surface side of the front plate 2F, which is a glass substrate, for example, and covers these electrodes. In this way, a dielectric (not shown, glass as a component) is arranged. Address electrodes 5 are formed on the back plate 2R so as to be orthogonal to the X sustain electrode 4 and the Y sustain electrode 3.

  The scan circuit 8 scans the Y sustain electrode 3 at the time of addressing. The Y sustain drive circuit 7 applies a high voltage pulse (Y sustain pulse) from the Y sustain electrode 3 side via the scan circuit 8 during the sustain discharge to generate a sustain discharge, and the X sustain drive circuit 6 A high voltage pulse (X sustain pulse) is applied from the sustain electrode 4 side to generate a sustain discharge. These sustain discharges are alternately performed from the X and Y sides during the sustain discharge period.

  Similarly to FIG. 27 of Patent Document 1, the scan circuit 8 is connected to the Y sustain drive circuit 7 in a floating state, as shown in FIG. That is, the virtual GND 8G of the scan circuit 8 is swung with the Y sustain pulse, and has a form similar to that of the address drive circuit described below.

  Reference numeral 100 denotes an address circuit unit that generates the effective address signal 24 described above, and the address circuit unit 100 includes a serial / parallel signal conversion circuit 11 and an address drive circuit 9. The serial / parallel signal conversion circuit 11 converts serial address data 15 input from the image processor LSI 13 via a coupler 12 (details will be described later) into parallel address data 16, and converts the converted parallel address data 16 into an address drive circuit 9. To supply. The address drive circuit 9 is composed of a plurality of address ICs 90, and at the time of addressing, each address IC 90 synchronizes a corresponding plurality of electrodes among the divided address electrodes 5 with a scanning signal (not shown) from the scanning circuit 8, respectively. Drive. The parallel address data 16 converted by the serial / parallel signal conversion circuit 11 is input to each address IC 90 of the corresponding address drive circuit 9, and each address IC 90 supplies an effective address signal 24 corresponding to the data to the address electrode 5. .

  The virtual GND 17 that is the reference potential of the address circuit unit 100 is floating from the GND that is the ground potential of the entire PDP display device. The virtual GND 17 is connected to the output of the address bias generation circuit 10 that gives the amplitude of the offset voltage Vaoff. That is, the virtual GND 17 of the address circuit unit 100 varies depending on the output of the address bias generation circuit 10.

  The address bias generation circuit 10 generates an offset voltage Vaoff in synchronization with a scanning signal (not shown) from the scanning circuit 8 at the time of addressing, and performs an operation of superimposing the offset voltage Vaoff on the effective address signal 24.

  Therefore, since the offset voltage Vaoff + effective address signal voltage (voltage 0, voltage Vsa) is applied to the address electrode 5 with respect to the GND, which is the ground potential of the PDP display device, at the time of addressing, it is effective as described above. An address operation corresponding to the address signal can be performed, and the power supply voltage of the address IC 90 can be lowered as compared with the prior art. That is, the breakdown voltage and loss can be reduced.

  Address data which is display data is supplied from the image processor LSI 13 to the address circuit unit 100 via the coupler 12. The image processor LSI 13 converts the address data into serial address data, and transmits the serial address data to the coupler 12 using the high-speed current differential transmission type interface 14 such as LVDS, TMDS, or CTL.

  The coupler 12 is a signal transmission component having a function of insulating and separating the GND of the PDP display device main body and the virtual GND 17 of the address circuit unit 100. In other words, the virtual GND 17 of the address circuit unit 100 is galvanically isolated from the GND of the PDP display device main body via the coupler 12.

  Needless to say, an optical fiber transmission system that can also be used as a coupler and a transmission line is also applicable. The transmission of high-speed signals by optical fiber is not particularly new and will not be described in detail, but the optical fiber itself is electrically insulated and also functions as a coupler.

  Further, depending on the form of the signal receiving side, simple separation by capacitance may be used instead of the coupler. In this embodiment, description will be made using a coupler whose principle can be easily explained.

  2A and 2B are diagrams for explaining the inside of the address IC in more detail. FIG. 2A is a simplified configuration diagram of the address IC, and FIG. 2B is a diagram showing a specific configuration of the output unit. In FIG. 2, components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 2A, the address IC 90 includes a plurality of address circuits 91 for driving one address electrode 5. A specific configuration of the output circuit is shown in FIG. . In the case of the address IC, the logic part (not shown) of the input circuit of the address circuit 91 is configured on the same chip together with the output circuit 92, but generally has a low operating voltage (for example, about 5V). On the other hand, although the output circuit 92 is superimposed with the output voltage (offset voltage Vaoff) of the address bias generation circuit 10, an applied voltage of several tens of volts is required for the virtual GND 17. Vcc (this voltage is almost equal to Vsa described above if the voltage drop by the circuit is ignored) is required.

  In FIG. 2, for convenience of illustration, the power supplied to the input circuit and the output circuit is collectively shown as the power supply 18 supplied to the address circuit unit 100 for the sake of convenience. However, for example, when the power supply voltages required for the serial / parallel signal conversion circuit, the logic unit of the address IC, and the output circuit are different, it is sufficient to have as many power supplies as the respective circuits require. Since the power supply of the address circuit unit 100 also needs to be floated, the power supply 18 GND of the address circuit unit 100 is used as a virtual GND 17 in a floating state.

  The circuit of the address IC 90 is generally divided into an output circuit of the high voltage unit and a logic unit (not shown) of the input circuit of the low voltage unit. However, since the IC is formed on the same chip, it is difficult to operate the logic portion at a high speed. Therefore, in FIG. 1, the serial / parallel signal conversion circuit 11 that processes high-speed signals is separated from the address IC 90 in order to optimize the operation. If the logic unit (not shown) of the address IC 90 can perform ultra-high speed processing, the function of the serial / parallel signal conversion circuit 11 may be taken in and the serial / parallel signal conversion circuit 11 may be omitted.

3 and 4 show a specific configuration of the coupler. The coupler 12 shown in FIG. 3 includes, for example, a light emitting element 19 (for example, a light emitting diode or a laser diode) that converts an electric signal provided at a terminal of the interface 14 into an optical signal, and an optical signal from the light emitting element 19 again (an electric signal ( It is composed of a light receiving element 20 (for example, a photodiode or a phototransistor) that converts it into serial address data 15), and insulates and isolates GND (virtual GND 17) of the address circuit unit 100 from GND that is the ground potential of the PDP display device. . The coupler 12 shown in FIG. 4 is an example of a high-speed pulse transformer 21 that efficiently transmits high-frequency and high-speed pulses. In any of the couplers of FIGS. 3 and 4, high-speed signal pulses are transmitted, but the direct current component is separated. The interface 14 of the input unit is a high-speed current differential transmission format such as the aforementioned LVDS, TMDS, CTL, and the serial address data 15 may be a current output or a voltage output. This is because the coupler 12 can be installed in the vicinity of the serial / parallel signal conversion circuit 11 of the address circuit unit 100 by using the high-speed current differential transmission type interface 14. Accordingly, it is possible to reduce signal deterioration, noise generation, and the like that cause signal inflow from the coupler 12 to the serial / parallel signal conversion circuit 11.
Further, it is needless to say that the coupler function can be substituted by simple capacitive coupling by providing a circuit capable of reproducing the DC component on the address circuit side.

  Hereinafter, the flow of signals will be described with reference to FIG. Address data is arranged in time series from the image processor LSI 13, and is transmitted as a high-speed pulse signal to the coupler 12 disposed in the vicinity of the address circuit unit 100 through the high-speed current differential transmission type interface 14. Conventionally, in general, the interface portion 14 is transmitted by a parallel voltage signal having a relatively high number of signal lines, and the distance between the image processor LSI 13 and the address circuit unit is long. Occurrence, signal degradation, etc. were significant. In the present embodiment, for example, the signal is transmitted through a high-speed current differential transmission interface typified by CTL and input to the coupler 12, so that the number of signal lines can be reduced and the signal voltage can be reduced. Therefore, generation of noise, signal degradation, etc. can be greatly suppressed.

  The coupler 12 disposed in the vicinity of the address circuit unit 100 transmits only a high-speed signal, and transmits an address signal to the address circuit unit 100 having a circuit configuration completely separated in terms of direct current.

  The serial address data signal input from the coupler 12 for isolation and separation to the address circuit unit 100 is first converted into a parallel data signal by the serial / parallel signal conversion circuit 11 so that the address IC 90 can process the signal. Is reduced to a speed that does not become noticeable, and is input to each corresponding address IC 90 constituting the address drive circuit 9. Since the serial / parallel signal conversion circuit 11 is arranged on the address drive circuit side, the number of signal lines of the interface 14 can be reduced.

  The address drive circuit 9 is floating and generates an effective address signal by subtracting the offset voltage Vaoff that substantially corresponds to the variation in the panel discharge start voltage, so that the drive voltage can be kept lower than before, Power loss can be reduced. This effective address signal is output from the address IC 90, and an offset voltage for correcting the variation voltage of the panel discharge start voltage from the address bias generation circuit 10 is superimposed on the effective address signal and applied to the address electrode 5. With this operation, the address drive circuit 9 can operate at a voltage lower than that of the prior art, can reduce the above-mentioned breakdown voltage, can reduce power loss, and can produce many other effects.

  That is, since the breakdown voltage and power loss can be reduced, the chip area of the address IC can be reduced, and high integration is facilitated. Accordingly, the cost of the address IC can be reduced, and the withstand voltage of the element can be lowered, so that a process capable of high-speed operation can be used, and the performance can be easily improved.

  Further, since power loss can be reduced, heat radiation design is facilitated, and not only mounting is easy, but also cost reduction as a part is facilitated. For example, there is a possibility that the number of cooling fans can be easily reduced.

  In the above-described embodiment, the address operation is limited to the address period. However, the present embodiment is not limited to this, and it is necessary to apply an address voltage during the reset period or the sustain period depending on the driving method of the PDP. Needless to say, the present invention can also be applied suitably.

  That is, if the above principle is applied, two kinds of potentials other than the GND potential can be applied to the address electrode depending on the output state (Low or High state) of the address IC. For example, in the above embodiment, the two kinds of potentials are the virtual GND potential and the voltage Va, but it goes without saying that the voltage values may be different from those other than the address operation period. In addition to the address period such as the reset period and the sustain period, the degree of freedom of the potential of the address electrode is increased, and it can be expected to have a great effect on the stable driving of the panel.

  Since it can be applied to general televisions and display terminals, the possibility of use is high. In addition, it becomes possible to easily realize what could not be realized from the viewpoint of the withstand voltage and loss of the conventional address IC, and it plays a large role not only in cost reduction but also in performance improvement.

1 shows an embodiment of the present invention. A specific example of an address IC output unit according to the embodiment. FIG. 3 is a structural diagram of a coupler using a photocoupler according to an example. 1 is a structural diagram of a coupler using a high-speed pulse transformer according to an embodiment. The figure which illustrates typically the address electrode drive principle by a present Example. Operation | movement explanatory drawing of a conventional circuit.

Explanation of symbols

1 PDP, 2F Front plate, 2R Rear plate, 3 Y sustain electrode, 4 X sustain electrode, 5 Address electrode, 6 X sustain drive circuit, 7 Y sustain drive circuit, 8 Scan circuit, 9 Address drive circuit, 10 Address bias generation Circuit, 11 serial / parallel signal conversion circuit, 12 coupler, 13 image processor LSI, 14 interface, 15 serial address data, 16 parallel address data, 17 virtual GND, 18 power supply, 19 light emitting element, 20 light receiving element, 21 high-speed pulse transformer , 22 Stable operating voltage range, 23 address signal waveform, 24 effective address signal, 25 address signal waveform, 90 address IC, 91 address circuit, 92 output circuit, 100 address circuit section,

Claims (7)

  A plasma display driving circuit, wherein the GND of the entire address circuit system is set in a floating state, and a voltage for correcting discharge variation of the cell is applied to the GND of the address circuit system.   A connection between a sending side for sending an address signal to an address driving circuit included in a signal processing circuit for performing signal processing of the plasma display and a receiving side for receiving an address signal sent from the sending side is made by a predetermined transmission method, A plasma display driving circuit, wherein data is serially processed and output. The plasma display driving circuit according to claim 2, wherein
The plasma display driving circuit, wherein the predetermined transmission system is a high-speed current transmission system for transmitting current at high speed. The plasma display driving circuit according to claim 3, wherein
A plasma display driving circuit, wherein the high-speed current method is CTL. The plasma display driving circuit according to claim 2, wherein
The plasma display driving circuit, wherein the predetermined transmission method is a transmission method using a high-speed optical fiber. In plasma displays that display images by discharge,
The GND of the entire address circuit system is set in a floating state, an output voltage of a circuit for generating an arbitrary voltage is applied to the GND of the address circuit system, and two types of potentials other than GND are applied to the address electrodes based on the output state of the address circuit system. A plasma display driving circuit configured to be applied to a plasma display. A plasma display display device comprising the plasma display driving circuit according to claim 1.

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