WO2010058469A1

WO2010058469A1 - Flat-panel display driving circuit

Info

Publication number: WO2010058469A1
Application number: PCT/JP2008/071127
Authority: WO
Inventors: 信義近藤; 哲也坂本; 外与志河田
Original assignee: 日立プラズマディスプレイ株式会社
Priority date: 2008-11-20
Filing date: 2008-11-20
Publication date: 2010-05-27

Abstract

There is provided a flat-panel display driving circuit for outputting, from a high-voltage output terminal (OUT), an electrode driving signal having a voltage higher than an input data signal and driving a flat-panel display electrode. The flat-panel display driving circuit comprises a low voltage logic circuit (LV) for processing the input data signal and outputting the result, a first switching element (Q31) connected between a high-voltage power supply (HVS) and the high-voltage output terminal (OUT), and a second switching element (Q32) connected between the high-voltage output terminal (OUT) and the power supply current return path (HVF) of the high-voltage power supply (HVS). The flat-panel display driving circuit further comprises a high-voltage output circuit (HV) for outputting the electrode driving signal to the high-voltage output terminal (OUT) and a level shift circuit (LS) for converting the output of the low voltage logic circuit (LV) to a signal level for controlling the high-voltage output circuit (HV). In the flat-panel display driving circuit, the power supply current return path (LVF) of the low voltage logic circuit (LV) is isolated from the power supply current return path (HVF) of the high-voltage output circuit (HV).

Description

Flat panel display drive circuit

The present invention relates to a driving circuit for a flat panel display such as a plasma display panel, and more particularly to an address driver IC used for driving address electrodes of a plasma display device or a driving circuit mounted on a scan driver IC used for driving scanning electrodes. About.

Conventionally, driver modules are known in which various driver ICs (Integrated Circuits, integrated circuits) are mounted as one of circuit members constituting a flat panel display such as a plasma display module. In particular, plasma display devices include an ADM (Address Driver Module) equipped with an address driver IC and an SDM (Scan Driver Module) equipped with a scan driver IC. This is a driver IC having a circuit function for driving the electrodes of the plasma display panel mounted on a substrate such as a tape carrier. The functions and number of ICs to be mounted, the plasma display panel to be connected, and the bus circuit to be connected There are various shapes depending on the shape, heat dissipation and mechanical fixing methods.

FIG. 1 is a diagram showing an example of the appearance of a general ADM conventionally used in an address circuit. Since the SDM with the scan driver IC mounted thereon has almost the same configuration, the ADM will be described below as an example.

FIG. 1 shows an ADM 90 in which one address driver IC 91 is flip-chip bonded to a tape carrier 92. In FIG. 1, the front side of the tape carrier 92 is an address bus circuit connecting portion 94 that supplies an address power supply, an address data signal, a control signal, and the like, and the opposite back side is a connecting portion 95 to a plasma display panel. is there. Note that the internal wiring 93 provided on the substrate such as the tape carrier 92 generally has a function as a mere lead line only for one-to-one connection between the internal and external electrical signals. Is.

FIG. 2 is an electrical connection diagram of the ADM 90 shown in FIG. In FIG. 2, the address driver IC 91 includes a low voltage logic circuit 60, a high voltage output circuit 80, and a level shift circuit 70. An address data signal sent from an address bus circuit (not shown) through a plurality of address data input lines DATA is sent to an address driver by a low voltage logic circuit 60 that operates according to two control signals, a clock signal CLK and a latch signal LE. The data is taken into the IC 91 and rearranged in a necessary order with a predetermined number of bits. Next, after being converted to a control signal level necessary for controlling the high voltage output circuit 80 by the level shift circuit 70, the high voltage switching element is controlled, and the address electrode drive signal Add1 is sent to the panel side as a high voltage output. ~ Addn is output. For simplification, the same symbol is used here for the signal name and the signal line name. A short diagonal line on each signal line indicates that there are a plurality of signal lines.

The control signal for the address data signal DATA, the clock signal CLK, and the latch signal LE is a low voltage logic level signal. The low voltage logic circuit 60 includes a shift register circuit 61 and a latch circuit 62 in the address driver IC 91. Received and processed by.

The processed signal is output to the plasma display panel as a high voltage output (address electrode drive signals Add1 to Addn) having an amplitude of a high voltage (between ground and + Va) by the high voltage output circuit 80 in the address driver IC 91. . In addition, the address driver IC 91 includes a level shift circuit 70 for mediating an electric signal level between the low voltage logic circuit 60 and the high voltage output circuit 80.

The power supply voltage Vcc of the low voltage logic circuit 60 of the general address driver IC 91 is +10 several V, and the power supply voltage + Va of the high voltage output circuit 80 is +10 [V], both of which are the reference potentials (LV− (GND, HV-GND) are generally connected inside the address driver IC 91 or on a substrate such as a tape carrier 92. Furthermore, the current consumption of the general low-voltage logic circuit 60 is almost constant and about several to several tens [mA]. Similarly, the current consumption of the high-voltage output circuit 80 flows in a pulse manner every address period, and the instantaneous peak value is reached. The current reaches several hundreds [mA], which is much larger than the current consumption of the low voltage logic circuit 61. The same applies to ADM.

FIG. 3 is a diagram showing an example of a general driving waveform applied to the plasma display panel. This is a waveform for one subfield, which is a basic waveform necessary for constructing one screen. A plurality of these are used in combination for actual screen display. FIG. 3 shows voltage waveforms of one subfield applied to each of the address electrode, X electrode (sustain electrode), and Y electrode (scan electrode) provided in the plasma display panel. Each waveform is divided into a reset period Tr, an address period Ta, and a sustain period Ts according to each function.

The address driver IC 91 described above outputs a voltage of + Va to the address electrode of the plasma display panel according to the image data from the control circuit during the address period Ta as shown by the address waveform in FIG. As shown in FIG. 3, the output amplitude level of the address driver IC 91 is generally a binary value of a ground (GND) level and an address voltage (abbreviated as + Va, and the voltage is generally several tens [V]). is there. In the address period Ta, a negative scan voltage (−Vy) is applied to the Y electrode in addition to the address electrode. Therefore, the potential difference between the address electrode and the Y electrode becomes (Va−Vy), and address discharge is generated by applying the address voltage and the scan voltage so that this potential difference exceeds the address discharge start voltage.

In the address period Ta, when an address discharge is generated to light a pixel, an address voltage Va is applied to the address electrode. When an address discharge is not generated and a pixel is not lighted, a ground level potential is set. Although it is applied, if lighting / non-lighting is repeated, the potential of the address electrode repeats + Va and GND, and power is frequently discarded to GND.

From such a viewpoint of reducing power consumption in the address period Ta, a database pulse set lower than a voltage for starting write discharge (address discharge) is applied to the column electrode (address electrode). A plasma display driving method that further applies a data pulse to a column electrode that generates an address discharge to generate an address discharge, thereby reducing potential fluctuation of the address electrode and reducing power consumption in the address period Ta Is known (see, for example, Patent Document 1).
JP 7-295506 A

By the way, recently, as part of the manufacturing cost reduction of a flat panel display headed by a plasma display device, the number of bits of each driver IC is increasing. The increase in the number of bits increases the size of the IC chip and the cost per chip increases, but the cost reduction due to the decrease in the number of ADMs and SDMs used, that is, the accompanying substrate members, exceeds that. When the number of bits of the driver IC increases, the current consumption of the IC itself, particularly the current consumption on the high voltage output circuit side, also increases proportionally. On the other hand, in the low voltage logic circuit, the amplitude of the logic signal level has been reduced as the control circuit for supplying signals to the ADM and the SDM and the speed of each bus circuit (both not shown) are increased.

FIG. 4 is a diagram schematically showing only one bit of the main circuit portion of the address driver IC 91 from FIG. In FIG. 4, the main part of the address driver IC 91 is a low voltage logic circuit 60a having an input terminal IN to which an input signal Vin from an address bus circuit (not shown) is input, and a high voltage that outputs a high voltage output Vout to the address bus electrode. A high voltage output circuit 80a having an output terminal OUT and a level shift circuit 70a connecting the two are constituted.

Note that, due to the custom of the circuit configuration, the first switching element connected between the high voltage power source (here, + Va) of the address driver IC 91 and the high voltage output terminal OUT, that is, the switching element QU on the high side and the high voltage output terminal. A second switching element connected between OUT and a power supply current feedback path (here, a ground line (GND)) of the high voltage power supply Va, that is, a switching element QD on the low side is used. Here, it is usual that the first switching element QU is a P-type FET and the second switching element QD is a N-type FET.
Also, as shown in FIG. 4, the power supply current feedback path (ground line) 68 of the low voltage logic circuit 1 and the power supply current feedback path (ground line) 88 of the high voltage output circuit 3 are address driver IC 91 in terms of circuit design. A part of each of the power supply

current feedback paths

68 and 88 must be shared as a common power supply current feedback path 98 in the chip. As the number of bits of the address driver IC 91 increases, the noise ΔV generated by the wiring resistance (common impedance) R0 of the common power supply current feedback path 98 becomes relatively large, but this is a low voltage logic circuit whose amplitude has been reduced. For this, the probability of malfunction increases. That is, the current flowing from the high voltage output circuit 80a through the power supply current feedback path 88 and into the common feedback path 98 is relatively larger than the current 68 of the low voltage logic circuit 60a, and if the parasitic wiring resistance R0 is large, the wiring resistance A large voltage fluctuation occurs at R0, which adversely affects the low voltage logic circuit 60a operating at a low voltage. Therefore, for stable operation of the address driver IC 91, it is desirable to eliminate the common impedance of the common power supply current feedback path 98 portion.

Also in the configuration described in Patent Document 1, the same problem occurs as long as the common feedback path 98 is provided in the address driver IC 91 as shown in FIG. 4, and the stable operation of the address driver IC 91 cannot be achieved. was there. Furthermore, this problem can occur in SDM as well, and can also occur in driver ICs of other flat display panels such as organic EL (Electro-Luminescence) and liquid crystal.

Therefore, an object of the present invention is to provide a driver IC that enables stable operation, including a driver IC designed to reduce power consumption.

In order to achieve the above object, a driving circuit for a flat panel display according to the first invention of the present invention outputs an electrode driving signal higher in voltage than the input data signal from a high voltage output terminal based on the input data signal. A flat panel display driving circuit for driving the electrodes of the flat panel display,
A low voltage logic circuit that receives the input data signal given in time series, processes the input data signal, and outputs in parallel with a predetermined number of bits;
A first switching element connected between a high voltage power supply and the high voltage output terminal; and a second switching element connected between the high voltage output terminal and a power supply current feedback path of the high voltage power supply. A control signal having a voltage level higher than that of the input data signal is input, and the electrode driving signal for driving the electrode of the display is output to the high voltage output terminal, corresponding to the predetermined number of bits. A high voltage output circuit;
The number of sets corresponding to the predetermined number of bits, which is obtained by converting the result of the predetermined number of bits processed by the low voltage logic circuit into a control signal level of the high voltage output circuit and supplying it to the high voltage output circuit A level shift circuit having
The power supply current feedback path of the low voltage logic circuit and the power supply current feedback path of the high voltage output circuit are electrically separated.

As a result, the large current flowing through the power supply current feedback path of the high voltage output circuit can be prevented from flowing into the power supply current feedback path of the low voltage logic circuit operating at a low voltage. Adversely affecting the operation of the low-voltage logic circuit can be prevented.

A second invention is a driving circuit for a flat panel display according to the first invention.
The voltage potential of the power supply current feedback path of the high voltage output circuit is made lower than the voltage potential of the power supply current feedback path of the low voltage logic circuit.

As a result, the voltage potential of the power supply current feedback path of the high voltage output circuit can be set to negative polarity, and the tribal IC can perform stable operation while operating the high voltage output circuit with a large voltage width. It becomes.

A third invention is a driving circuit for a flat panel display according to the second invention,
The first switching element is a P-channel FET, and the second switching element is an N-channel FET.

Thus, even when the operating voltage width is large, the push-pull circuit is used to make the first switching element a high voltage with reference to the potential of the high voltage power supply and the second switching element to the power supply current feedback path. Since the output circuits are operated, both can be operated with a fixed potential as a reference, and the operation of the driver IC can be stabilized.

4th invention is the drive circuit of the flat panel display based on 3rd invention,
The level shift circuit includes a first level shift circuit that supplies a control signal to the first switching element, and a second level shift circuit that supplies a control signal to the second switching element,
The control signal level output from the first level shift circuit is set between the potential of the high voltage power supply and the potential of the power supply current feedback path of the low voltage logic circuit,
The control signal level output from the second level shift circuit is set between a power supply potential of the low voltage logic circuit and a power supply current feedback path of the high voltage output circuit.

As a result, a control signal can be supplied to a high voltage output circuit that operates at a control signal level higher than that of a low voltage logic circuit using a level shift circuit that can handle a sufficient voltage width. Can be operated stably.

A fifth invention is a driving circuit for a flat panel display according to the first invention,
The power supply current feedback path of the high voltage output circuit has a potential lower than the power supply potential of the high voltage output circuit and higher than the power supply current feedback path of the low voltage logic circuit.

Thus, the potential of the power supply current feedback path of the high voltage output circuit can be set higher than the ground potential, the voltage operation width of the driver IC can be reduced, and the power consumption can be reduced.

A sixth invention is a drive circuit for a flat panel display according to the fifth invention,
The first switching element is a P-channel FET, and the second switching element is an N-channel FET.

Thus, a push-pull circuit is used for the high voltage output circuit, the reference potential of the first switching element can be the potential of the high voltage power supply, and the reference potential of the second switching element can be the potential of the current feedback path. Since both can be operated with a fixed potential as a reference, stable operation of the high voltage output circuit can be achieved.

A seventh invention is a driving circuit for a flat panel display according to the fifth invention,
A diode is inserted between the power supply current feedback path of the high voltage output circuit and the power supply current feedback path of the low voltage logic circuit.

Thus, even when there is an abrupt decrease in potential on the panel side, a protection diode can be provided to prevent a decrease due to potential pull-in of the power supply current feedback path.

An eighth invention is a drive circuit for a flat panel display according to the fifth invention,
The level shift circuit includes a first level shift circuit that supplies a control signal to the first switching element, and a second level shift circuit that supplies a control signal to the second switching element,
The control signal level output from the first level shift circuit and the control signal level output from the second level shift circuit are respectively the power supply potential of the high voltage output circuit and the power supply current feedback of the low voltage logic circuit. It is set between the potentials of the path.

Thereby, it is possible to set the control signal level supplied to the high voltage output circuit by utilizing the maximum potential width in the driver IC, and it is possible to correspond to the high voltage output circuit having various control signal levels.

A ninth invention is a driving circuit for a flat panel display according to the fifth invention,
The control signal level output by the first level shift circuit is set between the power supply potential of the high voltage output circuit and the power supply current feedback path of the low voltage logic circuit,
The control signal level output from the second level shift circuit is set between a potential lower than the power supply potential of the high voltage output circuit and higher than the potential of the power supply for the low voltage logic circuit. To do.

Thus, a control signal having a control signal level appropriate for driving the second switching element can be supplied from the second level shift circuit, and the second switching element can be operated appropriately. it can.

According to a tenth aspect of the present invention, in the flat panel display driving circuit according to the first aspect of the present invention,
The level shift circuit includes a first level shift circuit that supplies a control signal to the first switching element, and a second level shift circuit that supplies a control signal to the second switching element,
A buffer circuit is connected between the first level shift circuit and the first switching element and / or between the second level shift circuit and the second switching element.

Thus, when the control signal level by the level shift circuit is insufficient, the shortage can be compensated by the buffer circuit, and the high voltage output circuit can be stably operated.

An eleventh invention is a driving circuit for a flat panel display according to the tenth invention,
The output impedance of the buffer circuit is set to be higher than the output impedance of the level shift circuit.

Thus, the output waveform from the high voltage output circuit can be blunted, and it can be applied to a flat display panel that requires such output waveform characteristics.

A twelfth aspect of the invention is a flat panel display drive circuit according to the first aspect of the invention,
The flat panel display device is a plasma display panel;
The driving circuit of the flat panel display is mounted on an address driver IC for driving address electrodes.

Thereby, the address discharge of the plasma display panel can be performed stably.

According to the present invention, the flat panel display can be driven stably.

It is the figure which showed an example of the external appearance of the common ADM conventionally used with the address circuit. FIG. 2 is an electrical connection diagram of a conventional ADM 90 shown in FIG. It is the figure which showed an example of the general drive waveform applied to a plasma display panel. FIG. 10 is a diagram schematically showing only a main circuit portion of a conventional address driver IC 91 for one bit. 1 is an overall configuration diagram of a plasma display device using a driver IC according to an embodiment. FIG. 3 is a diagram illustrating an example of a circuit configuration of an address driver IC 21 according to the first embodiment. It is the figure which showed an example of the voltage waveform of an input data signal and a high voltage output terminal. FIG. 6 is a circuit configuration diagram of an address driver IC 21a according to a second embodiment. It is the figure which showed an example of the voltage waveform of an input data signal and a high voltage output terminal. It is the figure which showed an example of the voltage waveform of each electrode of 1 subfield. FIG. 10 is a circuit configuration diagram of an address driver IC 21b according to a third embodiment. It is the figure which showed an example of the voltage waveform of the input signal of Example 3, and the output signal of a high voltage output terminal. FIG. 10 is a circuit configuration diagram of an address driver IC 21c according to a fourth embodiment. It is the figure which showed the example of the voltage waveform of the input signal of Example 4, and a high voltage output terminal.

Explanation of symbols

10 Plasma display panel 20

Address drive circuit

21, 21a, 21b, 21c, 91 Address driver IC
30 sustain drive circuit 40 scan drive circuit 41 scan driver IC
42 Sustain driver IC
43 reset circuit 50 drive control circuit 51 subfield conversion circuit 52 address data generation circuit 53 scan data generation circuit 54 maintenance data generation circuit LV, LVb, LVc low voltage logic circuit LS, LSa, LS1, LS2, LS2a level shift circuit HV, HVa, HVc High voltage output circuit LVS, HVS Power supply LVF, HVF, HVFa Power supply current feedback path OUT High voltage output terminal

The best mode for carrying out the present invention will be described below with reference to the drawings.
FIG. 5 is an overall configuration diagram of a plasma display device using a flat panel display driving circuit according to an embodiment to which the present invention is applied. In FIG. 5, the plasma display device includes a plasma display panel 10, an address drive circuit 20, a sustain drive circuit 30, a scan drive circuit 40, and a drive control circuit 50. FIG. 5 shows an example in which the drive circuit of the flat panel display according to the present embodiment is applied as the address driver IC 21.

The plasma display panel 10 is a display panel for displaying an image. The plasma display panel 10 includes a plurality of sustain electrodes X1, X2, X3,... And a plurality of scan electrodes Y1, Y2, Y3,. Hereinafter, each of the sustain electrodes X1, X2, X3,... Or their generic name is referred to as a sustain electrode Xi, and each of the scan electrodes Y1, Y2, Y3,. It is called Yi. i means a subscript. The plasma display panel 10 includes a plurality of address electrodes A1, A2, A3,... Extending in the vertical direction. Hereinafter, each of the address electrodes A1, A2, A3,... Or their generic name is referred to as an address electrode Aj, and j means a subscript. The sustain electrodes Xi and the scan electrodes Yi extending in the horizontal direction are alternately arranged in the vertical direction. The sustain electrode Xi may be called the X electrode Xi, and the scan electrode Yi may be called the Y electrode Yi. In plan view, discharge cells Cij are formed at positions where the sustain electrodes Xi, the scan electrodes Yi, and the address electrodes Aj intersect. The discharge cells Cij correspond to pixels, and the plasma display panel 10 can display a two-dimensional image. The sustain electrode Xi and the scan electrode Yi in the display cell Cij have a space between them to constitute a capacitive load.

The address drive circuit 20 is a circuit for driving the address electrode Aj, and supplies an address pulse having a predetermined voltage value to the address electrode Aj in the address period Ta to generate an address discharge. The address drive circuit 20 has a plurality of address driver ICs 21. The address driver IC 21 is an IC having a plurality of outputs, and each of the plurality of outputs is connected to the address electrode Aj. Further, a plurality of address driver ICs 21 are provided in the address driving circuit 20, so that all the address electrodes Aj in the horizontal direction can be driven as a whole.

Each address driver IC 21 is configured as an address driver module 90 as described with reference to FIG. 1, and has an internal configuration block as described with reference to FIG. A specific internal configuration of the address driver IC 21 according to the present embodiment will be described later.

The scan drive circuit 40 is a circuit for driving the scan electrode Yi, and includes a scan driver IC 41, a sustain driver IC 42, and a reset circuit 43.
The scan driver IC 41 is an IC equipped with a drive circuit for supplying a scan pulse having a predetermined voltage value to the scan electrode Yi and generating an address discharge in accordance with the control of the drive control circuit 50 and the sustain driver IC 42. . In this embodiment, the driver IC of the present invention is described as an example applied to the address driver IC 21. However, the driver IC of the present invention can also be applied to the scan driver IC 41.

The sustain driver IC 42 is an IC equipped with a drive circuit that supplies a sustain pulse having the same voltage to the scan electrodes Yi and generates a sustain discharge.

The reset circuit 43 is a circuit that supplies a reset pulse having a predetermined voltage value to the scan electrode Yi according to the control of the drive control circuit 50, generates a reset discharge, and initializes and arranges the wall charge of the discharge cell Cij. is there.

The sustain drive circuit 30 is a circuit for driving the sustain electrode Xi, and supplies a sustain pulse having the same voltage to the sustain electrode Xi to generate a sustain discharge. Each sustain electrode Xi is interconnected and has the same voltage level.

The drive control circuit 50 is a circuit that drives and controls the address drive circuit 20, the sustain drive circuit 30, and the scan drive circuit 40. The drive control circuit 50 includes a subfield conversion circuit 51, an address data generation circuit 52, a scan data generation circuit 53, and a maintenance data generation circuit 54.

When one frame or one field input signal S, which is a general image signal, is input to the drive control circuit 50, the subfield conversion circuit 51 subdivides one frame or one field image into a plurality of subfields. Perform conversion. Based on the converted subfield, the address data generation circuit 52 and the scan data generation circuit 53 generate address data and scan data necessary for driving the address drive circuit 20 and the scan circuit 41 of the scan drive circuit 40. The sustain data generation circuit 55 generates sustain data necessary for driving the sustain drive circuit 30 and the sustain circuit 42 of the scan drive circuit 40.

In the driving circuit of the flat panel display according to the present embodiment, an example in which the driving circuit is applied to and mounted on the address driver IC 21 of the address driving circuit 20 that drives the plasma display panel 10 as shown in FIG. 5 will be described. As described above, the present invention can also be applied to a scan driver IC 41 of the scan drive circuit 40 and a driver IC equipped with a drive circuit of another flat panel display.

Next, specific examples of the address driver IC 21 according to the present embodiment will be described.

FIG. 6 is a diagram showing an example of the circuit configuration of the address driver IC 21 according to the first embodiment to which the present invention is applied. The address driver IC 21 according to the present embodiment includes a low voltage logic circuit LV, a level shift circuit LS, and a high voltage output circuit HV. The low voltage logic circuit LV has a high potential side connected to a power supply LVS (potential is + Vcc) and a low potential side connected to a power supply current feedback path LVF (potential is GND). The high voltage output circuit HV has a high potential side connected to a high voltage power supply HVS (potential is + Va1) and a low potential side connected to a power supply current feedback path HVF (potential is −Va2). Further, the low voltage logic circuit LV includes input lines IN1 and IN2 for receiving input data, and the high voltage output circuit HV includes a high voltage output terminal OUT for outputting a high voltage.

The low-voltage logic circuit LV is a circuit for receiving input data signals given in time series from the input terminals INa and INb, receiving them, processing them, and outputting them as parallel signals having a predetermined number of bits. As described with reference to FIG. 2, the processing at that time is controlled by the clock signal and the latch signal which are the control signals are input to the clock signal input line and the latch signal input line which are the control signal input lines. Thus, processing in the low-voltage logic circuit LV may be executed. The final stage of the low-voltage logic circuit LV includes buffers U1 and U2, and supplies the waveform-shaped output to the level shift circuit LS.

The level shift circuit LS is a circuit that converts a signal output from the low voltage logic circuit LV into a control signal level suitable for operating the high voltage output circuit HV. The level shift circuit LS includes a first potential level shift circuit LS1 on the high potential side that connects both the output of the low voltage logic circuit LV and the control signal level between the high voltage output circuit HV and a low potential side. Second level shift circuit LS2.

The high voltage output circuit HV is a circuit for supplying an address pulse to the address electrode Aj. The high voltage output circuit HV is connected between the high voltage power supply HVS (+ Va1) and the high voltage output terminal OUT, that is, the high side P-type FET Q31, the high voltage output terminal OUT, and the power supply for the high voltage output circuit HV. An N-type FET Q32 is provided between the current feedback path HVF (−Va2), that is, on the low side.

The address driver IC 21 according to this embodiment includes a power supply current feedback path LVF (ground level) of the low voltage logic circuit LS and a power supply current feedback path HVF (−Va2) of the high voltage output circuit HV, which have been shared in the past. The voltage of the power supply current feedback path HVF (−Va2) is made lower than the ground. As a result, the low voltage logic circuit LV and the high voltage output circuit HV can be electrically separated and separated. In the high voltage output circuit HV, a large current flows through the power supply current feedback path HVF, and the parasitic wiring resistance increases. Even if the voltage fluctuation occurs, it is possible to eliminate the adverse effect of the voltage fluctuation on the low voltage logic circuit LV. Here, the first switching element Q31 connected between the high-voltage power supply HVS (+ Va1) and the high-voltage output terminal OUT is a P-channel FET (Field-Effect-Transistor, field effect transistor). The second switching element Q32 connected between the high voltage output terminal OUT and the power supply current feedback path HVF (−Va2) of the high voltage output circuit HV is an N-channel FET. Since the power supply Vcc of the second level shift circuit LS2 is the same as the power supply voltage Vcc of the low voltage logic circuit LV, the output level of the second level shift circuit LS2 is Vcc to -Va2.

Note that the power supply voltage (+ Va1) on the high side of the high voltage output circuit HV is set to a voltage that is higher by several volts than the maximum lighting voltage (Vamax) of the panel display characteristics. The power supply voltage (−Va2) on the low side is set to a voltage lower by about several V than the minimum lighting voltage (Vamin) of the panel display characteristics.

The first level shift circuit LS1 is composed of input side FETs Q11 and Q12 and output side FETs Q13 and Q14. The high voltage side power supply of the first level shift circuit LS1 is the same as the high voltage side power supply HVS of the high voltage circuit HV (+ Va1), and the low voltage side power supply is at the ground level.

Similarly, the second level shift circuit LS2 includes Q21 and Q22 of the input side FET and Q23 and Q24 of the output side FET. The high voltage side power supply of the second level shift circuit LS2 is the same as the power supply LVS of the low voltage logic circuit LV (+ Vcc), and the low voltage side power supply is the same as the low voltage side power supply HVF of the high voltage output circuit HV (−Va2). It is.

Next, the operation of the address driver IC 21 according to the first embodiment during the address period Ta will be described. As shown in FIG. 6, input data signals INa and INb are input to input lines IN1 and IN2, respectively. The low voltage logic circuit LV performs waveform shaping in the buffers U1 and U2, and outputs the shaped input data signal. Here, the input signals INa and INb are usually the same signal. In the first embodiment, a configuration of an actual IC that performs high impedance output or operation during power recovery is cited, and in the figure, a configuration in which separate independent signals can be input. The outputs of the low voltage logic circuit LS, that is, the outputs of the buffers U1 and U2, are input to the first level shift circuit LS1 and the second level shift circuit LS2 of the level shift circuit LS, respectively. The outputs of the first level shift circuit LS1 and the second level shift circuit LS2 are the first switching element Q31 of the high-voltage output circuit HV that switches the two power supply potentials (+ Va1) and (−Va2) and the second level shift circuit LS2, respectively. The switching element Q32 is operated.

FIG. 7 is a diagram showing voltage waveforms of the input data signals INa and INb and the high voltage output terminal OUT of the high voltage output circuit HV. As shown in FIG. 7, the same pulse voltage signal is input to the input data signals INa and INb, and a square wave pulse having a binary value of 0 to Vcc [V] is input to both. On the other hand, the high voltage output terminal OUT outputs a square wave pulse whose voltage is binary between (−Va2) to (+ Va1) [V] in synchronization with the input data signals INa and INb. In FIG. 7, when the output voltage changes from (+ Va1) to (−Va2), a large current flows through the power supply current feedback path HVF of the high voltage output circuit HV, and the voltage drop due to the wiring resistance also increases. As described above, the power supply current feedback path HVF of the high voltage output circuit HV and the power supply current feedback path LVF of the low voltage logic circuit LV are electrically separated, so that the voltage fluctuation on the high voltage output circuit HV side is Can be prevented from affecting the low voltage logic circuit LV.

Returning to FIG. 6, the operation when the voltage pulses INa and INb as shown in FIG. 7 are supplied to the input lines IN1 and IN2 will be described. When INa and INb are at the high level, the input side FETs Q12 and Q21 are turned on. Since the low-level control signal is supplied to the first switching element Q31 of the high voltage output circuit HV and turned on, and the output side FET Q24 is turned on but the output side FET Q22 is turned off, the second switching element Q32 remains off. Therefore, Va1 is output to the high voltage output terminal OUT, as shown in FIG.

Similarly, when the input data signals INa and INb are at the low level, in the first level shift circuit LS1, the input side FET Q11 and the output side FET Q14 are turned on, but the input side FET Q12 remains off. The first switching element Q31 is turned off. On the other hand, in the second level shift circuit LS2, the input side FET Q22 and the output side Q23 are turned on, and the control signal supplied to the second switching element Q32 of the high voltage output circuit HV becomes the high level. Since the switching element Q32 is turned on, (−Va2) is output to the high voltage output terminal OUT, which matches the voltage waveform of FIG.

As described above, in the address driver IC 21 according to the first embodiment, the power supply current feedback path LVF (ground in the drawing) of the low voltage logic circuit LV and the power supply current feedback path HVF (−Va2 in the drawing) of the high voltage output circuit HV. ), The common feedback path 98 of both shown in FIG. 4 of the prior art can be eliminated. Thereby, even if the number of bits of the address driver IC21 increases and the power supply feedback current of the high voltage output circuit HV increases, the power supply current feedback path LVF on the low voltage logic circuit LV side is not affected, and the low voltage logic circuit LV Can be operated stably. At the same time, it is possible to set the output voltage amplitude of the high voltage output circuit HV so that the potential difference between + Va1 and -Va2 is smaller than that of the conventional address pulse. In this case, as the address driver IC and thus the plasma display product, Power consumption can also be reduced.

FIG. 8 is a circuit diagram of the address driver IC 21a according to the second embodiment to which the present invention is applied. The address driver IC 21a according to the second embodiment is the same as the address driver IC 21 according to the first embodiment in that it includes a low voltage logic circuit LS, a level shift circuit LSa, and a high voltage output circuit HVa. The configurations of the LSa and the high voltage output circuit HVa are different from those of the address driver IC 21 according to the first embodiment. Since the configuration of the low voltage logic circuit LS is the same as that of the first embodiment, the same reference numerals are given and the description thereof is omitted. Also, with respect to the other components, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified.

The address driver IC 21a according to the present embodiment separates the power supply current feedback path LVF (ground level) of the low voltage logic circuit LV that has been shared in the past from the power supply current feedback path HVFa (+ Va3) of the high voltage output circuit HV. The voltage is higher than the ground. Further, the first switching element Q31 connected between the high voltage power supply HVS and the high voltage output terminal OUT is a P-channel FET, and is connected between the high voltage output terminal OUT and the power supply current feedback path HVFa of the high voltage power supply HVS. The second switching element Q32 is an N-channel FET. The rating of the FETs Q31 and Q32 used here is Vgs = ± Vdd. The power sources of the first level shift circuit LS1 and the second level shift circuit LS2a are both the high voltage power supply HVS (+ Va1) on the high potential side and the power supply current feedback path on the low potential side is ground (GND). The output level is + Va1 to GND. A protective diode D is inserted between the power supply current feedback path HVFa of the high voltage output circuit HV and the ground.

The point that the buffer circuits U1 and U2 are shown as a part of the low voltage logic circuit LV is the same as that of the first embodiment.

The high voltage output circuit HVa includes the first switching element Q31 on the high side connected between the high voltage power supply HVS (+ Va1) and the high voltage output terminal OUT, the high voltage output terminal OUT, and the power supply current feedback path HVFa. And a second switching element Q32 on the low side connected between the two. The first switching element Q31 is a P-channel FET. The second switching element Q32 is lower than the power supply voltage (+ Va1) of the high voltage output terminal OUT and the high voltage output circuit HVa and higher than the voltage (GND) of the power supply current feedback path LVF of the low voltage logic circuit LV. This is a low-side N-type FET provided between the power supply current feedback path HVFa (+ Va3) of the high voltage output circuit HV. The high voltage output circuit HVa has a diode D connected between the ground and the power supply current feedback path HVFa (+ Va3), the anode of the diode D is connected to the ground GND, and the cathode of the diode D is the power supply current feedback path. It is connected to HVFa (+ Va3).

Further, in order to convert the control signal level between the output of the low voltage logic circuit LV and the high voltage output circuit HVa, a level shift circuit including a first level shift circuit LS1 and a second level shift circuit LS2a that connect both of them. It consists of LSa.

The power supply voltage (+ Va1) on the high side of the high voltage output circuit HV is set to a voltage several V higher than the maximum lighting voltage (Vamax) of the panel display characteristics. In addition, the low-side power supply voltage (+ Va3) is set to a voltage that is lower than the minimum lighting voltage (Vmamin) of the panel display characteristics by about several volts.

The level shift circuit LS1 is composed of input side FETs Q11 and Q12 and output side FETs Q13 and Q14. The high voltage side power supply of this circuit is the same as + Va1 as the high voltage side power supply of the high voltage circuit, and the low voltage side power supply is at the ground level. Similarly, the level shift circuit LS2 includes Q21 and Q22 of input side FETs and Q23 and Q24 of output side FETs. The high voltage side power supply of this circuit is + Va1 which is the same as the power supply HVS of the high voltage output circuit HVa, and the low voltage side power supply is the same ground as the power supply current feedback path LVF of the low voltage logic circuit LV.

Next, the operation of the address driver IC 21a according to the second embodiment during the address period Ta will be described. As shown in FIG. 8, the input signals INa and INb are input to the input lines IN1 and IN2, and the low voltage logic circuit LV shapes and outputs the waveform of the input signal with the buffers U1 and U2. As in the first embodiment, INa and INb normally use the same signal. Here, the configuration of an actual IC that performs an operation at the time of output high impedance or power recovery is cited, and in the figure, a configuration in which separate independent signals can be input. The respective outputs are input to the first level shift circuit LS1 and the second level shift circuit LS2. The outputs of the first level shift circuit LS1 and the second level shift circuit LS2 operate the FETs Q31 and Q32 that switch the two power supply potentials + Va1 and + Va3, respectively, and the two power supply potentials correspond to the input signals. Output.

FIG. 9 is a diagram showing an example of voltage waveforms of the output signals output from the input data signals INa and INb and the high voltage output terminal OUT. In FIG. 9, the same input signals INa and INb having a voltage amplitude of 0 to Vcc [V] are input at the same timing, and an output signal synchronized with the voltage change of the input signals INa and INb has a voltage amplitude of ( + Va3) to (+ Va1) [V] are output. In FIG. 9, the amplitude of the voltage is a waveform in which both the lowest potential and the highest potential are positive and the voltage width is small. In such an address pulse, if the potential difference from the scan electrode is adjusted so that an address discharge occurs at the highest potential (+ Va1) and no address discharge occurs at the lowest potential (+ Va3), Non-lighting potential fluctuations are reduced, and power consumption can be reduced.

FIG. 10 is a diagram showing an example of voltage waveforms of the address electrode Aj, the sustain electrode Xi, and the scan electrode Yi in one subfield. In FIG. 10, the voltage waveforms of the electrodes Aj, Xi, and Yi in the reset period Tr, the address period Ta, and the sustain period Ts are shown. The reset period Tr and the sustain period Ts are the same as the voltage waveforms shown in FIG. Since it is the same, the description is abbreviate | omitted.

On the other hand, paying attention to the address period Ta, the address driver IC 21a outputs an address voltage to the address electrodes of the plasma display panel according to the image data from the control circuit during the address period Ta. At that time, in the prior art, as shown in FIG. 3, the output amplitude level of the address driver IC is a binary level of a ground (GND) level and an address voltage (abbreviated as + Va, and the voltage is generally several tens of volts). It is common to do.

However, in practice, it is sufficient that the high voltage side is higher than the maximum lighting voltage (Vamax) of the panel display characteristics, and the general address voltage Va is set to be several V higher than this. Further, the low voltage side need only be equal to or lower than the minimum lighting voltage (generally about 10 V lower than Vamin and Vamax) of the panel display characteristics, and it is necessary to increase the amplitude with a high voltage that is widely used at present. There is no.

The increase in the output amplitude of a general address driver IC is simply due to the custom on the IC side. That is, the output of the address driver IC does not require an amplitude of several tens of volts as in the prior art. In practice, as shown in FIG. 10, the upper limit is Vamax + α, and the lower limit is about Vamin−α (α is several V). At most about 20 [V] is sufficient. With such a low amplitude, the charging / discharging current with the panel can be reduced, and the power consumption of the driver IC and thus the plasma display product can be reduced.

According to the address driver IC 21a according to the second embodiment, as shown in FIG. 10, the maximum value (+ Va1) of the address pulse applied to the address electrode Aj is (Vamax + α), and the minimum value (+ Va3) of the address pulse is (Vamin). -Α), the power supply current of the high voltage output circuit HVa is separated by separating the power supply current feedback path LVF of the low voltage logic circuit LS and the power supply current feedback path HVFa of the high voltage output circuit HVa while achieving low power consumption. A circuit that does not affect the low-voltage logic circuit LS due to the voltage fluctuation caused by the current flowing into the feedback path HVFa can be obtained. Further, since the potential difference between (Vamax + α) and (Vamin−α) is small, the current value itself flowing into the power supply current feedback path HVFa can be reduced, and further, the factors that cause potential fluctuations in the low voltage logic circuit LV can be reduced. Can do.

Note that the description in FIG. 10 can be applied to the scan driver IC 41 and driver ICs of other flat panel displays.

Return to FIG. In the diode D of the high voltage output circuit HVa, the output terminal OUT connected to the address electrode is charged / discharged between the sustain electrode Xi and the adjacent address electrode Aj, particularly by interelectrode capacitive coupling during the reset period Tr in FIG. It is a protection circuit that prevents a negative potential from being drawn due to the generated charge / discharge. The diode D is an essential component for realizing the present embodiment.

Thus, according to the address driver IC 21a according to the second embodiment, the power supply current feedback path LVF (ground in the figure) of the low voltage logic circuit LV and the power supply current feedback path HVFa (+ Va3 in the figure) of the high voltage output circuit HVa. 4), the common feedback path 98 shown in FIG. 4 is eliminated, and even if the number of bits of the address driver IC increases and the power supply feedback current of the high voltage output circuit increases, the power supply on the low voltage logic circuit side The low voltage logic circuit can be stably operated without affecting the current feedback path. At the same time, since the output voltage amplitude of the high voltage output circuit can be reduced to (+ Va1) to (+ Va3) as compared with the conventional case, the power consumption of the address driver IC and thus the plasma display product can be reduced.

FIG. 11 is a diagram showing a circuit configuration of the address driver IC 21b according to the third embodiment to which the present invention is applied. The address driver IC 21b according to the third embodiment is obtained by adding buffer circuits BF1 and BF2 to the circuit of the address driver IC 21a illustrated in the second embodiment. Accordingly, the input lines INB1 and INB2 for the buffer circuits BF1 and BF2 are added to the low voltage logic circuit LVb, respectively, so that the total number is four. The description of functions and operations similar to those used in FIG. Also, the same components as those of the address driver IC 21a according to the second embodiment illustrated in FIG. 8 are denoted by the same reference numerals, and the description thereof is omitted.

As the plasma display panel becomes larger, the driving capability of the address driver IC 21b, that is, the driving currents of the FETs Q31 and Q32 of the high voltage output circuit HVa also increases. In this case, since the gate drive capability of Q31 and Q32 is insufficient only with the conventional level shift circuit, in the address driver IC 21b according to the third embodiment, the P-channel type FETs Q61 and N are arranged in the subsequent stage of the first level shift circuit LS1. A buffer circuit BF1 including a channel type FET Q62 is added. Similarly, a buffer circuit BF2 including a P-channel FET Q71 and an N-channel FET Q72 is added to the subsequent stage of the level shift circuit LS2.

During the address period Ta, as shown in FIG. 11, the input signal INa-1 is input to the first level shift circuit LS1 via the buffer U1 of the low voltage logic circuit LVb, and the input signal INa-2 is input to the input line INB1. To the buffer circuit BF1. On the other hand, the input signal INb-1 is input to the second level shift circuit LS2a via the buffer U2 of the low voltage logic circuit LVb, and the input signal INb-2 is input to the buffer circuit BF2 from the input line INB2. The output of the first level shift circuit LS1 is input to the buffer circuit BF1, and the output of the second level shift circuit LS2a is input to the buffer circuit BF2. The outputs of the buffer circuits BF1 and BF2 operate the first switching element Q31 and the second switching element Q32 of FETs that switch the two power supply potentials + Va1 and + Va3, respectively.

FIG. 12 is a diagram illustrating an example of voltage waveforms of the input signals INa-1, INa-2, INb-1, INb-2 of the address driver IC 21b according to the third embodiment and the output signal of the high voltage output terminal OUT. . In FIG. 12, signals having the same voltage waveform are input to input signals INa-1 and INb-1, and signals having the same voltage waveform are input to input signals INa-2 and INb-2. The output waveform is output in the voltage range (+ Va3) to (+ Va1) [V] in synchronization with the input signals INa-1 and INb-1 in the voltage range 0 to Vcc [V]. Yes.

In the third embodiment, as in the second embodiment, only one input signal is required. However, the configuration of an actual IC that performs an operation at the time of output high impedance and power recovery is cited. The configuration is shown in which signals can be input. In the present embodiment, INa-1 has the same phase as INb-1, INa-2 and INb-2 have the same phase, and the respective sets are signals of opposite phases.
In this way, not only the stable operation of the low-voltage logic circuit obtained in the second embodiment and the reduction in power consumption of the address driver IC, but also a high-voltage drive that meets the demands of larger plasma display panels Ability can also be gained.

Moreover, if the current capability of each buffer circuit BF1 and BF2 is limited, the output waveform is dulled, and the output of the FETs Q31 and Q32 of the high voltage output circuit itself is dulled, thereby reducing the load dependency. it can. Thus, when it is desired to make the output waveform dull, each buffer circuit BF1, BF2 is set by setting the output impedance of the buffer circuits BF1, BF2 to be larger than the output impedance of the level shift circuit LSa. The output current characteristic having a dullness can be obtained.

FIG. 13 is a diagram showing a circuit configuration of the address driver IC 21c according to the fourth embodiment to which the present invention is applied. The address driver IC 21c according to the fourth embodiment is changed from the first switching element Q31 of the P-channel FET of the high voltage output circuit HVa of the circuit shown in the third embodiment to the first switching element Q33 of the N-channel FET. Totem pole configuration. The address driver IC 21c according to the fourth embodiment is basically changed in connection with the low-voltage logic circuit LVc due to the change in the polarity of the FET of the first switching element Q33 from the address driver IC 21b according to the third embodiment. Since there is no change in operation, detailed description thereof will be omitted.

FIG. 14 is a diagram illustrating an example of voltage waveforms of the input signals INa-1, INa-2, INb-1, INb-2 of the address driver IC 21c according to the fourth embodiment and the output of the high voltage output terminal OUT. In FIG. 14, the same input signal having a voltage amplitude of 0 to Vcc [V] is inputted to the input signals INa-1 and INb-2, and the voltage amplitude of 0 to Vcc [V] is inputted to the input signals INa-2 and INb-1. The same input signal is input. The output signal is synchronized with the input signals INa-1 and INb-2, and voltage waveforms with voltage amplitudes (+ Va3) to (+ Va1) [V] are output.

In this embodiment, as in the first and second embodiments, only one signal may be input during the address period Ta, but the actual IC configuration that performs high impedance output and operation during power recovery. In the configuration, four different signals can be input. In the present embodiment, INa-1 has the same phase as INb-2, INa-2 and INb-1 have the same phase, and the respective sets are signals having opposite phases.
As described above, the first switching element Q33 of the N-type FET on the high voltage side of the high-voltage output circuit HVc applied in the present embodiment has a smaller cell area than the first switching element Q31 of the P-type FET. Since the on-resistance is low, in addition to the effects described in the first and second embodiments, it is possible to reduce the size of the IC chip and reduce the power consumption of the address driver IC 21c.

As described above, according to the present invention, the common impedances of the high voltage output circuit units HV, HVa, HVc and the low voltage circuit units LV, LVb, LVc are separated by using the level shift circuits LS, LSa. It is possible to realize malfunction prevention due to noise generated due to load fluctuation and the like and to reduce power consumption by reducing the amplitude of the power source.

The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.
In particular, in the first to fourth embodiments, the driver IC of the present invention has been described as an example applied to the

address driver ICs

21 and 21a to 21c of the plasma display panel 10. However, the scan driver IC 41, organic EL, liquid crystal, etc. As long as the driver IC uses the level shift circuits LS and LSa, the present invention can be applied to all driver ICs.

The present invention can be used for a driving circuit of a flat panel display such as a plasma display, particularly a driver IC having a low voltage logic circuit and a high voltage output circuit.

Claims

A drive circuit for a flat panel display that drives an electrode of a flat panel display by outputting an electrode drive signal having a higher voltage than the input data signal from a high voltage output terminal based on an input data signal,
A low voltage logic circuit that receives the input data signal given in time series, processes the input data signal, and outputs in parallel with a predetermined number of bits;
A first switching element connected between a high voltage power supply and the high voltage output terminal; and a second switching element connected between the high voltage output terminal and a power supply current feedback path of the high voltage power supply. A control signal having a voltage level higher than that of the input data signal is input, and the electrode driving signal for driving the electrode of the display is output to the high voltage output terminal, corresponding to the predetermined number of bits. A high voltage output circuit;
The number of sets corresponding to the predetermined number of bits, which is obtained by converting the result of the predetermined number of bits processed by the low voltage logic circuit into a control signal level of the high voltage output circuit and supplying it to the high voltage output circuit A level shift circuit having
A driving circuit for a flat panel display, wherein a power supply current feedback path of the low voltage logic circuit and a power supply current feedback path of the high voltage output circuit are electrically separated.
2. The flat panel display driving circuit according to claim 1, wherein the voltage potential of the power supply current feedback path of the high voltage output circuit is lower than the voltage potential of the power supply current feedback path of the low voltage logic circuit.
3. The flat panel display driving circuit according to claim 2, wherein the first switching element is a P-channel FET, and the second switching element is an N-channel FET.
The level shift circuit includes a first level shift circuit that supplies a control signal to the first switching element, and a second level shift circuit that supplies a control signal to the second switching element,
The control signal level output from the first level shift circuit is set between the potential of the high voltage power supply and the potential of the power supply current feedback path of the low voltage logic circuit,
4. The control signal level output from the second level shift circuit is set between a power supply potential of the low voltage logic circuit and a power supply current feedback path of the high voltage output circuit. A driving circuit for a flat panel display according to 1.
The power supply current feedback path potential of the high voltage output circuit is lower than the power supply potential of the high voltage output circuit and higher than the power supply current feedback path of the low voltage logic circuit. 2. A driving circuit for a flat panel display according to 1.
6. The flat panel display driving circuit according to claim 5, wherein the first switching element is a P-channel FET and the second switching element is an N-channel FET.
6. The flat panel display driving circuit according to claim 5, wherein a diode is inserted between a power supply current feedback path of the high voltage output circuit and a power supply current feedback path of the low voltage logic circuit.
The level shift circuit includes a first level shift circuit that supplies a control signal to the first switching element, and a second level shift circuit that supplies a control signal to the second switching element,
The control signal level output from the first level shift circuit and the control signal level output from the second level shift circuit are respectively the power supply potential of the high voltage output circuit and the power supply current feedback of the low voltage logic circuit. 6. The driving circuit for a flat panel display according to claim 5, wherein the driving circuit is set between potentials of paths.
The control signal level output by the first level shift circuit is set between the power supply potential of the high voltage output circuit and the power supply current feedback path of the low voltage logic circuit,
The control signal level output from the second level shift circuit is set between a potential lower than the power supply potential of the high voltage output circuit and higher than the potential of the power supply for the low voltage logic circuit. The flat panel display driving circuit according to claim 5.
The level shift circuit includes a first level shift circuit that supplies a control signal to the first switching element, and a second level shift circuit that supplies a control signal to the second switching element,
A buffer circuit is connected between the first level shift circuit and the first switching element and / or between the second level shift circuit and the second switching element. Item 2. A driving circuit for a flat panel display according to Item 1.
11. The flat panel display driving circuit according to claim 10, wherein an output impedance of the buffer circuit is set to be higher than an output impedance of the level shift circuit.
The flat panel display device is a plasma display panel;
2. The driving circuit for a flat panel display according to claim 1, wherein the driving circuit for the flat panel display is mounted on an address driver IC for driving an address electrode.