JP4719813B2 - Plasma display device - Google Patents

Description

  The present invention relates to a capacitive load driving circuit and a plasma display device using the same, and more particularly to a circuit technology that can appropriately handle heat generated by driving a capacitive load such as a plasma display panel or an electroluminescence panel. In recent years, plasma display panels (PDP), electroluminescence (EL) panels, and the like have been researched and developed as thin flat display devices. In particular, the PDP is capable of displaying large screens and high speeds, and has improved display quality, and has attracted attention as a display device that replaces the CRT. However, in such a PDP, since display is performed by driving each display cell (and wiring capacitance, etc.), which is a capacitive load, with a high-voltage pulse signal, the size of the power consumption becomes a problem. Yes. Therefore, a circuit for driving a capacitive load (such as a display cell) with low power consumption has been proposed, but there is a problem such as heat radiation from the drive circuit itself. Therefore, it is desired to provide a capacitive load drive circuit that can solve problems such as heat dissipation.

  FIG. 1 is a block diagram schematically showing the overall configuration of the plasma display apparatus. In FIG. 1, reference numeral 101 is a display panel, 102 is an anode (address) drive circuit, 103 is a cathode (Y) drive circuit, 104 is a sub-anode drive circuit, 105 is a control circuit, 106 is an X drive circuit, and 107 Indicates a discharge cell.

  In the following description, an address driving circuit (address drive IC) in a plasma display apparatus will be mainly described. However, the capacitive load driving circuit of the present invention is not only an address driving circuit of a plasma display apparatus, but also an X driving circuit and a Y driving circuit. And a circuit for driving various capacitive loads other than the plasma display device, for example, a logic gate comprising MOS transistors. (The gate of the transistor to be driven is regarded as a capacitance, and a capacitance parasitic to a wiring or the like is added to be considered as a capacitive load) and can be widely applied to circuits and the like.

  FIG. 1 is drawn to show both a direct current (DC) plasma display device and an alternating current (AC) plasma display device. The DC plasma display device includes an anode drive circuit 102 and a cathode drive circuit 103. The AC type plasma display device includes an address driving circuit 102, a Y electrode driving circuit 103, and an X electrode driving circuit 106. Note that the display panel 101 and the control circuit 105 are provided in both an AC type and a DC type.

  That is, the display panel (plasma display panel: PDP) 101 is roughly classified into a DC type and an AC type. In the DC type PDP, the matrix discharge electrode is exposed in each discharge cell 107, and the electric field in the discharge space in the cell. It is easy to control. Further, in the DC type PDP, since the electrode polarities are specified as the anodes A1 to Ad and the cathodes K1 to KL, the discharge light emission state can be easily optimized, and the sub-electrode shared between adjacent anode electrodes can be easily used. By using a technique for causing preliminary discharge using the anode electrodes SA1 to SA (d / 2) or the like, the main discharge for display generated between the anode and the cathode can be reduced in voltage and speed. As described above, the drive unit includes the three types of drive circuits of the anode drive circuit 102, the cathode drive circuit 103, and the sub-anode drive circuit 104, and the control circuit 105 that controls these drive circuits.

  On the other hand, the AC type PDP is characterized in that the matrix discharge electrode is covered and protected by a dielectric, electrode deterioration due to discharge is suppressed, and the life is long. In addition, a simple three-electrode panel structure (three-electrode surface discharge AC type PDP) in which the front plate provided with the X electrodes and Y electrodes in the horizontal line direction and the back plate having the address electrodes in the vertical column direction are simply bonded together. It has been put into practical use, and high definition is easy. As described above, the driving unit simultaneously applies the address driving circuit 102 that selects the light emitting cells in the column direction according to the video data, the Y driving circuit 103 that selectively scans each line, and the sustain pulse for main light emission to all the lines. The X drive circuit 106 includes three types of drive circuits and a control circuit 105 that controls them.

  Here, the drive terminals of each electrode are all insulated from the circuit ground in a direct current manner except for the dummy electrodes at the end of the panel, and capacitive impedance is dominant as the load of the drive circuit. 2. Description of the Related Art Conventionally, as a technique for reducing power consumption of a pulse drive circuit for a capacitive load, a power recovery circuit that applies energy transfer between a load capacitance and an inductance due to a resonance phenomenon is known. Specifically, as a power recovery technique suitable for a drive circuit in which a load capacity for driving individual load electrodes such as an address electrode drive circuit with mutually independent voltages in accordance with a display image changes greatly, Japanese Patent Laid-Open No. 5/1990. A low power drive circuit described in Japanese Patent No. 249916.

  FIG. 2 is a block diagram showing an example of a driving circuit of a conventional plasma display apparatus, and shows a low power driving circuit disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 5-249916. In FIG. 2, reference numeral 110 is a power recovery circuit, 111 is an output terminal of the power recovery circuit, 120 is an address drive circuit (address drive IC), 121 is a power supply terminal of the address drive IC, 122 is an output circuit in the drive IC 120, Reference numeral 123 denotes an output terminal of the address drive IC. Reference sign CL indicates a load capacity including a discharge cell and a wiring capacity.

  The conventional capacitive load driving circuit shown in FIG. 2 suppresses power consumption by driving the power supply terminal 121 of the address drive IC 120 using the power recovery circuit 110 having a resonance inductance. The power recovery circuit 110 outputs a normal constant address drive voltage at a timing at which an address discharge is generated in the address electrode of the plasma display panel, and the power supply terminal before the switching state of the output circuit 122 in the address drive IC is switched. The voltage of 121 is dropped to the ground level. At that time, between the resonance inductance in the power recovery circuit 110 and the combined load capacity (for example, maximum: n × CL) of an arbitrary number (for example, maximum: n) of address electrodes driven to a high level. Resonance occurs in the output circuit, so that power consumption in the output element of the output circuit 122 in the address drive IC is greatly suppressed.

  In the conventional capacitive load driving circuit in which the power supply voltage of the address drive IC is made constant, all the change in the stored energy in the load capacitance CL before and after switching the discharge cell is consumed in the resistive impedance portion in the charge / discharge current path. When the power recovery circuit 110 is used, the potential energy amount stored in the load capacity with the intermediate potential of the address drive voltage serving as the resonance center of the output voltage as a reference is maintained via the resonance inductance in the recovery circuit. Is done. Then, when the power supply voltage is at ground, the switching state of the output circuit 122 is switched, and then the power supply voltage of the address drive IC is raised again to a normal constant drive voltage through resonance, thereby suppressing power consumption. ing.

JP-A-5-249916

The above-described conventional capacitive load driving circuit shown in FIG. 2 uses a resonance phenomenon to recover power. However, the power consumption of the plasma display panel in recent years has increased with higher definition and larger screen. The suppression effect has been greatly impaired. That is, when the output frequency of the drive circuit is increased in order to increase the definition of the panel, it is necessary to reduce the above resonance time in order to maintain the control performance of the panel. At that time, the value of the resonance inductance provided in the power recovery circuit 110 must be reduced, and the power suppression effect decreases as the resonance Q decreases. In addition, the parasitic capacitance of the address electrode also increases with the increase in the screen size of the panel, and in order to suppress the increase in resonance time, it is necessary to reduce the value of the inductance for resonance. The effect will decrease.
If the power consumption of the drive circuit cannot be suppressed sufficiently, the heat dissipation cost and component cost of each part of the display will increase, and furthermore, the light emission luminance will be suppressed due to the heat dissipation limit of the display device itself, and it is a characteristic of flat panel displays This also means that the thin and light weight cannot be fully exhibited. Further, as the output frequency of the drive circuit increases, the power consumption due to the high voltage pulse for driving the plasma display panel increases, and heat generation in the drive circuit (drive IC) has become a serious problem.

  An object of the present invention is to provide a capacitive load driving circuit capable of distributing heat generation (power consumption) in a circuit that drives a capacitive load, and a method using the same, in view of the problems of the conventional capacitive load driving circuit described above. It is to provide a plasma display device.

  According to the present invention, in a capacitive load driving circuit including a configuration in which a driving power source or a reference potential point is connected to an output terminal via a driving element, power distribution means is provided between the driving power source or the reference potential point and the driving element. The power consumption is distributed by this power distribution means.

  Furthermore, according to the present invention, in a capacitive load driving circuit including a configuration in which a plurality of driving elements corresponding to a plurality of capacitive loads are integrated, each driving element is connected to a driving power source or a reference via a power distribution unit. It is connected to a potential point, and power consumption is distributed by each power distribution means. FIG. 3 is a block diagram for explaining the principle configuration of the capacitive load driving circuit according to the present invention. In FIG. 3, reference numeral 1 is a drive power source, 2 is a power distribution means, 3 is a capacitive load drive circuit (address drive IC), 4 is a reference potential point (grounding point), 5 is a capacitive load (load capacitance), Reference numerals 6 and 7 denote drive elements, 8 and 9 denote power supply terminals and ground terminals (reference potential terminals) of the address drive IC, and 10 denotes a terminal of the address drive IC.

  As shown in FIG. 3, the drive current that flows when driving the load capacitor 5 flows from the drive power supply 1 to the load capacitor 5 via the power distribution means 2 and the drive element 6. At this time, the consumed power is distributed according to the ratio of the resistive impedance of the power distribution means 2 and the drive element 6. This power reduction effect is impaired even when the value of the load capacity 5 or the driving speed (driving frequency) increases, unlike the case of using the power recovery method based on the resonance phenomenon described with reference to FIG. There is no.

  Thus, according to the present invention, the power consumed by the address drive IC (capacitive load drive circuit) 3 can be reduced. That is, the power consumption as a whole is the same, but in the prior art, a part of the power consumed in the address drive IC 3 is consumed by the power distribution means 2, whereby the heat dissipation structure of the address drive IC 3 can be simplified. The circuit cost can be reduced.

  Here, many flat panel display devices, especially plasma display devices with high driving voltage, large screen and high definition, use a large number of display panel driving circuits with large load capacity and high driving speed. Therefore, by applying the capacitive load driving circuit according to the present invention, the heat radiation cost can be greatly reduced, and the high voltage LSI can be mounted in an extremely small space.

  The application of the capacitive load driving circuit according to the present invention can exert a great effect on a plasma display device that drives a large number of capacitive loads (discharge cells or the like) with high voltage pulses. The present invention is not limited to display devices, and can be widely applied to circuits that drive various capacitive loads.

  As described above in detail, according to the present invention, a capacitive load driving circuit capable of distributing heat generation (power consumption) in a circuit driving a capacitive load and a plasma display device using the same are provided. Can do.

It is a block diagram which shows roughly the whole structure of a plasma display apparatus. It is a block diagram which shows an example of the drive circuit of the conventional plasma display apparatus. It is a block diagram for demonstrating the principle structure of the capacitive load drive circuit which concerns on this invention. 1 is a block diagram showing a first embodiment of a capacitive load driving circuit according to the present invention. FIG. It is a block diagram which shows 2nd Example of the capacitive load drive circuit based on this invention. FIG. 6 is a circuit diagram showing an example of a constant current source in the capacitive load driving circuit shown in FIG. 5. It is a block diagram which shows 3rd Example of the capacitive load drive circuit based on this invention. It is a figure for demonstrating operation | movement of the drive power supply in 3rd Example shown in FIG. It is a block diagram which shows the 4th Example of the capacitive load drive circuit based on this invention. It is a block diagram which shows 5th Example of the capacitive load drive circuit based on this invention. It is a block diagram which shows 6th Example of the capacitive load drive circuit based on this invention. It is a block diagram which shows 7th Example of the capacitive load drive circuit based on this invention. It is a block diagram which shows 8th Example of the capacitive load drive circuit based on this invention. It is a circuit diagram of a totem pole type address drive IC as a ninth embodiment of the capacitive load driving circuit according to the present invention. It is a circuit diagram of a CMOS type address drive IC as a tenth embodiment of the capacitive load driving circuit according to the present invention. It is a block circuit diagram which shows the 11th Example of the capacitive load drive circuit based on this invention. It is a block circuit diagram which shows an example of the integrated circuit which comprises the drive module as a 12th Example of the capacitive load drive circuit based on this invention. It is a block circuit diagram which shows the other example of the integrated circuit which comprises the drive module as 13th Example of the capacitive load drive circuit based on this invention. It is a block circuit diagram which shows the further another example of the integrated circuit which comprises the drive module as 14th Example of the capacitive load drive circuit based on this invention. It is a block diagram which shows roughly a 3 electrode surface discharge alternating current drive type plasma display panel. It is sectional drawing for demonstrating the electrode structure of the plasma display panel shown in FIG. It is a block diagram which shows the whole structure of the plasma display apparatus using the plasma display panel shown in FIG. It is a figure which shows an example of the drive waveform of the plasma display apparatus shown in FIG. It is a block circuit diagram which shows an example of IC used for the plasma display apparatus shown in FIG. It is a block diagram which shows 15th Example of the capacitive load drive circuit based on this invention. It is a block diagram which shows the 16th Example of the capacitive load drive circuit based on this invention. It is a circuit diagram of a CMOS type address drive IC as a seventeenth embodiment of a capacitive load driving circuit according to the present invention. It is a figure which shows the cross section of the address electrode in the plasma display panel to which the capacitive load drive circuit which concerns on this invention is applied. It is a block diagram which shows the 18th Example of the capacitive load drive circuit based on this invention.

  Hereinafter, embodiments of a capacitive load driving circuit and a plasma display device according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 4 is a block diagram showing a first embodiment of the capacitive load driving circuit according to the present invention. In FIG. 4, reference numeral 1 is a drive power source, 21 is a power distribution means, 3 is an address drive IC, 4 is a reference potential point (ground point), 5 is a load capacity, 6 and 7 are drive elements, and 8 and 9 are addresses. A power supply terminal and a reference potential terminal (ground terminal) of the drive IC, and 10 indicates an output terminal of the address drive IC.

  As shown in FIG. 4, in the first embodiment, the power distribution means 21 is provided between the drive power supply 1 and the high potential power supply terminal 8 of the address drive IC 3, and the power distribution means 6 is configured as a resistive impedance (resistive element) 21 higher than about 1/10 of the resistive impedance during conduction (resistance component of the impedance during conduction). According to the first embodiment, about 1/10 or more of the power consumption of the drive element 6 during load driving can be distributed to the resistance element 21 to suppress the power consumption of the drive circuit 3.

  Here, the impedance of the resistance element (power distribution means) 21 is set to a value higher than about 1/10 of the resistive impedance during conduction of the drive element 6. This is because it is considered that the power distributed is too small to obtain a substantial power distribution effect. As for the upper limit of the impedance of the resistance element 21, if the value is increased too much, the effect of power dispersion increases, but the drive waveform becomes dull. Therefore, depending on the individual system (display device or the like) to which the drive circuit is applied. The appropriate range will be determined. Therefore, it is preferable to use a high power resistor that can ensure reliability at low cost so that the resistance element 21 has a resistance value as large as possible and the power consumption can be larger than the power consumption of the driving element.

  FIG. 5 is a block diagram showing a second embodiment of the capacitive load driving circuit according to the present invention. As shown in FIG. 5, in the second embodiment, the power dissipation means in the first embodiment described above is configured as a constant current source 22. Since the driving circuit of the second embodiment can minimize the effective current value flowing through the driving element 6 under the same driving conditions, the power consumption of the driving circuit 3 is set to the lowest value in principle. Is possible.

  6 is a circuit diagram showing an example of a constant current source in the capacitive load driving circuit shown in FIG. As shown in FIG. 6, the constant current source 22 is configured such that, for example, a gate-source voltage of an n-channel MOS transistor (nMOS transistor) 221 is biased to a constant voltage by a Zener diode 222. A resistor 225 may be connected in series to the source of the transistor 221 as illustrated in order to compensate for current accuracy deterioration due to element variations of the transistor 221. A resistor 223 is connected between the gate and drain of the transistor 221 to bias the Zener diode 222. In this embodiment, the constant current source 22 (transistor 221) dissipates (consumes) power and generates heat. For example, the constant current source 22 is integrated into an IC and attached to a heat sink, or A discrete transistor 221 is used by being attached to a heat sink or the like. The constant current source 22 can also be constituted by one MOS transistor having a gate and a source connected.

  Here, for example, when power is supplied to a plurality of drive circuits 3 (drive elements 6) via a plurality of constant current sources 22 using one drive power supply 1 in FIG. In order to avoid interference between the diodes, a diode 224 may be inserted in series with each constant current source 22. Further, as will be described later, when switching the voltage of the drive power source 1, the constant current source circuit 22 having the diode 224 inserted in series is connected in parallel so that current flows in opposite directions to constitute a current distribution means. You can also

  FIG. 7 is a block diagram showing a third embodiment of the capacitive load driving circuit according to the present invention, and FIG. 8 is a diagram for explaining the operation of the drive power supply in the third embodiment shown in FIG. The third embodiment is characterized by the configuration of the drive power supply 1, and other configurations (the address drive IC 3 and the power distribution means 2) are the same as those of the drive circuit of FIG.

  As shown in FIG. 7, the drive power supply 1 is configured to include voltage sources 10 and 11 and switches 12 to 14, and power distribution is performed by selecting (turning on) one of the switches 12 to 14. The voltage applied to the power supply terminal 8 of the address drive IC 3 is switched via the means 2. The drive power supply 1 outputs a high-potential power supply voltage V2 when the switch 12 is turned on, outputs an intermediate voltage V1 when the switch 13 is turned on, and outputs a ground potential V0 when the switch 14 is turned on. Yes. As shown in FIG. 8, the drive power supply 1 maintains the on / off state of the drive element 6, and uses the output voltage VD as the voltage amplitude of the drive voltage VC that drives the capacitive load (CL) 5. The voltage increases and decreases in stages while switching to a plurality of voltages (V0, V1, V2). As a result, the amplitude of the drive current is reduced to reduce its effective value, and the power consumption of the entire drive circuit system including the drive power supply 1 can be reduced. In the drive power supply 1, the voltage switched by the switch is not limited to the high potential power supply voltage V2, the low potential power supply voltage V0, and the intermediate potential power supply voltage V1, but for example, the high potential power supply voltage V2 and the low potential power supply voltage V0 may be equally divided into M, and the output voltage VD may be controlled by M + 1 switches corresponding thereto. In this case, the power consumption of the entire drive circuit system can be reduced to 1 / M. Further, by using a bidirectional element such as a MOSFET with a diode parasitic between the output terminals as the drive element 6, all power consumption associated with charging and discharging of the load capacitor 5 can be distributed to the power distribution means 2. It becomes like this. In this case, power consumption in the drive element 7 can be ignored.

  FIG. 9 is a block diagram showing a fourth embodiment of the capacitive load driving circuit according to the present invention. In the fourth embodiment, nMOS transistors 121; 131, 132; 141 whose gate voltages are controlled by the drive power supply control circuit 15 are used as the switches 12; 13; 14 of the drive power supply circuit 1 of FIG. As in the second embodiment shown in FIG. 5, the function of the power distribution means by the constant current source is also used. In the fourth embodiment, diodes 130 and 1301 are provided in series with the drains of the transistors 131 and 132, but these diodes may be inserted in series with the sources of the transistors 131 and 132. In FIG. 9, an nMOS transistor is used as a switch of the drive power supply circuit 1. However, it goes without saying that an active element such as a pMOS transistor or a bipolar transistor can also be applied.

  Thus, in the fourth embodiment, an nMOS transistor (active element) is applied as a switch (voltage switching means) of the drive power supply circuit 1, and the control terminal (gate) of the active element is controlled at a constant voltage or a constant current. As a result, the output characteristics are made constant. As a result, the power consumption of the entire drive system including the drive circuit 3 can be sufficiently reduced, and the number of elements used can be reduced.

  FIG. 10 is a block diagram showing a fifth embodiment of the capacitive load driving circuit according to the present invention. As shown in FIG. 10, in the fifth embodiment, the power distribution means 23 is provided between the low potential power supply terminal 9 of the address drive IC (drive circuit) 3 and the reference potential point (grounding point) 4. Yes.

  As described above, even when the voltage of the load capacitor 5 is driven to the potential of the reference potential point (for example, the ground point) 4, the power distribution means 23 is provided to the drive element 7 between the load capacitor 5 and the reference potential point 4. By inserting in series, the power consumption in the drive element 7 can be reduced and distributed to the power distribution means 23. That is, by consuming part of the power consumed in the address drive IC (capacitive load drive circuit) 3 by the power distribution means 23, the heat dissipation structure of the drive circuit 3 can be simplified and the circuit cost can be reduced. .

  FIG. 11 is a block diagram showing a sixth embodiment of the capacitive load driving circuit according to the present invention. In the sixth embodiment, as in the first embodiment described above, the power distribution means 23 in the fifth embodiment is configured as a resistance element (resistive impedance) 24. Here, the impedance of the resistance element 24 is set to a value higher than about 1/10 of the resistive impedance when the drive element 7 has conduction, and thus, approximately 1 / of the power consumption of the drive element 7 during load driving. The power consumption of the drive circuit 3 is suppressed by dispersing 10 or more in the resistance element 24.

  FIG. 12 is a block diagram showing a seventh embodiment of the capacitive load driving circuit according to the present invention. In the seventh embodiment, as in the second embodiment described above, the power distribution means 23 in the fifth embodiment is configured as a constant current source 25. In this way, by configuring the power distribution means with the constant current source 25, the effective current value flowing through the drive element 7 can be minimized under the same drive condition, so any other drive via the drive element. In principle, the lowest power consumption can be achieved for the method.

  FIG. 13 is a block diagram showing an eighth embodiment of the capacitive load driving circuit according to the present invention. In the eighth embodiment, the first power distribution means 26 is provided between the drive power supply 1 and the high potential power supply terminal 8 of the drive circuit 3, and the second power distribution means 27 is provided with the reference potential point and the drive circuit 3. In addition, diodes 60 and 70 are inserted between the drive element 6 and the drive terminal 10 and between the drive terminal 10 and the drive element 7.

  When driving a plurality of load capacitors CL (5) using the drive circuit 3 (when integrated), the drive circuit 3 is inserted by inserting a series diode 60 or 70 into at least one of the drive elements 6 and 7. The power consumption in can be sufficiently reduced. That is, by eliminating unnecessary output voltage changes with the series diode 60 or 70, an extra drive current to the load capacity due to interference between the outputs via the common potential wiring or the reference potential wiring connected to the grounding point, etc. And the power consumption in the drive circuit 3 can be reduced. In addition, since unnecessary driving voltage is not applied to the driving device in the plasma display apparatus, the display image quality is improved and the driving voltage margin can be suppressed to reduce the driving voltage.

  In the case where a plurality of load capacitors are driven using the drive circuit 3 and the resistive impedance (resistive element) is used as the power distribution means 26, 27, the value of the resistive impedance during conduction of the drive elements 6, 7 is used. Of the output elements N (for example, address lines A1 to Ad: d = N) is provided with a resistive impedance that is higher than about 1/10, thereby consuming the drive elements 6 and 7 during load driving. About 1/10 or more of the power can be distributed to the resistance elements, and the power consumption of the drive circuit 3 can be suppressed.

  Here, when the drive circuit 3 is applied as an address drive circuit (see 102 in FIG. 1) in the plasma display device, for example, a configuration is made such that one drive circuit (address drive IC) 3 drives 384 lines (N = In this case, if the on-resistance of the driving element 6 (7) is 200Ω, the impedance of the power distribution means 26 (27) is more than about 1/10 of 200 ÷ 384≈0.5 [Ω]. A large value, that is, a value of about 0.05Ω or more is set. As a result, about 1/10 or more of the power originally consumed by the address drive IC 3 is distributed to the power distribution means 26 (27), so that heat generation in the address drive IC 3 is reduced.

  FIG. 14 is a circuit diagram of a totem pole type address drive IC as a ninth embodiment of the capacitive load driving circuit according to the present invention. As shown in FIG. 14, the ninth embodiment is, for example, an address drive IC 3 for driving d address electrodes (A1 to Ad) in a plasma display device, and includes a drive element 6 on the pull-up side. 1 to 6-d and the pull-down drive elements 7-1 to 7-d are both configured as a totem pole type using nMOS transistors. The pull-up side and pull-down side drive elements are driven by drive stages 60 and 70, respectively.

  Thus, by configuring the drive circuit 3 as a totem pole type, it is possible to configure the drive circuit (IC) at low cost by reducing the chip area by using only nMOS transistors having higher current capability than pMOS transistors. . FIG. 15 is a circuit diagram of a CMOS address drive IC as a tenth embodiment of the capacitive load driving circuit according to the present invention.

  As shown in FIG. 15, the tenth embodiment is, for example, an address drive IC 3 for driving d address lines (A1 to Ad) in a plasma display device, and a pull-up side drive element 60- 1 to 60-d are pMOS transistors, and pull-down drive elements 70-1 to 70-d are nMOS transistors. Note that the pull-up side and pull-down side drive elements are driven by drive stages 600 and 700, respectively.

  Thus, by configuring the drive circuit 3 as a CMOS type, the drive power of the drive element on the pull-up side can be reduced, and the rise and fall of the drive voltage can be speeded up with good symmetry. FIG. 16 is a block circuit diagram showing an eleventh embodiment of the capacitive load driving circuit according to the present invention.

  In the eleventh embodiment, as in the eighth embodiment, a plurality of load capacitors 5 are driven by a single drive circuit (drive IC), and a drive circuit is inexpensively manufactured using a general drive integrated circuit. The dedicated drive module 36 (drive circuit 3) that drives a multi-terminal capacitive load such as a plasma display panel includes three integrated circuits (drive integrated circuits) 37, 38, and 39. Configured. Here, each of the integrated circuits 37, 38, and 39 has the same configuration and is a totem pole type as shown in FIG. 14, but may be a CMOS type. As is apparent from FIG. 16, each integrated circuit 37, 38, 39 directly receives the output voltage of the drive power supply 1 at each power supply terminal 84, 85, 86 of the pre-output circuit in the IC, and the power distribution means 26. Are received by each power supply terminal 81, 82, 83 (8) of the high-voltage output element. Similarly, each integrated circuit 37, 38, 39 receives the voltage at the reference potential point 4 directly at each power supply terminal 94, 95, 96 and also through each power supply terminal 91, 92, 93 (9 ). However, each power supply terminal 84, 85, 86 may be deleted in common with the power supply terminals 81, 82, 83 of the high-voltage output element, as will be described later with reference to FIG.

  As described above, in the eleventh embodiment, by connecting the power supply terminal 8 of the drive module 36 to the drive power supply 1 through the power distribution means 26, the consumption of the drive elements 6-1 to 6-d in the module is increased. By distributing the power to the power distribution means 26 outside the module and connecting the power supply terminal 9 of the drive module 36 to the reference potential point 4 via the power distribution means 27, the drive elements 7-1 to 7-7 in the module are connected. The power consumption such as −d is distributed to the power distribution means 27 outside the module. As a result, it is possible to improve reliability by suppressing heat generation from the drive module 36 and to provide an inexpensive drive module (capacitive load drive circuit) with reduced heat dissipation cost.

  Here, the power supply terminals 84, 85, 86 of the integrated circuits 36, 37, 38 are connected to the output of the drive power supply 1, and the power supply terminals 94, 95, 96 are connected to the reference potential point 4. The high-voltage output elements 6-1 to 6-d in the integrated circuits 36, 37, and 38 are controlled at high speed, and the ground terminals for low-voltage circuits such as logic circuits in the integrated circuits 36, 37, and 38 are directly connected to the reference potential. This is because by connecting to the point (grounding terminal) 4, signal voltages supplied to a large number of logic signal input terminals can be stably applied with reference to the ground.

  FIG. 17 is a block circuit diagram showing an example of an integrated circuit constituting a drive module as a twelfth embodiment of the capacitive load drive circuit according to the present invention. As shown in FIG. 17, the twelfth embodiment is an example of the integrated circuit 37 (38, 39) in the drive module 36 (3) shown in FIG. As described above, the integrated circuit 37 can be configured as a totem pole type composed of nMOS transistors, but in this twelfth embodiment, the gate thickness of the output elements 620 and 720 constituting the CMOS type output circuit is increased. By doing so, the input withstand voltage is increased to the drive power supply voltage value. These high-voltage (high withstand voltage) output elements 620 and 720 have their control inputs (gates) controlled by a preceding flip-flop circuit composed of transistors 621 to 624 and transistors 721 to 724, and either drive power supply voltage or reference voltage Driven at any full swing level of (ground voltage). Thereby, even when the potentials of the high potential power supply terminal 81 and the high potential element reference potential terminal (ground terminal) 91 are greatly changed in order to increase the power distribution effect by the power distribution means 26 and 27, the high voltage output can be stably performed. Elements 620 and 720 can be controlled.

  Note that transistors 620, 621, and 622 and 721 and 722 in FIG. 17 are driven at a full swing level, and thus elements with high input withstand voltage are used. Further, without providing the power supply terminal 84 for the circuit before the drive circuit in the previous stage of the high voltage output elements 620 and 720, the power supply line of the previous circuit is shared with the high voltage output element as shown by the broken line in FIG. The number of terminals of the circuit 37 may be reduced. When a driving mode for turning off both the output elements 620 and 720 is not necessary, the flip-flop circuit including the transistors 721 to 724 in the previous stage can be omitted. In that case, the control input terminal (gate) of the output element 720 may be disconnected from the drain terminal of the transistor 723 and connected to the drain terminal of the transistor 623 as indicated by a dashed line in the drawing.

  FIG. 18 is a block circuit diagram showing another example of the integrated circuit constituting the drive module as the thirteenth embodiment of the capacitive load drive circuit according to the present invention. In the integrated circuit 37 of the thirteenth embodiment, an inexpensive element (transistor) having a low input withstand voltage that can be sufficiently controlled by the logic power supply 75 is used as the high-voltage output elements 71-1 to 71-d. . That is, the integrated circuit 37 includes a logic power supply terminal 97 that receives a logic power supply 75 and a ground terminal 94, and an nMOS transistor 71-is generated by a logic voltage output of the buffers 72-1 to 72-d and a voltage drop generated in the power distribution means 27. 1 to 71-d is self-biased. Needless to say, the transistors 61-1 to 61-d are not limited to nMOS transistors but may be pMOS transistors or bipolar transistors.

  FIG. 19 is a block circuit diagram showing still another example of the integrated circuit constituting the drive module as the fourteenth embodiment of the capacitive load drive circuit according to the present invention. The integrated circuit 37 according to the fourteenth embodiment is different from the integrated circuit 37 according to the eleventh embodiment shown in FIG. 16 in that a switch element 451 is provided at least between the driving power source 1 and the power distribution means 26 or a reference potential is provided. A switch element 481 is provided between the point 4 and the power distribution means 27 to further increase the power distribution efficiency and reduce the power consumption of the drive element. That is, the switching elements 451 and 481 are turned on after the driving elements 6-1 to 6-d and 7-1 to 7-d are completely switched to the conductive state, thereby lowering the impedance at the start of the conduction of the driving elements. It is intended to avoid deterioration of the power distribution effect in the state where it is not. Further, in the fourteenth embodiment, power can be effectively distributed not only in the power distribution means 26 and 27 but also in the switch elements 451 and 481.

  As described above, according to each embodiment of the present invention, the capacitive load driving circuit, in particular, plasma, in which the power consumption due to the capacitive component of the load is distributed to the power distribution means to reduce the power consumption in the driving circuit itself. A drive circuit for a display device can be provided. As a result, for example, a plasma display device having a large load capacity of a 40-type class or higher, SVGA (800 × 600 dots), XGA (1024 × 768 dots), SXGA (1280 × 1024) having a high driving pulse rate. Thus, the problem of heat dissipation in the high-resolution plasma display device or the high-luminance and high-gradation plasma display device such as TV / HDTV can be alleviated, and miniaturization and low power consumption can be promoted. In addition, an increase in power consumption due to an increase in the drive pulse rate associated with false contour countermeasures during moving image display is also suppressed.

  20 is a block diagram schematically showing a three-electrode surface discharge AC drive type plasma display panel, and FIG. 21 is a sectional view for explaining an electrode structure of the plasma display panel shown in FIG. 20 and 21, reference numeral 207 is a discharge cell (display cell), 210 is a rear glass substrate, 211 and 221 are dielectric layers, 212 is a phosphor, 213 is a barrier rib, and 214 is an address electrode (A1 to Ad). 220 denotes a front glass substrate, and 222 denotes an X electrode (X1 to XL) or a Y electrode (Y1 to YL). Reference symbol Ca indicates the capacitance between adjacent electrodes in the address electrode, and Cg indicates the capacitance between the counter electrodes (X electrode and Y electrode) in the address electrode.

  The plasma display panel 201 includes two glass substrates, a rear glass substrate 210 and a front glass substrate 220. The front glass substrate 220 has X electrodes (X1, X1, X2) each composed of a sustain electrode BUS electrode and a transparent electrode. X2,... XL) and Y electrodes (scanning electrodes: Y1, Y2,... YL) are arranged. On the rear glass substrate 210, address electrodes (A1, A2,..., Ad) 214 are arranged so as to be orthogonal to sustain electrodes (X electrode and Y electrode) 222, and a display cell that generates discharge light emission by these electrodes. 207 is formed between the sustain electrodes having the same number (Y1-X1, Y2-X2,...) And intersecting the address electrodes.

  FIG. 22 is a block diagram showing an overall configuration of a plasma display device using the plasma display panel shown in FIG. 20, and shows a main part of a drive circuit for the display panel. As shown in FIG. 22, the three-electrode surface discharge AC drive type plasma display device includes a display panel 201 and a control circuit for forming a control signal for controlling a display panel drive circuit by an interface signal input from the outside. 205, an X common driver (X electrode drive circuit) 206 for driving the panel electrode by a control signal from the control circuit 205, a scan electrode drive circuit (scan driver) 203 and a Y common driver 204, and address electrode drive And a circuit (address driver) 202.

  The X common driver 206 generates a sustain voltage pulse, the Y common driver 204 also generates a sustain voltage pulse, and the scan driver 203 drives each scan electrode (Y1 to YL) independently for scanning. The address driver 202 applies an address voltage pulse corresponding to display data to each address electrode (A1 to Ad).

  The control circuit 205 receives the clock CLK and the display data DATA and receives the display data control unit 251 for supplying an address control signal to the address driver 202, and receives the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync and controls the scanning driver. A scan driver control unit 253 and a common driver control unit 254 that controls the common drivers (X common driver 206 and Y common driver 204) are provided. The display data control unit 251 includes a frame memory 252.

  FIG. 23 is a diagram showing an example of drive waveforms of the plasma display device shown in FIG. 22, which mainly includes a full write period (full W), a full erase period (full E), an address period (ADD), and a sustain period (sustain discharge). The outline of the voltage waveform applied to each electrode in the period (SUS) is shown. In FIG. 23, the driving period directly related to the image display is an address period ADD and a sustain period SUS, and a pixel to be displayed in the address period ADD is selected, and the selected pixel is caused to sustain light emission in the next sustain period. An image is displayed with a predetermined brightness. FIG. 23 shows drive waveforms in each subframe when one frame is composed of a plurality of subframes (subfields).

  First, in the address period, -Vmy that is an intermediate potential is applied to the Y electrodes (Y1 to YL) that are scan electrodes all at once, and then a scan voltage pulse of -Vy level is sequentially switched and applied. At this time, pixel selection on each scan line is performed by applying an address voltage pulse of + Va level to each address electrode (A1 to Ad) in synchronization with the application of the scan pulse to each Y electrode.

  In the next sustain period, a sustain voltage pulse having a common + Vs level is alternately applied to all the scan electrodes (Y1 to YL) and the X electrodes (X1 to XL), so that the previously selected pixel is applied. On the other hand, sustain light emission is generated, and display with a predetermined luminance is performed by this continuous application. Further, by controlling the number of times of light emission by combining the basic operations of such a series of drive waveforms, it becomes possible to perform grayscale display.

  Here, the entire writing period is for applying a writing voltage pulse to all the display cells of the panel to activate each display cell and keep the display characteristics uniform, and is inserted at a certain period. Is done. Also, during the entire erasure period, before the address operation and the sustain operation for displaying an image are newly started, the previous display contents are erased by applying an erasure voltage pulse to all the display cells of the panel. Is for.

  24 is a block circuit diagram showing an example of an IC used in the plasma display device shown in FIG. For example, when the number of address electrodes (A1 to Ad) of the display panel is 2560, the drive ICs connected to the address electrodes are usually 64-bit outputs, so a total of 40 drive ICs are used. Generally, the 40 drive ICs are mounted in a plurality of modules, and each module has a plurality of ICs.

  FIG. 24 shows an internal circuit configuration of a drive IC chip provided with an output circuit (234: OUT1 to OUT64) for 64 bits. Each output circuit 234 is configured by connecting a high-voltage power supply wiring VH and a ground wiring GND with push-pull FETs 2341 and 2342 in the final output stage interposed therebetween. The drive IC further includes a logic circuit 233 for controlling both FETs, a shift register circuit 231 for selecting a 64-bit output circuit, and a latch circuit 232.

  These control signals include a clock signal CLOCK of the shift register 231, data signals DATA1 to DATA4, a latch signal LATCH of the latch circuit 232, and a strobe signal STB for gate circuit control. In FIG. 24, the final output stage has a CMOS configuration (2341, 2342), but a totem pole configuration composed of MOSFETs having the same polarity can also be applied.

  Next, an example of a mounting method for the drive IC chip will be described. For example, a drive IC chip is mounted on a rigid printed circuit board, and the power supply, signal and output pad terminals of the drive IC chip and corresponding terminals on the printed circuit board are connected by wire bonding. The output wiring from the IC chip is drawn out to the end face side of the printed circuit board to provide an output terminal, and is connected to a flexible substrate provided with the same terminal by thermocompression bonding to form one module. A terminal for connecting to the panel display electrode is provided at the tip of the flexible substrate, and the terminal is connected to the panel display electrode by a technique such as thermocompression bonding.

  The drive terminals of the above electrodes are all insulated from the circuit ground in a direct current manner except for the dummy electrodes at the end of the panel, and capacitive impedance is dominant as the load of the drive circuit. As a technique for reducing power consumption of a pulse drive circuit of a capacitive load, a power recovery circuit that applies energy transfer between a load capacitance and an inductance due to a resonance phenomenon is known. As an example of a power recovery technique suitable for a drive circuit in which a load capacity for driving individual load electrodes with mutually independent voltages according to a display image, such as an address electrode drive circuit, varies greatly. And a low-power driving circuit described in Japanese Patent Laid-Open No. 5-249916 described with reference to FIG.

  FIG. 25 is a block diagram showing a fifteenth embodiment of the capacitive load driving circuit according to the present invention. In FIG. 25, reference numeral 1 is a drive power supply, 51 is a resistive impedance (distributed resistance), 3 is an address drive IC, 4 is a reference potential point (grounding point), 5 is a load capacitance, 6 and 7 are drive elements, 8 Reference numerals 9 and 9 denote a power supply terminal and a reference potential terminal (ground terminal) of the address drive IC, and 10 denotes an output terminal of the address drive IC. Reference numeral RL indicates a resistance value between both ends of the distributed resistor 51, and Ra indicates an effective electrode resistance value of the distributed resistor 51.

  As shown in FIG. 25, the capacitive load driving circuit of the fifteenth embodiment is provided with a distributed resistance (resistive impedance) 51 at the output terminal 10. By the way, in the driving electrode of the plasma display panel (PDP), the load has a structure in which the parasitic capacitance and the parasitic resistance are not concentrated, and the load capacitance 5 having the capacitance value CL is driven in the direction of increasing the voltage. The current that flows sometimes flows from the drive power supply 1 to the distributed resistor 51 that shows a resistance value Ra through the drive element 6 of the drive circuit 3. Further, the current that flows when driving the voltage of the load capacitor 5 in the falling direction flows into the reference potential point 4 via the drive element 7. That is, in any case, the drive current always flows through the distributed resistor 51 and through the impedance when the drive element 6 or 7 is conductive. In the capacitive load driving circuit of the fifteenth embodiment, the electrode resistance value Ra of the distributed resistor 51 is effectively 1/10 or more of the resistance component of the impedance during conduction of at least one of the driving elements 6 or 7 and cannot be ignored. The resistance value is selected. Here, assuming that the resistance value between both ends of the distributed resistor 51 is RL, and the current leaks evenly from the output terminal 10 side of the drive circuit 3 to the parasitic capacitance and becomes zero at the electrode tip, the effective electrode resistance value Ra Becomes １ ／ of the resistance value RL between both ends.

  The current that flows when driving the voltage of the load capacitor 5 in the rising direction flows from the drive power supply 1 in which the load is distributed to the load capacitor 5 through the drive element 6 and the distributed resistor 51. At this time, power consumption is distributed according to the ratio of the effective electrode resistance value Ra and the resistive impedance of the driving element 6. Similarly, when driving in the direction in which the voltage of the load capacitor 5 falls, similarly, the power consumption is distributed according to the ratio between the effective electrode resistance value Ra and the resistive impedance of the driving element 7. Here, if it is possible to insert a resistance member in series with respect to the drive current path flowing in the capacitance portion (5), the resistance member is inserted between the capacitance portion and the output terminal 10 of the drive circuit 3. Of course, it can also be connected to the output terminal 10 of the drive circuit via the capacitance portion.

  The power reduction effect in the drive circuit 3 described above is not impaired even when the load capacity 5 or the drive speed is increased, unlike the case where the conventional power recovery method based on the resonance phenomenon is applied. Thus, the capacitive load drive circuit of the fifteenth embodiment can reduce the power consumed by the drive circuit (drive IC) 3, and as a result, the heat dissipation structure of the drive circuit 3 can be simplified and the circuit can be reduced. It becomes possible to hold down the cost.

  Here, in a flat panel display device, particularly a plasma display device with a large screen and high definition and a high driving voltage, a large number of display panel driving circuits having a large load capacity and driving speed must be used. By applying the fifteenth embodiment, the drive circuit and its heat dissipation cost can be greatly reduced. That is, in the plasma display device, since the high-voltage LSI is mounted in a very small space, the display panel driving circuit and the cost rate required for heat dissipation are high in the display device. By distributing the power consumption (heat generation) in the drive circuit, the drive circuit and its heat dissipation cost can be greatly reduced. The effect of reducing power in the drive circuit can be similarly obtained when the drive circuit 3 is configured as an integrated circuit that drives a plurality of load capacitors.

  FIG. 26 is a block diagram showing a sixteenth embodiment of the capacitive load driving circuit according to the present invention. In FIG. 26, reference numeral 50 indicates an inductive load. As is clear from a comparison between FIG. 25 and FIG. 26, the sixteenth embodiment is such that the capacitive load 5 in the fifteenth embodiment shown in FIG. That is, the provision of the resistive impedance 51 for the output terminal 10 of the drive circuit 3 is applicable not only to the drive circuit that drives the capacitive load 5 but also to the drive circuit that drives the inductance load 50. Is possible. Here, examples of the inductive load 50 include a deflection coil that deflects an electron beam of a cathode ray tube used for a television or an oscilloscope, and a coil that is used for a speaker, a motor, or an actuator. Also when driving these inductive loads, the winding resistance value of the coil is increased or a series resistor is inserted to effectively reduce 1 / of the impedance during conduction of at least one of the drive elements 6 or 7. By inserting the resistor 51 having a resistance value of 10 or more in series, the power consumption (heat generation) of the drive circuit 3 can be reduced by power distribution.

  FIG. 27 is a circuit diagram of a CMOS type address drive IC as a seventeenth embodiment of a capacitive load driving circuit according to the present invention. Here, the drive circuit (address drive IC) 3 in the capacitive load drive circuit of the 17th embodiment is the same as the drive circuit shown in FIG. As shown in FIG. 27, in the seventeenth embodiment, the present invention is applied to, for example, an address drive IC 3 for driving d address lines (A1 to Ad) in a plasma display device. The IC itself has the same configuration as that shown in FIG. That is, the drive IC 3 is a CMOS type in which the pull-up side drive elements 60-1 to 60-d are pMOS transistors and the pull-down side drive elements 70-1 to 70-d are nMOS transistors. The drive elements on the side and the pull-down side are driven by drive stages 600 and 700, respectively.

  The output terminals 10, 10,..., 10 connected to the drive elements 60-1, 70-1; 60-2, 70-2; .., 51 as described with reference to FIG. 25 are provided, respectively, to reduce power consumption in the drive IC 3 and suppress heat generation from the drive IC. 27 shows a CMOS type address drive IC, the present invention is applied to, for example, a totem pole type drive circuit using the same polarity MOS transistor (NMOS transistor) as shown in FIG. Of course you can also. In FIG. 27, assuming that the drive voltage is the same between adjacent electrodes as the load capacitor 5, only the counter electrode capacitance Cg in FIG. 21 described above is shown. However, for example, the drive voltage between adjacent electrodes is Needless to say, the load capacitance (CL) is obtained by adding the adjacent interelectrode capacitance Ca to the counterelectrode capacitance Cg at different times. At this time, the maximum value of the effective series resistance Ra is 2/3 RL including the effective resistance of the adjacent electrode.

  FIG. 28 is a diagram showing a cross section of an address electrode in a plasma display panel to which the capacitive load driving circuit according to the present invention is applied. FIG. 28 (a) shows an example of an electrode made of a single material. (B) has shown the example of the electrode by a composite material. In FIG. 28A, reference numeral 210 denotes a rear glass substrate, 211 denotes a dielectric layer, and 2140 denotes a metal layer. In FIG. 28B, reference numeral 2141 indicates an adhesion material layer, 2142 indicates a main material layer, and 2143 indicates an exposed layer.

  When the electrode is formed of a single material as shown in FIG. 28A, the thickness of the metal layer 2140 or the width of the electrode can be increased in order to increase the distributed resistance (51) value RL to a desired resistance value. To reduce the cross-sectional area of the electrode. As the metal layer 2140, a material such as silver or chromium excellent in adhesion to the back glass 210 and the dielectric layer 211, manufacturability, weather resistance of the exposed portion, cost and reliability, and the like can be considered. Here, reducing the thickness of the electrode can shorten the manufacturing time because, for example, the etching process for patterning the electrode can be performed in a short time, and further, the electrode material, the etching solution, etc. This is also advantageous in terms of cost reduction.

  When the electrode is made of a composite material as shown in FIG. 28 (b), the cross-sectional area is increased in the same way as in the case of the single material described above in order to increase the value RL of the distributed resistance (51) to the desired resistance value. May be reduced (for example, the thickness of the main material layer 2142 that greatly affects the resistance value of the electrode) may be reduced, but the main material layer 2142 itself can be eliminated if conditions are satisfied. Here, as the main material (layer) 2142, copper or the like, which is advantageous in terms of control of electrode resistance, manufacturability and cost, is used. As the adhesion material layer 2141, the back glass 210 and the main material 2142 are used. Chromium, which is a material having excellent adhesion, cost, and reliability, is used, and as the exposed layer 2143, adhesion to the main material 2142 and the derivative layer, and weather resistance, cost, and reliability of the exposed portion are used. Chrome, which is an excellent material, is used. Note that the main material layer 2142 such as copper is formed by, for example, a sputtering process. However, the reduction in the thickness of the main material layer 2142 directly leads to a reduction in the time required for the sputtering process. Since the elimination also eliminates the manufacturing process for that purpose, the manufacturing time can be shortened and the cost can be reduced.

  29 is a block diagram showing an eighteenth embodiment of a capacitive load driving circuit according to the present invention. For example, the power distribution means 2 shown in FIG. 3 is applied to the fifteenth embodiment shown in FIG. It is what. Here, the power distribution means 2 and the like can have various configurations as described with reference to FIGS. 4 to 19, for example. In that case, the effect of the power consumption distribution in the drive circuit 3 is It will be displayed as it is added.

  (Supplementary note 1) A capacitive load drive circuit including a configuration in which a drive power supply is connected to an output terminal via a drive element, wherein power distribution means is inserted between the drive power supply and the drive element. Capacitive load drive circuit.

  (Supplementary Note 2) In the capacitive load driving circuit according to Supplementary Note 1, the power distribution means is a resistance element having an impedance of 1/10 or more with respect to a resistance component of the conduction impedance of the drive element. Capacitive load driving circuit.

  (Supplementary note 3) The capacitive load drive circuit according to supplementary note 2, wherein the power distribution means is a high power resistor having a power performance equal to or higher than an allowable power of the drive element. .

  (Additional remark 4) The capacitive load drive circuit of Additional remark 1 WHEREIN: The said electric power dispersion | distribution means is a constant current source, The capacitive load drive circuit characterized by the above-mentioned.

  (Additional remark 5) The capacitive load drive circuit of Additional remark 1 WHEREIN: The said drive power supply selects and outputs a several different voltage level, The capacitive load drive circuit characterized by the above-mentioned.

  (Supplementary note 6) The capacitive load driving circuit according to supplementary note 5, wherein the power distribution means includes a plurality of power distribution units provided for the plurality of different voltage levels, respectively. Driving circuit.

  (Additional remark 7) The capacitive load drive circuit of Additional remark 6 WHEREIN: Each said electric power distribution unit is provided with the function as a switch which selects the said different voltage level, The capacitive load drive circuit characterized by the above-mentioned.

  (Additional remark 8) The capacitive load drive circuit of Additional remark 1 WHEREIN: The said drive element is an element whose input withstand voltage is higher than an output voltage, The capacitive load drive circuit characterized by the above-mentioned.

  (Supplementary Note 9) A capacitive load drive circuit including a configuration in which a reference potential point is connected to an output terminal via a drive element, wherein power distribution means is inserted between the reference potential point and the drive element. Capacitive load drive circuit characterized.

  (Supplementary Note 10) In the capacitive load drive circuit according to Supplementary Note 9, the power distribution means is a resistance element having an impedance of 1/10 or more with respect to a resistance component of the conduction impedance of the drive element. Capacitive load driving circuit.

  (Supplementary note 11) The capacitive load drive circuit according to supplementary note 10, wherein the power distribution means is a high power resistor having a power performance equal to or higher than an allowable power of the drive element. .

  (Additional remark 12) The capacitive load drive circuit of Additional remark 9 WHEREIN: The said electric power dispersion | distribution means is a constant current source, The capacitive load drive circuit characterized by the above-mentioned.

  (Additional remark 13) The capacitive load drive circuit of Additional remark 9 WHEREIN: The said drive power supply selects and outputs a several different voltage level, The capacitive load drive circuit characterized by the above-mentioned.

  (Supplementary note 14) The capacitive load drive circuit according to supplementary note 13, wherein the power distribution means includes a plurality of power distribution units respectively provided for the plurality of different voltage levels. Driving circuit.

  (Additional remark 15) The capacitive load drive circuit of Additional remark 14 WHEREIN: Each said electric power distribution unit is provided with the function as a switch which selects the said different voltage level, The capacitive load drive circuit characterized by the above-mentioned.

  (Additional remark 16) The capacitive load drive circuit of Additional remark 9 WHEREIN: The said drive element is an element whose input withstand voltage is higher than an output voltage, The capacitive load drive circuit characterized by the above-mentioned.

  (Supplementary Note 17) A capacitive load driving circuit including a configuration in which a plurality of driving elements corresponding to a plurality of capacitive loads are integrated, wherein each driving element is connected to a driving power source or a reference potential via a power distribution unit. Capacitive load driving circuit characterized by being connected to a point.

  (Additional remark 18) The capacitive load drive circuit of Additional remark 17 WHEREIN: The diode was provided between each said capacitive load and the said corresponding drive element, The capacitive load drive circuit characterized by the above-mentioned.

  (Supplementary note 19) In the capacitive load driving circuit according to supplementary note 17, each of the power distribution means is 1/10 or more of a value obtained by dividing the conduction impedance of the drive element by the number of drive elements connected to the power distribution means. Capacitive load drive circuit characterized by being a resistance element having an impedance of

  (Supplementary note 20) The capacitive load driving circuit according to supplementary note 19, wherein each of the power distribution means is a high power resistor having a power performance equal to or higher than an allowable power of the drive element. circuit.

  (Supplementary note 21) The capacitive load drive circuit according to supplementary note 17, wherein each of the power distribution means is a constant current source.

  (Supplementary note 22) The capacitive load drive circuit according to supplementary note 17, wherein the drive power supply is configured to select and output a plurality of different voltage levels.

  (Supplementary note 23) The capacitive load driving circuit according to supplementary note 22, wherein the power distribution means includes a plurality of power distribution units respectively provided for the plurality of different voltage levels. Driving circuit.

  (Supplementary note 24) The capacitive load drive circuit according to supplementary note 23, wherein each of the power distribution units has a function as a switch for selecting the different voltage level.

  (Additional remark 25) The capacitive load drive circuit of Additional remark 17 WHEREIN: The said drive element is an element whose input withstand voltage is higher than an output voltage, The capacitive load drive circuit characterized by the above-mentioned.

  (Supplementary Note 26) The capacitive load drive circuit according to supplementary note 17, wherein a ground terminal of each of the integrated drive elements is connected to the drive power supply through the power distribution means. circuit.

  (Supplementary note 27) The capacitive load drive circuit according to supplementary note 17, wherein a ground terminal of each of the integrated drive elements is connected to the reference potential point via the power distribution means. circuit.

  (Supplementary Note 28) In the capacitive load drive circuit according to Supplementary Note 17, the power distribution means and the switch element are connected in series between the drive elements and the driving power source or a reference potential point. Capacitive load driving circuit.

  (Supplementary note 29) The capacitive load drive circuit according to supplementary note 17, wherein the capacitive load drive circuit is configured as a drive module including a plurality of drive integrated circuits that drive the capacitive load. Capacitive load drive circuit.

  (Supplementary Note 30) In the capacitive load drive circuit according to Supplementary Note 29, each of the drive integrated circuits includes a high-voltage output element whose input withstand voltage is increased to a drive power supply voltage value, and a control input of the output element as a drive power supply. A capacitive load drive circuit comprising a flip-flop driven at a full swing level of either a voltage or a reference voltage.

  (Supplementary note 31) In the capacitive load drive circuit according to supplementary note 29, each of the drive integrated circuits includes a buffer driven by a logic voltage, and an output of the buffer is connected to an input terminal of each of the drive elements. A capacitive load drive circuit, wherein a power distribution means is connected to an inverting input terminal of each of the drive elements, so that the drive elements are self-biased by a voltage drop generated by the power distribution means.

  (Supplementary note 32) In the capacitive load drive circuit according to supplementary note 29, a switch element is provided between the power distribution means and the drive power source or a reference potential point, and the drive element is switched to a conductive state. A capacitive load drive circuit characterized in that a switch element is made conductive.

  (Supplementary Note 33) A capacitive load driving circuit including a configuration in which a driving power source is connected to an output terminal via a driving element, wherein the driving power source selects and outputs a plurality of different voltage levels. A capacitive load driving circuit characterized by the above.

  (Supplementary Note 34) In the capacitive load drive circuit according to Supplementary Note 33, the drive power source is configured to switch the plurality of voltage levels between drive voltage amplitudes while maintaining the on / off state of the drive element. Capacitive load driving circuit characterized in that it rises and falls automatically.

  (Supplementary Note 35) A capacitive load driving circuit for driving a capacitive load connected to an output terminal by a drive element, wherein a resistive impedance is inserted in series with the output terminal. Driving circuit.

  (Supplementary Note 36) In the capacitive load drive circuit according to Supplementary Note 35, the resistive impedance has an impedance of 1/10 or more with respect to a resistance component of at least one conduction impedance of the drive element. Capacitive load drive circuit.

  (Supplementary Note 37) In the capacitive load drive circuit according to Supplementary Note 35, the resistive impedance is a distributed resistance that exhibits a resistance value of 3/10 or more with respect to a resistance component of at least one conduction impedance of the drive element. A capacitive load drive circuit characterized by

  (Supplementary Note 38) In the capacitive load drive circuit according to any one of Supplementary Notes 35 to 37, a drive power supply is connected to the output terminal via the drive element, and the drive power supply and the drive element are interposed between the drive power supply and the drive element. 35. A capacitive load drive circuit comprising the power distribution means in the capacitive load drive circuit according to any one of appendices 1 to 34.

  (Supplementary note 39) The capacitive load drive circuit according to any one of supplementary notes 1 to 38, wherein the capacitive load drive circuit is used as an electrode drive circuit.

  (Supplementary note 40) The plasma display device according to supplementary note 39, wherein the capacitive load drive circuit is used as a drive circuit for address electrodes.

  (Supplementary note 41) In the plasma display device according to supplementary note 40, the plasma display device has the three-electrode surface in which the address electrodes are arranged on the first substrate and the X and Y electrodes are arranged on the second substrate. It is a discharge AC drive type plasma display device, wherein the thickness of the conductor layer of the address electrode is reduced to less than half the thickness of the conductor layer made of the same material as the conductor layer of the X and Y electrodes. Plasma display device.

  (Supplementary note 42) The plasma display device according to supplementary note 40, wherein the plasma display device has the three-electrode surface in which the address electrodes are arranged on the first substrate and the X and Y electrodes are arranged on the second substrate. A plasma display device, characterized in that it is a discharge AC drive type plasma display device, wherein the conductor layer of the address electrode is composed of a plurality of metal layers, and any conductor layer in the metal layer is excluded.

  (Supplementary Note 43) An inductive load driving circuit for driving an inductive load connected to an output terminal by a driving element, wherein a resistive impedance is inserted in series with the output terminal. Driving circuit.

  (Supplementary Note 44) The inductance load drive circuit according to Supplementary Note 43, wherein the resistive impedance has an impedance of 1/10 or more with respect to a resistance component of at least one conduction impedance of the drive element. Inductive load drive circuit.

DESCRIPTION OF SYMBOLS 1 ... Drive power supply 2, 21, 22, 23, 24, 25, 26, 27, 121, 131, 132, 141 ... Power distribution means 3 ... Drive circuit 4 ... Reference potential point 5 ... Load capacity 6, 7 ... Drive element DESCRIPTION OF SYMBOLS 8 ... Drive circuit power supply terminal 9 ... Drive circuit reference potential terminal 10 ... Drive circuit output terminal 15 ... Drive power supply control circuit 36 ... Drive module 37 (38, 39) ... Drive integrated circuit 101 ... Plasma display panel 102 ... Anode (Address) drive circuit 103 ... Cathode (Y) drive circuit 104 ... Sub-anode drive circuit 105 ... Control circuit 106 ... X drive circuit 107,207 ... Discharge cell 110 ... Power recovery circuit 120 ... Address drive IC
122 ... Output circuit in address drive IC 121 ... Address drive IC power supply terminal 210 ... Rear glass substrates 211, 221 ... Dielectric layer 212 ... Phosphor 213 ... Partition 214 ... Address electrode 220 ... Front glass substrate 222 ... X electrode or Y electrode

Claims (7)

A plurality of scan electrodes; a plurality of address electrodes intersecting the scan electrodes; and a drive circuit for driving the address electrodes; the address electrodes in a display cell of a line selected by a voltage applied to the scan electrodes A plasma display device for generating discharge by applying an address voltage to
The drive circuit is
A driving power supply for supplying an address voltage;
A reference potential point for supplying a reference potential;
An address drive IC having a plurality of drive elements for applying the address voltage to the plurality of address electrodes according to display data,
The address drive IC includes a first terminal connected to the driving power source and a second terminal connected to the reference potential point, respectively, and between the first terminal and the driving power source or the second terminal. And a resistance element is connected to at least one of the reference potential point,
The impedance of the resistive element is such that the address voltage is supplied to the plurality of address electrodes via the first terminal in the address drive IC, or the reference voltage is supplied to the plurality of address electrodes via the second terminal. A plasma display device having an impedance of 1/10 or more of a combined impedance when a plurality of driving elements supplying electric potential are conducted. A plurality of scan electrodes; a plurality of address electrodes intersecting the scan electrodes; and a drive circuit for driving the address electrodes; the address electrodes in a display cell of a line selected by a voltage applied to the scan electrodes A plasma display device for generating discharge by applying an address voltage to
The drive circuit is
A driving power supply for supplying an address voltage;
A reference potential point for supplying a reference potential;
An address drive IC having a plurality of drive elements for applying the address voltage to the plurality of address electrodes according to display data,
The drive circuit includes a plurality of the address drive ICs, and each of the plurality of address drive ICs includes a first terminal connected to the drive power supply and a second terminal connected to the reference potential point, A common resistance element is connected between at least one of the first terminal and the drive power supply or between the second terminal and the reference potential point,
The impedance of the resistive element is such that the address voltage is supplied to the plurality of address electrodes via the first terminal in the address drive IC, or the reference voltage is supplied to the plurality of address electrodes via the second terminal. A plasma display device having an impedance of 1/10 or more of a combined impedance when a plurality of driving elements supplying electric potential are conducted. A scan electrode, a sustain electrode, and an address electrode are provided, and one frame is composed of a plurality of subframes. At least one subframe includes an erase period in which an erase voltage pulse is applied to a display cell, an address period in which a display cell is selected A plasma display apparatus having a sustain discharge period for generating sustain light emission for a selected display cell,
An address driving circuit for applying a positive address voltage pulse to the address electrode in the address period; and a scan driving circuit for applying a negative scanning pulse to the scan electrode;
A common driving circuit for applying a sustain voltage to the sustain electrodes in the sustain discharge period;
With
The address driving circuit includes a driving power source for supplying an address voltage, a reference potential point for supplying a reference potential,
An address drive IC having a plurality of drive elements for applying the address voltage to the plurality of address electrodes according to display data,
The address drive circuit includes a plurality of the address drive ICs, and each of the plurality of address drive ICs includes a first terminal connected to the drive power supply and a second terminal connected to the reference potential point. A resistance element is connected between at least one of the first terminal and the drive power supply or between the second terminal and the reference potential point,
The impedance of the resistance element is such that the address voltage is supplied to the plurality of address electrodes via the first terminal in the predetermined number of the address drive ICs to which the resistance element is connected, or the second terminal A plasma display device having an impedance of 1/10 or more of a combined impedance when the plurality of drive elements are turned on, wherein the reference potential is supplied to the plurality of address electrodes through the plurality of address electrodes.   4. The plasma display apparatus according to claim 1, wherein the driving power source outputs a plurality of different voltage levels.   4. The address drive IC according to claim 1, further comprising a third terminal connected to the drive power supply, wherein the third terminal is connected to the address drive IC without passing through the resistance element. The plasma display device according to any one of the above.   4. The switch element is connected with the resistance element between the first terminal and the drive power source or between the second terminal and the reference potential point. 5. Plasma display device. 7. The plasma display apparatus according to claim 6 , wherein when the address voltage is applied to the address electrode, the switch element becomes conductive after the element in the address drive IC becomes conductive.

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