JP2006058799A - Integrated circuit for driving display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit for driving a display device in which variation in switching characteristics between chips can be restrained with simple configuration. <P>SOLUTION: In a delay time adjustment circuit 10, at least one or more among a plurality of delay elements 11-1, 11-2 to 11-m for delaying an input signal are trimmed and thereby, the propagation delay time of the output signal driving the flat panel display outputted according to the input signal is adjusted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an integrated circuit for driving a display device, and more particularly to an integrated circuit for driving a display device that drives a flat panel display such as a plasma display panel.

In recent years, large-screen, thin wall-mounted televisions using plasma display panels (hereinafter referred to as PDPs) have attracted attention.
FIG. 5 is a diagram illustrating a schematic configuration example of a PDP driving device for driving a PDP.

For simplicity, an example of a two-electrode PDP is shown here.
The PDP 700 has a plurality of scan driver ICs (Integrated Circuits) 800-1, 800-2, 800-3,..., 800-k, and data (address) driver ICs 900-1, 900-2, 900-3, ..., 900-l, etc. (where k and l are arbitrary numbers).

  Each of the scan driver ICs 800-1 to 800-k drives a plurality of scan / sustain electrodes 911, and each of the data (address) driver ICs 900-1 to 900-l corresponds to each of R, G, and B colors. A plurality of data electrodes 912 are driven. The scan / sustain electrodes 911 and the data electrodes 912 are arranged in a grid so as to be perpendicular to each other, and discharge cells (not shown) are arranged at the intersections.

  For example, if the number of scan driver ICs 800-1 to 800-k can drive 64 scan / sustain electrodes 911, the number of pixels of the PDP 700 is 1024 × 768 in the case of an XGA (eXtended video Graphics Array). Therefore, k = 12 are arranged.

  In displaying an image, the scan driver ICs 800-1 to 800-k and the data (address) driver ICs 900-1 to 900-l use the scan driver ICs 9-1 to 900-1 to transfer data from the data electrodes 912 to the discharge cells. Each time scanning is performed for writing (address discharge period), a discharge sustain pulse is output to the scan / sustain electrode 911 several times to maintain discharge (discharge sustain period), and an image is displayed.

FIG. 6 is a block diagram of a conventional integrated circuit for driving a display device.
Here, an example of a scan driver IC is shown.
The scan driver IC 800 receives a serial signal for controlling the scan / sustain electrode 911 shown in FIG. 5 from a terminal DATA, and converts it into a parallel signal in synchronization with a clock signal input to the terminal CLK. 810-2, 810-3,..., 810-n, and signals transferred bit by bit from the shift registers 810-1, 810-2, 810-3,. , 830-2, 830-3,..., 830-n, data selectors 820-1, 820-2, 820-3,. n is an arbitrary number. For example, in the case of a 64-bit scan driver IC 800, n = 64, and 64 scan / sustain electrodes 911 are driven.

  Note that the terminals SH and SL connected to the data selectors 820-1, 820-2, 820-3,..., 820-n are in the discharge sustain period, and all the scan / sustain electrodes 911 are in the terminal SH. Is set to H (High) level, and all output H level fixed signals are input to the terminal SL, and all scan / sustain electrodes 911 are set to L (Low) level. Is entered.

In addition, for example, Patent Document 1 discloses a driver IC in which a temperature detection circuit for preventing overheating is additionally integrated.
FIG. 7 is a timing chart for explaining the operation of a conventional display device driving integrated circuit.

  In this figure, during the address discharge period, the clock signal input to the terminal CLK, the output waveforms (Do1 to Do1) of the output terminals Do1 to Don of the output stage circuits 830-1, 830-2, 830-3,. Don output waveform).

  In the address discharge period, the signal from the terminal DATA is taken in for each bit by the shift registers 810-1, 810-2, 810-3, ..., 810-n in synchronization with the rising edge of the clock signal. Then, the data are sequentially input to the output stage circuits 830-1 to 830-n via the data selectors 820-1 to 820-n. As a result, the output waveforms of the output stage circuits 830-1 to 830-n become waveforms that sequentially fall in synchronization with the rise of the clock signal and rise again at the rise of the next clock signal, as shown in the figure. Although illustration is omitted here, in practice, a predetermined delay occurs between the rising edge of the clock signal and the output of the output signal due to the propagation delay in the output stage circuits 830-1 to 830-n. Has propagation delay time.

FIG. 8 is a circuit diagram of an output stage circuit in a conventional display device driving integrated circuit.
The output stage circuit 830 includes a level shifter circuit 831, inverters 832 and 833, a buffer circuit 834, and two IGBTs (Insulated Gate Bipolar Transistors) 835 and 836 that directly drive the scan / sustain electrodes 911. Note that the inverters 832 and 833 and the buffer circuit 834 have an appropriate delay time to prevent a through current during switching. A technique for preventing a through current is further disclosed in Patent Document 2, for example.

  The level shifter circuit 831 is a circuit composed of high breakdown voltage p-channel type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (hereinafter referred to as PMOS) 831a and 831b and n-channel type MOSFET (hereinafter referred to as NMOS) 831c and 831d. is there. The PMOS 831a has a source terminal connected to a high voltage power supply terminal VDH that supplies a high voltage of 0 to 100V, and a drain terminal connected to the drain terminal of the NMOS 831c, the gate terminal of the PMOS 831b, and the gate terminal of the IGBT 836. The gate terminal of the PMOS 831a is connected to the drain terminal of the PMOS 831b and the drain terminal of the NMOS 831d. Similarly, the PMOS 831b has a source terminal connected to the high voltage power supply terminal VDH, and a drain terminal connected to the drain terminal of the NMOS 831d and the gate terminal of the PMOS 831a. The gate terminal of the PMOS 831b is connected to the drain terminal of the PMOS 831a. The source terminals of the NMOSs 831c and 831d are both grounded. Further, the gate terminal of the NMOS 831c is passed through the inverter 832 and the gate terminal of the NMOS 831d is passed through the inverters 832 and 833, and the signal from the input terminal IN (sent from the above-described data selectors 820-1 to 820-n). Input signal).

The buffer circuit 834 receives the signal from the input terminal IN through the inverters 832 and 833, inverts the level of the signal, and inputs the signal to the gate terminal of the IGBT 835.
The collector terminal of the IGBT 836 is connected to the high voltage power supply terminal VDH, and the emitter is connected to the output terminal Do and the collector of the IGBT 835. The emitter of the IGBT 835 is grounded.

The output terminal Do is connected to the scan / sustain electrode 911 as shown in FIG. 5, and is further connected to a discharge cell (which can be regarded as a capacitor).
The operation of the output stage circuit 830 will be described with reference to a timing chart.

FIG. 9 is a timing chart for explaining the operation of the conventional output stage circuit, and shows the address discharge period.
This figure shows voltage waveforms of the input signal input to the input terminal IN, the gate signals of the IGBTs 835 and 836, and the output signal of the output terminal Do.

  Now, an input signal of 5V (VDL) is input to the input terminal IN in synchronization with the clock signal described above, and when the input terminal IN becomes H level, an L level signal is input to the gate terminal of the NMOS 831c of the level shifter circuit 831. Be off. Further, an H level signal is input to the gate terminal of the NMOS 831d and turned on. As a result, the PMOS 831a is turned on, and the gate signal input to the gate terminal of the IGBT 836 becomes 100V. As a result, the IGBT 836 is turned on and outputs an output signal of 100 V to the output terminal Do. At this time, the signal rises with a delay of td1 shown in FIG. 9 due to the delay time of the inverter 832 and the propagation delay time of the level shifter circuit 831. Since the gate signal input to the gate terminal of the IGBT 835 is at the L level (GND (0 V) in the figure (hereinafter the same)), the IGBT 835 is turned off.

  Next, when the input signal becomes L level in synchronization with the clock signal, an H level signal is inputted to the gate terminal of the NMOS 831c of the level shifter circuit 831 and turned on, and an L level signal is inputted to the gate terminal of the NMOS 831d and turned off. To do. As a result, the PMOS 831a is turned off and the PMOS 831b is turned on. As a result, the gate signal input to the gate terminal of the IGBT 836 becomes L level, and the IGBT 836 is turned off. Further, since the gate signal input to the gate terminal of the IGBT 835 is at the H level, the IGBT 835 is turned on, and the output signal output from the output terminal Do is 0V. Also at this time, the signal falls after the propagation delay time of the inverter 833 and the buffer circuit 834 by the timing td2 shown in FIG.

FIG. 10 is a timing chart for explaining the operation of the conventional output stage circuit, and shows the discharge sustain period.
In this figure, the all output H level fixed signal (SH signal) input to the terminal SH, the all output L level fixed signal (SL signal) input to the terminal SL, and the output stage circuits 830-1, 830-2, 830. -3,..., 830-n shows output waveforms (Do1-Don output waveforms) of the output terminals Do1-Don.

  Now, when the terminal SH becomes H level, H level signals are inputted to all the output stage circuits 830-1 to 830-n, and the output terminals Do1 to Don are inputted to the output terminals Do1 to Don in the same manner as when the input terminal IN becomes H level. Outputs 100V output signal. At this time, the signal rises with a delay of the timing td3 shown in FIG. 10 due to the delay time of the inverter 832 and the propagation delay time of the level shifter circuit 831.

Next, when the terminal SL becomes H level, L level signals are inputted to all the output stage circuits 830-1 to 830-n, and the output terminals Do1 to Don are input in the same manner as when the input terminal IN becomes L level. Output an output signal of 0V. Also at this time, the signal falls after the propagation delay time of the inverter 833 and the buffer circuit 834 by the timing td4 shown in FIG.
JP-A-11-201830 JP 2000-164730 A

  However, in the conventional display device driving integrated circuit 800 as shown in FIG. 6, the switching characteristics (propagation delay time) of the output terminals Do1, Do2,... Switching characteristics tend to vary in the semiconductor manufacturing process. This is due to variations in processing line width, temperature, gas flow rate, and the like.

  If this switching characteristic varies, there are problems in that the light emission luminance of the flat panel display varies and a malfunction display occurs. In addition, when the standard of variation is strict, the yield deteriorates, and there is a problem that the cost increases and the product cannot be supplied stably.

  The present invention has been made in view of these points, and an object of the present invention is to provide a display device driving integrated circuit capable of suppressing variations in switching characteristics between chips with a simple configuration.

  In the present invention, in order to solve the above problem, in a display device driving integrated circuit for driving a flat panel display, a delay for adjusting a propagation delay time of an output signal for driving the flat panel display which is output according to an input signal. There is provided a display device driving integrated circuit comprising a time adjusting circuit.

  According to the above configuration, the delay time adjustment circuit adjusts the propagation delay time of the output signal that drives the flat panel display that is output in accordance with the input signal.

  In the display device driving integrated circuit of the present invention, the delay time adjusting circuit adjusts the propagation delay time of the output signal that drives the flat panel display that is output in accordance with the input signal. It is possible to suppress the influence of time and make the propagation delay time between chips constant with a simple configuration. Thereby, a yield can be improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit diagram of a display device driving integrated circuit according to the first embodiment.
Hereinafter, the display device driving integrated circuit will be described as a scan driver IC for driving the scan / sustain electrode 911 as shown in FIG.

  The scan driver IC1 of the first embodiment includes a delay time adjustment circuit 10, shift registers 20-1, 20-2, 20-3,..., 20-n, data selectors 30-1, 30-2, 30-n and output stage circuits 40-1, 40-2, 40-3,..., 40-n. n is an arbitrary number. For example, in the case of a 64-bit scan driver IC1, n = 64, and 64 scan / sustain electrodes 911 are driven.

  The delay time adjustment circuit 10 includes a plurality of delay elements 11-1, 11-2,..., 11-m that delay an input signal. In the scan driver IC1 of the first embodiment, this input signal is a clock signal, and the clock signal is delayed by these delay elements 11-1 to 11-m. Further, by trimming at least one of these delay elements 11-1 to 11-m, the propagation delay time of the output signal for driving the flat panel display output in accordance with the input signal is adjusted.

  The shift registers 20-1 to 20-n receive a signal (serial signal) for controlling the scan / sustain electrode 911 shown in FIG. 5 from the terminal DATA, and are input to the terminal CLK and delayed by the delay time adjustment circuit 10. It is taken in bit by bit in synchronization with the clock signal and converted into a parallel signal.

  The data selectors 30-1 to 30-n send the signals transferred bit by bit from the shift registers 20-1 to 20-n to the output stage circuits 40-1 to 40-n. The terminals SH connected to the data selectors 30-1 to 30-n receive all output H level fixed signals when all the scan / sustain electrodes 911 are set to the H level. All output L level fixed signals when the scan / sustain electrode 911 is set to L level are input.

  The output stage circuits 40-1 to 40-n have the same configuration as the output stage circuit 830 shown in FIG. 8, and output an output signal that drives the flat panel display in accordance with the input signal. Further, as described above, in order to prevent a through current when the transistors (IGBTs 835 and 836 in FIG. 8) are switched, a propagation delay time of a predetermined (for example, 50 ns to 300 ns) is provided.

  Here, details of the delay time adjustment circuit 10 which is a characteristic part of the scan driver IC 1 of the present embodiment will be described. The delay time adjustment circuit 10 has, for example, the following two circuit configurations.

2 and 3 are circuit diagrams of examples of the delay time adjustment circuit.
The delay time adjusting circuit 10a shown in FIG. 2 includes a plurality of inverters 11a-1, 11a-2,..., 11a-m as the delay elements 11-1 to 11-m as shown in FIG. The clock signal input terminal CLK and the shift register 20-1 are connected in series. The propagation delay time is adjusted by trimming at least one of these. For this purpose, Zener diodes 12-1, 12-2,..., 12-m are connected in parallel to the inverters 11a-1 to 11a-m. 11a-m is trimmed to adjust the propagation delay time. The propagation delay time of each inverter 11a-1 to 11a-m is the gate width and gate length ratio (hereinafter referred to as W / L) of CMOS (Complementary Metal-Oxide Semiconductor) constituting the inverters 11a-1 to 11a-m. It is about several ns to several tens ns.

  The delay time adjustment circuit 10b shown in FIG. 3 includes resistors 11b-1, 11b-2,..., 11b-m connected in series as delay elements 11-1 to 11-m as shown in FIG. Is connected to the final stage resistor 11b-m, and the other terminal is grounded. Furthermore, one terminal of the resistor 11b-m and the capacitor 13 at the final stage is connected to the input terminal of the inverter 14, and the output of the inverter 14 is input to the shift register 20-1. The propagation delay time is determined by the resistors 11b-1 to 11b-m, the time constant by the capacitor 13, and the threshold voltage of the inverter 14. In the delay time adjusting circuit 10b, the time constant is changed by trimming at least one of the resistors 11b-1 to 11b-m connected in series to adjust the propagation delay time. For this purpose, Zener diodes 15-1, 15-2,..., 15-m are connected in parallel to the resistors 11b-1 to 11b-m, and some resistors 11b-1 are short-circuited. Trimming of ~ 11b-m is performed to adjust the propagation delay time.

Hereinafter, the operation of the scan driver IC 1 of the first embodiment will be described.
Here, the case where the all output H level fixed signal or the all output L level fixed signal is not input from the terminal SH or the terminal SL will be described.

  When a serial signal is input from the terminal DATA, the serial signal is converted into a parallel signal by the shift registers 20-1 to 20-n in synchronization with the clock signal input to the terminal CLK and delayed by the delay time adjusting circuit 10. Converted. Then, after being transferred by the data selectors 30-1 to 30-n, the output stage circuits 40-1 to 40-n output output signals (Do1 to Don output waveforms) as shown in FIG. Each output signal has a propagation delay time as shown in FIG.

  For example, if the scan driver IC1 can drive 64 scan / sustain electrodes 911, for example, in the case of XGA, the number of pixels of the PDP 700 as shown in FIG. Twelve will be arranged. Since the propagation delay time varies from chip to chip depending on the propagation delay time of the output stage circuits 40-1 to 40-n, for example, at the time of a shipping characteristic test, the entire delay time adjustment circuit 10 included in each scan driver IC1 is used. Adjust so as to reduce variation. Specifically, during the test, the propagation delay time of the switching characteristics is measured, and the optimum value (the variation is minimized) while temporarily shorting the test pads provided at both ends of each Zener diode shown in FIGS. The value is found and current is supplied to the desired Zener diode to trim the delay element. In general, in the case of a PDP driver IC, the propagation delay time is 50 ns to 300 ns, and the variation between chips is about 10%. Therefore, a propagation delay time adjusted by trimming is sufficient from several ns to several tens ns.

In this way, variation in switching characteristics between chips can be suppressed with a simple configuration.
Next, a display device driving integrated circuit according to a second embodiment will be described.

  In the scan driver IC 1 of the first embodiment described above, the delay time adjustment is performed when the all output H level fixed signal or the all output L level fixed signal is not input from the terminal SH or the terminal SL (address discharge period). The case where the clock signal is delayed as the input signal by the circuit 10 has been described.

  As shown in FIG. 10, when a full output H level fixed signal or a full output L level fixed signal is input from the terminal SH or terminal SL (discharge sustaining period), the output signal regardless of the clock signal or serial signal. Becomes full output H level or L level. Also at this time, a propagation delay time occurs, and variations occur between chips. If the propagation delay time varies in the discharge sustain period, erroneous discharge between outputs and luminance unevenness are affected. The display device driving integrated circuit according to the second embodiment is for preventing this problem.

FIG. 4 is a circuit diagram of a display device driving integrated circuit according to the second embodiment.
Hereinafter, the display device driving integrated circuit will be described as a scan driver IC for driving the scan / sustain electrode 911 as shown in FIG. Further, the same components as those of the scan driver IC 1 of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  Unlike the scan driver IC1 of the first embodiment, the scan driver IC2 of the second embodiment has a delay time adjustment circuit 10c that delays all output H level fixed signals from the terminal SH as input signals, and a terminal SL. Delay time adjusting circuit 10d for delaying all output L level fixed signals from. Note that the delay time adjustment circuit 10 may be further arranged between the terminal CLK and the shift register 20-1 like the scan driver IC1 of the first embodiment.

The circuit configurations of the delay time adjusting circuits 10c and 10d are the same as those in FIG.
All output H level fixed signals or all output L level fixed signals delayed by the delay time adjusting circuits 10c and 10d are sent to the output stage circuits 40-1 to 40-n via the data selectors 30-1 to 30-n. The output terminals Do1 to Don all output H level or L level output signals. Propagation delay time also occurs in the output signal at this time, and this propagation delay time varies between chips. Therefore, as described above, for example, during the shipping characteristic test, the delay time adjustment circuits 10c and 10d included in the respective scan driver ICs 2 are adjusted so as to reduce the overall variation. Specifically, during the test, the delay time of the switching characteristics is measured, and an optimum value (a value at which variation is minimized) while temporarily shorting the test pads provided at both ends of each zener diode shown in FIGS. ) And a current is supplied to a desired Zener diode to trim the delay element.

In this way, variation in switching characteristics between chips can be suppressed with a simple configuration.
In the above description, the trimming using the Zener diode as shown in FIGS. 2 and 3 has been described. However, a polysilicon resistor may be used instead of the Zener diode.

  In the above description, the scan driver IC is taken as an example, but it goes without saying that the present invention can also be applied to a data (address) driver IC.

1 is a circuit diagram of a display device driving integrated circuit according to a first embodiment; It is a circuit diagram of an example of a delay time adjustment circuit. It is a circuit diagram of an example of a delay time adjustment circuit. It is a circuit diagram of a display device driving integrated circuit of a second embodiment. It is a figure which shows the example of a schematic structure of the PDP drive device for driving PDP. It is a block diagram of a conventional display device driving integrated circuit. It is a timing diagram explaining operation | movement of the conventional display apparatus drive integrated circuit. It is a circuit diagram of an output stage circuit in a conventional display device driving integrated circuit. It is a timing diagram explaining operation | movement of the conventional output stage circuit, and has shown about the address discharge period. It is a timing diagram explaining operation | movement of the conventional output stage circuit, and has shown about the discharge maintenance period.

Explanation of symbols

1. Display device driving integrated circuit (scan driver IC)
DESCRIPTION OF SYMBOLS 10 Delay time adjustment circuit 11-1, 11-2, ..., 11-m Delay element 20-1, 20-2, 20-3, ..., 20-n Shift register 30-1, 30-2, 30-3 30-n Data selector 40-1, 40-2, 40-3, ..., 40-n Output stage circuit

Claims (8)

In a display device driving integrated circuit for driving a flat panel display,
An integrated circuit for driving a display device, comprising: a delay time adjusting circuit for adjusting a propagation delay time of an output signal for driving the flat panel display output in accordance with an input signal.   The delay time adjustment circuit includes a plurality of delay elements that delay the input signal, and adjusts the propagation delay time of the output signal by trimming at least one of the delay elements. The display device driving integrated circuit according to claim 1, wherein:   3. The display device driving integrated circuit according to claim 1, wherein the input signal is a clock signal, and the delay time adjusting circuit delays the clock signal.   The input signal is an H level fixed signal for fixing the output signal to an H level or an L level fixed signal for fixing the output signal to an L level, and the delay time adjustment circuit is configured to fix the H level fixed signal or the L level. 3. The integrated circuit for driving a display device according to claim 1, wherein the level fixing signal is delayed.   The delay element is an inverter element, and a plurality of the inverter elements are connected in series, and the propagation delay time is adjusted by trimming at least one of the inverter elements. Integrated circuit for driving a display device.   The delay element is a resistance element and a capacitance element, and the plurality of resistance elements are connected in series, and the time constant is changed by trimming at least one of the resistance elements to adjust the propagation delay time. The integrated circuit for driving a display device according to claim 2.   3. The display device driving integrated circuit according to claim 2, wherein the delay time adjusting circuit performs trimming by using a plurality of Zener diodes connected in parallel to the plurality of delay elements.   3. The display device driving integrated circuit according to claim 2, wherein the delay time adjusting circuit performs trimming using a plurality of polysilicon resistors respectively connected in parallel to the plurality of delay elements.

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