JP2009075507A - Inspection method and manufacturing method for electro-optical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inspection method which perform highly precise inspection to an electro-optical device, and to provide a manufacturing method for an electro-optical device. <P>SOLUTION: The inspection method for inspecting an electro-optical device whose substrate (10) has: a picture signal supply circuit (101) comprising (i) a shift register (160) sequentially transferring transfer start pulses (DX) having a pulse height defined by a high power source potential (VDDX) and a low power source potential (VSSX) to sequentially output transfer signals and (ii) another circuit for supplying the picture signal to data lines on the basis of the transfer signal; and a monitor circuit (27) simulating part of the picture signal supply circuit. The inspection method includes: a step (S30) of inputting the high power source potential (VDDX) in the monitor circuit to detect an output signal outputted from the monitor circuit as a first inspection signal (CK2); and a step (S50) of inputting the low power source potential (VSSX) in the monitor circuit to detect an output signal outputted from the monitor circuit as a second inspection signal (CK3). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technical field of an inspection method of an electro-optical device such as a liquid crystal device and a manufacturing method of the electro-optical device including the inspection method.

  In this type of electro-optical device, for example, a plurality of scanning lines and a plurality of data lines are provided in a pixel region (or pixel array region) on a substrate in order to drive a pixel portion provided for each pixel. . In the peripheral region located around the pixel region on the substrate, for example, a sampling circuit that samples and supplies the image signal to the data line, or the sampling circuit supplies the image signal to the data line. A data line driving circuit for supplying a driving signal for defining output timing or a sampling circuit driving signal is provided.

  A start pulse and a clock signal are supplied to the data line driver circuit, and in synchronization with the clock cycle of the clock signal, the start pulse is transferred to each stage of the built-in shift register and a transfer signal is output. The output transfer signal is sequentially output to the sampling circuit as a sampling circuit drive signal via a buffer circuit, a level shifter circuit, and the like. The sampling circuit samples the image signal according to the sampling circuit drive signal.

  At this time, due to the signal delay generated in the buffer circuit or the sampling circuit in the data line driving circuit or the sampling circuit, there may be a delay that cannot be ignored on the basis of the clock signal in the timing of supplying the image signal.

  Therefore, for example, in Patent Document 1, a monitor circuit that simulates a data line driving circuit and a sampling circuit is provided on a substrate, and the delay amount of the output timing of the image signal is indirectly determined based on the monitor signal from the monitor circuit. Techniques for measuring are disclosed.

  On the other hand, for example, Patent Document 2 discloses an inspection method in which a shift register built in a scanning line driving circuit that supplies a scanning signal to a scanning line is inspected using a logic circuit.

JP 2007-25532 A JP 2003-271109 A

  At the time of inspection performed during or after the manufacture of the electro-optical device, the data line driving circuit and the sampling circuit may be inspected based on the above-described delay amount (that is, the delay amount indirectly measured using the monitor circuit). it can.

  Here, in the data line driving circuit and the sampling circuit, in addition to the signal delay described above, there is a possibility that the signal potential shifts. Due to this signal potential shift, the potential of the image signal is changed to a predetermined potential. Deviations that cannot be ignored may occur. Therefore, it is conceivable to indirectly measure the potential shift of the image signal based on the monitor signal from the monitor circuit described above. By comparing the potential deviation measured in this way with a predetermined reference value, the data line driving circuit and the sampling circuit can be inspected. It becomes possible to perform high-precision inspection.

  However, since the monitor signal includes noise such as overshoot, it is difficult to read the potential of the monitor signal using an oscilloscope, for example, and there is a technical problem that the inspection accuracy may be lowered. is there.

  The present invention has been made in view of the above-described problems, for example, and can be used to accurately measure a signal potential shift in a monitor circuit and perform a highly accurate inspection. It is another object of the present invention to provide an electro-optical device manufacturing method including the inspection method.

  In order to solve the above problems, an inspection method for an electro-optical device according to the present invention includes a plurality of pixel portions on a substrate, a plurality of data lines and a plurality of scanning lines electrically connected to the pixel portions, (I) A transfer start pulse having a pulse height defined by a high power supply potential higher than a predetermined potential and a low power supply potential lower than the predetermined potential is sequentially transferred, and a transfer signal is sequentially output from each of a plurality of stages. And (ii) at least one of the image signal supply circuits, and (ii) an image signal supply circuit comprising: another circuit that supplies an image signal to the plurality of data lines based on the sequentially output transfer signals. An electro-optical device inspection method for inspecting an electro-optical device including a monitor circuit simulating a unit, wherein the high power supply potential is input to the monitor circuit, and an output signal output from the monitor circuit And a step of detecting a first inspection signal, and the step of the low power supply potential is input to the monitor circuit detects an output signal output from the monitor circuit as the second test signal.

  In the electro-optical device to be inspected by the electro-optical device inspection method according to the present invention, during operation, various signals such as an image signal, a clock signal, a control signal, and a power signal are supplied to the image signal supply circuit. The In parallel with this, for example, various signals such as a clock signal, a control signal, and a power supply signal are supplied from an external circuit to the scanning line driving circuit. Accordingly, a scanning signal is supplied to the pixel portion via the scanning line, and an image signal is supplied to the pixel portion via the data line by the image signal supply circuit. For example, an electro-optical material such as liquid crystal is supplied to each pixel portion. By driving, active matrix driving is performed.

  The image signal supply circuit includes a shift register that sequentially outputs transfer signals and another circuit that supplies image signals to a plurality of data lines based on the transfer signals. The other circuit is, for example, an enable circuit that shapes the transfer signal sequentially output from the shift register using a plurality of series of enable signals and outputs the shaped signal, and the shaping signal or a sampling circuit drive signal based on the shaped signal And a sampling circuit that samples the image signal and supplies it to the data line.

  In an image signal supply circuit, depending on the logical product or logical sum of circuit elements constituting the image signal supply circuit, or the characteristics of the circuit elements themselves, signal delays or signal potential deviations occur.

  Here, the electro-optical device to be inspected by the inspection method for the electro-optical device according to the present invention includes a monitor circuit. The monitor circuit includes at least a part of the image signal supply circuit, for example, one part of the plurality of stages of the shift register in the image signal supply circuit and a part provided corresponding to the one of the other circuits. Simulated. Therefore, the monitor circuit, for example, the pseudo sampling circuit drive signal output from the enable circuit included in the image signal supply circuit or the pseudo output of the sampling circuit included in the image signal supply circuit. A signal that simulates a signal output from a part of the image signal supply circuit, such as an image signal, can be output.

  For such a monitor circuit, for example, by inputting a predetermined pulse and indirectly measuring a signal delay or a signal potential shift in the image signal supply circuit based on a signal output from the monitor circuit, When inspecting the image signal supply circuit, the signal output from the monitor circuit includes noise such as overshoot, so it is difficult to accurately measure the potential of the signal output from the monitor circuit. There is a risk that the inspection accuracy may be lowered.

  However, in the present invention, in particular, a high power supply potential is input to the monitor circuit, and an output signal output from the monitor circuit is detected as the first inspection signal. Further, before or after the step of detecting the first inspection signal, a low power supply potential is input to the monitor circuit, and an output signal output from the monitor circuit is detected as a second inspection signal. Here, the high power supply potential and the low power supply potential are power supply potentials that define the pulse height of the transfer start pulse of the shift register, and are signals having a fixed potential (that is, a constant potential) with respect to time. Therefore, the first and second inspection signals include little or no noise such as overshoot as compared with the output signal from the monitor circuit when a transfer start pulse is input as a predetermined pulse to the monitor circuit, for example. I can't. Accordingly, it is possible to accurately measure the potentials of the first and second inspection signals, and further the signal potential shift in the monitor circuit. Thereby, it is possible to indirectly and accurately measure the deviation of the signal potential in a part of the image signal supply circuit simulated by the monitor circuit.

  As described above, according to the inspection method for an electro-optical device according to the present invention, a signal potential shift in the monitor circuit can be accurately measured with respect to the electro-optical device including the monitor circuit. It is possible to perform a highly accurate inspection.

  In an aspect of the inspection method of the electro-optical device according to the invention, the potential of the first inspection signal is set to the high power supply potential or the low power supply potential based on the first inspection signal and the high power supply potential or the low power supply potential. Based on the step of measuring the first potential deviation amount deviating from the power supply potential, and the second inspection signal and the high power supply potential or the low power supply potential, the potential of the second inspection signal is the high power supply potential or Measuring a second potential shift amount deviating from the low power supply potential.

  According to this aspect, the quality of the image signal supply circuit can be easily determined by comparing the first and second potential deviation amounts with a predetermined reference value or reference range determined in advance. It is possible to easily inspect the supply circuit.

  In the aspect including the step of measuring the first and second potential shift amounts described above, the transfer start pulse is input to the monitor circuit, and an output signal output from the monitor circuit is detected as a third inspection signal. And a step of measuring, based on the transfer start pulse and the third check signal, a signal delay amount by which the third check signal is delayed with respect to the transfer start pulse.

  In this case, the signal delay amount in a part of the image signal supply circuit simulated by the monitor circuit can be indirectly measured, and the inspection accuracy of the image signal supply circuit can be increased.

  In the aspect including the step of measuring the signal delay amount described above, the step of determining whether or not a defect has occurred in the image signal supply circuit based on the first and second potential shift amounts and the signal delay amount. May be included.

  In this case, for example, the accuracy of the inspection of the image signal supply circuit can be improved as compared with the case where it is determined whether or not a defect has occurred in the image signal supply circuit based only on the signal delay amount.

  In order to solve the above problems, a method for manufacturing an electro-optical device according to the present invention includes a step of inspecting an electro-optical device using the above-described inspection method (including various aspects) of the electro-optical device according to the present invention. Including.

  According to the electro-optical device manufacturing method of the present invention, since the inspection accuracy in the inspection process of the electro-optical device is improved, the rate of non-defective electro-optical devices to be sent to the subsequent process is improved, and wasteful man-hours are reduced. It can be omitted. Or the non-defective product rate of the product shipped improves, and it is effective in the improvement of reliability.

  In another aspect of the method for manufacturing an electro-optical device according to the invention, the step of receiving the electro-optical device in a mounting case is included, and the inspecting step is performed after the step of storing in the mounting case.

  According to this aspect, the step of inspecting the electro-optical device using the above-described inspection method for the electro-optical device according to the present invention is preferably performed after the electro-optical device is accommodated in the mounting case. It is performed in the process as late as possible (in other words, immediately before being shipped as a product). Thus, for example, when the electro-optical device is assembled, the image signal supply circuit and the monitor circuit are deteriorated or destroyed by static electricity generated around the electro-optical device during other inspections or transportation, The situation where the electro-optical device is shipped as a product can be avoided more reliably.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this embodiment, an example in which the electro-optical device inspection method and the electro-optical device manufacturing method according to the invention are applied to a liquid crystal device that is an example of an electro-optical device.
<Electro-optical device inspection method>
An inspection method for the liquid crystal device according to the present embodiment will be described with reference to FIGS.

  First, an overall configuration of a liquid crystal device to which a liquid crystal device inspection method according to the present embodiment is applied will be described with reference to FIG. FIG. 1 is a block diagram showing the overall configuration of a liquid crystal device to which the liquid crystal device inspection method according to this embodiment is applied.

  As shown in FIG. 1, the liquid crystal device 1 includes a liquid crystal panel 100, a timing control circuit 200, and an image signal processing circuit 300 as main parts.

  The timing control circuit 200 and the image signal processing circuit 300 are built in an external circuit formed on a wiring substrate including a flexible substrate, for example, as an FPC (Flexible Printed Circuit). The external circuit is electrically connected to an external circuit connection terminal 102, which will be described later, and is mounted on the liquid crystal panel 100.

  The timing control circuit 200 is configured to output various timing signals used in the drive circuit 120. As will be described in detail later with reference to FIG. 4, a timing signal output circuit unit that is a part of the timing control circuit 200 generates a dot clock for scanning each pixel, which is a minimum unit clock. Based on the clock, a Y clock signal CLY, an inverted Y clock signal CLYinv, an X clock signal CLK, an inverted X clock signal CLXinv, a Y start pulse DY, and an X start pulse DX are generated.

  When the image signal processing circuit 300 receives one system of the image signal VID, the image signal processing circuit 300 serial-parallel converts the image signal VID into 6-phase image signals VID1 to VID6 and outputs the converted signals to the liquid crystal panel 100.

  In the liquid crystal panel 100, an element substrate on which a TFT 116 is formed as a pixel switching element and a counter substrate are pasted with their electrode formation surfaces facing each other with a certain gap therebetween, and liquid crystal is sandwiched between the gaps.

  In the liquid crystal panel 100, a driving circuit 120, a scanning line driving circuit 130, and an image signal supply circuit 101 are arranged in a peripheral region located around the image display region 110 composed of a plurality of pixels arranged on the element substrate. In addition, a monitor circuit 27 is provided. The image signal supply circuit 101 includes a sampling circuit 140 and a data line driving circuit 150.

  In FIG. 1, the monitor circuit 27 is schematically shown as one block as a part of the block diagram, and the configuration and operation thereof will be described later in detail.

  The liquid crystal panel 100 further includes data lines 114 and scanning lines 112 wired vertically and horizontally in an image display area 110 occupying the center of the element substrate, and is arranged in a matrix in each pixel corresponding to the intersections thereof. A pixel electrode 118 and a TFT 116 for controlling the switching of the pixel electrode 118 are provided. The six-phase image signals VID1 to VID6 supplied to the image signal supply line 711 are sampled by the sampling circuit 140 in accordance with the sampling signals S1, S2,..., Sn supplied from the data line driving circuit 150. The data line 114 is supplied.

  The data line 114 to which an image signal is supplied in this way is electrically connected to the source electrode of the TFT 116, while the scanning line 112 to which a scanning signal is supplied is electrically connected to the gate electrode of the TFT 116. In addition, the pixel electrode 118 is connected to the drain electrode of the TFT 116. Each pixel is composed of a pixel electrode 118, a common electrode formed on the counter substrate, and a liquid crystal sandwiched between the two electrodes. As a result, each pixel corresponds to each intersection of the scanning line 112 and the data line 114. Thus, they are arranged in a matrix.

  Note that a storage capacitor 119 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 118 and the counter electrode in order to prevent the held image signal from leaking.

  In FIG. 1, the scanning line driving circuit 130 has a shift register and performs scanning based on the Y clock signal CLY, the inverted Y clock signal CLYinv, the Y start pulse DY, and the like supplied from the timing control circuit 200. A signal is sequentially output to each scanning line 112.

  Here, the configuration of the image signal supply circuit 101 will be described in detail with reference to FIG. FIG. 2 is a circuit diagram showing a part of the image signal supply circuit and the configuration of the monitor circuit according to this embodiment.

  In FIG. 2, the data line driving circuit 150 included in the image signal supply circuit 101 is bidirectional for enabling the data lines 114 to be sequentially driven from the bidirectional direction along the arrangement direction (ie, the X direction in FIG. 2). A shift register 160 is provided. The shift direction in the bidirectional shift register 160 is determined by the direction control signal D. When the direction instruction signal D is at a high level, the bidirectional shift register 160 receives an X start pulse DX as an example of the “transfer start pulse” according to the present invention from the left side in FIG. Each stage SRS (i) of the bidirectional shift register 160 (where i = 1, 2, 3,..., N) is sequentially shifted from left to right (ie, in the X direction) at a timing based on the X clock signal XCLXinv. ) To output transfer signals SR1 to SRn. When the inversion direction control signal Dinv is at a high level, the X start pulse DX is input from the right direction in FIG. 2 of the bidirectional shift register 160 and is sequentially shifted from right to left.

  Further, the data line driving circuit 150 includes an enable circuit provided for each stage SRS (i) of the bidirectional shift register 160. 2 corresponds to the first and second stages of the bidirectional shift register 160 when the X start pulse DX is transferred from the left to the right in the figure. Only the configuration of the enable circuits 170a and 170b is shown. It is assumed that the same enable circuits as those in the first and second stages are provided for the third to nth stages. That is, in the present embodiment, one stage of the data line driving circuit 150 includes one stage of the shift register 160 and an enable circuit. The data line driving circuit 150 may be provided with a buffer circuit, a level shifter circuit, or the like instead of or in addition to these.

  The enable circuits 170a and 170b are composed of NAND circuits 171a and 171b and inverters 172a and 172b. The transfer signals SR1 and SR2 output from the bidirectional shift register 160 are supplied to enable circuits 170a and 170b. Also, one of enable signals ENB1 and ENB2 is input to enable circuits 170a and 170b, respectively. As a result, when the transfer signal SR1 or SR2 is output and the enable signal ENB1 or ENB2 is output, the sampling signal S1 or S2 is supplied to the sampling circuit 140. Then, the image signal VID1 or VID2 is supplied to the data line 114 via the sampling switch 141 to which the sampling signal S1 or S2 is supplied, and the data line 114 is driven.

  The image signals VID1 to VID6 are transmitted from the image signal processing circuit 300 to the image signal line 711 at a timing synchronized with various timing signals such as an X clock signal. In the present embodiment, as described above, the stable output of the image signals VID1 to VID6 is more specifically synchronized with the transmission timing of the image signals VID1 to VID6 to the image signal supply line 711 by the enable signal ENB1 or ENB2. The data line 114 is sometimes controlled to be activated.

  The transfer signals SR1 and SR2 are ANDed with the enable signals ENB1 and ENB2 by the enable circuits 170a and 170b, and then supplied to the sampling circuit 140 as the sampling signals S1 and S2.

  In the data line driving circuit 150, the enable circuits provided from the third stage to the n-th stage are driven in the same manner as the enable circuits 170a and 170b provided in the first and second stages. Sampling signals S 1 to Sn are output from the stage and supplied to the sampling circuit 140.

  The sampling circuit 140 includes a plurality of single-channel TFTs as the sampling switch 141, for example. Then, the sampling circuit 140 samples the image signals VID1 to VID6, which are serially and parallelly developed in six phases, in accordance with the sampling signals S1 to Sn for each data line group including six data lines 114 as one group. And supply. Therefore, in the present embodiment, if attention is paid to one stage of the image signal supply circuit 101, the one stage includes one stage of the data line driving circuit 150 and six sampling switches 141 corresponding to one stage of the data line driving circuit 150. Is done.

  Specifically, in the sampling circuit 140, a sampling switch 141 is provided at one end of each data line 114, and the source electrode of each sampling switch 141 is an image signal line 711 to which any of the image signals VID1 to VID6 is supplied. The drain electrode is connected to the data line 114. In the sampling circuit 140, the sampling signal Si is supplied to the gate electrode of each sampling switch 141 for every six sampling switches 141 corresponding to the data line group.

  In the present embodiment, for example, the sampling signals S1 to Sn are sequentially applied to each sampling switch 141 along the arrangement direction of the data lines 114 so that the data lines 114 are driven line-sequentially along the arrangement direction. May be supplied. In this case, the image signals VID1 to VID6 are supplied to the image signal line 711 at the sequentially shifted timing.

  Next, the operation of the image signal supply circuit 101 will be described with reference to FIGS. FIG. 3 is a timing chart showing changes over time of various signals related to the image signal supply circuit according to the present embodiment.

  As shown in FIG. 3, in the data line driving circuit 150 included in the image signal supply circuit 101, the X start pulse DX input to the bidirectional shift register 160 is generated by the X clock signal CLX and the inverted X clock signal CLXinv. Transfer signals SR1 to SRn, which are shifted in half cycle units of the clock signal and delayed by half cycle of the clock signal, are sequentially output from each stage of the bidirectional shift register 160.

  The transfer signals SR1 to SRn are ANDed with the enable signal ENB1 or ENB2 by the enable circuit of the data line driving circuit 150 in order to synchronize the driving period of the data line 114 with the stable output period of the image signals VID1 to VID6. Are output as sampling signals S1 to Sn.

  As a result, the transmission timing of the image signals VID1 to VID6 can be synchronized with the sampling signal Si, and if the synchronization of the sampling hold timing in the sampling switch 141 and the transmission timing of the image signals VID1 to VID6 can be ensured, display defects are caused. Generation of high quality images can be prevented.

  In the above description, an example in which two types of enable signals ENB1 and ENB2 are supplied to the image signal supply circuit 101 has been described, but sampling may be performed with one type or three or more types of ENB signals.

  Next, the configuration and operation of the above-described timing control circuit 200 will be described in detail with reference to FIG. 4 in addition to FIG. FIG. 4 is a circuit diagram showing the configuration of the timing control circuit according to this embodiment.

  As shown in FIG. 4, the timing control circuit 200 includes a timing signal output circuit unit 200a and a timing adjustment circuit unit 200b.

  The timing signal output circuit unit 200 a includes an oscillation circuit 21, a counter 22, and a decoder 23. The oscillation circuit 21 outputs a clock signal OSCI having a frequency several times that of the dot clock DC. The counter 22 is reset in synchronization with the rising edge of the horizontal synchronization signal HSYNC. After the reset, the counter 22 counts the number of pulses of the clock signal OSCI from the initial value. Here, the counter 22 is provided with an initial value input terminal INIT for inputting an initial value of the count value when reset. The decoder 23 decodes the output value of the counter 22, and performs dot clock DC, X start pulse DX and Y start pulse DY, X clock signal CLX and Y clock signal CLY, and inverted X clock signal CLXinv and inverted Y clock signal. Various timing signals such as CLYinv are output.

  The timing adjustment circuit unit 200 b includes a register 25 and a counter 26. The counter 26 starts counting the clock signal OSCI when the X start pulse DX is input to its input terminal START, and counts when the monitor signal MON described later is input from the monitor circuit 27 to the input terminal STOP. Terminate.

  Thus, the delay amount of the output timing of the monitor signal MON with respect to the output timing of the X start pulse DX is measured with reference to the clock signal OSCI that determines the rising and falling cycles of the X clock signal CLX and the inverted X clock signal CLXinv. It becomes possible. The delay amount of the output timing of the monitor signal MON indirectly indicates the delay amount of the output timing of the image signals VID1 to VID6 in at least one stage of the image signal supply circuit 101 by the configuration and function of the monitor circuit 27 described later. Is. The initial value in the counter 22 is preset based on the delay amount of the output timing of the monitor signal MON, and the timing signals such as the dot clock DC, X start pulse DX, and X clock signal CLX output from the decoder 23 are the monitor signal. It is output at an earlier timing by a time corresponding to the delay amount of the output timing of MON. Thereby, the output timing of the image signals VID1 to VID6 in the image signal supply circuit 101 is adjusted.

  The register 25 is a storage means, and latches the count result of the counter 26 in synchronization with the vertical synchronization signal VSYNC.

  Next, the configuration of the monitor circuit 27 described above will be described in detail with reference to FIGS.

  In FIG. 1, the monitor circuit 27 is provided for indirectly monitoring the output timing of the image signals VID <b> 1 to VID <b> 6 in the image signal supply circuit 101. In a plurality of stages of the image signal supply circuit 101, a logical product by circuit elements constituting each stage of the data line driving circuit 150, characteristics of the circuit elements themselves, characteristics of the sampling switch 141 in the sampling circuit 140, etc. Signal delay occurs, and the output timing of the image signals VID1 to VID6 may be delayed from the timing based on the X clock signal CLX.

  As shown in FIG. 2, the monitor circuit 27 is configured to simulate one stage of the image signal supply circuit 101. That is, the monitor circuit 27 includes a simulation circuit 271 including a unit circuit 271a for simulating one stage of the shift register 160 of the data line driving circuit 150 and a unit circuit 271b for simulating an enable circuit corresponding to the one stage, It has six switching elements 272 that simulate the sampling switch 114 corresponding to one stage of the line driving circuit 150. Here, in FIG. 2, for the sake of simplicity, one of the six switching elements 272 is shown, and the other five are not shown. The configuration of the monitor circuit 27 according to FIG. 5 described later is also the same as that of FIG.

  The main part of the unit circuit 271a in the simulation circuit 271 has a configuration including a NAND circuit 71 and a NOR circuit 72, and the unit circuit 271b includes two inverters 73b and 73c. In addition, the switching element 272 is formed by, for example, a single channel TFT. The switching element 272 may be formed of, for example, an n-channel type or a p-channel type TFT corresponding to the configuration of the TFT forming the sampling switch 141. As a result, the configuration of the monitor circuit 27 can be brought close to the configuration of each stage of the image signal supply circuit 101 simulated by the monitor circuit 27, and as a result, monitoring using the monitor circuit 27 can be performed with higher accuracy. Is possible.

  Therefore, the monitor circuit 27 can simulate the operation of one stage of the data line driving circuit 150 and the sampling switch 141 corresponding to the one stage simulated by the monitor circuit 27. Therefore, by operating the monitor circuit 27 and measuring the output timing of the monitor signal MON, the output of the image signals VID1 to VID6 based on the signal delay in one stage of the data line driving circuit 150 and the sampling switch 141 corresponding to the one stage. Timing can be measured indirectly.

  Next, the operation of the monitor circuit 27 configured as described above will be described with reference to FIG. 5 in addition to FIGS. FIG. 5A is a diagram schematically showing changes in the signal waveform in the monitor circuit, and FIG. 5B is a diagram schematically showing the signal waveform of the monitor signal.

  5A, when the liquid crystal device 1 is driven, the X start pulse DX is input to the monitor circuit 27 at a timing substantially coincident with the timing input to the shift register 160. In the simulation circuit 271 of the monitor circuit 27, the NAND circuit 71 of the unit circuit 271a is supplied with the high power supply potential VDDX by electrically connecting one of the two input terminals to the high potential power supply of the image signal supply circuit 101. The X start pulse DX is input to the other side.

  Here, in FIG. 5A, signal waveforms at respective parts of the monitor circuit 27 are schematically shown on the right side of the circuit diagram showing the configuration of the monitor circuit 27. The X start pulse DX is inverted and output by the logical product of the NAND circuit 71 and input to the NOR circuit 72 of the unit circuit 271a. Here, the output signal of the NAND circuit 71 is input to one of the two input terminals of the NOR circuit 72, and the other is electrically connected to the low potential power source of the image signal supply circuit 101 via the inverter 73a. Thus, the low power supply potential VSSX is supplied. The output signal of the NAND circuit 71 is further inverted by the logical sum of the NOR circuit 72 and output.

  The output signal of the NOR circuit 72 is further inverted and output by the two inverters 73b and 73c of the unit circuit 271b. That is, the X start pulse DX is inverted and output four times in the simulation circuit 271 and input to the gate of the switching element 272, and the switching element 272 is turned on.

  Here, the source of the switching element 272 is electrically connected to the low-potential power supply of the image signal supply circuit 101 so that the low power supply potential VSSX is supplied, and when the switching element 272 is turned on, the source is directed toward the source. When the current flows, the monitor signal MON is output to the monitoring terminal 29 as a falling signal as shown in FIG. As shown in FIG. 1, the monitor signal MON output from the monitoring terminal 29 is input to the timing control circuit 200, and the delay amount of the output timing of the monitor signal MON with respect to the output timing of the X start pulse DX is measured. By outputting the monitor signal MON as a falling signal, the signal waveform is prevented from being rounded and the delay amount of the output timing of the monitor signal MON is measured more accurately than when the monitor signal MON is output as a rising signal. It becomes possible.

  Next, an inspection method for the liquid crystal device according to the present embodiment will be described with reference to FIGS. FIG. 6 is a flowchart showing the inspection flow of the image signal supply circuit using the monitor circuit. FIG. 7 to FIG. 9 are schematic diagrams for explaining the inspection of the image signal supply circuit using the monitor circuit. FIG. 7A is an input to the monitor circuit and the monitor circuit in each process at the time of inspection. FIG. 4B is a diagram schematically showing signal waveforms of an input signal to the monitor circuit and an inspection signal from the monitor circuit in each step during inspection.

  As described above with reference to FIGS. 1 to 5, the liquid crystal device 1 includes the monitor circuit 27, and the monitor circuit 27 is a part of the image signal supply circuit 101 (more specifically, the shift register 160. And a sampling switch 114) corresponding to one stage of the data line driving circuit 150, and an enable circuit corresponding to the one stage. Therefore, the monitor circuit 27 can output a signal that simulates a signal output from a part of the image signal supply circuit 101.

  Therefore, in the inspection method for the liquid crystal device according to the present embodiment, the image signal supply circuit 101 using the monitor circuit 27 is inspected as shown in FIG.

  In FIG. 6, in the inspection of the image signal supply circuit 101 using the monitor circuit 27, first, the X start pulse DX is input to the monitor circuit 27, and the inspection signal CK1 is detected from the monitor circuit 27 (step S10). That is, as shown in FIG. 7A, the X start pulse DX defined by the low power supply potential VSSX and the high power supply potential VDDX is input to the monitor circuit 27 as in the case of normal driving, and the monitor circuit 27 An output signal output from the monitoring terminal 29 via the monitoring terminal 29 is detected as the inspection signal CK1. The detection of the inspection signal CK1 is performed using a measuring instrument such as an oscilloscope that is electrically connected to the monitoring terminal 29. The inspection signal CK1 is an example of the “third inspection signal” according to the present invention.

  Next, in FIG. 6, the signal delay in the monitor circuit 27 is measured (step S20). That is, as shown in FIG. 7B, the signal delay amount t <b> 1 that the inspection signal CK <b> 1 detected in the step S <b> 10 is delayed with respect to the X start pulse DX input to the monitor circuit 27 is measured. The measurement of the signal delay amount t1 is performed using a measuring instrument such as an oscilloscope that is electrically connected to the monitoring terminal 29. By measuring the signal delay amount t1, the signal delay amount in a part of the image signal supply circuit 101 simulated by the monitor circuit 27 can be indirectly measured.

  Next, in FIG. 6, the high power supply potential VDDX is input to the monitor circuit 27, and the inspection signal CK2 is detected from the monitor circuit 27 (step S30). That is, as shown in FIG. 8A, the high power supply potential VDDX is input to the monitor circuit 27, and the output signal output from the monitor circuit 27 via the monitor rig terminal 29 is detected as the inspection signal CK2. The inspection signal CK2 is detected using a measuring instrument such as an oscilloscope that is electrically connected to the monitoring terminal 29. The inspection signal CK2 is an example of the “first inspection signal” according to the present invention.

  Next, in FIG. 6, the signal potential shift in the monitor circuit 27 is measured (step S40). That is, as shown in FIG. 8B, the potential deviation amount ΔVL2 in which the inspection signal CK2 detected by the process according to step S30 deviates from the low power supply potential VSSX is measured. The potential deviation amount ΔVL <b> 2 is measured using a measuring instrument such as an oscilloscope that is electrically connected to the monitoring terminal 29. By measuring the potential deviation amount ΔVL2, the deviation of the signal potential in a part of the image signal supply circuit 101 simulated by the monitor circuit 27 can be indirectly measured. Here, in particular, the inspection signal CK2 contains little or no noise such as overshoot, as compared with the inspection signal CK1 detected by the process according to step S10, for example. That is, the high power supply potential VDDX input to the monitor circuit 27 in the process related to step S30 is not a pulse signal having a portion where the potential changes abruptly like the X start pulse DX, but a potential fixed with respect to time. Therefore, there is little or no noise such as overshoot. Therefore, the potential deviation amount ΔVL2 (that is, the signal potential deviation in the monitor circuit 27) can be easily and accurately measured. Accordingly, it is possible to indirectly accurately measure the signal potential shift in a part of the image signal supply circuit 101 simulated by the monitor circuit 27.

  In FIG. 7B, the potential deviation amount ΔVL1 in which the low potential side potential VL1 in the inspection signal CK1 detected by the process related to step S30 is shifted from the low power supply potential VSSX without taking any countermeasure. In addition, when measuring the potential deviation amount ΔVH1 in which the high potential side potential VH1 in the inspection signal CK1 deviates from the high power supply potential VDDX, the potential deviation amount ΔVL1 is caused by noise such as overshoot included in the inspection signal CK1. It is difficult to accurately measure ΔVH1.

  Next, in FIG. 6, the low power supply potential VSSX is input to the monitor circuit 27, and the inspection signal CK3 is detected from the monitor circuit 27 (step S50). That is, as shown in FIG. 9A, the low power supply potential VSSX is input to the monitor circuit 27, and the output signal output from the monitor circuit 27 via the monitor rig terminal 29 is detected as the inspection signal CK3. The detection of the inspection signal CK3 is performed using a measuring instrument such as an oscilloscope that is electrically connected to the monitoring terminal 29.

  Next, in FIG. 6, the signal potential shift in the monitor circuit 27 is measured (step S60). That is, as shown in FIG. 9B, the potential deviation amount ΔVH2 that the inspection signal CK3 detected by the process according to step S50 deviates from the high power supply potential VDDX is measured. The potential deviation amount ΔVH2 is measured by using a measuring instrument such as an oscilloscope that is electrically connected to the monitoring terminal 29. By measuring the potential deviation amount ΔVH2, the signal potential deviation in a part of the image signal supply circuit 101 simulated by the monitor circuit 27 can be indirectly measured. Here, in particular, the inspection signal CK3 includes little or no noise such as overshoot, as compared with the inspection signal CK1 detected by the process according to step S10, for example. Therefore, the potential deviation amount ΔVH2 (that is, the signal potential deviation in the monitor circuit 27) can be easily and accurately measured. Accordingly, it is possible to indirectly accurately measure the signal potential shift in a part of the image signal supply circuit 101 simulated by the monitor circuit 27.

  Next, in FIG. 6, based on the signal delay and the signal potential shift in the monitor circuit 27, it is determined whether or not a problem has occurred in the image signal supply circuit 101 (step S70). That is, the signal delay amount t1 (see FIG. 7B) measured by the process according to step S20, the potential shift amount ΔVL2 (see FIG. 8B) measured by the process according to step S40, and the step S60. Based on the potential deviation amount ΔVH2 measured in the process (see FIG. 9B), it is determined whether or not a defect has occurred in the image signal supply circuit 101 (in other words, whether the image signal supply circuit 101 is good or bad). inspect). Specifically, the quality of the image signal supply circuit 101 is inspected by comparing each of the signal delay amount t1 and the potential deviation amounts ΔVL2 and ΔVH2 with a predetermined reference value or reference range set in advance. For example, the signal delay amount t1 is within the predetermined reference range of 40 ns to 120 ns, the potential shift amount ΔVL2 is smaller than the predetermined reference value 1.0V, and the potential shift amount ΔVH2 is If it is smaller than the predetermined reference value 0.7V, it is determined that no problem has occurred in the image signal supply circuit 101, and at least one of the signal delay amount t1, the potential deviation amounts ΔVL2 and ΔVH2 is the predetermined reference value. If it is out of range or greater than a predetermined reference value, it is determined that a problem has occurred in the image signal supply circuit 101. Here, in the present invention, in particular, the quality of the image signal supply circuit 101 is inspected based on the potential deviation amounts ΔVL2 and ΔVH2 in addition to the signal delay amount t1, and therefore, the image is assumed to be based only on the signal delay amount t1. Compared with the case of inspecting the quality of the signal supply circuit 101, the inspection accuracy can be increased. Further, in the present invention, in particular, since the potential deviation amounts ΔVL2 and ΔVH2 are measured, it is only determined whether the image signal supply circuit 101 is good or bad, and it is determined that no defect has occurred in the image signal supply circuit 101. It is also possible to detect a margin or margin until a problem occurs in the image signal supply circuit 101.

  As described above, according to the inspection method of the liquid crystal device according to the present embodiment, the signal potential shift in the monitor circuit 27 can be accurately measured with respect to the liquid crystal device 1 provided with the monitor circuit 27. It becomes possible to perform a highly accurate inspection of the device 1.

Further, in the present embodiment, since it is determined whether or not a defect has occurred in the image signal supply circuit 101 based on the signal delay amount t1 and the potential deviation amounts ΔVL2 and ΔVH2, the accuracy of the inspection of the image signal supply circuit 101 is determined. Can be further increased.
<Method of manufacturing electro-optical device>
A method for manufacturing the electro-optical device according to the present embodiment will be described with reference to FIGS.

  First, a specific overall configuration of the liquid crystal device 1 described above will be described with reference to FIGS. 10 and 11. FIG. 10 is a plan view of the TFT array substrate 10 as viewed from the counter substrate 20 side together with the components formed thereon, and FIG. 11 is a cross-sectional view taken along the line H-H ′ of FIG. 10.

  10 and 11, a TFT array substrate 10 as an element substrate and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are provided with a sealing material 52 provided in a seal region located around the image display region 110. Are bonded to each other.

  In FIG. 10, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 110 is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed.

  An image signal supply circuit 101 and an external circuit connection terminal 102 for driving the data line 114 by supplying an image signal to the data line 114 at a predetermined timing are provided in an area located outside the seal area where the seal material 52 is disposed. It is provided along one side of the TFT array substrate 10. A scanning line driving circuit 130 that drives the scanning line 112 by supplying a scanning signal to the scanning line 112 at a predetermined timing is provided along one of the two sides adjacent to the one side. Note that when the delay of the scanning signal supplied to the scanning line 112 becomes a problem, the scanning line driving circuit 130 is adjacent to one side of the TFT array substrate 10 provided with the image signal supply circuit 101 and the external circuit connection terminal 102. It may be provided along two sides. In this case, the two scanning line driving circuits 130 are connected to each other by a plurality of wirings provided along the remaining one side of the TFT array substrate 10. Alternatively, the image signal supply circuit 101 may be arranged on both sides of the image display area 110.

  On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with a vertical conduction material are disposed in regions facing the four corners of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  In FIG. 11, on the TFT array substrate 10, although not shown here, the pixel switching TFT 116, the scanning line 112, the data line 114, and the like described above with reference to FIG. A structure is formed. In the image display region 110, pixel electrodes 118 made of a transparent material such as ITO (Indium Tin Oxide) are provided in a matrix on the upper layer of wiring such as the TFT 116, the scanning line 112, and the data line 114. An alignment film is formed on the pixel electrode 118. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. The light shielding film 23 is formed of, for example, a light shielding metal film or the like, and is patterned in, for example, a lattice shape in the image display region 110 on the counter substrate 20. A counter electrode 21 made of a transparent material such as ITO is formed in a solid shape on the light shielding film 23 so as to face the plurality of pixel electrodes 118. An alignment film is formed on the counter electrode 21. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  On the TFT array substrate 10, in addition to the image signal supply circuit 101, the scanning line driving circuit 130, and the like, a precharge signal having a predetermined voltage level is supplied to a plurality of data lines 114 in advance of the image signal. A precharge circuit, an inspection circuit for inspecting the quality, defects, etc. of the electro-optical device during manufacture or at the time of shipment may be formed.

  Further, for example, a TN (Twisted Nematic) mode, an STN (Super Twisted Nematic) mode, a VA (Vertically Aligned) mode, Depending on the operation mode such as PDLC (Polymer Dispersed Liquid Crystal) mode and the normally white mode / normally black mode, a polarizing film, a retardation film, a polarizing plate and the like are arranged in a predetermined direction.

  The liquid crystal device 1 described above is applied to, for example, a projector. In this case, three liquid crystal devices are used as light valves for the three primary colors of RGB. Thus, when the liquid crystal device 1 is used as a light valve in a projector, the liquid crystal device 1 is mounted on the projector in a state of being housed in a mounting case as described below. In addition, the manufacturing method of the liquid crystal device according to the present embodiment manufactures the liquid crystal device 1 as a mounting case-containing liquid crystal device housed in a mounting case.

  FIG. 12 is an exploded perspective view showing the mounting case together with the liquid crystal device.

  In FIG. 12, the liquid crystal device 1 is housed in a mounting case 601 and mounted on an electronic device such as a projector.

  As shown in FIG. 12, an FPC 501 is connected to the external circuit connection terminal 102 on the TFT array substrate 10. In addition to the drive circuit 120 that is a built-in circuit on the TFT array substrate 10, an external circuit including the timing control circuit 200 and the image signal processing circuit 300 is formed on the FPC 501. Each of the TFT array substrate 10 and the counter substrate 20 is provided with an optical member such as an antireflection plate on the outer surface. However, the polarizing plate, the retardation film, and the like may be attached to the outer surfaces of the TFT array substrate 10 and the counter substrate 20, but may be provided in, for example, a projector optical system on which the liquid crystal device 1 is mounted.

  As shown in FIG. 12, the mounting case 601 includes a frame 610 that houses the liquid crystal device 1 and a cover member 620 that covers the frame 610. The liquid crystal device 1 is accommodated in a direction in which the counter substrate 20 side faces the frame 610, and the outer surface on the TFT array substrate 10 side is covered with a cover member 620.

  The liquid crystal device 1 is fixed by being bonded to the frame 610 with an adhesive while being surrounded by the frame 610 from the peripheral edge side, and is accommodated in the frame 610. Therefore, the liquid crystal device 1 is surrounded by the frame 610 from the peripheral side.

  The frame 610 and the cover member 620 are provided with window portions 610h and 620h opened in these members. The window portions 610h and 620h are disposed on the frame 610 and the cover member 620 corresponding to the position of the image display area 110 in a state where the liquid crystal device is accommodated in the mounting case 601. As a result, in the liquid crystal device, the peripheral area located around the image display area 110 is covered in a frame shape by the frame 610 and the cover member 620.

  When the liquid crystal device is housed in the mounting case 601 and mounted on, for example, a liquid crystal projector and used as a liquid crystal light valve, for example, projection light is incident from the frame 610 side and passes through the image display area 110 of the liquid crystal device 1. The light is emitted from the cover member 620 side. In this case, since the peripheral area in the liquid crystal device 1 is covered with the frame light shielding film 53 provided on the mounting case 601 and the counter substrate 20, it is difficult for incident light to enter the peripheral area.

  On the other hand, when return light is incident on the liquid crystal device 1 such as back surface reflection on the TFT array substrate 10 or light emitted from another liquid crystal device 1 by a multi-plate projector or the like and penetrating the composite optical system. There is. Such return light can also be shielded by the mounting case 601, and is difficult to be incident on the peripheral region of the liquid crystal device 1.

  Therefore, the mounting case 601 and the frame light shielding film 53 can prevent light from leaking in the peripheral region of the liquid crystal device 1 or prevent stray light from entering the image display region 10a from the peripheral region.

  Next, a manufacturing method of the liquid crystal device according to the present embodiment will be described with reference to FIG. FIG. 13 is a flowchart for explaining each step of the manufacturing process of the liquid crystal device according to this embodiment. In the present embodiment, the liquid crystal device 1 is manufactured as a mounting case-containing liquid crystal device housed in a mounting case as described above with reference to FIG.

  First, in FIG. 13, various components such as the data line 114, the scanning line 112, the TFT 116, and the pixel electrode 118 are formed on the TFT array substrate 10, and the light shielding film 23 and the frame light shielding film 53 are formed on the counter substrate 20. After forming various components such as the counter electrode 21, the TFT array substrate 10 and the counter substrate 20 are bonded to each other through the sealing material 52 so that the pixel electrode 118 and the counter electrode 21 face each other. The apparatus 1 is manufactured (step S110).

  Next, in FIG. 13, the liquid crystal device 1 is accommodated in the mounting case 601 (step S120).

  Next, in FIG. 13, in a state where the liquid crystal device 1 is accommodated in the mounting case 601, it is inspected whether the light transmittance, contrast, and the like in the liquid crystal device 1 satisfy predetermined standards (step S <b> 130). .

  Next, in FIG. 13, in the state where the liquid crystal device 1 is accommodated in the mounting case 601, the image signal supply circuit 101 using the monitor circuit 27 is inspected for the liquid crystal device 1 (step S140). In other words, in a state where the liquid crystal device 1 is accommodated in the mounting case 601, an inspection is performed using the inspection method described in detail with reference to FIGS. Thereafter, the liquid crystal device 1 determined as a non-defective product is shipped or stored as a product.

  Here, particularly in the present embodiment, the inspection process (step S140) for inspecting the image signal supply circuit 101 using the monitor circuit 27 is performed after the process (step S120) of housing the liquid crystal device 1 in the mounting case 601 (further, Is performed after the step of inspecting the light transmittance and contrast of the liquid crystal device 1 (after step S130), in other words, as far as possible in the manufacturing process of the liquid crystal device 1. Therefore, for example, the state in which the image signal supply circuit 101 and the monitor circuit 27 are deteriorated or destroyed by static electricity generated around the liquid crystal device 1 when the liquid crystal device 1 is assembled, at the time of other inspections or during transportation. Thus, the situation where the liquid crystal device 1 is shipped as a product can be avoided more reliably.

  In the above-described embodiment of the present invention, the liquid crystal device has been described as an example. However, the liquid crystal device to which the present invention is applicable includes a reflective liquid crystal device (LCOS) using a semiconductor substrate.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and an electro-optical device with such a change. The inspection method and the manufacturing method of the electro-optical device including the inspection method are also included in the technical scope of the present invention.

It is a block diagram which shows the whole structure of the liquid crystal device to which the test | inspection method of the liquid crystal device which concerns on this embodiment is applied. It is a circuit diagram which shows a part of image signal supply circuit which concerns on this embodiment, and the structure of a monitor circuit. 6 is a timing chart showing changes with time of various signals related to the image signal supply circuit according to the present embodiment. It is a circuit diagram which shows the structure of the timing control circuit which concerns on this embodiment. FIG. 5A is a diagram schematically showing changes in the signal waveform in the monitor circuit, and FIG. 5B is a diagram schematically showing the signal waveform of the monitor signal. It is a flowchart which shows the flow of a test | inspection of the image signal supply circuit using a monitor circuit. FIG. 5 is a schematic diagram (part 1) for explaining an inspection of an image signal supply circuit using a monitor circuit. FIG. 10 is a schematic diagram (part 2) for explaining the inspection of the image signal supply circuit using the monitor circuit. FIG. 10 is a schematic diagram (part 3) for explaining the inspection of the image signal supply circuit using the monitor circuit. It is a top view which shows the whole structure of the liquid crystal device in this embodiment. It is H-H 'sectional drawing of FIG. It is a disassembled perspective view which shows a mounting case with a liquid crystal device. It is a flowchart for demonstrating each process of the manufacturing process of the liquid crystal device which concerns on this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... TFT array substrate, 20 ... Counter substrate, 27 ... Monitor circuit, 101 ... Image signal supply circuit, 150 ... Data line drive circuit, 140 ... Sampling circuit, 160 ... Shift register, CK1, CK2, CK3 ... Inspection signal, DX ... X start pulse, VDDX ... high power supply potential, VSSX ... low power supply potential

Claims (6)

On the board
A plurality of pixel portions;
A plurality of data lines and a plurality of scanning lines electrically connected to the pixel portion;
(I) A transfer start pulse having a pulse height defined by a high power supply potential higher than a predetermined potential and a low power supply potential lower than the predetermined potential is sequentially transferred, and a transfer signal is sequentially output from each of a plurality of stages. And (ii) an image signal supply circuit comprising: another circuit for supplying an image signal to the plurality of data lines based on the sequentially output transfer signals;
An inspection method for an electro-optical device for inspecting an electro-optical device provided with a monitor circuit that simulates at least a part of the image signal supply circuit,
Inputting the high power supply potential to the monitor circuit and detecting an output signal output from the monitor circuit as a first inspection signal;
An inspection method for an electro-optical device, comprising: inputting the low power supply potential to the monitor circuit; and detecting an output signal output from the monitor circuit as a second inspection signal. A step of measuring a first potential shift amount in which the potential of the first inspection signal is deviated from the high power supply potential or the low power supply potential based on the first inspection signal and the high power supply potential or the low power supply potential. When,
A step of measuring a second potential shift amount in which the potential of the second inspection signal deviates from the high power supply potential or the low power supply potential based on the second inspection signal and the high power supply potential or the low power supply potential. The method for inspecting an electro-optical device according to claim 1, further comprising: Inputting the transfer start pulse to the monitor circuit and detecting an output signal output from the monitor circuit as a third inspection signal;
The method according to claim 2, further comprising: measuring a signal delay amount that the third inspection signal is delayed with respect to the transfer start pulse based on the transfer start pulse and the third inspection signal. Inspection method of electro-optical device.   4. The electricity according to claim 3, further comprising a step of determining whether or not a defect occurs in the image signal supply circuit based on the first and second potential shift amounts and the signal delay amount. Inspection method for optical devices.   5. A method for manufacturing an electro-optical device, comprising a step of inspecting the electro-optical device using the inspection method according to claim 1. Containing the electro-optical device in a mounting case;
The method of manufacturing an electro-optical device according to claim 5, wherein the inspecting step is performed after the step of housing in the mounting case.

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