JP5407311B2 - Electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  In this type of electro-optical device, for example, a plurality of scanning lines and a plurality of data lines are provided in a pixel region (or pixel array region) on a substrate in order to drive a pixel portion provided for each pixel. . In the peripheral region located around the pixel region on the substrate, for example, a sampling circuit that samples and supplies the image signal to the data line, or the sampling circuit supplies the image signal to the data line. A data line driving circuit that supplies a driving signal or a sampling signal for defining output timing is provided.

  A start pulse and a clock signal are supplied to the data line driver circuit, and in synchronization with the clock cycle of the clock signal, the start pulse is transferred to each stage of the built-in shift register and a transfer signal is output. The output transfer signal is sequentially output as a sampling signal to the sampling circuit via an enable circuit, a buffer circuit, and the like. The sampling circuit samples the image signal according to the sampling signal.

  At this time, due to the signal delay generated in the buffer circuit or the sampling circuit in the data line driving circuit or the sampling circuit, there may be a delay that cannot be ignored on the basis of the clock signal in the timing of supplying the image signal.

  Therefore, for example, in Patent Document 1, a monitor circuit that simulates a data line driving circuit and a sampling circuit is provided on a substrate, and the delay amount of the output timing of the image signal is indirectly determined based on the monitor signal from the monitor circuit. Techniques for measuring are disclosed.

JP 2006-163223 A

  However, the monitor circuit described above is generally formed in the same manner as a plurality of transistors constituting a circuit portion to be simulated in a data line driving circuit or a sampling circuit (for example, each having the same channel width and channel length). It is configured to include the same number of transistors. In this case, there is a technical problem that the area on the substrate only for forming the monitor circuit becomes relatively large, and it is difficult to downsize the electro-optical device.

  The present invention has been made in view of the above-mentioned problems, for example, and can accurately monitor the delay in the output timing of an image signal generated in an image signal supply unit such as a data line driving circuit or a sampling circuit, and is small in size. It is an object of the present invention to provide an electro-optical device suitable for conversion and an electronic apparatus including such an electro-optical device.

In order to solve the above problems, the electro-optical device of the present invention shapes a plurality of data lines provided in an image display area, a shift register that sequentially outputs a transfer signal, and shapes the transfer signal and outputs it as a sampling signal An image signal supply unit including a logic circuit unit that performs sampling, and a sampling circuit that supplies an image signal to the plurality of data lines according to the sampling signal, and a plurality of components constituting at least part of the logic circuit unit A first monitor circuit section including a plurality of first dummy transistors provided corresponding to the first transistors, and a plurality provided corresponding to a plurality of second transistors constituting at least a part of the sampling circuit. a second dummy transistor comprise Naru second monitoring circuit portion and a monitor circuit having the plurality of first dummy transistor, The plurality of second dummy transistors have a channel width smaller than that of the plurality of second transistors, and the channel width is smaller than that of the plurality of first transistors. The channel width of the plurality of first dummy transistors with respect to the channel width of the plurality of first transistors or the number of the plurality of first transistors is formed so that the number is reduced or the number is decreased. The ratio of the number of the first dummy transistors and the ratio of the channel width of the plurality of second dummy transistors to the channel width of the plurality of second transistors or the number of the second dummy transistors with respect to the number of the plurality of second transistors The ratios are equal to each other.

  According to the electro-optical device of the present invention, during the operation, various signals such as an image signal, a clock signal, a control signal, and a power signal are supplied from the external circuit to the image signal supply unit. In parallel with this, for example, various signals such as a clock signal, a control signal, and a power supply signal are supplied from an external circuit to the scanning line driving circuit. Thus, for example, a scanning signal is supplied to the pixel unit via the scanning line, and an image signal is supplied to the pixel unit via the data line by the image signal supply unit. By driving at, active matrix driving is performed. Note that, for example, a plurality of such scanning lines and data lines are wired on the substrate so as to cross each other. Further, such a pixel portion selectively supplies, for example, a pixel electrode and an image signal having a gate connected to the scanning line and supplied from the data line to the pixel portion in accordance with the scanning signal supplied from the scanning line. And a pixel switching transistor. At this time, in the image signal supply unit, for example, the output timing of each image signal in the sampling circuit is basically determined according to the clock signal input to the shift register and the start pulse instructing the start of the transfer operation. Is done. Then, image signals are supplied to the plurality of data lines line-sequentially, or image signals are simultaneously applied to each data line group including N (where N is a natural number of 2 or more) data lines. Is supplied. In any case, in the image signal supply unit, a signal delay occurs due to the logical product or logical sum in the circuit elements constituting the image signal, or the characteristics of the circuit elements themselves, and compared with the timing based on the clock signal and the start pulse. Thus, the output timing of the image signal is delayed more or less.

  Therefore, in the electro-optical device of the present invention, a monitor signal is generated by the monitor circuit during inspection during manufacturing or after completion, inspection after shipment or after use, and actual use. Here, the monitor circuit is formed by simulating at least a part of the image signal supply unit, for example, one stage of the data line driving circuit, and the generated monitor signal is, for example, the start of the data line driving circuit. A pseudo sampling signal that is output at a predetermined timing based on the cycle of the clock signal with respect to the pulse, or a pulse that is supplied at a predetermined timing based on the cycle of the clock signal with respect to the start pulse of the data line driving circuit, for example. This is a signal for monitoring the timing of supplying the image signal in this simulated part, such as the pseudo image signal. The output timing of the image signal can be indirectly monitored by the monitor signal.

  In the present invention, the monitor circuit includes a first monitor circuit unit including a plurality of first dummy transistors and a second monitor circuit unit including a plurality of second dummy transistors.

  The plurality of first dummy transistors included in the first monitor circuit unit are a plurality of transistors for simulating the plurality of first transistors constituting at least a part of the logic circuit unit included in the image signal supply unit. The plurality of second dummy transistors included in the second monitor circuit unit includes a plurality of second transistors (for example, one of a plurality of data line groups included in at least a part of the sampling circuit included in the image signal supply unit. These are a plurality of transistors for simulating N sampling transistors corresponding to the data line group.

  In the present invention, in particular, the plurality of first dummy transistors are formed so as to have a smaller channel width or a smaller number than the plurality of first transistors, and the plurality of second dummy transistors include a plurality of second dummy transistors. The second transistor is formed so as to have a smaller channel width or a smaller number than the second transistor. Further, the ratio of the channel width of the plurality of first dummy transistors to the channel width of the plurality of first transistors, or the ratio of the number of first dummy transistors to the number of the plurality of first transistors, and the channel width of the plurality of second transistors. The ratio of the channel width of the plurality of second dummy transistors or the ratio of the number of second dummy transistors to the number of the plurality of second transistors is equal to each other.

  That is, the channel width or the number of the first and second dummy transistors is set so that any one of the following relational expressions (1) to (4) is established. However, in the following relational expressions (1) to (4), W1 is the channel width of the first transistor, W2 is the channel width of the second transistor, and Wd1 is the channel width of the first dummy transistor. Wd2 is the channel width of the second dummy transistor, N1 is the number of the plurality of first transistors, N2 is the number of the plurality of second transistors, and Nd1 is the number of the first dummy transistors. Nd2 is the number of second dummy transistors.

Wd1 / W1 = Wd2 / W2 (1)
(However, Wd1 <W1, Wd2 <W2, and Nd1 = N1 and Nd2 = N2)
Nd1 / N1 = Nd2 / N2 (2)
(However, Wd1 = W1, Wd2 = W2, Nd1 <N1, and Nd2 <N2)
Wd1 / W1 = Nd2 / N2 (3)
(However, Wd1 <W1, Wd2 = W2, Nd1 = N1, and Nd2 <N2)
Nd1 / N1 = Wd2 / W2 (4)
(However, Wd1 = W1, Wd2 <W2, Nd1 <N1, and Nd2 = N2)
Therefore, the size of the monitor circuit can be reduced or reduced (that is, the monitor circuit can be shrunk), and the delay amount of the signal output from the monitor circuit should be simulated by the monitor circuit in the image signal supply unit. It can be almost or exactly the same as the signal delay in the part. In other words, it is possible to reduce the area on the substrate only for forming the monitor circuit while appropriately maintaining the original function of the monitor circuit that simulates a part of the image signal supply unit. Accordingly, it is possible to accurately monitor the delay of the output timing of the image signal generated in the image signal supply unit, and to locate the peripheral region on the substrate (that is, the periphery of the pixel region provided with a plurality of pixel units). Area) can be narrowed with respect to the pixel area, and the size of the substrate can be reduced without narrowing the pixel area. As a result, the electro-optical device can be reduced in size. By reducing the size of the electro-optical device, the manufacturing cost for manufacturing the electro-optical device can be reduced.

  As described above, according to the electro-optical device of the present invention, the delay of the output timing of the image signal generated in the image signal supply unit can be accurately monitored, and the electro-optical device can be downsized. it can.

  In one aspect of the electro-optical device of the present invention, the number of the plurality of first transistors and the number of the plurality of first dummy transistors are the same, the channel width of the plurality of second transistors, and the plurality of the plurality of first transistors. The channel widths of the second dummy transistors are the same as each other, the ratio of the channel widths of the plurality of first dummy transistors to the channel widths of the plurality of first transistors, and the number of the plurality of second transistors The ratio of the number of the second dummy transistors is equal to each other.

  According to this aspect, for example, each of the plurality of first dummy transistors is formed smaller in the channel width direction (for example, the direction in which the data line extends, that is, the Y direction) than each of the plurality of first transistors. In addition, the plurality of second dummy transistors can be compared with the plurality of second transistors in the direction intersecting the channel width direction (in other words, in the channel length direction, for example, the direction in which the scanning line extends, that is, the X direction). It can be formed small. In other words, the direction in which the plurality of first dummy transistors is reduced with respect to the plurality of first transistors is different from the direction in which the plurality of second dummy transistors is reduced with respect to the plurality of second transistors. In addition, a plurality of first dummy transistors and a plurality of second dummy transistors can be formed. Therefore, a plurality of first dummy transistors and a plurality of second dummy transistors can be laid out relatively easily in a limited area on the substrate.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  According to the electronic apparatus of the present invention, since it includes the electro-optical device of the present invention described above, it can be downsized, a projection display device, a television, a mobile phone, an electronic notebook, a word processor, and a viewfinder type. Alternatively, various electronic devices such as a monitor direct-view video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. In addition, as an electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper, an electron emission device (Field Emission Display and Conduction Electron-Emitter Display), and a display device using these electrophoretic device and electron emission device are realized. Is also possible.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the electro-optical device of the present invention is applied to a TFT active matrix driving type liquid crystal device.

<First Embodiment>
The liquid crystal device according to the present embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIG.

  FIG. 1 is a block diagram showing the overall configuration of the liquid crystal device according to the present embodiment.

  As shown in FIG. 1, the liquid crystal device 1 includes a liquid crystal panel 100, a timing control circuit 200, and an image signal processing circuit 300 as main parts.

  The timing control circuit 200 and the image signal processing circuit 300 are built in an external circuit formed on a wiring substrate including a flexible substrate, for example, as an FPC (Flexible Printed Circuit). The external circuit is electrically connected to an external circuit connection terminal 102, which will be described later, and is mounted on the liquid crystal panel 100.

  The timing control circuit 200 is configured to output various timing signals used in the drive circuit 120. As will be described in detail later with reference to FIG. 5, a timing signal output circuit unit that is a part of the timing control circuit 200 generates a dot clock for scanning each pixel, which is a minimum unit clock. Based on the clock, a Y clock signal CLY, an inverted Y clock signal CLYinv, an X clock signal CLX, an inverted X clock signal CLXinv, a Y start pulse DY, and an X start pulse DX are generated.

  When the image signal processing circuit 300 receives one system of the image signal VID, the image signal processing circuit 300 serial-parallel converts the image signal VID into 6-phase image signals VID1 to VID6 and outputs the converted signals to the liquid crystal panel 100.

  In the liquid crystal panel 100, an element substrate on which a TFT 116 is formed as a pixel switching element and a counter substrate are pasted with their electrode formation surfaces facing each other with a certain gap therebetween, and liquid crystal is sandwiched between the gaps.

  In the liquid crystal panel 100, a driving circuit 120, a scanning line driving circuit 130, and an image signal supply circuit 101 are arranged in a peripheral region located around the image display region 110 composed of a plurality of pixels arranged on the element substrate. In addition, a monitor circuit 27 is provided. The image signal supply circuit 101 includes a sampling circuit 140 and a data line driving circuit 150. The image signal supply circuit 101 is an example of the “image signal supply unit” according to the present invention.

  In FIG. 1, the monitor circuit 27 is schematically shown as one block as a part of the block diagram, and the configuration and operation thereof will be described later in detail.

  The liquid crystal panel 100 further includes data lines 114 and scanning lines 112 wired vertically and horizontally in an image display area 110 occupying the center of the element substrate, and is arranged in a matrix in each pixel corresponding to the intersections thereof. A pixel electrode 118 and a TFT 116 for controlling the switching of the pixel electrode 118 are provided. The six-phase image signals VID1 to VID6 supplied to the image signal supply line 711 are sampled by the sampling circuit 140 in accordance with the sampling signals S1, S2,..., Sn supplied from the data line driving circuit 150. The data line 114 is supplied.

  The data line 114 to which an image signal is supplied in this way is electrically connected to the source electrode of the TFT 116, while the scanning line 112 to which a scanning signal is supplied is electrically connected to the gate electrode of the TFT 116. In addition, the pixel electrode 118 is connected to the drain electrode of the TFT 116. Each pixel is composed of a pixel electrode 118, a common electrode formed on the counter substrate, and a liquid crystal sandwiched between the two electrodes. As a result, each pixel corresponds to each intersection of the scanning line 112 and the data line 114. Thus, they are arranged in a matrix.

  Note that a storage capacitor 119 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 118 and the counter electrode in order to prevent the held image signal from leaking.

  In FIG. 1, the scanning line driving circuit 130 has a shift register and performs scanning based on the Y clock signal CLY, the inverted Y clock signal CLYinv, the Y start pulse DY, and the like supplied from the timing control circuit 200. A signal is sequentially output to each scanning line 112.

  Here, the configuration of the image signal supply circuit 101 will be described in detail with reference to FIG.

  FIG. 2 is a circuit diagram showing the configuration of a part of the image signal supply circuit and the monitor circuit according to the present embodiment.

  In FIG. 2, the data line driving circuit 150 included in the image signal supply circuit 101 is bidirectional for enabling the data lines 114 to be sequentially driven from the bidirectional direction along the arrangement direction (ie, the X direction in FIG. 2). A shift register 160 is provided. The shift direction in the bidirectional shift register 160 is determined by the direction control signal D. When the direction instruction signal D is at a high level, the X shift pulse 160 is input with the X start pulse DX from the left side in FIG. 2, and from left to right at the timing based on the X clock signal CLX and the inverted X clock signal XCLXinv. The signals are sequentially shifted (ie, in the X direction), and transfer signals SR1 to SRn are output from each stage SRS (i) (where i = 1, 2, 3,..., N) of the bidirectional shift register 160. When the inversion direction control signal Dinv is at a high level, the X start pulse DX is input from the right direction in FIG. 2 of the bidirectional shift register 160 and is sequentially shifted from right to left.

  Further, the data line driving circuit 150 includes a logic circuit unit 700 (i) (where i = 1, 2, 3,..., N) provided for each stage SRS (i) of the bidirectional shift register 160. I have. FIG. 2 shows logics corresponding to the first and second stages of the bidirectional shift register 160 when the X start pulse DX is transferred from left to right in the bidirectional shift register 160. Only circuit portions 700 (1) and 700 (2) are shown. Note that the logic circuit 700 (i) similar to the first and second stages is also provided for the third to nth stages. That is, in the present embodiment, one stage of the data line driving circuit 150 includes one stage of the shift register 160 and the logic circuit unit 700 (i).

  FIG. 3 is a circuit diagram showing a configuration of the logic circuit unit according to the present embodiment.

  In FIG. 3, the logic circuit unit 700 (i) includes an enable circuit 400 and a buffer circuit 500.

  The enable circuit 400 includes a NAND circuit 410, a NOR circuit 420, and an inverter 430.

  In the NAND circuit 410, the transfer signal SR (i) output from the bidirectional shift register 160 is input to one of the two input terminals, and the enable signal ENB1 or ENB2 is input to the other of the two input terminals. Entered. The enable signal ENB1 is input to the NAND circuit 410 included in the logic circuit unit 700 (i) (where i = 1, 3, 5,...) Corresponding to the odd-numbered stages of the bidirectional shift register 160. The enable signal ENB2 is input to the NAND circuit 410 included in the logic circuit unit 700 (i) (where i = 2, 4, 6,...) Corresponding to the even-numbered stages of the direction shift register 160.

  In the NOR circuit 420, the output terminal of the NAND circuit 410 is electrically connected to one of the two input terminals, and the output terminal of the inverter 430 is electrically connected to the other of the two input terminals. Yes.

  The inverter 430 is supplied with the low power supply potential VSSX at the input end and is electrically connected to the NOR circuit 420 at the output end.

  Note that each of the NAND circuit 410, the NOR circuit 420, and the inverter 430 includes a plurality of transistors. The channel width W6 of each of the plurality of transistors constituting the NAND circuit 410 is, for example, 40 μm. The channel width W4 of each of the plurality of transistors constituting the NOR circuit 420 is, for example, 40 um. The channel width W5 of each of the plurality of transistors constituting the inverter 430 is, for example, 40 um. The plurality of transistors constituting the NAND circuit 410, the plurality of transistors constituting the NOR circuit 420, and the plurality of transistors constituting the inverter 430 are each an example of “a plurality of first transistors” according to the present invention.

  The buffer circuit 500 is configured by electrically connecting a plurality of inverters. The buffer circuit 500 is driven by the high power supply potential VDDX supplied through the power supply wiring 602 and the low power supply potential VSSX supplied through the power supply wiring 601. More specifically, the buffer circuit 500 is configured by connecting two stages of inverters 501 and 502 in series in the direction along the data line 114 (that is, the Y direction). The input terminal of the inverter 501 is electrically connected to the output terminal of the enable circuit 400 (that is, the output terminal of the NOR circuit 420), and the output terminal of the inverter 502 corresponds to one stage of the bidirectional shift register 160. The six sampling transistors 141 are electrically connected to the gate electrodes. Each of the inverters 501 and 502 includes four inverters connected in parallel in the direction along the scanning line 112 (that is, the X direction). That is, the inverter 501 is configured by connecting inverters 511, 512, 513, and 514 in parallel, and the inverter 502 is configured by connecting inverters 521, 522, 523, and 524 in parallel. As a result, the driving capability of each of the inverters 501 and 502 (ie, one-stage inverter) is enhanced.

  Further, each of the inverters 511 to 514 and 521 to 524 is configured as a complementary transistor in which a P channel type transistor and an N channel type transistor whose channel width direction is formed in the Y direction are combined. That is, each of the inverters 511 to 514 and 521 to 524 includes a P-channel transistor and an N-channel transistor between the lead-out line 610 drawn from the power supply line 601 and the lead-out line 620 drawn from the power supply line 602. Are connected in series. Note that the channel width W3 of each of the plurality of transistors constituting the inverter 501 (that is, the P-channel and N-channel transistors constituting each of the inverters 511 to 514) is, for example, 100 um. The channel width W2 of each of the transistors (that is, the P-channel and N-channel transistors constituting each of the inverters 521 to 524) is, for example, 300 um. Thus, since the channel width W2 of each of the plurality of transistors constituting the inverter 502 is larger than the channel width W3 of each of the plurality of transistors constituting the inverter 501, the buffer circuit 500 as a whole can handle a high load. Thus, the number of sampling transistors 141 that can be driven simultaneously can be increased.

  The channel width W1 of each of the plurality of sampling transistors 141 is, for example, 600 μm.

  When the transfer signal SRi is output and the enable signal ENB1 or ENB2 is output by the logic circuit unit 700 (i) configured as described above, the sampling signal Si is output from the six sampling transistors 141. Supplied to the gate electrode. Then, the image signals VID1 to VID6 are supplied to the data line 114 via the six sampling transistors 141 supplied with the sampling signal Si, and the data line 114 is driven.

  1 and 2 again, the image signals VID1 to VID6 are transmitted from the image signal processing circuit 300 to the image signal line 711 at a timing synchronized with various timing signals such as an X clock signal. In the present embodiment, the data line 114 is connected to the image signal VID1 to VID6 at the stable output in synchronization with the transmission timing of the image signals VID1 to VID6 to the image signal supply line 711 by the enable signal ENB1 or ENB2. Control to activate.

  The transfer signal SRi is logically ANDed with the enable signal ENB1 or ENB2 by the logic circuit unit 700 (i) and then supplied to the sampling circuit 140 as the sampling signal Si.

  In the data line driving circuit 150, the logic circuit unit 700 (i) provided in the i-th stage (where i = 1, 2, 3,..., N) is driven, so that the sampling signal S1 is output from each stage. -Sn is output and supplied to the sampling circuit 140.

  The sampling circuit 140 includes a plurality of sampling transistors 141 as switching elements. The sampling transistor 141 is configured as a single-channel transistor. Then, the sampling circuit 140 performs serial-parallel expansion or serial-parallel conversion into six phases according to the sampling signals S1 to Sn for each data line group including six data lines 114 as one group, that is, a phase. The developed image signals VID1 to VID6 are sampled and supplied. Therefore, in this embodiment, if attention is paid to one stage of the image signal supply circuit 101, the one stage includes one stage of the data line driving circuit 150 and six sampling transistors 141 corresponding to one stage of the data line driving circuit 150. Composed. The six sampling transistors 141 corresponding to one stage of the data line driving circuit 150 are an example of “a plurality of second transistors” according to the present invention. Further, the number of phase expansion of the image signal (that is, the number of series of image signals that are serial-parallel-expanded) is not limited to 6 phases, and is not limited to 9 phases, 12 phases, 24 phases, 48 phases, 96 phases, ... etc. In other words, the number of sampling transistors 141 corresponding to one stage of the data line driving circuit 150 is not limited to 6, and may be 9, 12, 24, 48, 96,. Good.

  Specifically, in the sampling circuit 140, a sampling transistor 141 is provided at one end of each data line 114, and the source electrode of each sampling transistor 141 is an image signal to which any one of the image signals VID1 to VID6 is supplied. The drain electrode is connected to the line 711 and the drain electrode is connected to the data line 114. In the sampling circuit 140, the output terminal of the buffer circuit 500 described above with reference to FIG. 3 is electrically connected to the gate electrode of each sampling transistor 141 for each of the six sampling transistors 141 corresponding to the data line group. Are connected to each other, and a sampling signal Si is supplied.

Next, the operation of the above-described image signal supply circuit 101 will be described with reference to FIGS. 2 to 4. FIG. 4 is a timing chart showing temporal changes of various signals related to the image signal supply circuit according to this embodiment. It is.

  As shown in FIG. 4, in the data line driving circuit 150 included in the image signal supply circuit 101, the X start pulse DX input to the bidirectional shift register 160 is generated by the X clock signal CLX and the inverted X clock signal CLXinv. Transfer signals SR1 to SRn, which are shifted in half cycle units of the clock signal and delayed by half cycle of the clock signal, are sequentially output from each stage of the bidirectional shift register 160.

  The transfer signals SR1 to SRn are logically ANDed with the enable signal ENB1 or ENB2 by the enable circuit 400 of the data line driving circuit 150 in order to synchronize the driving period of the data line 114 with the stable output period of the image signals VID1 to VID6. And output as sampling signals S1 to Sn.

  As a result, the transmission timing of the image signals VID1 to VID6 can be synchronized with the sampling signal Si, and further, the display can be displayed if synchronization between the sampling hold timing in the sampling transistor 141 and the transmission timing of the image signals VID1 to VID6 can be secured. It is possible to prevent defects from occurring and display a high-quality image.

  In the above description, an example in which two types of enable signals ENB1 and ENB2 are supplied to the image signal supply circuit 101 has been described, but sampling may be performed with one type or three or more types of ENB signals.

  Next, the configuration and operation of the above-described timing control circuit 200 will be described in detail with reference to FIG. 5 in addition to FIG.

  FIG. 5 is a circuit diagram showing a configuration of the timing control circuit according to the present embodiment.

  As shown in FIG. 5, the timing control circuit 200 includes a timing signal output circuit unit 200a and a timing adjustment circuit unit 200b.

  The timing signal output circuit unit 200 a includes an oscillation circuit 21, a counter 22, and a decoder 23. The oscillation circuit 21 outputs a clock signal OSCI having a frequency several times that of the dot clock DC. The counter 22 is reset in synchronization with the rising edge of the horizontal synchronization signal HSYNC. After the reset, the counter 22 counts the number of pulses of the clock signal OSCI from the initial value. Here, the counter 22 is provided with an initial value input terminal INIT for inputting an initial value of the count value when reset. The decoder 23 decodes the output value of the counter 22, and performs dot clock DC, X start pulse DX and Y start pulse DY, X clock signal CLX and Y clock signal CLY, and inverted X clock signal CLXinv and inverted Y clock signal. Various timing signals such as CLYinv are output.

  The timing adjustment circuit unit 200 b includes a register 25 and a counter 26. The counter 26 starts counting the clock signal OSCI when the X start pulse DX is input to its input terminal START, and ends the counting when the monitor signal MON is input from the monitor circuit 27 to the input terminal STOP. .

  Thus, the delay amount of the output timing of the monitor signal MON with respect to the output timing of the X start pulse DX is measured with reference to the clock signal OSCI that determines the rising and falling cycles of the X clock signal CLX and the inverted X clock signal CLXinv. It becomes possible. The delay amount of the output timing of the monitor signal MON indirectly indicates the delay amount of the output timing of the image signals VID1 to VID6 in at least one stage of the image signal supply circuit 101 by the configuration and function of the monitor circuit 27 described later. Is. The initial value in the counter 22 is preset based on the delay amount of the output timing of the monitor signal MON, and the timing signals such as the dot clock DC, X start pulse DX, and X clock signal CLX output from the decoder 23 are the monitor signal. It is output at an earlier timing by a time corresponding to the delay amount of the output timing of MON. Thereby, the output timing of the image signals VID1 to VID6 in the image signal supply circuit 101 is adjusted.

  The register 25 is a storage means, and latches the count result of the counter 26 in synchronization with the vertical synchronization signal VSYNC.

  Next, the configuration of the monitor circuit 27 described above will be described in detail with reference to FIG. 6 in addition to FIGS.

  FIG. 6 is a circuit diagram showing a configuration of the monitor circuit according to the present embodiment.

  In FIG. 1, the monitor circuit 27 is provided for indirectly monitoring the output timing of the image signals VID <b> 1 to VID <b> 6 in the image signal supply circuit 101. In the plurality of stages of the image signal supply circuit 101, the logical product of the circuit elements constituting each stage of the data line driving circuit 150, the characteristics of the circuit elements themselves, and further the characteristics of the sampling transistor 141 in the sampling circuit 140. Signal delay occurs, and the output timing of the image signals VID1 to VID6 may be delayed from the timing based on the X clock signal CLX.

  2 and 6, the monitor circuit 27 is configured to simulate one stage of the image signal supply circuit 101. That is, the monitor circuit 27 includes a unit circuit 271a that simulates an enable circuit 400 (see FIG. 3) corresponding to one stage of the shift register 160 of the data line driving circuit 150, and a buffer circuit 500 (FIG. 3) corresponding to the one stage. A logic circuit unit simulating unit 271 including a unit circuit 271b for simulating a reference circuit) and three dummy transistors 272 for simulating a sampling transistor 114 (see FIG. 3) corresponding to one stage of the data line driving circuit 150. doing. In FIG. 2, for simplicity, one of the three dummy transistors 272 is illustrated, and the other two are not illustrated. Each of the unit circuits 271a and 272b included in the logic circuit unit simulation unit 271 is an example of the “first monitor circuit unit” according to the present invention, and the three dummy transistors 272 include the “first monitor circuit unit” according to the present invention. This is an example of “2 monitor circuit section”.

  The unit circuit 271a includes a NAND circuit 71, a NOR circuit 72, and an inverter 73a for simulating the NAND circuit 410, the NOR circuit 420, and the inverter 430 described above with reference to FIG.

  The NAND circuit 71 is configured such that the X start pulse DX is input to one of the two input terminals, and the low power supply potential VSSX is supplied to the other of the two input terminals.

  In the NOR circuit 72, the output terminal of the NAND circuit 71 is electrically connected to one of the two input terminals, and the output terminal of the inverter 73a is electrically connected to the other of the two input terminals. Yes.

  The inverter 73 a has the input terminal supplied with the low power supply potential VSSX and the output terminal electrically connected to the NOR circuit 72.

  Each of the NAND circuit 71, the NOR circuit 72, and the inverter 73a includes a plurality of transistors. The channel width Wd6 of each of the plurality of transistors constituting the NAND circuit 71 is, for example, 20 um. The channel width Wd4 of each of the plurality of transistors constituting the NOR circuit 72 is 20 μm, for example. The channel width Wd5 of each of the plurality of transistors constituting the inverter 73a is, for example, 20 μm. In this embodiment, as will be described in detail later, (i) the ratio Wd4 / the ratio of the channel width Wd4 of the transistor constituting the NOR circuit 72 to the channel width W4 of the transistor constituting the NOR circuit 420 described above with reference to FIG. W4, (ii) the ratio Wd5 / W5 of the channel width Wd5 of the transistor constituting the inverter 73a to the channel width W5 of the transistor constituting the inverter 430 described above with reference to FIG. 3, and (iii) with reference to FIG. The ratio Wd6 / W6 of the channel width Wd6 of the transistor constituting the NAND circuit 71 to the channel width W6 of the transistor constituting the NAND circuit 410 described above is equal to each other, and both are, for example, ½ (ie 0.5). Is set. That is, in the present embodiment, each of the plurality of transistors constituting the unit circuit 271a is formed so as to satisfy the relational expression of ratio Wd4 / W4 = ratio Wd5 / W5 = ratio Wd6 / W6 = 1/2. Yes. The plurality of transistors constituting the NAND circuit 71, the plurality of transistors constituting the NOR circuit 72, and the plurality of transistors constituting the inverter 73a are examples of the “first dummy transistor” according to the present invention.

  The NAND circuit 71, the NOR circuit 72, and the inverter 73a are different from each other in that the channel width of the transistor included in each of the NAND circuit 71, the NOR circuit 72, and the inverter 73a is different from the channel width of the transistor included in each of the NAND circuit 410, the NOR circuit 420, The circuit 410, the NOR circuit 420, and the inverter 430 are configured in substantially the same manner, and are configured by the same number of transistors as the transistors included in the NAND circuit 410, the NOR circuit 420, and the inverter 430.

  Next, the circuit configuration of the NAND circuit 71 will be described with reference to FIG. 7 in addition to FIG.

  FIG. 7 is a circuit diagram showing a circuit configuration of a NAND circuit included in the monitor circuit according to the present embodiment.

  In FIG. 7, the NAND circuit 71 includes a P-channel transistor 810, an N-channel transistor 820, an N-channel transistor 830, and a P-channel transistor 840. The gate electrodes of the P-channel transistor 810 and the N-channel transistor 820 are electrically connected to the input terminal α (see also FIG. 6), and the X start pulse DX is input. In the P-channel transistor 810, the source is electrically connected to the power supply wiring 602, and the drain is electrically connected to the output terminal OUT (see also FIG. 6). The N-channel transistor 820 has a source electrically connected to a drain of the N-channel transistor 830 and a drain electrically connected to the output terminal OUT. The source of the N-channel transistor 830 is electrically connected to the power supply wiring 601. The gate electrode of the N-channel transistor 830 is electrically connected to the input terminal β (see also FIG. 6), and is supplied with the high power supply potential VDDX. In the P-channel transistor 840, the source is electrically connected to the power supply wiring 602, and the drain is electrically connected to the output terminal OUT. The gate electrode of the P-channel transistor 840 is electrically connected to the input terminal β (see also FIG. 6), and is supplied with the high power supply potential VDDX. As described above, the channel width W6d of each of the P-channel transistor 810, the N-channel transistor 820, the N-channel transistor 830, and the P-channel transistor 840 is 20 um, for example.

  In the present embodiment, the NAND circuit 410 described above with reference to FIG. 3 is configured by four transistors in substantially the same manner as the NAND circuit 71. However, as described above, the NAND circuit 410 is configured. The ratio of the channel width Wd6 of the four transistors (that is, the P-channel transistor 810, the N-channel transistor 820, the N-channel transistor 830, and the P-channel transistor 840) constituting the NAND circuit 71 to the channel width W6 of the transistor is For example, 1/2.

  Returning to FIG. 6, the unit circuit 271b includes inverters 73b and 73c for simulating the inverters 501 and 502 described above with reference to FIG. The inverters 73b and 73c are configured to be connected in series in the direction along the data line 114 (that is, the Y direction). The input end of the inverter 73b is electrically connected to the output end of the unit circuit 271a (that is, the output end of the NOR circuit 72), and the output end of the inverter 73c is the gate electrode of three dummy transistors 272 described later. Is electrically connected. In each of the inverters 73b and 73c, two inverters are connected in parallel in the direction along the scanning line 112 (that is, the X direction). That is, the inverter 73b is configured by connecting inverters 711 and 712 in parallel, and the inverter 73c is configured by connecting inverters 721 and 722 in parallel.

  Furthermore, the inverters 711 and 712 and 721 and 722 are substantially the same as the inverters 511 to 514 and 521 to 524 described above with reference to FIG. It is configured as a complementary transistor in which channel type transistors are combined. That is, each of the inverters 711 and 712 and 721 and 722 includes a P-channel transistor and an N-channel transistor between the lead wire 611 drawn from the power wire 601 and the lead wire 621 drawn from the power wire 602. Are connected in series.

  The channel width Wd3 of each of the plurality of transistors constituting the inverter 73b (that is, the P-channel and N-channel transistors constituting each of the inverters 711 and 712) is, for example, 100 um, and the plurality of transistors constituting the inverter 73c The channel width Wd2 of each of the transistors (that is, the P-channel and N-channel transistors constituting each of the inverters 721 and 724) is, for example, 300 μm. That is, the channel width Wd3 of each of the plurality of transistors constituting the inverter 73b is the same as the channel width W3 of each of the plurality of transistors constituting the inverter 501 described above with reference to FIG. The channel width Wd2 of each of the plurality of transistors is the same as the channel width W2 of each of the plurality of transistors constituting the inverter 502 described above with reference to FIG. In this embodiment, (i) the ratio Nd2 / N2 of the number Nd2 of transistors constituting the inverter 73c with respect to the number N2 (four in this embodiment) of the transistors constituting the inverter 502 described above with reference to FIG. (Ii) The ratio Nd3 / N3 of the number Nd3 of transistors constituting the inverter 73b with respect to the number N3 (four in this embodiment) of the transistors constituting the inverter 501 described above with reference to FIG. For example, it is set to 1/2 (that is, 0.5). That is, in the present embodiment, the plurality of transistors constituting the unit circuit 271b are formed so as to satisfy the relational expression of ratio Nd2 / N2 = ratio Nd3 / N3 = 1/2.

  The three dummy transistors 272 are an example of “a plurality of second dummy transistors” according to the present invention, and are connected in parallel to each other to simulate the six sampling transistors 141 described above with reference to FIG. Transistor. The dummy transistor 272 may be formed of, for example, an N channel type or P channel type transistor corresponding to the configuration of the sampling transistor 141. The source of the dummy transistor 272 is electrically connected to the power supply wiring 601 and is supplied with the low power supply potential VSSX. The gate electrode of the dummy transistor 272 is electrically connected to the output terminal of the inverter 73c described above. The drain of the dummy transistor 272 is electrically connected to the monitoring terminal 29 via the resistance element 30.

  In the present embodiment, the channel width Wd1 of each of the three dummy transistors 272 is, for example, 600 μm.

  In the monitor circuit 27 configured as described above, the operation of one stage of the data line driving circuit 150 and the sampling transistor 141 corresponding to the one stage simulated by the monitor circuit 27 can be simulated. Therefore, by operating the monitor circuit 27 and measuring the output timing of the monitor signal MON output from the monitoring terminal 29, the signal delay in one stage of the data line driving circuit 150 and the sampling transistor 141 corresponding to the one stage is reduced. The output timing of the based image signals VID1 to VID6 can be indirectly measured.

  Next, a specific configuration of the above-described monitor circuit 27 will be described in detail with reference to FIGS.

  FIG. 8 is a plan view showing a specific configuration of the three dummy transistors 272 and the unit circuit 271b described above with reference to FIG.

  In FIG. 8, the monitor circuit 27 includes three dummy transistors 272 and a unit circuit 271b.

  The dummy transistor 272 includes a semiconductor layer 272a formed on the element substrate, a gate electrode 272G formed on the upper layer side through the gate insulating film than the semiconductor layer 272a, and an interlayer insulating film from the gate electrode 272G. A source wiring 272S formed on the upper layer side and a drain wiring 272D arranged in the same layer as the source wiring 272 are provided.

  In the semiconductor layer 272a, a channel region in which a channel is formed by an electric field from the gate electrode 272G, a source region electrically connected to the source wiring 272S through the contact hole 901, a drain wiring 272D, and a contact hole 902 are provided. And a drain region electrically connected to each other.

  The gate electrode 272G is electrically connected to the drains of a P-channel transistor 721p, an N-channel transistor 271n, a P-channel transistor 722p, and an N-channel transistor 272n, which will be described later.

  The source wiring 272 </ b> S is formed as a part of the extraction wiring extracted from the power supply wiring 601, and is supplied with the low power supply potential VSSX.

  The drain wiring 272D is electrically connected to the resistance element 30 (see FIG. 6).

  In this embodiment, the channel width Wd1 of the dummy transistor 272 is, for example, 600 μm, and is the same size as the channel width W1 of the sampling transistor 41 described above with reference to FIG.

  The unit circuit 271b includes a P-channel transistor 711p and an N-channel transistor 711n that constitute an inverter 711 (see FIG. 6), and a P-channel transistor 712p and an N-channel transistor 712n that constitute an inverter 712 (see FIG. 6). And a P-channel transistor 721p and an N-channel transistor 721n constituting the inverter 721 (see FIG. 6), and a P-channel transistor 722p and an N-channel transistor 722n constituting the inverter 722 (see FIG. 6). .

  The N-channel transistor 711n includes a semiconductor layer 711na formed on the element substrate, a gate electrode 711nG formed on the upper layer side of the semiconductor layer 711na via a gate insulating film, and an interlayer insulating film from the gate electrode 711nG. And a source wiring 711nS formed on the upper layer side, and a drain wiring 711nD disposed in the same layer as the source wiring 711nS.

  In the semiconductor layer 711na, an N-type channel region in which a channel is formed by an electric field from the gate electrode 711nG, a source region electrically connected to the source wiring 711nS through the contact hole 909, a drain wiring 711nD, and a contact hole A drain region electrically connected through 910 is formed.

  The gate electrode 711nG is electrically connected to an input wiring 950 to which an output signal of the unit circuit 271a is input.

  The source wiring 711nS is formed as a part of the extraction wiring 611 extracted from the power supply wiring 601 and is supplied with the low power supply potential VSSX.

  The drain wiring 711nD is electrically connected to each gate electrode of a P-channel transistor 721p, an N-channel transistor 721n, a P-channel transistor 722p, and an N-channel transistor 722n, which will be described later, through a contact hole 908.

  The P-channel transistor 711p is substantially similar to the N-channel transistor 711n, and includes a semiconductor layer formed on the element substrate, a gate electrode 711pG formed on the upper layer side of the semiconductor layer via a gate insulating film, A source wiring formed on an upper layer side than the gate electrode 711pG via an interlayer insulating film, and a drain wiring arranged in the same layer as the source wiring are provided.

  In the semiconductor layer of the P-channel transistor 711p, a P-type channel region in which a channel is formed by an electric field from the gate electrode 711pG, a source region electrically connected to the source wiring through a contact hole, a drain wiring, A drain region electrically connected through the contact hole is formed.

  Similarly to the gate electrode 711nG, the gate electrode 711pG is electrically connected to the input wiring 950 to which the output signal of the unit circuit 271a is input.

  The source wiring of the P-channel transistor 711p is formed as a part of the extraction wiring 621 extracted from the power supply wiring 602, and is supplied with the high power supply potential VDDX.

  Similarly to the drain wiring 711nD described above, the drain wiring of the P-channel transistor 711p is connected to the gate electrode of each of the P-channel transistor 721p, N-channel transistor 721n, P-channel transistor 722p, and N-channel transistor 722n described later. It is electrically connected through a contact hole 908.

  The P-channel transistor 712p is configured in substantially the same manner as the P-channel transistor 711p. The N-channel transistor 712n is configured in substantially the same manner as the N-channel transistor 711n.

  In the present embodiment, each of four transistors (that is, a P-channel transistor 711p, an N-channel transistor 711n, a P-channel transistor 712p, and an N-channel transistor 712n) constituting the inverter 73b (see FIG. 6). The channel width Wd3 is, for example, 100 μm, and is the same size as the channel width W3 of each of the eight transistors constituting the inverter 501 (see FIG. 3).

  The N-channel transistor 721n includes a semiconductor layer 721na formed on the element substrate, a gate electrode 721nG formed on the upper layer side of the semiconductor layer 721na via a gate insulating film, and an interlayer insulating film than the gate electrode 721nG. A source wiring 721nS formed on the upper layer side, and a drain wiring 721nD arranged in the same layer as the source wiring 721nS.

  In the semiconductor layer 721na, an N-type channel region in which a channel is formed by an electric field from the gate electrode 721nG, a source region electrically connected to the source wiring 721nS through the contact hole 903, a drain wiring 721nD, and a contact hole A drain region electrically connected via 904 is formed.

  The gate electrode 721nG is electrically connected to the drain wiring of the above-described P-channel transistor 711p, N-channel transistor 711n, P-channel transistor 712p, and N-channel transistor 712n through a contact hole 908.

  The source wiring 721nS is formed as a part of the extraction wiring 611 extracted from the power supply wiring 601 and is supplied with the low power supply potential VSSX.

  The drain wiring 721pD is electrically connected to the gate electrodes 272G of the three dummy transistors 272 described above via the contact hole 907.

  The P-channel transistor 721p includes a semiconductor layer formed on the element substrate, a gate electrode 721pG formed on the upper layer side through the gate insulating film from the semiconductor layer, and an interlayer insulating film from the gate electrode 721pG. A source wiring 721pS formed on the upper layer side and a drain wiring 721pD arranged in the same layer as the source wiring 721pS.

  In the semiconductor layer of the P-channel transistor 721p, a P-type channel region in which a channel is formed by an electric field from the gate electrode 721pG, a source region electrically connected to the source wiring 721pS through the contact hole 905, a drain A drain region electrically connected to the wiring 721pD through the contact hole 906 is formed.

  Similarly to the gate electrode 721nG described above, the gate electrode 721pG is electrically connected to the drain wiring of the above-described P-channel transistor 711p, N-channel transistor 711n, P-channel transistor 712p, and N-channel transistor 712n through the contact hole 908. Connected.

  The source wiring 721pS is formed as a part of the extraction wiring 621 extracted from the power supply wiring 602, and is supplied with the high power supply potential VDDX.

  Similarly to the drain wiring 721nD described above, the drain wiring 721pD is electrically connected to the gate electrodes 272G of the three dummy transistors 272 described above via the contact holes 907.

  The P-channel transistor 722p is configured in substantially the same manner as the P-channel transistor 721p. The N-channel transistor 722n is configured in substantially the same manner as the N-channel transistor 721n.

  In this embodiment, each of four transistors (that is, a P-channel transistor 721p, an N-channel transistor 721n, a P-channel transistor 722p, and an N-channel transistor 722n) constituting the inverter 73c (see FIG. 6). The channel width Wd2 is, for example, 100 μm, and is the same size as the channel width W2 of each of the eight transistors constituting the inverter 502 (see FIG. 3).

  FIG. 9 is a plan view showing a specific configuration of the NAND circuit 71 described above with reference to FIGS.

  In FIG. 9, the NAND circuit 71 includes a P-channel transistor 810, an N-channel transistor 820, an N-channel transistor 830, and a P-channel transistor 840.

  The P-channel transistor 810 and the P-channel transistor 840 have a common semiconductor layer 810a. The P-channel transistor 810 has a gate electrode 810G formed as a part of the input wiring 960 that is electrically connected to the input terminal β (see also FIG. 6). The P-channel transistor 840 has a gate electrode 840G formed as a part of the input wiring 970 electrically connected to the input terminal α (see also FIG. 6).

  The semiconductor layer 810a includes a P-type channel region in which a channel is formed by an electric field from the gate electrode 810G, a P-type channel region in which a channel is formed by an electric field from the gate electrode 840G, and a contact hole in the first output wiring 990. A drain region electrically connected via 913 and a drain region electrically connected to the first output wiring 990 via a contact hole 915 are formed. Further, the semiconductor layer 810a includes a power supply wiring 602 between a P-type channel region where a channel is formed by an electric field from the gate electrode 810G and a P-type channel region where a channel is formed by an electric field from the gate electrode 840G. A common source region is formed in the P-channel transistor 810 and the P-channel transistor 840 that are electrically connected to the drawn-out wiring 622 through the contact hole 914.

  The N-channel transistor 820 and the N-channel transistor 830 have a common semiconductor layer 820a. The N-channel transistor 820 includes a gate electrode 820G formed as a part of the input wiring 970 that is electrically connected to the input terminal α (see also FIG. 6). The N-channel transistor 830 includes a gate electrode 830G formed as a part of the input wiring 960 that is electrically connected to the input terminal β (see also FIG. 6).

  In the semiconductor layer 820a, an N-type channel region in which a channel is formed by an electric field from the gate electrode 820G, an N-type channel region in which a channel is formed by an electric field from the gate electrode 830G, and an extraction wiring drawn from the power supply wiring 601 A source region electrically connected to 612 via a contact hole 911 and a drain region electrically connected to the first output wiring 990 via a contact hole 912 are formed. Further, in the semiconductor layer 820a, an N channel type channel is formed between an N type channel region where a channel is formed by an electric field from the gate electrode 820G and an N type channel region where a channel is formed by an electric field from the gate electrode 830G. A source / drain region is formed as a drain region of the transistor 820 and a source region of the N-channel transistor 830.

  The first output wiring 990 is electrically connected to the second output wiring 980 through the contact hole 916. The second output wiring 980 is disposed in the same layer as the input wirings 960 and 970. The first output wiring 990 is arranged on the upper layer side through the interlayer insulating film than the second output wiring 980.

  In this embodiment, the channel width Wd6 of each of the four transistors constituting the NAND circuit 71 (that is, the P-channel transistor 810, the N-channel transistor 820, the N-channel transistor 830, and the P-channel transistor 840). Is 20 μm, for example, and is ½ times the channel width W6 of each of the four transistors constituting the NAND circuit 410 (see FIG. 3).

  Next, a characteristic configuration of the monitor circuit according to the present embodiment will be described mainly with reference to FIGS.

  3 and 6, in the present embodiment, the plurality of transistors constituting the logic circuit unit simulation unit 271 are more than the plurality of transistors constituting the logic circuit unit 700 (that is, the enable circuit 400 and the buffer circuit 500). The channel width is reduced or the number is reduced. Specifically, the plurality of transistors constituting the unit circuit 271a are formed to have a smaller channel width than the plurality of transistors constituting the enable circuit 400, and constitute the inverters 73b and 73c of the unit circuit 271b, respectively. The plurality of transistors are formed so as to have a smaller number than the plurality of transistors constituting the inverters 501 and 502 of the buffer circuit 500, respectively. Furthermore, the number of dummy transistors 272 is smaller (three in this embodiment) than the six sampling transistors 141 to be simulated (in other words, the sampling transistors 141 corresponding to one stage of the data line driving circuit 150). It is formed as follows.

  In this embodiment, in particular, (i) the channel widths W4, W5, and W6 of the plurality of transistors constituting the enable circuit 400 (in this embodiment, the channel widths W4, W5, and W6 are the same in size, For example, the channel widths Wd4, Wd5, and Wd6 of the plurality of transistors that form the unit circuit 271a for the unit circuit 271a (in this embodiment, the channel widths Wd4, Wd5, and Wd6 are the same size, and each is, for example, 20 um) And (ii) the number of transistors constituting the inverters 73b and 73c (four in this embodiment) with respect to the number of transistors constituting the inverters 501 and 502 (eight in this embodiment). (Iii) a sample corresponding to one stage of the data line driving circuit 150 to be simulated (In this embodiment, six) number of grayed transistor 141 (in this embodiment, three) dummy number of transistors 272 for the ratio of the mutually equal both 1/2.

  Accordingly, the size of the monitor circuit 27 can be reduced or reduced (that is, the monitor circuit 27 is shrunk), and the delay amount of the monitor signal MON output from the monitor circuit 27 is monitored in the image signal supply circuit 101. The delay amount of the signal in the circuit portion to be simulated by the circuit 27 (that is, the logic circuit portion 700 (i) corresponding to one stage of the data line driving circuit 150 and the six sampling transistors 141 corresponding to the one stage) or almost or Can be exactly the same. In other words, the area on the element substrate only for forming the monitor circuit 27 can be reduced while appropriately maintaining the original function of the monitor circuit 27 that simulates a part of the image signal supply circuit 1010. Accordingly, it is possible to accurately monitor the output timing delay of the image signal generated in the image signal supply circuit 101 by the monitor signal MON, and to narrow the peripheral area on the element substrate with respect to the image display area 110. Accordingly, the size of the element substrate can be reduced without narrowing the image display area 110. As a result, the liquid crystal device 1 can be reduced in size. By reducing the size of the liquid crystal device 1 as described above, the manufacturing cost for manufacturing the liquid crystal device 1 can be reduced.

  (I) the ratio of the channel widths Wd4, Wd5 and Wd6 of the plurality of transistors constituting the unit circuit 271a to the channel widths W4, W5 and W6 of the plurality of transistors constituting the enable circuit 400, and (ii) the inverter 501 and The ratio of the number of transistors constituting each of the inverters 73b and 73c to the number of transistors constituting each of the 502, and (iii) dummy transistors for the number of sampling transistors 141 corresponding to one stage of the data line driving circuit 150 to be simulated The ratio of the number of 272 may be equal to each other, and may be another value different from 1/2, such as 1/3. Also in this case, the delay of the output timing of the image signal generated in the image signal supply circuit 101 can be monitored with high accuracy, and the liquid crystal device can be downsized.

  3 and 6, in the present embodiment, in particular, the number of transistors constituting the enable circuit 400 and the number of transistors constituting the unit circuit 271a are the same, and the channel of the sampling transistor 141 is the same. The width W1 and the channel width Wd1 of the dummy transistor 272 are the same as each other. (I) Channel widths W4, W5, and W6 of each of the plurality of transistors constituting the enable circuit 400 (in this embodiment, for example, 40 μm) And the ratio of channel widths Wd4, Wd5 and Wd6 (in this embodiment, for example, 20 um) of the transistors constituting the unit circuit 271a to (ii), and for sampling corresponding to one stage of the data line driving circuit 150 to be simulated The number of transistors 141 (six in this embodiment) (In this embodiment, three) dummy number of transistors 272 that the ratio of equal to each other.

  Therefore, each of the plurality of transistors included in the unit circuit 271a (for example, the transistors 810, 820, 830, and 840 described above with reference to FIG. 9) is compared with the plurality of transistors included in the enable circuit 400, The three dummy transistors 272 can be formed smaller in the width direction (that is, for example, the Y direction in FIG. 3, FIG. 6, or FIG. 9) and the three dummy transistors 272 are compared with the six sampling transistors 141. (In other words, in the channel length direction, that is, the X direction in FIG. 3 or FIG. 6). In other words, the direction in which the plurality of transistors constituting the unit circuit 271a is reduced with respect to the plurality of transistors constituting the enable circuit 400, and the three dummy transistors 272 correspond to the six sampling transistors 141. A plurality of transistors and three dummy transistors 272 constituting the unit circuit 271a can be formed so that the directions of reduction are different from each other. Therefore, the plurality of transistors and the three dummy transistors 272 constituting the unit circuit 271a can be laid out relatively easily in a limited region on the element substrate.

  As described above, according to the liquid crystal device 1 according to the present embodiment, the delay of the output timing of the image signal generated in the image signal supply circuit 101 can be accurately monitored, and the liquid crystal device can be downsized. be able to.

  A specific overall configuration of the liquid crystal device 1 according to the above embodiment will be described with reference to FIGS. 10 and 11.

  FIG. 10 is a plan view of the TFT array substrate 10 as viewed from the counter substrate 20 side together with the components formed thereon, and FIG. 11 is a cross-sectional view taken along the line H-H ′ of FIG. 10.

  10 and 11, a TFT array substrate 10 as an element substrate and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are provided with a sealing material 52 provided in a seal region located around the image display region 110. Are bonded to each other.

  In FIG. 10, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 110 is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed.

  An image signal supply circuit 101 and an external circuit connection terminal 102 for driving the data line 114 by supplying an image signal to the data line 114 at a predetermined timing are provided in an area located outside the seal area where the seal material 52 is disposed. It is provided along one side of the TFT array substrate 10. A scanning line driving circuit 130 that drives the scanning line 112 by supplying a scanning signal to the scanning line 112 at a predetermined timing is provided along one of the two sides adjacent to the one side. Note that when the delay of the scanning signal supplied to the scanning line 112 becomes a problem, the scanning line driving circuit 130 is adjacent to one side of the TFT array substrate 10 provided with the image signal supply circuit 101 and the external circuit connection terminal 102. It may be provided along two sides. In this case, the two scanning line driving circuits 130 are connected to each other by a plurality of wirings provided along the remaining one side of the TFT array substrate 10. Alternatively, the image signal supply circuit 101 may be arranged on both sides of the image display area 110.

  On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with a vertical conduction material are disposed in regions facing the four corners of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  In FIG. 11, on the TFT array substrate 10, although not shown here, the pixel switching TFT 116, the scanning line 112, the data line 114, and the like described above with reference to FIG. A structure is formed. In the image display region 110, pixel electrodes 118 made of a transparent material such as ITO (Indium Tin Oxide) are provided in a matrix on the upper layer of wiring such as the TFT 116, the scanning line 112, and the data line 114. An alignment film is formed on the pixel electrode 118. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. The light shielding film 23 is formed of, for example, a light shielding metal film or the like, and is patterned, for example, in a lattice shape in the image display region 110 on the counter substrate 20. A counter electrode 21 made of a transparent material such as ITO is formed in a solid shape on the light shielding film 23 so as to face the plurality of pixel electrodes 118. An alignment film is formed on the counter electrode 21. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  On the TFT array substrate 10, in addition to the image signal supply circuit 101, the scanning line driving circuit 130, and the like, a precharge signal having a predetermined voltage level is supplied to a plurality of data lines 114 in advance of the image signal. A precharge circuit, an inspection circuit for inspecting the quality, defects, etc. of the electro-optical device during manufacture or at the time of shipment may be formed.

<Electronic equipment>
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described.

  First, a projector using this liquid crystal device as a light valve will be described. FIG. 12 is a plan view showing a configuration example of the projector. As shown in FIG. 12, a projector 1100 is provided with a lamp unit 1102 composed of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R and 1110B.

  In addition, since light corresponding to each primary color of R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic device described with reference to FIG. 12, a mobile personal computer, a mobile phone, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, and an electronic notebook , Calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), The present invention can also be applied to an organic EL display, a digital micromirror device (DMD), an electrophoresis apparatus, and the like.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and an electro-optical device with such a change. In addition, an electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

1 is a block diagram illustrating an overall configuration of a liquid crystal device according to a first embodiment. It is a circuit diagram which shows a part of image signal supply circuit which concerns on 1st Embodiment, and the structure of a monitor circuit. FIG. 3 is a circuit diagram illustrating a configuration of a logic circuit unit according to the first embodiment. 5 is a timing chart showing changes with time of various signals related to the image signal supply circuit according to the first embodiment. 1 is a circuit diagram showing a configuration of a timing control circuit according to a first embodiment. FIG. 1 is a circuit diagram illustrating a configuration of a monitor circuit according to a first embodiment. FIG. FIG. 3 is a circuit diagram showing a configuration of a NAND circuit included in the monitor circuit according to the first embodiment. FIG. 5 is a plan view showing a specific configuration of three dummy transistors that simulate six sampling transistors and a unit circuit that simulates a buffer circuit according to the first embodiment. 3 is a plan view showing a specific configuration of a NAND circuit included in the monitor circuit according to the first embodiment. FIG. It is a top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment. It is H-H 'sectional drawing of FIG. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  27, monitor circuit, 101, image signal supply circuit, 114, data line, 140, sampling circuit, 141, sampling transistor, 150, data line driving circuit, 160, bidirectional shift register, 271a, 271b, unit circuit, 271 ... Logic circuit part simulation part, 272 ... Dummy transistor, 400 ... Enable circuit, 500 ... Buffer circuit, 700 ... Logic circuit part, 771 ... Image signal supply line

Claims (4)

A plurality of data lines provided in the image display area;
A shift register that sequentially outputs transfer signals;
A logic circuit unit that shapes the transfer signal and outputs the signal as a sampling signal;
An image signal supply unit including a sampling circuit for supplying an image signal to the plurality of data lines according to the sampling signal;
A monitor circuit unit provided corresponding to the logic circuit unit and the image signal supply unit,
The logic circuit unit includes an enable circuit and a buffer circuit,
The monitor circuit unit is
A plurality of first dummy transistors provided corresponding to the plurality of first transistors included in the enable circuit and having the same number as the plurality of first transistors;
A plurality of second dummy transistors provided corresponding to the plurality of second transistors included in the sampling circuit and having a smaller number than the plurality of second transistors;
A plurality of third dummy transistors provided corresponding to the plurality of third transistors included in the buffer circuit and having a smaller number than the plurality of third transistors,
The plurality of second dummy transistors and the plurality of third dummy transistors are all arranged along a first direction and arranged to have a channel width in a second direction intersecting the first direction,
The plurality of first dummy transistors are arranged to have a channel width in the second direction,
The ratio between the number of the plurality of second transistors and the number of the plurality of second dummy transistors is a predetermined ratio equal to the ratio between the number of the plurality of third transistors and the number of the plurality of third dummy transistors. Yes, and
Electro-optical device which is a ratio equal to a predetermined ratio of each channel width of the first dummy transistor each channel width of said plurality of said plurality of first transistors. The electro-optical device according to claim 1.
Each of the channel widths of the plurality of second transistors is equal to each of the channel width of the plurality of second dummy transistor,
Wherein each of the plurality of channel width of the third transistor, an electro-optical device, characterized in that equal to the respective channel widths of the plurality of third dummy transistor. The electro-optical device according to claim 1,
A power supply wiring extending along the first direction between the plurality of second dummy transistors and the plurality of third dummy transistors;
The power supply wiring is electrically connected to each of the plurality of second dummy transistors and each of the plurality of third dummy transistors by a plurality of extraction wirings drawn out along the second direction. An electro-optical device.   An electronic apparatus comprising the electro-optical device according to claim 1.

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