JP4961790B2 - Electro-optical device and electronic apparatus including the same - Google Patents

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  This type of electro-optical device is generally driven on the basis of an image signal subjected to serial-parallel conversion. For example, in a liquid crystal device, a plurality of data lines wired to an image display area on a substrate are divided into blocks every predetermined number, and serial-parallel converted image signals are included in the block in block units. The data line is supplied via a sampling switch. Thus, a predetermined number of data lines are simultaneously driven and a plurality of data lines are sequentially driven every predetermined number. In this case, the sampling switch is generally composed of a single-channel or complementary TFT. An image signal line is connected to the source of the sampling switch, a data line is connected to the drain, and a sampling signal line for supplying a sampling signal is connected to the gate. Here, in particular, due to the parasitic capacitance between the image signal lines and the data lines connected to the adjacent sampling switches, the potential of the adjacent image signal lines causes noise in the data line potential. There is a risk that.

  For example, in Patent Document 1, by providing a shielding electrode between each sampling switch, the data line connected to the drain region of the sampling switch and the image signal line connected to the source region of the sampling switch adjacent thereto are arranged. A technique for electrostatic shielding is disclosed.

JP 2002-49330 A

  However, in the technique of Patent Document 1, it is difficult to reliably reduce the parasitic capacitance between adjacent image signal lines or between sampling signal lines and image signal lines at the boundary between adjacent blocks. There is a technical problem in that display unevenness or block unevenness may occur in display.

  The present invention has been made in view of the above-described problems, for example, and includes an electro-optical device capable of displaying a high-quality image with reduced luminance unevenness generated at the boundary between adjacent blocks, and the electro-optical device. It is an object to provide various electronic devices.

In order to solve the above problems, an electro-optical device according to an aspect of the invention includes a plurality of pixel portions on a substrate, a plurality of scanning lines and a plurality of data lines wired in a pixel region provided with the plurality of pixel portions. The N lines of the plurality of data lines (where N is a natural number greater than or equal to 2) N-line serial-parallel conversion supplied for each of a plurality of data line groups configured as one group. N image signal lines for supplying an image signal, and a plurality of arrayed lines corresponding to the array of the plurality of data lines are formed to intersect the wiring direction of the N image signal lines. A plurality of image signal branch lines electrically connected to a corresponding one of the N image signal lines and the other end side of the plurality of image signal branch lines, and the image The signal is sent to the data lines according to the sampling signal. A sampling circuit including a plurality of sampling switches to be supplied and an image signal branch wiring group in which N image signal branch wirings corresponding to the data line group are bundled and both sides of the image signal branch wiring group are provided. A plurality of sampling signal lines that respectively supply the sampling signal for each of the sampling switches electrically connected to the N image signal branch wirings, respectively. A first constant potential wiring provided between the wiring portions respectively corresponding to the image signal branch wiring group, and the plurality of pixel portions are electrically connected to the scanning line and the data line, respectively. The first constant potential wiring includes various electronic elements, and the first constant potential wiring is different from each other among a plurality of conductive films constituting the scanning line, the data line, and the electronic element. Comprising the conductive film and the three conductive film electrically connected to each other while being respectively formed of the same film.

  According to the electro-optical device of the present invention, at the time of driving, the N-series image signals subjected to serial-parallel conversion are supplied to the N image signal lines, and further, the image signals are arranged corresponding to the data lines. It is supplied to the sampling circuit via the branch wiring. For example, for an N-sequence image signal, a serial image signal is converted into 3-phase, 6-phase, 12-phase, 24-phase,... By an external circuit in order to realize high-definition image display while suppressing an increase in drive frequency. Etc., and generated by being converted into a plurality of parallel image signals.

  In parallel with the supply of the image signal, the sampling signal is sequentially supplied via the sampling signal line for each sampling switch corresponding to the data line group, for example, by the data line driving circuit. Then, the N-series image signals are sequentially supplied to the plurality of data lines for each data line group according to the sampling signal by the sampling circuit. Therefore, data lines belonging to the same data line group are driven simultaneously. In other words, the plurality of data lines are divided into blocks every predetermined number, and are driven simultaneously in units of blocks. The sampling switches are each constituted by, for example, a single-channel TFT, the source is electrically connected to the image signal branch wiring, the drain is connected to the data line, and the sampling signal is sent to the gate via the sampling signal line. It is turned on by being supplied.

  When the data line is driven in this manner, in each pixel unit, for example, the data line is connected via a pixel switching element that performs a switching operation in accordance with a scanning signal supplied from the scanning line driving circuit via the scanning line. Thus, an image signal is supplied to the display element. Thereby, for example, a liquid crystal element as a display element performs image display based on the supplied image signal.

  Since the drive is performed as described above, if no countermeasure is taken, the image signal is supplied to one data line group among the plurality of data line groups, and the one data line group is adjacent to the one data line group. When an image signal is supplied to another data line group to be driven next, the potential of the data line belonging to one data line group fluctuates due to the potential fluctuation of the data line belonging to the other data line group. May occur. Such potential fluctuations occur between data lines located at the boundary between adjacent data line groups (that is, at the boundary between blocks) (that is, other data lines among N data lines belonging to one data line group). Between the data line located at the end on the group side and the data line located on the one data line group side among the N data lines belonging to the other data line group). There is a risk of becoming.

  In addition, when an image signal is supplied to one data line group among the plurality of data line groups, the sampling signal is output to another data line group that is adjacent to the one data line group and is driven next. Is supplied, the potential of the data lines belonging to one data line group may fluctuate due to the fluctuation of the potential of the sampling signal line. Such potential fluctuation has a portion in which the sampling signal lines are wired on both sides (that is, outside) of the image signal branch wiring group as in the present invention (in other words, between the adjacent image signal branch wiring groups. When a part of the signal line is wired), it is likely to occur at the boundary of the block, resulting in stripe-like luminance unevenness along two data lines located at both ends of the data line group, that is, series unevenness or block unevenness. There is a risk that.

  However, in the present invention, in particular, the first shield wiring provided between the wiring portions of the sampling signal lines that are wired on both sides along the branch wiring group corresponding to the adjacent image signal branch wiring groups is provided. That is, the i-th image signal branch line is located at the boundary between the i-th (where i is a natural number) image signal branch line group and the (i + 1) -th image signal branch line group. Image signal branch lines belonging to the group, sampling signal lines corresponding to the i-th image signal branch line group (that is, the (i + 1) -th image among the wiring portions wired on both sides of the i-th image signal branch line group One of the signal branch wiring group side), the first shield wiring, and the sampling signal line corresponding to the (i + 1) th image signal branch wiring group (that is, the wiring portion wired on both sides of the (i + 1) th image signal branch wiring group. Among them, one of the i-th image signal branch wiring group side) and the image signal branch wiring belonging to the i + 1th image signal branch wiring group are arranged in this order. Therefore, the first shield wiring can reduce the parasitic capacitance between the image signal branch wirings at the block boundaries (in other words, between the data lines connected to the branch wirings through the sampling switches). Therefore, at the boundary between one adjacent data line group and another data line group, the potential of the data line belonging to one data line group varies due to the potential fluctuation of the data line belonging to the other data line group. Can be suppressed or prevented.

  Further, particularly in the present invention, the first shield wiring is formed between one data line group and a sampling signal line for supplying a sampling signal to another data line group. Therefore, the first shield wiring can reduce the parasitic capacitance between the data line belonging to one data line group and the sampling signal line supplying the sampling signal to the other data line group at the block boundary. Therefore, it is possible to suppress or prevent the potential of the data line belonging to one data line group from fluctuating due to the potential fluctuation of the sampling signal line caused by the supply of the sampling signal to the other data line group.

  As described above, according to the present invention, since the first shield wiring is provided between the wiring portions wired on both sides of the adjacent image signal branch wiring group among the sampling signal lines, the image signal at the block boundary is provided. The parasitic capacitance between the branch lines or between the image signal branch line and the sampling signal line can be reduced, and the potential of one image signal branch line (in other words, the potential fluctuation of another adjacent image signal branch line or sampling signal line) The fluctuation of the potential of the data line connected thereto via the sampling switch can be suppressed or prevented. As a result, series unevenness or block unevenness in image display can be reduced, and high-quality image display becomes possible.

In one aspect of the electro-optical device of the present invention, the electro-optical device is provided for each of the data line groups and a shift register that outputs a transfer signal that defines a timing at which the image signal should be supplied to the plurality of pixel units. A plurality of buffer circuits for supplying a signal for each of the sampling signal lines corresponding to the data line group as the sampling signal; and a power supply wiring for supplying a power supply potential to each of the plurality of buffer circuits . The constant potential wiring is electrically connected to the power supply wiring.

  According to this aspect, since the first shield wiring has a constant potential, the shielding function of the first shield wiring can be enhanced, that is, between the image signal branch lines or the image signal branch lines and the sampling signal lines at the block boundary. Electromagnetic interference between the two can be further reliably reduced. Furthermore, since the first shield wiring is set to a constant potential by being electrically connected to the power supply wiring for supplying the power supply potential to the buffer circuit, the manufacturing process is hardly complicated.

  In another aspect of the electro-optical device of the present invention, each of the plurality of pixel units includes various electronic elements electrically connected to the scanning line and the data line, and the first shield wiring is the scanning line. The data lines and the electronic elements are formed of the same film as at least one of the plurality of conductive films.

  According to this aspect, the first shield wiring is formed of the same film as at least one of the plurality of conductive films constituting the scanning line, the data line, and the electronic element. Here, the “same film” according to the present invention means films formed on the same occasion in the manufacturing process, and are the same kind of film. Note that “formed from the same film” according to the present invention does not mean that it is continuously formed as a single film, but is basically divided from each other in the same film. If it is formed as a film portion, it is sufficient. Therefore, the first shield wiring can be formed on the same occasion as the formation of the scanning lines, the data lines, and various electronic elements in the pixel portion. That is, the first shield wiring can be formed without complicating the manufacturing process.

  In the aspect in which the pixel portion includes various electronic elements, the pixel portion includes three shield layers that are formed from the same film as the three different conductive films among the plurality of conductive films and are electrically connected to each other. You may comprise as follows.

  In this case, the first shield wiring includes three shield layers located in different layers in the laminated structure on the substrate. Therefore, the electromagnetic interference between the image signal branch lines or the image signal branch lines and the sampling signal lines at the block boundary can be more reliably reduced.

In another aspect of the electro-optical device according to the aspect of the invention, a second constant potential wiring provided between the image signal branch wiring group and the wiring portion is provided on the substrate.

  According to this aspect, the parasitic capacitance between the image signal branch lines or between the image signal branch lines and the sampling signal line at the block boundary can be further reduced. Therefore, it is possible to further suppress or prevent the potential of one image signal branch wiring from fluctuating due to the potential fluctuation of another adjacent image signal branch wiring or sampling signal line.

In the aspect including the second constant potential wiring described above, a shift register that outputs a transfer signal that defines a timing at which the image signal should be supplied to the plurality of pixel units, and a data line group are provided. A plurality of buffer circuits for supplying the transfer signal as the sampling signal for each of the sampling signal lines corresponding to the data line group; and a power supply wiring for supplying a power supply potential to each of the plurality of buffer circuits, The second constant potential wiring may be configured to be electrically connected to the power supply potential wiring.

  In this case, since the second shield wiring has a constant potential, the shielding function of the second shield wiring can be enhanced, that is, between the image signal branch lines or the image signal branch lines and the sampling signal lines at the block boundary. Can be reduced more reliably. Further, since the second shield wiring is set to a constant potential by being electrically connected to the power supply wiring for supplying the power supply potential to the buffer circuit, the manufacturing process is hardly complicated.

In the aspect including the second constant potential wiring described above, each of the plurality of pixel portions includes various electronic elements electrically connected to the scanning line and the data line, and the second constant potential wiring includes: The scanning line, the data line, and the electronic element are formed of the same film as at least one of the plurality of conductive films.

  In this case, the second shield wiring can be formed on the same occasion as the formation of the scanning line, the data line, and various electronic elements in the pixel portion. That is, the second shield wiring can be formed without complicating the manufacturing process.

In the aspect including the above-described second constant potential wiring and the pixel portion including various electronic elements, the second constant potential wiring is formed from the same film as three different conductive films among the plurality of conductive films. And three conductive films that are electrically connected to each other.

  In this case, the second shield wiring includes three shield layers: a first partial shield layer, a second partial shield layer, and a third partial shield layer. Therefore, the electromagnetic interference between the image signal branch lines or the image signal branch lines and the sampling signal lines at the block boundary can be more reliably reduced.

  In order to solve the above-described problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention.

  According to the electronic apparatus of the present invention, since it includes the electro-optical device of the present invention described above, a projection display device, a mobile phone, an electronic notebook, a word processor, a viewfinder type, or a monitor capable of high-quality display. Various electronic devices such as a direct-view video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. Further, as the electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper can be realized.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.
<First Embodiment>
The liquid crystal device according to the first embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line H-H 'in FIG.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are provided with a sealing material 52 provided in a seal region positioned around the image display region 10a. Are bonded to each other.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. The sampling circuit 7 is provided so as to be covered with the frame light shielding film 53 on the inner side of the seal region along the one side. Further, the scanning line driving circuit 104 is provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side. On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  On the TFT array substrate 10, a lead wiring 90 is formed for electrically connecting the external circuit connection terminal 102 to the data line driving circuit 101, the scanning line driving circuit 104, the vertical conduction terminal 106, and the like. .

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which wiring such as a pixel switching TFT (Thin Film Transistor) as a driving element, a scanning line, and a data line is formed. In the image display area 10a, a pixel electrode 9a is provided in an upper layer of wiring such as a pixel switching TFT, a scanning line, and a data line. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. A counter electrode 21 made of a transparent material such as ITO is formed on the light shielding film 23 so as to face the plurality of pixel electrodes 9a. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Although not shown here, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the TFT array substrate 10 is used for inspecting the quality, defects, etc. of the liquid crystal device during manufacturing or at the time of shipment. An inspection circuit, an inspection pattern, or the like may be formed.

  Next, the electrical configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. FIG. 3 is a block diagram schematically showing the arrangement of various drive circuits in the peripheral region on the TFT array substrate, the electrical connection relationship, and the like. FIG. 4 shows various elements in a plurality of pixel portions. It is a circuit diagram which shows equivalent circuits, such as wiring.

  3, in the pixel display region 10a on the TFT array substrate 10, a plurality of pixel electrodes 9a arranged in a matrix and a plurality of scanning lines 11a and data lines 6a arranged so as to cross each other are formed. A pixel portion corresponding to the pixel is constructed corresponding to the intersection of the scanning line 11a and the data line 6a.

  In the peripheral region on the TFT array substrate 10, a data line driving circuit 101, a sampling circuit 7, and a scanning line driving circuit 104 are provided.

  For example, the scanning line driving circuit 104 receives an Y clock signal CLY, an inverted Y clock signal CLYinv, a Y start pulse DY, and Y-side high potential power supplies VDDY and Y from an external circuit (not shown) via the external circuit connection terminal 102. Side low potential power supply VSSY is supplied. When the Y start pulse DY is input, the scanning line driving circuit 104 sequentially generates and outputs a scanning signal at a timing based on the Y clock signal CLY and the inverted Y clock signal CLYinv.

  The data line driver circuit 101 includes a shift register 101a and a buffer circuit 101b.

  The shift register 101a receives, for example, an X clock signal CLX, an inverted X clock signal CLXinv, an X start pulse DX, an X side high potential power supply VDDX, and an X side low potential power supply VSSX from an external circuit via the external circuit connection terminal 102. Supplied.

  The shift register 101a receives the transfer signal SRi (i = 1,..., N) from each stage based on the X-side clock signal CLX, the inverted X clock signal CLXinv, and the X start pulse DX of a predetermined cycle, on the signal line 404. Are sequentially output to the buffer circuit 101b.

  The buffer circuit 101b outputs the sampling signal Si based on the transfer signal SRi sequentially output from the shift register 101b.

  Since the transfer signal SRi passes through the buffer circuit 101b, the driving capability of the later-described sampling circuit 7 by the sampling signal Si is improved.

  Here, the X-side high-potential power supply VDDX and the X-side low-potential power supply VSSX are supplied to the shift register 101a and the buffer circuit 101b in the data line driving circuit 101 via the corresponding power supply wirings 601 and 602. Further, for example, the power supply lines 601 and 602 are arranged close to each other in the vicinity of a signal line for supplying the X clock signal CLX and the inverted X clock signal CLXinv to the shift register 101a, and an external circuit connection terminal together with these signal lines. From 102, the shift register 101a and the buffer circuit 101b are routed around each of the shift register 101a and the buffer circuit 101b to be connected to the shift register 101a and the buffer circuit 101b.

  The image signals VID <b> 1 to VID <b> 12 are serial-parallel converted into, for example, 12 phases, that is, phase-expanded, for example, by an external circuit, and supplied to the sampling circuit 7 via 12 image signal lines 6. The twelve image signal lines 6 are connected to the external circuit by bypassing the periphery of the shift register 101a and the buffer circuit 101b from the opposite side of the shift register 101a and the buffer circuit 101b with respect to the power supply lines 601 and 602, respectively. It is routed from the terminal 102 and wired along the arrangement direction of the sampling switches 71 in the sampling circuit 7 (that is, the arrangement direction of the data lines 6a in FIG. 3 or the X direction). By wiring the twelve image signal lines 6 in this way, the X clock signal CLX and the inverted X clock which are higher in frequency than the Y clock signal CLY and the inverted Y clock signal CLYinv supplied to the scanning line driving circuit 104. It is possible to prevent electromagnetic signal interference from the signal line serving as the signal CLXinv supply path to each image signal line 6.

  Note that the number of phase expansion of the image signal (that is, the number of image signal sequences to be serial-parallel expanded) is not limited to 12 phases, for example, 6 phases, 9 phases, 24 phases, 48 phases, 96 phases. ... and so on.

  The sampling circuit 7 includes a sampling switch 71 composed of a P-channel or N-channel single-channel TFT or a complementary TFT. A signal output from the buffer circuit 101 b of the data line driving circuit 101 is supplied to each sampling switch 71 through the sampling signal line 114 as the sampling signal Si.

  Each sampling switch 7a supplies image signals VID1 to VID12 for each data line group (or block) including 12 data lines 6a as a group in accordance with the sampling signal Si. Accordingly, since the plurality of data lines 6a are driven for each data line group, the driving frequency can be suppressed.

  Various timing signals such as the clock signals CLX and CLY are generated by, for example, a timing generator formed in an external circuit (not shown) and supplied to each circuit on the TFT array substrate 10 via the external circuit connection terminal 102. . Further, the power necessary for driving each drive circuit is also supplied from an external circuit, for example. Further, the counter electrode potential LCC is supplied to the signal line drawn from the vertical conduction terminal 106 from, for example, an external circuit. The counter electrode potential LCC is supplied to the counter electrode 21 through the vertical conduction terminal 106. The counter electrode potential LCC is a reference potential of the counter electrode 21 for appropriately holding the potential difference from the pixel electrode 9a and forming a liquid crystal storage capacitor.

  In FIG. 4, each of a plurality of pixels formed in a matrix that forms the image display area 10 a of the liquid crystal device according to the present embodiment includes a pixel electrode 9 a and a TFT 30 for switching control of the pixel electrode 9 a. The data line 6 a that is formed and supplied with the image signal VIDk (where k = 1, 2, 3,..., 12) is electrically connected to the source of the TFT 30. Further, the gate electrode 3 a is electrically connected to the gate of the TFT 30, and the pixel electrode 9 a is electrically connected to the drain of the TFT 30.

  Each scanning line 11a is selected line-sequentially by scanning signals G1,..., Gm output from the scanning line driving circuit 104. When the scanning signal Gj (j = 1, 2, 3,..., M) is supplied to the TFT 30 via the gate electrode 3a in the pixel portion corresponding to the selected scanning line 11a, the TFT 30 is turned on. The pixel electrode 9a is supplied with the image signal VIDk from the data line 6a at a predetermined timing by closing the switch of the TFT 30 for a certain period. As a result, an applied voltage defined by the potentials of the pixel electrode 9a and the counter electrode 21 is applied to the liquid crystal. The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to the image signals VID1 to VID12 is emitted from the liquid crystal device as a whole.

  In order to prevent the image signal held here from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. The storage capacitor 70 includes a fixed potential side capacitor electrode that is provided side by side with the scanning line 11a and is electrically connected to the capacitor line 400 fixed at a constant potential.

  Next, the electrical configuration of the data line driving circuit, the sampling circuit, and the image signal line of the liquid crystal device according to the present embodiment will be described in more detail with reference to FIGS. FIG. 5 is an equivalent circuit diagram schematically showing the arrangement relation of the data line driving circuit, the sampling circuit, the image signal line, and other various signal lines, and their electrical connection relation. FIG. 6 is an equivalent circuit diagram showing an electrical configuration of the buffer unit circuit. FIG. 7 is an explanatory diagram schematically showing the arrangement of the first and second shield wires, the branch wires, and the sampling signal lines in the vicinity of the boundary between adjacent branch wire groups. FIG. 8 is a timing chart showing changes in potential on data lines near the boundary between the i-th data line group and the (i + 1) -th data line group of the liquid crystal device of the present embodiment. FIG. 9 is a timing chart having the same concept as in FIG. 8 in the comparative example.

  In FIG. 5, the transfer signal SRi sequentially output from the shift register 101a is input to the buffer unit circuit 500 at each stage of the buffer circuit 101b. In the buffer circuit 101b, each buffer unit circuit 500 is arranged along the X direction (that is, the arrangement direction of the data lines 6a).

  As shown in FIG. 6, the buffer unit circuit 500 is configured by connecting three stages of inverters 510 to 530 in the direction along the data line 6a (that is, the Y direction). As will be described later, the inverters 510 to 530 are each configured as a complementary TFT combining a P-channel TFT and an N-channel TFT. In each of the inverters 510 to 530, a plurality of inverters may be connected in parallel in the direction along the scanning line 11a (that is, the X direction). In this case, the driving capability of each of the inverters 510 to 530 (that is, the inverter for one stage) can be increased. The inverters 510 to 530 constituting each buffer unit circuit 500 are supplied with the X-side high-potential power supply VDDX and the X-side low-potential power supply VSSX via the power supply wirings 601 and 602. As a result, each buffer unit circuit 500 is driven to buffer the transfer signal SRi input from the signal line 404 to generate a buffer output signal, which is output to the sampling signal line 114 as the sampling signal Si.

  In FIG. 5 again, the data line 6a (that is, the data line Dk (where k = 1, 2, 3,..., N) belonging to the i-th data line group (where i = 1, 2, 3,..., N)). .., 12)) corresponding to the arrangement of 12) (that is, for each phase expanded block), 12 branch wirings Ek (where k = 1, 2, 3,..., 12) are arranged. ing. The branch wiring Ek is an example of the “image signal branch wiring” according to the present invention. The twelve image signal lines 6 are arranged along a direction intersecting the arrangement direction of the data lines 6a. One end of each of the twelve branch lines Ek is electrically connected to a corresponding one of the twelve image signal lines 6, and the other end of each of the twelve branch lines Ek is a sampling switch. 71 is electrically connected to the data line Dk. The TFT 71 constituting each sampling switch has a source connected to the branch wiring Ek and a drain electrically connected to the data line Dk. The gate of each TFT 71 is electrically connected to the sampling signal line 114 via the control wirings X1 to X12. The control wiring X1 to X12 is supplied with the i-th sampling signal Si from the data line driving circuit 101 (more specifically, the buffer unit circuit 500) via the sampling signal line 114.

  Note that the data line driving circuit 101 may further include, for example, a level shifter circuit that shifts the potential of the output signal of the buffer circuit 101b, or the data line driving circuit 101 further includes an X clock signal CLX and an inversion. A phase difference correction circuit or the like that corrects each phase difference of the X clock signal CLXinv to mutually invert signals may be provided.

  As shown in FIG. 5, the sampling signal line 114 is provided along the branch wiring Ek (that is, along the Y direction) on both sides of the i-th branch wiring group including 12 branch wirings Ek corresponding to the i-th data line group. And wiring portions 114a and 114b to be wired. That is, the sampling signal line 114 corresponding to the i-th data line group (or corresponding to the i-th branch line) is on the i-1th branch line group side (FIG. 5) with respect to the branch line E1 belonging to the i-th branch line group. A wiring portion 114a formed on the (i + 1) -th branch wiring group side (right side in FIG. 5) with respect to the branch wiring E12 belonging to the i-th branch wiring group. ing.

  As shown in FIG. 5, the present embodiment particularly includes a first shield wiring 210 and a second shield wiring 220. The first shield wiring 210 and the second shield wiring 220 are provided for each boundary of the branch wiring group (that is, for each block boundary).

  FIG. 7 schematically shows the arrangement of the first and second shield wirings in the vicinity of the boundary of the branch wiring group. Here, a description will be given focusing on the configuration near the boundary between the i-th branch wiring group and the i + 1-th branch wiring group. The configuration related to the vicinity of the boundary between the i-th branch wiring group and the i + 1-th branch wiring group described below is the same as the configuration near the boundary between the i-th branch wiring group and the i-th branch wiring group.

  As shown in FIG. 7, the first shield wiring 210 is connected between the wiring portion 114b of the sampling signal line 114 that supplies the sampling signal Si and the wiring portion 114a of the sampling signal line 114 that supplies the sampling signal Si + 1. Wiring is performed along the portion 114a or 114b (that is, along the Y direction). The first shield wiring 210 is electrically connected to the power supply wiring 602 to which the X-side low potential power supply VSSX is supplied.

  The second shield wiring 220 is connected between the branch wiring E12 belonging to the i-th branch wiring group and the wiring portion 114b in the sampling signal line 114 for supplying the sampling signal Si, and the branch wiring E1 belonging to the i + 1-th branch wiring group and the sampling signal. Between the sampling signal line 114 for supplying Si + 1 and the wiring portion 114a, wiring is performed along the wiring portion 114a or 114b (that is, along the Y direction). That is, one second shield wiring 220 is provided on each side of each branch wiring group, and two are provided for each branch wiring group (see FIG. 5). The second shield wiring 220 is electrically connected to the power supply wiring 602 to which the X-side low potential power supply VSSX is supplied.

  FIG. 8 shows potential changes in each of the data line D12 belonging to the i-th data line group and the data line D1 belonging to the i + 1th data line group of the liquid crystal device according to the present embodiment. FIG. 9 shows potential changes in the data line D12 belonging to the i-th data line group and the data line D1 belonging to the i + 1-th data line group in the comparative example.

  In FIG. 8, in this embodiment, video precharge is performed in a precharge period preceding the image signal supply period in which the image signals VID1 to VID12 are supplied to the data line 6a. That is, in the precharge period, not the image signals VID1 to VID12 but the precharge signal is supplied to the image signal line 6 and the sampling switch 71 is turned on. As a result, the precharge signal is simultaneously applied to the plurality of data lines 6a, and the potential of the data line 6a is set to the potential of the precharge signal (that is, the precharge potential Vp). The sampling switch 71 is turned off after the precharge period, and in the subsequent image signal supply period, the sampling switch 71 is sequentially turned on in accordance with the sampling signal Si (i = 1, 2, 3,..., N). The image signals VID1 to VID12 are supplied to the plurality of data lines 6a for each data line group.

  That is, as shown in FIG. 8, the potential of the data line D12 belonging to the i-th data line group and the potential of the data line D1 belonging to the i + 1-th data line group are the precharge potential Vp before the image signal is supplied. Is held in.

  When the pulsed sampling signal Si is supplied to the sampling switch 71 at the timing t1, the sampling switch 71 is turned on, and the image signal VID12 is supplied to the data line D12 belonging to the i-th data line group. At this time, the image signals VID1 to VID11 are also supplied to the other data lines D1 to D11 belonging to the i-th data line group, respectively. Thereafter, the sampling switch 71 is turned off in response to the stop of the sampling signal Si. In this way, the potential of the data line D12 belonging to the i-th data line group is held at the potential of the image signal VID12 in the horizontal period after the timing t1. Subsequently, similarly, at timing t2, when the pulsed sampling signal Si + 1 is supplied to the sampling switch 71, the sampling switch 71 is turned on, and the image signal VID1 is supplied to the data line D1 belonging to the i + 1th data line group. Is done. At this time, the image signals VID2 to VID12 are also supplied to the other data lines D2 to D12 belonging to the i + 1th data line group, respectively. Thereafter, the sampling switch 71 is turned off. In this way, the potential of the data line D1 belonging to the i + 1th data line group is held at the potential of the image signal VID1 after the timing t2 in the horizontal period.

  In the liquid crystal device of the present embodiment, as described above, the image signal for each data line group (in other words, for each branch wiring group electrically connected to this via the sampling switch 71) according to the sampling signal Si. VID 1-12 are supplied.

  As shown in FIG. 9 as a comparative example, if no countermeasure is taken, the i + 1th data line group is maintained while the data line D12 belonging to the ith data line group is held at the potential of the image signal VID12. When the image signal VID1 is supplied to the data line D1, the data line belonging to the i-th data line group is caused by the potential fluctuation ΔV from the precharge potential Vp to the potential of the image signal VID1 in the data line D1 of the i + 1-th data line group. In D12, a potential fluctuation Δ12 from the potential of the image signal VID12 may occur. Such potential fluctuation Δ12 is caused by the branch wiring E12 belonging to the i-th branch wiring group corresponding to the data line D12 belonging to the i-th data line group and the i + 1-th branch wiring group corresponding to the data line D1 belonging to the i + 1-th data line group. This is considered to be caused by a relatively large parasitic capacitance with respect to the branch wiring E1 belonging to.

  Further, in FIG. 9, when the sampling signal Si + 1 is supplied to the (i + 1) th data line group while the data line D12 belonging to the ith data line group is held at the potential of the image signal VID12, the sampling signal line 114 ( More specifically, a potential variation from the potential of the image signal VID12 may occur in the data line D12 belonging to the i-th data line group due to the potential variation ΔS of the wiring portion 114a). Such potential fluctuation is a parasitic between the branch wiring E12 belonging to the i-th branch wiring group corresponding to the data line D12 belonging to the i-th data line group and the wiring portion 114a of the sampling signal line 114 that supplies the sampling signal Si + 1. The reason is that the capacity is relatively large.

  Such potential fluctuations are likely to occur at block boundaries, and in image display, streaky luminance unevenness along two data lines located at both ends of the data line group, that is, series unevenness or block unevenness. There is a fear.

  However, in the present embodiment, as described above with reference to FIG. 7, since the first shield wiring 210 is provided, the branch wiring E12 belonging to the i-th branch wiring group and the branch wiring belonging to the i + 1-th branch wiring group. Parasitic capacitance with E1 can be reduced. In other words, the first shield wiring 210 functions as an electromagnetic shield that reduces or prevents electromagnetic interference between the branch wiring E12 belonging to the i-th branch wiring group and the branch wiring E1 belonging to the i + 1-th branch wiring group. Therefore, the potential fluctuation from the potential of the image signal VID12 in the data line D12 belonging to the i-th data line group (that is, the data line D1 of the i + 1-th data line group in the data line D12 of the i-th data group of the comparative example described above). It is possible to suppress or preferably prevent the occurrence of potential variation due to potential variation ΔV.

  Further, the first shield wiring 210 is located between the branch wiring E12 belonging to the i-th branch wiring group and the wiring portion 114a of the sampling signal line 114 that supplies the sampling signal Si + 1. Therefore, the parasitic capacitance between the branch wiring E12 belonging to the i-th branch wiring group corresponding to the data line D12 belonging to the i-th data line group and the wiring portion 114a of the sampling signal line 114 that supplies the sampling signal Si + 1 can be reduced. In other words, the first shield wiring 210 is connected between the branch wiring E12 belonging to the i-th branch wiring group corresponding to the data line D12 belonging to the i-th data line group and the wiring portion 114a of the sampling signal line 114 that supplies the sampling signal Si + 1. It functions as an electromagnetic shield that reduces or prevents electromagnetic interference between the two. Therefore, the potential fluctuation from the potential of the image signal VID12 in the data line D12 belonging to the i-th data line group (that is, the potential fluctuation ΔS of the sampling signal line 114 in the data line D12 of the i-th data group of the comparative example described above). Occurrence of potential fluctuations) can be suppressed or preferably prevented.

  In addition, particularly in the present embodiment, as described above with reference to FIG. 7, since the second shield wiring 220 is provided, the branch wiring E12 belonging to the i-th branch wiring group and the branch belonging to the i + 1 branch wiring group. The parasitic capacitance between the wiring E1 can be further reduced. That is, the electromagnetic interference between the branch wiring E12 belonging to the i-th branch wiring group and the branch wiring E1 belonging to the i + 1-th branch wiring group can be further reduced. Furthermore, the parasitic capacitance between the branch wiring E12 belonging to the i-th branch wiring group and the wiring portion 114a of the sampling signal line 114 that supplies the sampling signal Si + 1 can be further reduced. Electromagnetic interference between the branch wiring E12 belonging to the i-th branch wiring group and the wiring portion 114a of the sampling signal line 114 that supplies the sampling signal Si + 1 can be further reduced.

  In addition, as shown in FIG. 7, in the present embodiment, the first shield wiring 210 and the second shield wiring 220 are electrically connected to the power supply wiring 602, in particular. Therefore, the shielding function of the first shield wiring 210 and the second shield wiring 220 can be enhanced, that is, between the branch wiring E12 belonging to the i-th branch wiring group and the branch wiring E1 belonging to the i + 1-th branch wiring group, or Electromagnetic interference between the branch wiring E12 belonging to the i-th branch wiring group and the wiring portion 114a of the sampling signal line 114 that supplies the sampling signal Si + 1 can be more reliably reduced. In the present embodiment, the first shield wiring 210 and the second shield wiring 220 are electrically connected to the power supply wiring 602 that supplies the power supply potential to each buffer unit circuit 500, so that the manufacturing process is not complicated. Almost no.

  Next, regarding the specific configurations of the first and second shield wirings of this embodiment, refer to FIGS. 10 to 13 together with the specific configurations of various wirings such as a pixel portion, a buffer unit circuit, and an image signal line. explain.

  First, a specific configuration of the pixel portion of the liquid crystal device according to the present embodiment will be described with reference to FIG. FIG. 10 is a cross-sectional view showing a configuration of a cross-sectional portion of the pixel portion. In FIG. 10, the scale of each layer / member is different for each layer / member so that each layer / member can be recognized on the drawing. This is the same for FIG. 13 described later, and the scale may be different for each figure.

  In FIG. 10, for example, a TFT array substrate 10 made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and a counter substrate 20 made of, for example, a glass substrate or a quartz substrate are provided so as to face each other.

  A pixel electrode 9a is provided on the TFT array substrate 10 side, and an alignment film 16 subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive film such as an ITO film. On the other hand, a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 21. . The counter electrode 21 is made of a transparent conductive film such as an ITO film, for example, like the pixel electrode 9a described above.

  Between the TFT array substrate 10 and the counter substrate 20 arranged so as to face each other, liquid crystal is sealed in a space surrounded by a sealing material 52 (see FIGS. 1 and 2), and a liquid crystal layer 50 is formed. The liquid crystal layer 50 takes a predetermined alignment state by the alignment films 16 and 22 in a state where an electric field from the pixel electrode 9a is not applied.

  On the other hand, on the TFT array substrate 10, in addition to the pixel electrode 9a and the alignment film 16, various configurations including these are provided in a laminated structure. Below, this laminated structure is demonstrated in order from the bottom.

  First, on the TFT array substrate 10, a scanning line 11a is provided in the first layer, and a base insulating film 12 is provided on the upper layer side of the scanning line 11a.

  A TFT 30 including the gate electrode 3a is provided in the second layer above the base insulating film 12. The TFT 30 has, for example, an LDD (Lightly Doped Drain) structure, and includes, as its constituent elements, a gate electrode 3a, a channel region 1a ′ of the semiconductor layer 1a in which a channel is formed by an electric field from the gate electrode 3a, a gate electrode An insulating film 2 including a gate insulating film that insulates 3a from the semiconductor layer 1a, a low concentration source region 1b and a low concentration drain region 1c in the semiconductor layer 1a, and a high concentration source region 1d and a high concentration drain region 1e. In addition, a relay electrode 719 is formed on the second layer as the same film as the gate electrode 3a described above.

  Here, a contact hole 12cv is dug in the base insulating film 12, and the gate electrode 3a is formed so as to fill the entire contact hole 12cv, whereby the gate electrode 3a is integrally formed therewith. Side wall portions 3b formed in the above are extended.

  On the TFT array substrate 10, a first interlayer insulating film 41 is formed on the upper layer side from the TFT 30 to the gate electrode 3 a and the relay electrode 719. A contact hole 81 for electrically connecting the high-concentration source region 1d of the TFT 30 and a data line 6a described later is opened in the first interlayer insulating film 41 while penetrating the second interlayer insulating film 42 described later. Yes. Further, the first interlayer insulating film 41 is provided with a contact hole 83 for electrically connecting the high concentration drain region 1e of the TFT 30 and the lower electrode 71 constituting the storage capacitor 70. In addition, the first interlayer insulating film 41 is provided with a contact hole 881 for electrically connecting the lower electrode 71 serving as a pixel potential side capacitor electrode constituting the storage capacitor 70 and the relay electrode 719. . In addition, a contact hole 882 for electrically connecting the relay electrode 719 and a second relay electrode 6a2 described later passes through the second interlayer insulating film 42 described later in the first interlayer insulating film 41. It is open.

  A storage capacitor 70 is provided in the third layer above the first interlayer insulating film 41. The storage capacitor 70 includes a lower electrode 71 as a pixel potential side capacitor electrode connected to the high concentration drain region 1e of the TFT 30 and the pixel electrode 9a, and a capacitor electrode 300 as a fixed potential side capacitor electrode. It is formed by arrange | positioning through.

  The lower electrode 71 has a function of relaying and connecting the pixel electrode 9a and the high concentration drain region 1e of the TFT 30 in addition to a function as a pixel potential side capacitor electrode. The capacitor electrode 300 is electrically connected to a capacitor line 400 having a fixed potential described later. The dielectric film 75 has a two-layer structure, for example, a silicon oxide film 75a in the lower layer and a silicon nitride film 75b in the upper layer.

  A second interlayer insulating film 42 is formed above the storage capacitor 70. The second interlayer insulating film 42 is provided with the contact hole 81 for electrically connecting the high-concentration source region 1d of the TFT 30 and the data line 6a, and the capacitor line relay layer 6a1 and the storage. A contact hole 801 is formed to electrically connect the capacitor electrode 300 which is the upper electrode of the capacitor 70. Further, the contact hole 882 described above for electrically connecting the second relay electrode 6a2 and the relay electrode 719 is formed in the second interlayer insulating film.

  A data line 6 a is provided in the fourth layer above the second interlayer insulating film 42. For example, the data line 6a is formed as a film having a three-layer structure of a layer 41A made of aluminum, a layer 41TN made of titanium nitride, and a layer 401 made of a silicon nitride film in order from the lower layer. Further, a capacitor line relay layer 6a1 and a second relay electrode 6a2 are formed on the fourth layer as the same film as the data line 6a.

  A third interlayer insulating film 43 is formed above the data line 6a. The third interlayer insulating film 43 includes a contact hole 803 for electrically connecting the capacitor line 400 and the capacitor line relay layer 6a1, and a third relay electrode 402 and a second relay electrode 6a2. Contact holes 804 for electrical connection are respectively opened.

  In the fifth layer above the third interlayer insulating film 43, the capacitor line 400 is formed, and the third relay electrode 402 is formed as the same film as the capacitor line 400. The third relay electrode 402 has a function of relaying an electrical connection between the second relay electrode 6a2 and the pixel electrode 9a through contact holes 804 and 89 described later. Here, the capacitor line 400 and the third relay electrode 402 have a two-layer structure in which a lower layer is made of aluminum and an upper layer is made of titanium nitride.

  Finally, on the sixth layer, the pixel electrodes 9a are formed in a matrix as described above, and the alignment film 16 is formed on the pixel electrodes 9a. A fourth interlayer insulating film 44 is formed under the pixel electrode 9a. In the fourth interlayer insulating film 44, a contact hole 89 for electrically connecting the pixel electrode 9a and the third relay electrode 402 is opened. Between the pixel electrode 9a and the TFT 30, the contact hole 89, the third relay layer 402 and the contact hole 804, the second relay layer 6a2, the contact hole 882, the relay electrode 719, the contact hole 881, the lower electrode 71, and the contact hole described above. It is electrically connected through 83.

  The configuration in the pixel portion as described above is common to each pixel portion, and the configuration in the pixel portion is periodically formed in the image display region 10a described with reference to FIGS. .

  Next, a specific configuration of the buffer unit circuit of the liquid crystal device according to the present embodiment will be described with reference to FIG. FIG. 11 is a plan view showing a specific configuration of the buffer unit circuit.

  In FIG. 11, the buffer unit circuit 500 includes inverters 510, 520, and 530. As described above with reference to FIG. 6, inverters 510, 520, and 530 are connected in series in the Y direction.

  The inverter 530 includes a P-channel TFT 530a and an N-channel TFT 530b.

  The TFT 530a includes a semiconductor layer formed from the same film as the semiconductor layer 1a (see FIG. 10) in the pixel portion, a gate electrode 530ga formed from the same film as the gate electrode 3a (see FIG. 10) in the pixel portion, and a gate electrode. A P-type channel region in a semiconductor layer in which a channel is formed by an electric field from 530ga, a source region 530sa and a drain region 530da in the semiconductor layer are provided.

  The source region 530sa is electrically connected to a branch wiring 601a formed of the same film as the data line 6a through a contact hole 801 opened through the interlayer insulating films 41 and 42. The branch wiring 601a is branched from the power supply wiring 601 and supplied with the X-side high potential power VDDX.

  The drain region 530da is electrically connected to an output wiring 550 formed of the same film as the data line 6a through a contact hole 802 opened through the interlayer insulating films 41 and 42.

  The TFT 530b has a semiconductor layer formed from the same film as the semiconductor layer 1a in the pixel portion, a gate electrode 530gb formed from the same film as the gate electrode 3a (see FIG. 10) in the pixel portion, and a channel by an electric field from the gate electrode 530gb. An N-type channel region in the semiconductor layer in which is formed, and a source region 530sb and a drain region 530db in the semiconductor layer.

  The source region 530sb is electrically connected to a branch wiring 602a formed of the same film as the data line 6a through a contact hole 804 that is opened through the interlayer insulating films 41 and 42. The branch wiring 602a is branched from the power supply wiring 602 and supplied with the X-side low-potential power supply VSSX.

  The drain region 530 db is electrically connected to the output wiring 550 through a contact hole 803 that is opened through the interlayer insulating films 41 and 42. Therefore, the drain region 530db is electrically connected to the drain region 530da through the output wiring 550.

  The output wiring 550 is electrically connected to the sampling signal line 114 made of the same film as the gate electrode 3a in the pixel portion through a contact hole 808 opened through the interlayer insulating films 41 and 42.

  Inverters 510 and 520 are configured in substantially the same manner as inverter 530. Note that the gate electrodes of the P-channel TFT and the N-channel TFT constituting the inverter 510 are electrically connected to the signal line 404, respectively.

  As shown in FIG. 11, in the present embodiment, the channel widths L1 to L3 of the TFTs constituting the inverters 510 to 530 are increased stepwise (that is, the channel width L2 is larger than the channel width L1 and the channel width). The channel width L3 is larger than L2. Therefore, the entire buffer unit circuit 500 can cope with a high load, and the number of sampling switches 71 that can be driven simultaneously can be increased.

  Next, a specific configuration of the first and second shield wirings of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 12 and 13 together with various wirings such as image signal lines. FIG. 12 is a plan view showing a specific configuration of the first and second shield wirings. 13 is a cross-sectional view taken along line AA ′ of FIG.

  FIG. 12 shows various wirings such as image signal lines in the vicinity of the boundary between the i-th branch wiring group and the i + 1-th branch wiring group.

  In FIG. 12, on the TFT array substrate 10, a power supply wiring 601, sampling signal lines 114, control wirings X1 to X12, image signal lines 6 and branch wirings E1 to E12 are formed. First shield wiring 210 and second shield wiring 220 are formed.

  The power supply wiring 601 is formed from the same film as the data line 6a (see FIG. 10) and is formed from the same film as the main line portion wired along the X direction and the capacitor line 400 (see FIG. 10). It consists of a redundant wiring section. The redundant wiring portion is wired along the X direction in the same manner as the main line portion, but is not formed at a portion intersecting with other wiring, in other words, is formed in an island shape along the X direction. Yes. The main line portion of the power supply wiring 601 and the redundant wiring portion are electrically connected through a contact hole 61 opened in the third interlayer insulating film 43. Note that, as described above with reference to FIG. 3, the X-side low potential power supply VSSX is supplied to the power supply wiring 601.

  The sampling signal line 114 is made of the same film as the gate electrode 3a (see FIG. 10). The sampling signal 114 has wiring portions 114a and 114b wired along the branch wiring Ek on both sides of the i-th branch wiring group composed of twelve branch wirings Ek.

  The control wirings X1 to X12 are respectively branched from the sampling signal line 114 and are electrically connected to the gate electrode of the TFT 71 constituting the sampling switch.

  Twelve image signal lines 6 are formed to supply the image signals VID1 to VID12, respectively. Each image signal line 6 is formed of the same film as the data line 6a (see FIG. 10). The twelve image signal lines 6 are formed so as to run in parallel along the X direction.

  Each of the branch wirings E1 to E12 is wired along the Y direction, and has a first partial wiring formed of the same film as the capacitor line 400 and a second partial wiring formed of the same film as the gate electrode 3a. is doing. The first partial wirings of the branch wirings E1 to E12 are electrically connected to the corresponding image signal lines 6 through contact holes 64a opened in the third interlayer insulating film 43 (see FIG. 10). ing. The second partial wirings of the branch wirings E1 to E12 correspond to each other through contact holes 64b opened through the second interlayer insulating film 42 and the first interlayer insulating film 41 (see FIG. 10). It is electrically connected to the image signal line 6. In FIG. 12, both contact holes 64 a and 64 b are shown as contact holes 64. Further, each of the branch wirings E1 to E12 has a third partial wiring formed of the same film as the data line 6a (see FIG. 10). The third partial wiring is electrically connected to the first partial wiring via a contact hole 65a opened in the third interlayer insulating film, and penetrates the second interlayer insulating layer 42 and the first interlayer insulating film 41. The second partial wiring is electrically connected through the contact hole 65b opened. In FIG. 12, both contact holes 65a and 65b are shown as contact holes 65. That is, each of the branch wirings E1 to E12 is formed as a double wiring composed of the first partial wiring and the second partial wiring at a portion intersecting with the image signal line 6, and is a portion not intersecting with the image signal line 6. Is formed as a triple wiring composed of a first partial wiring, a second partial wiring, and a third partial wiring.

  In FIG. 12, the first shield wiring 210 extends along the Y direction between the wiring portion 114b in the sampling signal line 114 that supplies the sampling signal Si and the wiring portion 114a in the sampling signal line 114 that supplies the sampling signal Si + 1. Are wired.

  12 and 13, the first shield wiring 210 includes a first shield layer 210a formed of the same film as the capacitor line 400 (see FIG. 10) and a film of the same film as the gate electrode 3a (see FIG. 10). The second shield layer 210b is formed, and the third shield layer 210c is formed of the same film as the data line 6a (see FIG. 10).

  The first shield layer 210a and the second shield layer 210b are formed so as to overlap each other when viewed in plan on the TFT array substrate, and are formed so as to intersect with the 12 image signal lines 6. The first shield layer 210 a is electrically connected to the power supply wiring 601 through the contact hole 62 a opened in the third interlayer insulating film 43. The second shield layer 210b is electrically connected to the power supply wiring 601 through a contact hole 62b opened through the second interlayer insulating film 42 and the first interlayer insulating film 41. In FIG. 12, both contact holes 62 a and 62 b are shown as contact holes 62.

  The third shield layer 210c is formed closer to the control wirings X1 to X12 than a region that does not intersect the 12 image signal lines 6, that is, a region in the first shield wiring 210 that intersects the 12 image signal lines 6. ing. The third shield layer 210c is electrically connected to the first shield layer 210a through the contact hole 66a opened in the third interlayer insulating film 43, and the second interlayer insulating film 42 and the first interlayer insulating film. 41 is electrically connected to the second shield layer 210b through a contact hole 66b opened through 41. In FIG. 12, both contact holes 66a and 66b are shown as contact holes 66.

  That is, the first shield wiring 210 is formed as a double wiring composed of the first shield layer 210a and the second shield layer 210b at a portion that intersects with the image signal line 6, and a portion that does not intersect with the image signal line 6. Are formed as a triple wiring composed of a first shield layer 210a, a second shield layer 210b, and a third shield layer 210c.

  In FIG. 12, one second shield wiring 220 is provided on each side of each branch wiring group, and two second shield wirings 220 are provided for each branch wiring group. More specifically, between the branch wiring E1 belonging to the i-th branch wiring group and the wiring portion 114a that supplies the sampling signal Si, and between the branch wiring E12 belonging to the i-th branch wiring group and the wiring portion that supplies the sampling signal Si. 114b is formed along the Y direction.

  The second shield wiring 220 is configured in substantially the same manner as the first shield wiring.

  That is, the second shield wiring 220 includes a first shield layer formed of the same film as the capacitor line 400 (see FIG. 10) and a second shield formed of the same film as the gate electrode 3a (see FIG. 10). And a third shield layer formed of the same film as the data line 6a (see FIG. 10).

  The first shield layer and the second shield layer of the second shield wiring 220 are formed so as to intersect the twelve image signal lines 6. The first shield layer of the second shield wiring 220 is electrically connected to the power supply wiring 601 through a contact hole 63 a opened in the third interlayer insulating film 43. The second shield layer of the second shield wiring 220 is electrically connected to the power supply wiring 601 through a contact hole 63b opened through the second interlayer insulating film 42 and the first interlayer insulating film 41. . In FIG. 12, both contact holes 63a and 63b are shown as contact holes 63.

  The third shield layer of the second shield wiring 220 has control wirings X1 to X1 that are in a region that does not intersect the twelve image signal lines 6, that is, a region that intersects the twelve image signal lines 6 in the first shield wiring 210. It is formed on the X12 side. The third shield layer of the second shield wiring 220 is electrically connected to the first shield layer of the second shield wiring 220 through the contact hole 67a opened in the third interlayer insulating film 43, and is The second shield layer 220 is electrically connected to the second shield layer through a contact hole 67b opened through the interlayer insulating film 42 and the first interlayer insulating film 41. In FIG. 12, both contact holes 67 a and 67 b are shown as contact holes 67.

  That is, like the first shield wiring 210, the second shield wiring 220 is formed as a double wiring composed of the first shield layer and the second shield layer at a portion intersecting with the image signal line 6. In a portion not intersecting with the signal line 6, it is formed as a triple wiring composed of the first shield layer, the second shield layer, and the third shield layer.

  12 and 13, in the present embodiment, as described above, the first shield wiring 210 and the second shield wiring 220 are the same films as the capacitor line 400, the data line 6a, and the gate electrode 3a (that is, manufactured), respectively. Film formed on the same occasion in the process). Therefore, the first shield wiring 210 and the second shield wiring 220 can be formed on the same occasion as the formation of the capacitor line 400, the data line 6a, and the gate electrode 3a. That is, the first shield wiring 210 and the second shield wiring 220 can be formed without complicating the manufacturing process.

  Further, in FIG. 12, particularly in the present embodiment, as described above, the first shield wiring 210 and the second shield wiring 220 are electrically connected to the power supply wiring 601. Since the first shield wiring 210 and the second shield wiring 220 have the potential of the X-side low-potential power supply VSSX that is a constant potential, the shielding function of the first shield wiring 210 and the second shield wiring 220 can be enhanced. Specifically, between the branch lines at the block boundary, that is, the branch line E12 belonging to the i-th branch line group (that is, the branch line on the i + 1-th branch line group side among the branch lines Ek belonging to the i-th branch line group). And E1 belonging to the i + 1 branch wiring group (that is, the branch wiring on the i-th branch wiring group side of the branch wiring Ek belonging to the i + 1 branch wiring group) can be more reliably reduced. Similarly, between the branch wiring Ek and the sampling signal line 114 at the block boundary, that is, the branch wiring E12 belonging to the i-th branch wiring group (that is, the sampling signal line 114 side of the branch wiring Ek belonging to the i-th branch wiring group). Electromagnetic interference between the branch wiring) and the wiring portion 114b of the sampling signal line 114 can be more reliably reduced. Furthermore, since the first shield wiring 210 and the second shield wiring 220 are set to a constant potential by being electrically connected to the power supply wiring 601, the manufacturing process is hardly complicated.

As described above, according to the liquid crystal device according to the present embodiment, the first shield wiring 210 and the second shield wiring are provided between the i-th branch wiring group and the i + 1-th branch wiring group (that is, the block boundary). 220, between the branch wirings Ek at the block boundary (that is, the branch wiring Ek on the i + 1 branch wiring group side of the branch wiring Ek belonging to the i th branch wiring group and the branch wiring Ek belonging to the i + 1 branch wiring group). Among them, electromagnetic interference between the branch wiring Ek on the i-th branch wiring group side can be reduced or prevented. Further, the second shield wiring 220 can reduce or prevent electromagnetic interference between the branch wiring Ek and the sampling signal line 114 (specifically, the wiring portion 114a or 114b). As a result, the potential of one branch wiring Ek (in other words, the data line Dk connected thereto via the sampling switch 71 due to the potential fluctuation of another adjacent branch wiring Ek or sampling signal line 114 at the boundary of the block. Can be suppressed or prevented from fluctuating. As a result, series unevenness or block unevenness in image display can be reduced, and high-quality image display is possible.
<Electronic equipment>
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described.

  First, a projector using this liquid crystal device as a light valve will be described. FIG. 14 is a plan view showing a configuration example of the projector. As shown in FIG. 14, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R and 1110B.

  In addition, since light corresponding to each primary color of R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic device described with reference to FIG. 14, a mobile personal computer, a mobile phone, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, and an electronic notebook , Calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), The present invention can also be applied to an organic EL display, a digital micromirror device (DMD), an electrophoresis apparatus, and the like.

  The present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and an electro-optical device with such a change, In addition, an electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

It is a top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment. It is the HH 'sectional view taken on the line of FIG. FIG. 2 is a block diagram schematically showing the configuration of various drive circuits of the liquid crystal device according to the first embodiment. 3 is an equivalent circuit diagram of a plurality of pixel units of the liquid crystal device according to the first embodiment. FIG. FIG. 3 is an equivalent circuit diagram of a data line driving circuit, a sampling circuit, an image signal line, and other various signal lines of the liquid crystal device according to the first embodiment. FIG. 3 is an equivalent circuit diagram of a buffer unit circuit of the liquid crystal device according to the first embodiment. FIG. 6 is an explanatory diagram showing an arrangement of first and second shield wirings, branch wirings, and sampling signal lines in the vicinity of the boundary between adjacent branch wiring groups of the liquid crystal device according to the first embodiment. 6 is a timing chart showing potential changes in data lines near the boundary between the i-th data line group and the (i + 1) -th data line group of the liquid crystal device according to the first embodiment. It is a timing chart of the same meaning as FIG. 8 in a comparative example. It is sectional drawing which shows the structure of the cross-sectional part of the pixel part of the liquid crystal device which concerns on 1st Embodiment. FIG. 3 is a plan view showing a specific configuration of a buffer unit circuit of the liquid crystal device according to the first embodiment. FIG. 3 is a plan view showing a specific configuration of first and second shield wirings of the liquid crystal device according to the first embodiment. It is the sectional view on the AA 'line of FIG. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  6a ... data line, 6 ... image signal line, 7 ... sampling circuit, 9a ... pixel electrode, 10 ... TFT array substrate, 10a ... image display area, 20 ... counter substrate, 11a ... scanning line, 21 ... counter electrode, 23 ... Light shielding film, 50 ... Liquid crystal layer, 52 ... Sealing material, 53 ... Frame light shielding film, 71 ... Sampling switch, 101 ... Data line driving circuit, 102 ... External circuit connection terminal, 104 ... Scanning line driving circuit, 106 ... Vertical conduction terminal 107 ... Vertical conductive material, 114 ... Sampling signal line, 210 ... First shield wiring, 220 ... Second shield wiring, E1-E12 ... Branch wiring

Claims (7)

On the board
A plurality of pixel portions;
A plurality of scanning lines and a plurality of data lines wired in a pixel region provided with the plurality of pixel portions;
Of the plurality of data lines, N systems (where N is a natural number of 2 or more) N lines of serial-parallel converted images supplied for each of a plurality of data line groups configured as one group. N image signal lines for supplying signals;
The N image signal lines are formed so as to intersect with the wiring direction, and a plurality of data lines are arranged corresponding to the arrangement of the plurality of data lines, and one end side corresponds to one of the N image signal lines. A plurality of image signal branch wirings each electrically connected to the book;
A sampling circuit that is electrically connected to the other end side of the plurality of image signal branch wirings and includes a plurality of sampling switches that respectively supply the image signal to the plurality of data lines according to a sampling signal;
The N image signal branch lines corresponding to the data line group are provided for each image signal branch line group, and each of the N image signal branch lines includes a wiring portion wired on both sides of the image signal branch line group. A plurality of sampling signal lines for supplying the sampling signal for each of the sampling switches electrically connected to the image signal branch wiring of
A first constant potential wiring provided between the wiring portions respectively corresponding to the image signal branch wiring group adjacent to each other ;
Each of the plurality of pixel portions includes various electronic elements electrically connected to the scanning line and the data line,
The first constant potential wiring is formed from the same film as three different conductive films among the plurality of conductive films constituting the scanning line, the data line, and the electronic element, and is electrically connected to each other. An electro-optical device comprising the three conductive films formed . A shift register that outputs a transfer signal that defines a timing at which the image signal should be supplied to the plurality of pixel units;
A plurality of buffer circuits which are provided for each data line group and supply the transfer signal as the sampling signal for each sampling signal line corresponding to the data line group;
Power supply wiring for supplying a power supply potential to each of the plurality of buffer circuits,
The electro-optical device according to claim 1, wherein the first constant potential wiring is electrically connected to the power supply wiring. 3. The electro-optical device according to claim 1, further comprising a second constant potential wiring provided between the image signal branch wiring group and the wiring portion on the substrate. A shift register that outputs a transfer signal that defines a timing at which the image signal should be supplied to the plurality of pixel units;
A plurality of buffer circuits which are provided for each data line group and supply the transfer signal as the sampling signal for each sampling signal line corresponding to the data line group;
Power supply wiring for supplying a power supply potential to each of the plurality of buffer circuits,
The electro-optical device according to claim 3 , wherein the second constant potential wiring is electrically connected to the power supply potential wiring. Each of the plurality of pixel portions includes various electronic elements electrically connected to the scanning line and the data line,
Said second constant potential wiring, the scanning lines, to claim 3 or 4, characterized in that it is formed of the same film and at least one of a plurality of conductive films respectively constituting the data lines and the electronic device The electro-optical device described. It said second constant potential wiring, and characterized in that it comprises three conductive film are electrically connected to each other while being respectively formed from different three conductive film and the same film of the plurality of conductive films The electro-optical device according to claim 5 . Electronic apparatus including the electro-optical device according to any one of claims 1 to 6.

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