JP4945985B2 - Electro-optical device and electronic apparatus including the same - Google Patents

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  This type of electro-optical device is generally driven on the basis of an image signal subjected to serial-parallel conversion. For example, in a liquid crystal device, a plurality of data lines wired to an image display area on a substrate are divided into blocks every predetermined number, and serial-parallel converted image signals are included in the block in block units. The data line is supplied via a sampling switch. Thus, a predetermined number of data lines are simultaneously driven and a plurality of data lines are sequentially driven every predetermined number. Further, in this type of electro-optical device, it is desired to increase the driving capability of the buffer circuit for sufficiently increasing or shaping the sampling control signal for turning on / off the sampling switch. For example, Patent Document 1 discloses a buffer circuit in which a plurality of stages each including a plurality of inverters connected in parallel are connected in series. As a result, the drive capability of the buffer circuit is enhanced, and a sufficiently large sampling control signal can be simultaneously supplied to a plurality of sampling switches included in each block. As a result, so-called ghost and crosstalk in image display can be prevented.

JP 2003-337545 A

  However, the technique disclosed in Patent Document 1 has a technical problem in that a vertical band or a vertical stripe is generated on the screen every phase development because the power is not supplied uniformly between the phase developments.

  The present invention has been made in view of, for example, the above-described problems, and provides an electro-optical device that reduces the occurrence of a vertical band on a screen for each phase development, and an electronic apparatus including the electro-optical device. Is an issue.

Electro-optical device of the present invention, in order to solve the above problems, a pixel portion of the multiple, a plurality of scanning lines and a plurality of data lines to said plurality of pixel areas where the pixel portion is arranged, wherein the N In order to supply an image signal for each data line group including one data line, N images (where N is a natural number of 2 or more) N-images to which the serial-parallel converted image signals are supplied are supplied. A sampling circuit including a plurality of sampling switches electrically connected to the signal lines and supplying the image signals to the plurality of data lines in response to a sampling signal; and the plurality of pixel portions. A shift register that outputs a transfer signal that defines the timing at which the image signal should be supplied is provided for each data line group, and the transfer signal is provided as a sampling signal to the data line group. A buffer circuit for supplying to each of the sampling switch, the power is supplied to the buffer circuit, and a power source wiring formed of a plurality of partial lines formed in different layers with an interlayer insulating film, wherein the buffer circuit, A plurality of inverters connected in parallel in a first direction; and the power supply wiring extends along the plurality of inverters in the first direction and extends in a second direction intersecting the first direction. Are connected to the plurality of inverters via a plurality of lead wirings, and the plurality of partial wirings constituting the power supply wiring are respectively connected to the inverters at both ends in the first direction. Are electrically connected to each other through a contact hole provided between the lead-out regions of the power supply wiring.

  According to the electro-optical device of the present invention, during operation, N image signals subjected to serial-parallel conversion (also referred to as “serial-parallel expansion” or “phase expansion”) are converted into N images. The signal is supplied to the signal line, and further supplied to a plurality of sampling switches constituting the sampling circuit. For example, N image signals are converted into three-phase, six-phase, twelve-phase, twenty-four-phase, and so on by an external circuit in order to realize high-definition image display while suppressing an increase in drive frequency. Etc., and generated by being converted into a plurality of parallel image signals.

  In parallel with such supply of the image signal, the transfer signal transferred from the shift register at a predetermined timing for each sampling switch corresponding to the data line group is increased in potential by each of the plurality of buffer circuits, and sampled. Supplied as a signal. That is, a sampling signal is simultaneously supplied from one corresponding buffer circuit to N sampling switches corresponding to N data lines constituting the data line group. The sampling switch is composed of, for example, a single-channel TFT, and the source is electrically connected to the output terminal of the buffer circuit, the drain is connected to the data line, and the sampling signal is supplied to the gate to turn it on. It becomes. Then, N image signals are sequentially supplied to the plurality of data lines by the sampling circuit for each data line group according to the sampling signal. Therefore, data lines belonging to the same data line group are driven simultaneously. Each of the plurality of buffer circuits includes, for example, inverters that are electrically connected in a plurality of stages in series, and a level shifter that shifts the driving capability or the voltage level of the transfer signal to the voltage of the transfer signal transferred from the shift register. Further, for example, it functions as a buffer for performing waveform shaping and phase correction of the transfer signal.

  When the data line is driven in this way, in each pixel unit, for example, the pixel electrode is selected according to the scanning signal supplied from the scanning line driving circuit via the scanning line, and the pixel switching element that performs the switching operation Then, an image signal is supplied from the data line to the pixel electrode. Thus, for example, a liquid crystal element as a display element performs image display in a pixel area or a pixel array area (or also referred to as “image display area”) based on the supplied image signal.

  In the present invention, in particular, the power supply wiring for supplying power to each of the plurality of buffer circuits is formed from a plurality of conductive films located in different layers via an interlayer insulating film, and through a plurality of contact holes. It has a plurality of partial wirings electrically connected. Therefore, compared with the case where the power supply wiring for supplying power to each of the plurality of buffer circuits is formed from only one conductive film, the resistance of the wiring is reduced without increasing the area of the region for wiring. Can be achieved. Therefore, power can be stably supplied to the plurality of buffer circuits, and the driving capability of the plurality of buffer circuits can be increased.

  Further, in the present invention, in particular, a plurality of contact holes for electrically connecting a plurality of partial wirings are provided for each data line group. That is, a plurality of contact holes are provided for each block or phase development that has undergone serial-barrel conversion (or phase development). In other words, the plurality of contact holes are arranged on the power supply wiring in a plan view on the substrate, for example, at almost or completely the same pitch as the arrangement pitch of the plurality of buffer circuits arranged along the power supply wiring. . Therefore, almost or completely the same potential can be supplied to each of the plurality of buffer circuits. That is, the power can be supplied to the plurality of buffer circuits almost or completely uniformly. Therefore, it is possible to reduce the variation in the voltage of the sampling signal that can occur for each data line group (or for each block). As a result, display unevenness (that is, vertical band-shaped display unevenness) due to variations in sampling signal voltage, such as display brightness varying from block to block, can be reduced or completely eliminated.

  A plurality of contact holes may be provided for each data line group, or a plurality of contact holes may be provided. When a plurality of data lines are provided, the positional relationship between the plurality is preferably the same for each data line group.

  In another aspect of the electro-optical device according to the aspect of the invention, the power supply wiring includes a first power supply wiring that supplies a power supply having a first potential and a second power supply that supplies a power supply having a second potential lower than the first potential. Power supply wiring including power supply wiring.

  According to this aspect, the first potential power and the second potential lower than the first potential are supplied to each buffer circuit. The voltage of the transfer signal is changed between the first potential and the second potential by, for example, a plurality of inverters connected in series constituting each buffer circuit, and the driving capability is gradually increased. That is, it is possible to output a transfer signal whose driving capability is reliably increased by each buffer circuit as a sampling signal. At this time, since the plurality of contact holes are provided for each data line group in each of the first and second power supply wirings, the display unevenness (that is, the vertical band-like shape) for each block due to the variation in the voltage of the sampling signal. Display unevenness) can be reduced or completely eliminated.

  In another aspect of the electro-optical device according to the aspect of the invention, each of the plurality of pixel units includes a storage capacitor in which a lower electrode, a dielectric film, and an upper electrode are sequentially stacked on the substrate. The first partial wiring formed from the same film as the data line, and the second partial wiring formed from the same film as the capacitor line electrically connected to one of the lower electrode and the upper electrode It consists of.

  According to this aspect, the plurality of partial wirings are composed of the first and second partial wirings. The first partial wiring is formed from the same film as the data line, and the second partial wiring is formed from the same film as the capacitor line. Here, the “same film” according to the present invention means films formed on the same occasion in the manufacturing process, and are the same kind of film. Note that the phrase “same film” does not mean that the film is continuous as a single film, but basically a film part of the same film that is separated from each other is sufficient. It is. Therefore, the first and second partial wirings can be formed on the same occasion as the data line and the capacitor wiring, respectively. That is, the power supply wiring can be formed from a plurality of conductive films without complicating the manufacturing process.

  Note that the storage capacitor improves, for example, the potential holding characteristic of the pixel electrode constituting the pixel portion, and the display can have high contrast.

  In another aspect of the electro-optical device according to the aspect of the invention, a sampling signal line that is disposed on a lower layer side of the plurality of partial wirings on the substrate and supplies the sampling signal, and planar on the substrate As seen from the above, in the region where the plurality of contact holes are formed, the same film as at least one of the scanning line, the sampling signal line, the lower electrode, and the upper electrode on the lower layer side than the plurality of partial wirings And an adjustment film.

  According to this aspect, for example, the height of the plurality of partial wirings from the substrate surface is adjusted by the adjustment film as compared with the case where there is no adjustment film, so the interlayer distance between the plurality of partial wirings is shortened. be able to. More specifically, among the plurality of partial wirings, one partial wiring adjusted to be higher from the substrate surface by the adjustment film is laminated on the chemical polishing process (Chemical Mechanical Polishing: The distance from the surface of the interlayer insulating film flattened by CMP) or polishing treatment is shorter than that of the portion without the adjustment film. Therefore, if the surface of the interlayer insulating film between the plurality of partial wirings is planarized, the resistance caused by the contact hole (that is, contact resistance) can be reduced. Therefore, the resistance of the power supply wiring can be reduced, and the power can be supplied more stably to the plurality of buffer circuits. Furthermore, the time required for manufacturing a plurality of contact holes (for example, etching time) can be shortened, and time control in etching becomes easy.

  In another aspect of the electro-optical device according to the aspect of the invention, each of the plurality of contact holes includes a plurality of partial contact holes that are adjacent to each other when viewed in plan on the substrate.

  According to this aspect, each of the plurality of contact holes includes a plurality of partial contact holes. Here, the “partial contact hole” according to the present invention is a contact hole that constitutes a part of a plurality of contact holes, and is a contact smaller than each of the plurality of contact holes as viewed in plan on the substrate. It means a hall. Further, the plurality of partial contact holes are adjacent to each other. Here, “adjacent to each other” according to the present invention means that a plurality of partial contact holes are arranged at a distance that is the same or shorter than the diameter of any of the plurality of partial contact holes. means. Therefore, for example, a plurality of partial contact holes are opened in an interlayer insulating film located between a plurality of power supply wirings, as compared with a case where a plurality of partial contact holes are not adjacent to each other, that is, apart from each other. As a result, the occurrence of cracks in the interlayer insulating film can be reduced or prevented.

  An electronic apparatus of the present invention comprises the above-described electro-optical device of the present invention in order to solve the above problems.

  According to the electronic apparatus of the present invention, since it includes the electro-optical device of the present invention described above, a projection display device, a mobile phone, an electronic notebook, a word processor, a viewfinder type, or a monitor capable of high-quality display. Various electronic devices such as a direct-view video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. Further, as the electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper can be realized.

  Particularly, since the plurality of power supply lines are electrically connected by a plurality of contact holes provided for each data line group, display unevenness or band unevenness for each data line group is reduced.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.
<First Embodiment>
The liquid crystal device according to the first embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line H-H 'in FIG.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are surrounded by an image display region 10a as an example of the “pixel region” of the present invention. They are bonded to each other by a sealing material 52 provided in the sealing area located.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. The sampling circuit 7 is provided so as to be covered with the frame light shielding film 53 on the inner side of the seal region along the one side. Further, the scanning line driving circuit 104 is provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side. On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  On the TFT array substrate 10, a lead wiring 90 is formed for electrically connecting the external circuit connection terminal 102 to the data line driving circuit 101, the scanning line driving circuit 104, the vertical conduction terminal 106, and the like. . In particular, the power supply wiring 601 for the data line driving circuit as an example of the “power supply wiring” according to the present invention for supplying power for driving the data line driving circuit, which will be described later, 602 is included.

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which wiring such as a pixel switching TFT (Thin Film Transistor) as a driving element, a scanning line, and a data line is formed. In the image display area 10a, a pixel electrode 9a is provided in an upper layer of wiring such as a pixel switching TFT, a scanning line, and a data line. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. A counter electrode 21 made of a transparent material such as ITO is formed on the light shielding film 23 so as to face the plurality of pixel electrodes 9a. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Although not shown here, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the TFT array substrate 10 is used for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or at the time of shipment. An inspection circuit, an inspection pattern, or the like may be formed.

  Next, the operation of the liquid crystal device of this embodiment will be described with reference to FIGS. FIG. 3 is a block diagram showing the main configuration of the liquid crystal device of the present embodiment, and FIG. 4 is a block diagram showing the configuration of the data line driving circuit.

  3, in the liquid crystal device of this embodiment, a TFT array substrate 10 made of, for example, a quartz substrate, a glass substrate, or a silicon substrate and a counter substrate 20 (not shown here) are arranged to face each other with a liquid crystal layer interposed therebetween. The voltage applied to the pixel electrodes 9a that are partitioned in the image display region 10a is controlled to modulate the electric field applied to the liquid crystal layer for each pixel. Thereby, the amount of transmitted light between the two substrates is controlled, and the image is displayed in gradation. The liquid crystal device according to the present embodiment employs a TFT active matrix driving method, and a plurality of pixel electrodes 9 a arranged in a matrix and a plurality of pixel electrodes 9 a arranged in a matrix are arranged in the pixel display region 10 a of the TFT array substrate 10. The scanning line 11a and the data line 6a are formed, and a pixel portion corresponding to the pixel is constructed. Although not shown here, between each pixel electrode 9a and the data line 6a, a TFT or a pixel electrode whose conduction or non-conduction is controlled according to a scanning signal supplied via the scanning line 11a. A storage capacitor for maintaining the voltage applied to 9a is formed. In addition, a drive circuit such as the data line drive circuit 101 is formed in the peripheral area of the image display area 10a.

  The data line driving circuit 101 drives the sampling circuit 7, and converts the image signals VID1 to VID6 supplied to the image signal line 6 into sampling circuit driving signals Si (i = 1,...) As reference clock signals for applying data signals. n), and each is applied as a data signal to the data line 6a.

  As shown in FIG. 4, the data line driving circuit 101 includes a shift register 400 and n buffer circuits 500 (where n is a natural number).

  The shift register 400 receives a plurality of transfer signals Pi (i = 1,..., N) via the signal line 404 based on the X-side clock signal CLX (and its inverted signal CLX ′) and the shift register start signal DX. Are sequentially output to the buffer circuit 500.

  The buffer circuit 500 is configured by electrically connecting a plurality of inverters as will be described later. The buffer circuit 500 is driven by a power supply VSSX having a potential lower than that of the power supply VDDX supplied via the data line drive circuit power supply wiring 601 and the power supply VDDX supplied via the data line drive circuit power supply wiring 602. ing. The data line drive circuit power supply wirings 601 and 602 are examples of the “power supply wiring” according to the present invention. The transfer signal Pi transferred from the shift register 400 is level-shifted in the drive capability or voltage level of the voltage, and is output to the signal line 114 as a sampling circuit drive signal Si (i = 1,..., N). Furthermore, the buffer circuit 500 also functions as a buffer for performing waveform shaping and phase correction of the transfer signal Pi.

  In FIG. 4, image signals VID <b> 1 to VID <b> 6 are serial-parallel converted into six phases, that is, phase-expanded by an external image signal processing circuit, and input to a sampling circuit 7 via six image signal lines 6. . Note that the number of serial-parallel conversion of the image signal, that is, the number of phase expansions is not limited to six phases, and may be three phases, twelve phases, twenty-four phases,.

  The sampling circuit 7 includes a sampling switch 71 composed of a P-channel or N-channel single-channel TFT or a complementary TFT. On the other hand, the sampling circuit drive signal Si (i = 1,..., N) output from the data line drive circuit 101 (in other words, the buffer circuit 500) has six signal lines 114 that branch into six. Input to the adjacent sampling switch 71. Accordingly, the sampling circuit 7 is driven for every six sampling switch 71 groups. In this way, when parallel image signals obtained by converting serial image signals are simultaneously supplied to a plurality of image signal lines 6, image signals can be input to the data lines 6a for each group and driven. The frequency is suppressed.

  In FIG. 3 again, the scanning line driving circuit 104 uses a scanning signal application reference clock to scan the plurality of pixel electrodes 9a arranged in a matrix in the array direction of the scanning lines 11a by a data signal and a scanning signal. A scanning signal generated based on a certain Y-side clock signal CLY (and its inverted signal CLY ′) and a shift register start signal DY is sequentially applied to the plurality of scanning lines 11a. In that case, a voltage is simultaneously applied to each scanning line 11a from both ends.

  Next, the configuration of the buffer circuit of the liquid crystal device according to the present embodiment will be described with reference to FIGS. FIG. 5 is a circuit diagram showing the circuit configuration of the buffer circuit, and FIG. 6 is an equivalent circuit diagram showing the configuration of the buffer circuit. FIG. 7 is a plan view showing a specific configuration of the power supply wiring for the buffer circuit and the data line driving circuit.

  As shown in FIGS. 5 to 7, the buffer circuit 500 is configured by connecting inverters 501 to 503 in three stages in series in the direction along the data line 6 a (that is, the Y direction), and further inverters 501 to 503. In each of the above, seven inverters are connected in parallel in the direction along the scanning line 11a (that is, the X direction). That is, the inverter 501 is configured by connecting inverters 511 to 517 in parallel, the inverter 502 is configured by connecting inverters 521 to 527 in parallel, and the inverter 503 is configured by connecting inverters 531 to 537 in parallel. ing. Thereby, the driving capability by each of the inverters 501 to 503 (that is, the inverter for one stage) is enhanced.

  Further, as shown in FIGS. 5 and 7, the inverters 511 to 517, 521 to 527, and 531 to 537 are all complementary by combining P channel type and N channel type TFTs whose channel width direction is formed in the Y direction. It is configured as a type TFT. That is, all of the inverters 511 to 517, 521 to 527, and 531 to 537 have the lead wiring 610 drawn from the data line driving circuit power supply wiring 601 and the lead wiring 620 drawn from the data line driving circuit power supply wiring 602. In between, a P-channel TFT and an N-channel TFT are connected in series.

  In addition, as shown in FIG. 7, the channel widths L1 to L3 of the TFTs constituting the inverters 501 to 503 are increased stepwise (that is, the channel width L2 is larger than the channel width L1 and is larger than the channel width L2). Since the channel width L3 is also larger), the entire buffer circuit 500 can cope with a high load, and the number of sampling switches 71 that can be driven simultaneously can be increased.

  Next, the configuration of the pixel portion of the liquid crystal device according to the present embodiment will be described with reference to FIGS. FIG. 8 is an equivalent circuit of various elements and wirings in the plurality of pixel portions, and FIGS. 9 and 10 are plan views of the plurality of adjacent pixel portions. 9 and 10 respectively show the lower layer portion (FIG. 9) and the upper layer portion (FIG. 10) in the laminated structure described later.

  FIG. 11 is a cross-sectional view taken along line AA ′ when FIGS. 9 and 10 are overlapped. In FIG. 11, the scale of each layer / member is different for each layer / member so that each layer / member can be recognized on the drawing.

  In FIG. 8, a pixel electrode 9a and a TFT 30 for controlling the switching of the pixel electrode 9a are formed in a plurality of pixel portions formed in a matrix in the image display region of the liquid crystal device according to the present embodiment. The data line 6 a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals VS1, VS2,..., VSn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group of a plurality of adjacent data lines 6a. Good.

  Further, the gate electrode 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are pulse-sequentially applied in this order to the scanning line 11a and the gate electrode 3a at a predetermined timing. It is comprised so that it may apply. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal VS1, VS2,..., VSn supplied from the data line 6a is obtained by closing the switch of the TFT 30 as a switching element for a certain period. Write at a predetermined timing.

  Image signals VS1, VS2,..., VSn written to the liquid crystal through the pixel electrode 9a are held for a certain period with the counter electrode formed on the counter substrate. The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to the image signal is emitted from the electro-optical device as a whole.

  Further, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. The storage capacitor 70 is provided side by side with the scanning line 11a, and includes a fixed potential side capacitor electrode and a capacitor electrode 300 fixed to a constant potential.

  Hereinafter, with reference to FIGS. 9 to 11, a specific configuration of the electro-optical device that realizes the above-described circuit operation by the data line 6a, the scanning line 11a, the gate electrode 3a, the TFT 30, and the like will be described. explain.

  First, in FIG. 10, a plurality of pixel electrodes 9a are provided in a matrix on the TFT array substrate 10 (the outline is indicated by a dotted line portion), and as shown in FIGS. Data lines 6a and scanning lines 11a are provided along the vertical and horizontal boundaries of the pixel electrode 9a. The data line 6a has a laminated structure including, for example, an aluminum film, and the scanning line 11a has, for example, a conductive polysilicon film. Further, the scanning line 11a is electrically connected to the gate electrode 3a facing the channel region 1a ′ shown by the hatched region rising to the right in FIG. 9 in the semiconductor layer 1a through the contact hole 12cv. The electrode 3a is included in the scanning line 11a. That is, each of the intersections between the gate electrode 3a and the data line 6a is provided with a pixel switching TFT 30 in which the gate electrode 3a included in the scanning line 11a is opposed to the channel region 1a ′. As a result, the TFT 30 (excluding the gate electrode) is configured to exist between the gate electrode 3a and the scanning line 11a.

  Next, as shown in FIG. 11, for example, a TFT array substrate 10 made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and a counter substrate 20 made of, for example, a glass substrate or a quartz substrate, are provided. Yes.

  The pixel electrode 9a is provided on the TFT array substrate 10 side, and an alignment film 16 subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive film such as an ITO film. On the other hand, a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 21. . The counter electrode 21 is made of a transparent conductive film such as an ITO film, for example, like the pixel electrode 9a described above.

  Between the TFT array substrate 10 and the counter substrate 20 arranged so as to face each other, an electro-optical material such as liquid crystal is sealed in a space surrounded by the above-described sealing material 52 (see FIGS. 1 and 2). 50 is formed. The liquid crystal layer 50 takes a predetermined alignment state by the alignment films 16 and 22 in a state where an electric field from the pixel electrode 9a is not applied.

  On the other hand, on the TFT array substrate 10, in addition to the pixel electrode 9a and the alignment film 16, various configurations including these are provided in a laminated structure. As shown in FIG. 11, this stacked structure includes, in order from the bottom, a first layer including the scanning line 11a, a second layer including the TFT 30 including the gate electrode 3a, a third layer including the storage capacitor 70, and the data line 6a. And the like, a fifth layer including the capacitor wiring 400 and the like, and a sixth layer (uppermost layer) including the pixel electrode 9a and the alignment film 16 and the like. Further, the base insulating film 12 is provided between the first layer and the second layer, the first interlayer insulating film 41 is provided between the second layer and the third layer, and the second interlayer insulating film 42 is provided between the third layer and the fourth layer. A third interlayer insulating film 43 is provided between the fourth layer and the fifth layer, and a fourth interlayer insulating film 44 is provided between the fifth layer and the sixth layer, so that the above-described elements are short-circuited. Is preventing. These various insulating films 12, 41, 42, 43, and 44 are also provided with contact holes for electrically connecting the high concentration source region 1d in the semiconductor layer 1a of the TFT 30 and the data line 6a, for example. ing. Hereinafter, each of these elements will be described in order from the bottom. Of the foregoing, the first to third layers are shown in FIG. 9 as lower layer portions, and the fourth to sixth layers are shown in FIG. 10 as upper layer portions.

(Laminated structure / Structure of first layer-Scanning line, etc.)
First, for example, the first layer includes at least one of refractory metals such as Ti, Cr, W, Ta, and Mo, a metal simple substance, an alloy, a metal silicide, a polysilicide, and a laminate of these, Alternatively, a scanning line 11a made of conductive polysilicon or the like is provided. The scanning lines 11a are patterned in stripes along the X direction in FIG.

(Laminated structure / Second layer structure-TFT, etc.)
Next, the TFT 30 including the gate electrode 3a is provided as the second layer. As shown in FIG. 11, the TFT 30 has an LDD (Lightly Doped Drain) structure, and includes the above-described gate electrode 3a, for example, a polysilicon film, and a channel formed by an electric field from the gate electrode 3a. The channel region 1a ′ of the semiconductor layer 1a to be formed, the insulating film 2 including a gate insulating film that insulates the gate electrode 3a from the semiconductor layer 1a, the low concentration source region 1b and the low concentration drain region 1c in the semiconductor layer 1a, and the high concentration A source region 1d and a high concentration drain region 1e are provided.

  In addition, a relay electrode 719 is formed on the second layer as the same film as the gate electrode 3a described above. As shown in FIG. 9, the relay electrode 719 is formed in an island shape so as to be located at the approximate center of one side extending in the X direction of each pixel electrode 9a as seen in a plan view. Since the relay electrode 719 and the gate electrode 3a are formed as the same film, when the latter is made of a conductive polysilicon film or the like, the former is also made of a conductive polysilicon film or the like.

  The above-described TFT 30 preferably has an LDD structure as shown in FIG. 11, but may have an offset structure in which impurities are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c. A self-aligned TFT that implants impurities at a high concentration as a mask and forms a high concentration source region and a high concentration drain region in a self-aligning manner may be used.

(Laminated structure / Structure between first layer and second layer-Underlying insulating film-)
A base insulating film 12 made of, for example, a silicon oxide film is provided on the scanning line 11a described above and below the TFT 30. The base insulating film 12 has a function of insulating the TFT 30 from the scanning line 11a.

  Groove-shaped contact holes 12cv along the channel length direction of the semiconductor layer 1a extending along the data line 6a described later are dug in the base insulating film 12 on both sides of the semiconductor layer 1a in plan view. In correspondence with the contact hole 12cv, the gate electrode 3a stacked above the contact hole 12cv includes a concave portion formed on the lower side. Further, since the gate electrode 3a is formed so as to fill the entire contact hole 12cv, a side wall portion 3b formed integrally with the gate electrode 3a is extended. ing.

(Laminated structure / 3rd layer configuration-storage capacity, etc.)
A storage capacitor 70 is provided in the third layer following the second layer. The storage capacitor 70 includes a lower electrode 71 as a pixel potential side capacitor electrode connected to the high concentration drain region 1e of the TFT 30 and the pixel electrode 9a, and a capacitor electrode 300 as a fixed potential side capacitor electrode. It is formed by arrange | positioning through. According to the storage capacitor 70, it is possible to remarkably improve the potential holding characteristic in the pixel electrode 9a. Here, the lower electrode 71 is an example of a “lower electrode” according to the present invention, and the capacitor electrode 300 is an example of an “upper electrode” according to the present invention.

  More specifically, the lower electrode 71 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitor electrode. However, the lower electrode 71 may be composed of a single layer film or a multilayer film containing a metal or an alloy. In addition to the function as a pixel potential side capacitor electrode, the lower electrode 71 has a function of relay-connecting the pixel electrode 9a and the high concentration drain region 1e of the TFT 30. The relay connection here is performed through the relay electrode 719.

  The capacitor electrode 300 functions as a fixed potential side capacitor electrode of the storage capacitor 70. The capacitor electrode 300 is electrically connected to a capacitor wiring 400 having a fixed potential described later. Further, the capacitor electrode 300 includes at least one of refractory metals such as Ti, Cr, W, Ta, and Mo, a simple metal, an alloy, a metal silicide, a polysilicide, a laminate of these, or preferably It consists of tungsten silicide.

  As shown in FIG. 11, the dielectric film 75 is, for example, a relatively thin silicon oxide film such as an HTO (High Temperature Oxide) film, an LTO (Low Temperature Oxide) film having a film thickness of about 5 to 200 nm, or a silicon nitride film. Consists of More specifically, the dielectric film 75 has a two-layer structure such that the lower layer is a silicon oxide film 75a and the upper layer is a silicon nitride film 75b. The dielectric film 75 may be configured to have a three-layer structure such as a silicon oxide film, a silicon nitride film, and a silicon oxide film, or a laminated structure of more than that. Of course, a single layer structure may be used.

(Laminated structure, configuration between second layer and third layer—first interlayer insulating film)
On the TFT 30 to the gate electrode 3a and the relay electrode 719 described above and below the storage capacitor 70, for example, NSG (non-silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG ( A silicate glass film such as boron phosphorus silicate glass), a silicon nitride film, a silicon oxide film, or the like, or a first interlayer insulating film 41 preferably made of NSG is formed.

  A contact hole 81 that electrically connects a high-concentration source region 1 d of the TFT 30 and a data line 6 a described later is opened in the first interlayer insulating film 41 while penetrating the second interlayer insulating film 42 described later. . The first interlayer insulating film 41 is provided with a contact hole 83 that electrically connects the high-concentration drain region 1 e of the TFT 30 and the lower electrode 71 constituting the storage capacitor 70. Further, the first interlayer insulating film 41 is provided with a contact hole 881 for electrically connecting the lower electrode 71 as a pixel potential side capacitor electrode constituting the storage capacitor 70 and the relay electrode 719. In addition, a contact hole 882 for electrically connecting the relay electrode 719 and a later-described second relay electrode 6a2 is opened in the first interlayer insulating film 41 while penetrating the second interlayer insulating film 42 described later. It is holed.

(Laminated structure / 4th layer configuration-data lines, etc.)
A data line 6a is provided in the fourth layer following the third layer. As shown in FIG. 11, the data line 6a includes, in order from the lower layer, a layer made of aluminum (see reference numeral 41A in FIG. 11), a layer made of titanium nitride (see reference numeral 41TN in FIG. 11), and a layer made of a silicon nitride film ( It is formed as a film having a three-layer structure (see reference numeral 401 in FIG. 11).

  Further, the fourth layer is formed with the capacitor wiring relay layer 6a1 and the second relay electrode 6a2 as the same film as the data line 6a. As shown in FIG. 10, these are not formed so as to have a planar shape continuous with the data line 6a when viewed in plan, but are formed so that each person is divided by patterning. Yes.

(Laminated structure / Structure between third and fourth layers-second interlayer insulating film)
Above the storage capacitor 70 described above and below the data line 6a, for example, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film or a silicon oxide film, or preferably TEOS gas is used. A second interlayer insulating film 42 formed by plasma CVD is formed. The second interlayer insulating film 42 is provided with the contact hole 81 for electrically connecting the high-concentration source region 1d of the TFT 30 and the data line 6a, and the storage layer 6a1 for accumulation with the capacitor wiring. A contact hole 801 is formed to electrically connect the capacitor electrode 300 which is the upper electrode of the capacitor 70. Furthermore, the contact hole 882 is formed in the second interlayer insulating film 42 to electrically connect the second relay electrode 6a2 and the relay electrode 719.

(Laminated structure / Fifth layer structure-capacitor wiring, etc.)
A capacitor wiring 400 is formed in the fifth layer following the fourth layer. When viewed in plan, the capacitor wiring 400 is formed in a lattice shape so as to extend in the X direction and the Y direction in the drawing, as shown in FIG. The portion extending in the Y direction in the figure in the capacitor wiring 400 is formed so as to cover the data line 6a and wider than the data line 6a. In addition, the portion extending in the X direction in the drawing has a notch in the vicinity of the center of one side of each pixel electrode 9a in order to secure a region for forming a third relay electrode 402 described later.

  The capacitor wiring 400 is extended from the image display region 10a where the pixel electrode 9a is disposed to the periphery thereof, and is electrically connected to a constant potential source to have a fixed potential.

  Furthermore, a third relay electrode 402 is formed on the fifth layer as the same film as the capacitor wiring 400. The third relay electrode 402 has a function of relaying an electrical connection between the second relay electrode 6a2 and the pixel electrode 9a through contact holes 804 and 89 described later. In addition, as shown in FIG. 10, the space between the capacitor wiring 400 and the third relay electrode 402 is not continuously formed in a planar shape, but is formed so as to be divided by patterning. .

  On the other hand, the capacitor wiring 400 and the third relay electrode 402 described above have a two-layer structure in which a lower layer is made of aluminum and an upper layer is made of titanium nitride.

(Laminated structure / Structure between the 4th and 5th layers-3rd interlayer insulation film)
A silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or preferably TEOS gas is used on the above-described data line 6a and below the capacitor wiring 400. A third interlayer insulating film 43 formed by the plasma CVD method is formed. The third interlayer insulating film 43 includes a contact hole 803 for electrically connecting the capacitor wiring 400 and the capacitor wiring relay layer 6a1, and the third relay electrode 402 and the second relay electrode 6a2. Contact holes 804 for electrical connection are respectively opened.

(Laminated structure, 6th layer, 5th layer and 6th layer configuration-pixel electrode, etc.)
Finally, on the sixth layer, the pixel electrodes 9a are formed in a matrix as described above, and the alignment film 16 is formed on the pixel electrodes 9a. Under the pixel electrode 9a, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or a fourth interlayer insulating film 44 preferably made of NSG is formed. In the fourth interlayer insulating film 44, a contact hole 89 for electrically connecting the pixel electrode 9a and the third relay electrode 402 is opened. Between the pixel electrode 9a and the TFT 30, the contact hole 89, the third relay layer 402 and the contact hole 804, the second relay layer 6a2, the contact hole 882, the relay electrode 719, the contact hole 881, the lower electrode 71, and the contact hole described above. It is electrically connected through 83.

  The configuration in the pixel portion as described above is common to each pixel portion as shown in FIGS. In the image display area 10a described with reference to FIGS. 1 and 2, the configuration of the pixel portion is periodically formed.

  Next, a specific configuration of the buffer circuit of the liquid crystal device of the present embodiment will be described with reference to FIGS. FIG. 12 is a cross-sectional view taken along the line CC ′ of FIG. Note that the specific configuration of the buffer circuit will be described focusing on the specific configuration of the inverter 513.

  7 and 12, the inverter 513 includes a P-channel TFT 513a and an N-channel TFT 513b.

  The TFT 513a includes a semiconductor layer formed of the same film as the semiconductor layer 1a in the pixel portion, a gate electrode 513ga, a P-type channel region 513ca in a semiconductor layer in which a channel is formed by an electric field from the gate electrode 513ga, and a source region 513sa in the semiconductor layer. And a drain region 513da.

  The source region 513sa is electrically connected to a branch wiring 610 formed of the same film as the data line 6a through a contact hole 801 opened through the interlayer insulating films 41 and 42.

  The drain region 513da is electrically connected to an output wiring 550 formed of the same film as the data line 6a through a contact hole 802 opened through the interlayer insulating films 41 and 42.

  The TFT 513b includes a semiconductor layer formed from the same film as the semiconductor layer 1a in the pixel portion, a gate electrode 513gb, an N-type channel region 513cb in a semiconductor layer in which a channel is formed by an electric field from the gate electrode 513gb, and a source region 513sb in the semiconductor layer. And a drain region 513db.

  The source region 513sb is electrically connected to a branch wiring 620 formed of the same film as the data line 6a through a contact hole 804 opened through the interlayer insulating films 41 and 42.

  The drain region 513db is electrically connected to the output wiring 550 via a contact hole 803 opened through the interlayer insulating films 41 and 42. Therefore, the drain 513 region 513db is electrically connected to the drain region 513da through the output wiring 550.

  The inverters 511, 512 and 514 to 517, the inverters 521 to 527 and the inverters 531 to 537 are configured in the same manner.

  Next, a specific configuration of the power supply wiring for the data line driving circuit of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 13 to 16 in addition to FIG. FIG. 13 is a cross-sectional view taken along the line DD ′ of FIG. 14 is a cross-sectional view taken along line EE ′ of FIG. FIG. 15 is an explanatory diagram for explaining a layout of contact holes for electrically connecting the partial wirings. FIG. 16 is an explanatory diagram having the same concept as in FIG. 15 in the modified example.

  In FIG. 7 and FIG. 13, in the present embodiment, in particular, the data line driving circuit power supply wiring 601 has two partial wirings 601a and 601b.

  The partial wiring 601a is formed from the same film as the capacitor wiring 400, and the partial wiring 601b is formed from the same film as the data line 6a (see FIG. 11). The partial wirings 601 a and 601 b are electrically connected through a contact hole 61 opened in the third interlayer insulating film 43. Further, as shown in FIG. 15, the contact hole 61 is provided for each buffer circuit 500. In other words, it is provided for each partial region 661 on the data line driving circuit power supply wiring 601 corresponding to the buffer circuit 500. That is, the data line driving circuit power supply wiring 601 is formed of two conductive films located in different layers through the interlayer insulating film 43 and is electrically connected to each other through the plurality of contact holes 61. Two partial wirings 601a and 601b are provided.

  7 and 14, the data line driving circuit power supply wiring 602 includes two partial wirings 602 a and 602 b, similar to the data line driving circuit power supply wiring 601.

  The partial wiring 602a is formed from the same film as the capacitor wiring 400, and the partial wiring 602b is formed from the same film as the data line 6a (see FIG. 11). The partial wirings 602 a and 602 b are electrically connected through a contact hole 62 opened in the third interlayer insulating film 43. Further, as shown in FIG. 15, the contact hole 62 is provided for each buffer circuit 500 similarly to the contact hole 61. In other words, it is provided for each partial region 662 on the data line driving circuit power supply wiring 602 corresponding to the buffer circuit 500. That is, the data line driving circuit power supply wiring 602 is formed of two conductive films located in different layers via the interlayer insulating film 43 and is electrically connected to each other via a plurality of contact holes 62. Two partial wirings 602a and 602b are provided.

  As described above, since the data line driving circuit power supply wirings 601 and 602 each have two electrically connected partial wirings, the data line driving circuit power supply wirings 601 and 602 are formed of only one conductive film. As compared with the case of doing so, the resistance of the power supply wirings 601 and 602 for the data line driving circuit can be reduced without increasing the area of the region on the TFT array substrate 10 for wiring. Therefore, power can be stably supplied to the buffer circuit 500, and the driving capability of the buffer circuit can be increased.

  Moreover, as described above, the partial wirings 601 a and 602 are each formed from the same film as the capacitor wiring 400, and thus can be formed on the same occasion as the capacitor wiring 400. Since the partial wirings 601b and 602b are each formed from the same film as the data line 6a, they can be formed at the same opportunity as the data line 6a. That is, the power supply wirings 601 and 602 for the data line driving circuit can be formed from two different conductive films arranged via the interlayer insulating film without complicating the manufacturing process.

  Further, in FIG. 15, in the embodiment, the contact holes 61 and 62 are provided for each buffer circuit 500, in other words, for each group of data lines 6a that are simultaneously driven by the sampling circuit drive signal Si output from each buffer circuit 500. Is provided. In other words, the contact holes 61 and 62 are provided for each block or phase development that has undergone serial-parallel conversion (or phase development). In other words, the contact holes 61 and 62 are an arrangement of a plurality of buffer circuits 500 (see FIG. 4) arranged along the data line driving circuit power supply wirings 601 and 602 when viewed in plan on the TFT array substrate 10. The data lines are arranged on the data line drive circuit power supply wirings 601 and 602 at almost or preferably the same pitch as the pitch. Therefore, it is possible to supply almost or preferably the power source having the same potential to each of the plurality of buffer circuits 500. That is, power can be supplied to the plurality of buffer circuits 500 almost or completely uniformly. Accordingly, it is possible to reduce the variation in the voltage of the sampling circuit drive signal Si that can be generated for each data line group (or for each block). As a result, display unevenness (that is, vertical band-like display unevenness) due to variations in the voltage of the sampling circuit drive signal Si, such as display brightness varying from block to block, is reduced or preferably completely eliminated. be able to.

  In addition, the contact holes 61 and 62 are arranged in the same region for each of the partial regions 661 and 662 corresponding to each of the plurality of buffer circuits 500. That is, the contact holes 61 and 62 are arranged at the centers of the partial regions 661 and 662 when viewed in plan on the TFT array substrate 10. Therefore, the power can be supplied to the plurality of buffer circuits 500 almost or preferably completely uniformly.

  As shown as a modification in FIG. 16, the contact holes 61 and 62 may be arranged so as to be shifted from each other in the direction along the data line driving circuit power supply wiring 61. Also in this case, the contact holes 61 and 62 are arranged in the same region for each of the partial regions 661 and 662 corresponding to each of the plurality of buffer circuits 500. Therefore, the power can be supplied to the plurality of buffer circuits 500 almost or preferably completely uniformly. One contact hole 61 and 62 may be provided for each buffer circuit 500 (that is, for each data line 6a group), or a plurality of contact holes may be provided. When providing a plurality, it is desirable that the positional relationship between the plurality is the same for each buffer circuit 500.

  Next, the adjustment film of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 13 and 14 again.

  As shown in FIG. 13, in the present embodiment, in particular, when viewed in plan on the TFT array substrate 10, in the region where the contact hole 61 is formed, a plurality of adjustment films 700, that is, lower than the partial wiring 601b, The adjustment film 701 made of the same film as the scanning line 11a, the adjustment film 702 made of the same film as the sampling circuit drive signal line 114 (that is, the gate electrode 3a in the pixel portion), and the adjustment film made of the same film as the lower electrode 71 703 and an adjustment film 704 made of the same film as the capacitor electrode 300. Therefore, compared with the case where the adjustment film 700 is not provided, the height of the partial wiring 601b from the surface of the TFT array substrate 10 is adjusted by the adjustment film 700, so that the interlayer distance between the partial wirings 601a and 601b is shortened. Can do. That is, the partial wiring 601b adjusted to be higher from the surface of the TFT array substrate 10 by the adjustment film 700 has a distance from the surface of the interlayer insulating film 43 flattened by CMP or the like laminated thereon. Shorter than the portion without the adjustment film 700. Therefore, resistance (that is, contact resistance) due to the contact hole opened in the planarized interlayer insulating film 43 can be reduced. Accordingly, the resistance of the power supply wiring 601 can be reduced, and power can be supplied to the plurality of buffer circuits 500 more stably. Furthermore, the time required for manufacturing the plurality of contact holes 61 (for example, etching time) can be shortened, which is very effective in practice.

As shown in FIG. 14, in the region where the contact hole 62 is formed, a plurality of adjustment films 710, that is, scanning lines, are formed on the lower layer side of the partial wiring 602b, similarly to the region where the contact hole 61 is formed. 11a, an adjustment film 711 made of the same film as the lower electrode 71, an adjustment film 713 made of the same film as the lower electrode 71, and an adjustment film 714 made of the same film as the capacitor electrode 300 are provided. The signal line 404 is formed of the same film as the gate electrode 3a in the pixel portion. Therefore, resistance (that is, contact resistance) due to the contact hole opened in the planarized interlayer insulating film 43 can be reduced. Therefore, the resistance of the power supply wiring 602 can be reduced, and power can be supplied to the plurality of buffer circuits 500 more stably. Furthermore, the time required for manufacturing the plurality of contact holes 62 can be shortened.
Second Embodiment
Next, a liquid crystal device according to a second embodiment will be described with reference to FIG. FIG. 17 is an enlarged plan view showing an enlarged contact hole for electrically connecting the partial wirings. In FIG. 17, the same components as those in the first embodiment shown in FIGS. 1 to 16 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  As shown in FIG. 17, the contact hole 61 may be composed of nine partial contact holes 61p. The partial contact holes 61p are smaller than each of the contact holes 61 when viewed in plan on the TFT array substrate 10. Further, the nine partial contact holes 61p are adjacent to each other. That is, the nine partial contact holes 61p are spaced apart by a distance L5 that is shorter than the diameter R1 of the partial contact hole 61p. Therefore, for example, as compared with the case where the nine partial contact holes 61p are not adjacent to each other, that is, apart from each other, they are arranged in the interlayer insulating film 43 positioned between the partial wirings 601a and 601b. By opening the holes, it is possible to reduce or prevent the occurrence of cracks in the interlayer insulating film 43.

(Electronics)
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described.

  First, a projector using this liquid crystal device as a light valve will be described. FIG. 18 is a plan view showing a configuration example of the projector. As shown in FIG. 18, a projector 1100 includes a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.

  Note that since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  Next, an example in which the liquid crystal device is applied to a mobile personal computer will be described. FIG. 19 is a perspective view showing the configuration of this personal computer. In FIG. 19, a computer 1200 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal device 1005 described above.

  Further, an example in which the liquid crystal device is applied to a mobile phone will be described. FIG. 20 is a perspective view showing the configuration of this mobile phone. In FIG. 20, a mobile phone 1300 includes a reflective liquid crystal device 1005 together with a plurality of operation buttons 1302. In the reflective liquid crystal device 1005, a front light is provided on the front surface thereof as necessary.

  In addition to the electronic devices described with reference to FIGS. 18 to 20, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Examples include a station, a videophone, a POS terminal, a device equipped with a touch panel, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), The present invention can also be applied to an organic EL display, a digital micromirror device (DMD), an electrophoresis apparatus, and the like.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. An electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

It is a top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment of this invention. It is sectional drawing of HH 'of FIG. It is a block diagram which shows the main structures of the liquid crystal device of 1st Embodiment. It is a block diagram which shows the structure of a data line drive circuit. It is a circuit diagram which shows the circuit structure of a buffer circuit. It is an equivalent circuit diagram showing the configuration of the buffer circuit. It is a top view which shows the concrete structure of the power supply wiring for a buffer circuit and a data line drive circuit. It is an equivalent circuit diagram of various elements, wirings, etc. in a plurality of pixel portions. FIG. 11 is a plan view of a plurality of adjacent pixel portions, and shows only a configuration relating to a lower layer portion (a lower layer portion up to reference numeral 70 (storage capacitor) in FIG. 11). FIG. 11 is a plan view of a plurality of adjacent pixel portions, and shows only a configuration relating to an upper layer portion (an upper layer portion exceeding reference numeral 70 (storage capacity) in FIG. 11). It is AA 'sectional drawing at the time of superposing FIG.9 and FIG.10. It is sectional drawing in the CC 'line of FIG. It is sectional drawing in the DD 'line of FIG. It is sectional drawing in the EE 'line | wire of FIG. It is explanatory drawing for demonstrating the layout of the contact hole for electrically connecting between partial wiring. It is explanatory drawing of the same meaning as FIG. 15 in a modification. It is an enlarged plan view which expands and shows the contact hole for electrically connecting between partial wiring. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied. 1 is a perspective view showing a configuration of a personal computer as an example of an electronic apparatus to which an electro-optical device is applied. It is a perspective view which shows the structure of the mobile telephone which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  6a ... data line, 6 ... image signal line, 7 ... sampling circuit, 9a ... pixel electrode, 10 ... TFT array substrate, 10a ... image display area, 11a ... scanning line, 20 ... counter substrate, 61, 62 ... contact hole, DESCRIPTION OF SYMBOLS 71 ... Sampling switch, 101 ... Data line drive circuit, 104 ... Scanning line drive circuit, 400 ... Shift register, 500 ... Buffer circuit, 601, 602 ... Power supply wiring for data line drive circuit

Claims (6)

And several of the pixel portion,
A plurality of scanning lines and a plurality of data lines to said plurality of pixel areas where the pixel portion is arranged,
In order to supply an image signal for each data line group including N data lines as a group, N (where N is a natural number of 2 or more) serial-parallel converted image signals are supplied. N image signal lines;
A sampling circuit that is electrically connected to the image signal line and includes a plurality of sampling switches that respectively supply the image signal to the plurality of data lines according to a sampling signal;
A shift register that outputs a transfer signal that defines a timing at which the image signal should be supplied to the plurality of pixel units;
Provided for each said data line groups, a buffer circuit for supplying the transfer signal, for each of the sampling switches corresponding to the data lines as the sampling signal,
A power supply wiring that supplies power to the buffer circuit and includes a plurality of partial wirings formed in different layers via an interlayer insulating film;
The buffer circuit has a plurality of inverters connected in parallel in the first direction,
The power supply wiring extends along the plurality of inverters in the first direction and is connected to the plurality of inverters via a plurality of lead wirings extending in a second direction intersecting the first direction. Has been
The plurality of partial wirings constituting the power supply wiring are electrically connected to each other through contact holes provided between the lead-out areas of the power supply wiring from which the lead-out wiring is drawn out in order to connect to the inverters at both ends in the first direction. An electro-optical device characterized by being connected to each other . The power supply wiring includes a first power supply wiring that supplies power of a first potential and a second power supply wiring that supplies power of a second potential lower than the first potential. 2. The electro-optical device according to 1. Each of the plurality of pixel portions includes a storage capacitor in which a lower electrode, a dielectric film, and an upper electrode are sequentially stacked,
The plurality of partial wirings are formed from the same film as a first partial wiring formed from the same film as the data line and a capacitor line electrically connected to one of the lower electrode and the upper electrode. the electro-optical device according to claim 1 or 2, characterized in that it consists of a second portion wirings. Than the previous SL plurality of partial wiring is disposed on the lower layer side, and the sampling signal lines for supplying the sampled signal,
In a region before Symbol plurality of contact holes are formed, the plurality of partial lines the scanning lines on the lower layer side than the sampling signal line, adjustment of the same film and at least one of the lower electrode and the upper electrode the electro-optical device according to any one of claims 1 to 3, characterized in that it comprises a membrane. Wherein the plurality of contact holes respectively, the electro-optical device according to claims 1 to 4, characterized in that multi-part contact holes adjacent to each other physician. An electronic apparatus comprising the electro-optical device according to claim 1 .

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