JP5103717B2 - Electro-optical device and electronic apparatus including the same - Google Patents

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  This type of electro-optical device is generally driven based on an image signal supplied from an external circuit via an external circuit connection terminal. For example, in a liquid crystal device, an image signal is supplied via a sampling switch to a plurality of data lines wired in an image display area on a substrate. As a result, the plurality of data lines are sequentially driven. More specifically, the image signal line is wired on the substrate from the external circuit connection terminal to the image signal supply unit including the sampling switch, and further wired along the left and right direction of the image display area in the image signal supply unit. Is done. The image signal lines are connected to sampling switches arranged in the left-right direction of the image display area, and the image signals are sequentially supplied to the data lines, for example, from left to right through such sampling switches.

  For such image signal lines, for example, in Patent Document 1, when the image signals are phase-expanded into a plurality of series, the time constant between the plurality of image signal lines is made substantially uniform, thereby suppressing image display unevenness. Techniques to do this are disclosed by the present applicant.

Japanese Patent No. 3402112

  However, as described above, when the image signal is supplied to the data line via the image signal line wired along the left-right direction of the image display area, the left and right sides of the screen display area are caused by the resistance of the image signal line. There is a technical problem in that there is a difference in display performance.

  SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical device capable of displaying an image with high quality by reducing the resistance of an image signal line.

In order to solve the above problems, an electro-optical device of the present invention includes a data line, a transistor electrically connected to the data line, a pixel electrode provided corresponding to the transistor, and one electrode A storage capacitor electrically connected to the capacitor line and the other electrode electrically connected to the pixel electrode, an image signal line for supplying an image signal to the data line, and an electric signal to the image signal line The capacitor line is provided between the layer provided with the data line and the layer provided with the pixel electrode, and the image signal line comprises: A first partial wiring formed from the same film as the conductive film constituting the data line; a second partial wiring formed from the same film as the conductive film constituting the capacitor line; and the first partial wiring; Between the second partial wiring Via a first contact hole formed in the edge layer are connected, the second partial wiring is extended from the external circuit connection terminals.

  According to the electro-optical device of the present invention, at the time of driving, an image signal is supplied from an external circuit to an image signal line via, for example, an external circuit connection terminal, and further, for example, branch wiring arranged corresponding to the data line Is supplied to, for example, a sampling circuit. For example, in order to realize high-definition image display while suppressing an increase in drive frequency, the image signal is converted into a serial image signal by an external circuit such as 3-phase, 6-phase, 12-phase, 24-phase,. Or may be generated by being converted into a plurality of parallel image signals. In this case, a plurality of image signal lines such as 3, 6, 12, 24,... May be wired side by side, for example.

  In parallel with the supply of the image signal, the sampling signal is sequentially supplied to each sampling switch corresponding to the data line, for example, by the data line driving circuit. Then, for example, an image signal is sequentially supplied to the plurality of data lines for each data line according to the sampling signal by the sampling circuit. The sampling switch is configured by, for example, a single-channel TFT, and the source is electrically connected to the branch wiring, the drain is connected to the data line, and the sampling signal is supplied to the gate so that the sampling switch is turned on. Is done.

  When the data line is driven in this manner, each pixel unit provided in the pixel array region performs pixel switching, for example, according to a scanning signal supplied from the scanning line driving circuit via the scanning line. An image signal is supplied to the display element from the data line through the element.

  As a result, for example, a liquid crystal element as a display element can perform image display by an active matrix driving method based on an image signal.

  In the present invention, in particular, the image signal line is formed from a plurality of conductive films located in different layers via an interlayer insulating film, and has a plurality of partial wirings electrically connected to each other. Therefore, the resistance (that is, the electrical resistance of the wiring or the wiring resistance) is lower than that in the case where the image signal line is formed from one conductive film. Therefore, even if the image signal line includes a portion in which the image signal line is wired along one side of the pixel array region, for example, the left-right direction in the pixel array region as in the present invention, the left-right difference in image display performance is almost or practically practiced. The top can be completely eliminated. In other words, the degree to which the image signal is rounded or the timing at which the image signal is supplied depends on the difference in time constant between the position corresponding to the left side of the pixel array area in the image signal line and the position corresponding to the right side. It is possible to reduce or prevent the occurrence of a difference in right and left, such as the difference in density of image display depending on the left and right, due to the difference, by the configuration having a plurality of partial wirings according to the present invention. Such an effect is particularly effective when the image signal lines can be routed only from one of the left and right sides due to the arrangement of the external circuit terminals and restrictions from other wirings.

  Further, since the plurality of partial wirings are respectively formed from a plurality of conductive films located in different layers, they can be wired so as to overlap each other when viewed in plan on the substrate. Therefore, the degree of freedom in design for wiring a plurality of partial wirings is high. Therefore, for example, by arranging a plurality of partial wirings so as to overlap each other almost or completely when viewed in plan on the substrate, the area on the substrate necessary for wiring of the image signal lines is increased almost or not at all. In other words, in other words, the resistance of the image signal line can be reduced without increasing the substrate size.

As described above, according to the electro-optical device of the present invention, the resistance of the image signal line can be reduced without increasing the area on the substrate necessary for the wiring of the image signal line. Enables high-quality image display.
In one aspect of the electro-optical device of the present invention, a branch wiring branching from the image signal line, a sampling switch connected between the branch wiring and the data line, and a sampling circuit drive signal from the data line drive circuit A sampling circuit drive signal line to be supplied to the gate of the sampling switch, and the branch wiring is formed of a conductive film located on a lower layer side of the first partial wiring and the second partial wiring.
In another aspect of the electro-optical device of the present invention, the one electrode is formed of a conductive film located on a lower layer side of the layer provided with the data line, and the branch wiring is the same film as the one electrode Formed with.

In another aspect of the electro-optical device according to the aspect of the invention, the first partial wiring may be formed through the contact hole that is opened in a region where the external circuit connection terminal is located when viewed in plan on the substrate. Each is electrically connected to a circuit connection terminal .

  In this case, it is possible to form a partial wiring formed of a conductive film different from the external circuit connection terminal even in a region where the external circuit connection terminal is located in plan view on the substrate. Therefore, the resistance of the partial wiring can be lowered by effectively using the region where the external circuit connection terminal is located. Therefore, the resistance of the image signal line can be lowered, and high-quality image display can be performed.

In another aspect of the electro-optical device according to the aspect of the invention, the first partial wiring and the second partial wiring include a portion at least partially overlapping each other when viewed in plan on the substrate, and at least one of the overlapping portions is at least one. They are electrically connected to each other through two contact holes.

  According to this aspect, the plurality of partial wirings are electrically connected to each other via at least one contact hole in the overlapping portion. Therefore, for example, by electrically connecting a plurality of partial wirings to each other through a plurality of contact holes, electrical connection between the plurality of partial wirings can be ensured, and the resistance of the image signal lines can be further reduced. It can be done reliably.

In another aspect of the electro-optical device according to the aspect of the invention, the first partial wiring and the second partial wiring may be arranged so that the respective wiring widths are aligned with each other and overlap each other when viewed in plan on the substrate. It is formed.

  According to this aspect, the plurality of partial wirings are formed so that the respective wiring widths are aligned with each other when viewed in plan on the substrate. That is, the wiring widths of the plurality of partial wirings are almost the same in a practical or practical sense. Further, the plurality of partial wirings are formed so as to overlap each other. That is, the plurality of partial wirings overlap with each other almost or in a practical sense when viewed in plan on the substrate. Therefore, a plurality of partial wirings can be wired to a region on the substrate having almost the same area as the area necessary for wiring one partial wiring. Accordingly, the resistance of the image signal line is reduced without increasing the area on the substrate necessary for wiring, in other words, without increasing the substrate size, and with little change in the planar layout in the design. be able to.

  In another aspect of the electro-optical device according to the aspect of the invention, each of the plurality of pixel units includes a storage capacitor in which a lower electrode, a dielectric film, and an upper electrode are sequentially stacked on the substrate. The first partial wiring formed from the same film as the data line, and the second partial wiring formed from the same film as the capacitor line electrically connected to one of the lower electrode and the upper electrode It consists of.

  According to this aspect, the plurality of partial wirings are composed of the first and second partial wirings. The first partial wiring is formed from the same film as the data line, and the second partial wiring is formed from the same film as the capacitor wiring. Here, the “same film” means films formed on the same occasion in the manufacturing process and are the same type of film. Note that the phrase “same film” does not mean that the film is continuous as a single film, but basically a film part of the same film that is separated from each other is sufficient. It is. Therefore, the first and second partial wirings can be formed on the same occasion as the data line and the capacitor wiring, respectively. That is, the image signal line can be formed from a plurality of conductive films without complicating the manufacturing process.

  Note that the storage capacitor improves, for example, the potential holding characteristic of the pixel electrode constituting the pixel portion, and the display can have high contrast.

  In the aspect provided with the first and second partial wirings described above, the image signal is a plurality of systems of image signals developed serially and in parallel, and the image signal line supplies the image signals of each system. A plurality of image signal lines for forming a plurality of image signal lines corresponding to an arrangement of the plurality of data lines and formed from a conductive film located on either the upper layer side or the lower layer side of the first and second partial wirings. A plurality of branch wirings, one end of which is electrically connected to at least one of the first and second partial wirings, and the image signal supplied from the other end of the plurality of branch wirings, A sampling circuit including a plurality of sampling switches respectively supplied to the data line according to the sampling signal, and the sampling signal for each sampling switch corresponding to the data line. It may further include a data line driving circuit for supplying.

  In this case, during the operation, a plurality of system image signals that have undergone serial-parallel expansion or serial-parallel conversion, that is, phase expansion, are simultaneously supplied via a plurality of image signal lines. Particularly in this aspect, the plurality of branch wirings are formed from a conductive film located on either the upper layer side or the lower layer side of the first and second partial wirings. If a plurality of branch wirings are formed from a conductive film located between the first and second partial wirings, the plurality of branch wirings are connected to the first and second partial wirings via an interlayer insulating film, respectively. Each will form a capacity. However, according to this aspect, the plurality of branch lines form a capacitance with only one of the upper layer side and the lower layer side of the first and second partial lines, or the plurality of branch lines are connected to the first and second parts. It is also possible to form the conductive film at a position separated to such an extent that the capacitance is reduced or almost eliminated on either the upper layer side or the lower layer side of the wiring. Therefore, it is possible to prevent the image signals of the plurality of branch wirings from fluctuating or fluctuating due to the influence of the image signals of the first and second partial wirings.

  An electronic apparatus of the present invention comprises the above-described electro-optical device of the present invention in order to solve the above problems.

  According to the electronic apparatus of the present invention, since it includes the electro-optical device of the present invention described above, a projection display device, a mobile phone, an electronic notebook, a word processor, a viewfinder type, or a monitor capable of high-quality display. Various electronic devices such as a direct-view video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. Further, as the electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper can be realized.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.
<First Embodiment>
The liquid crystal device according to the first embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line H-H 'in FIG.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are included in an image display region 10a as an example of the “pixel array region” according to the present invention. They are bonded to each other by a sealing material 52 provided in a surrounding sealing region.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. The sampling circuit 7 is provided so as to be covered with the frame light shielding film 53 on the inner side of the seal region along the one side. Further, the scanning line driving circuit 104 is provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side. On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  On the TFT array substrate 10, a lead wiring 90 is formed for electrically connecting the external circuit connection terminal 102 to the data line driving circuit 101, the scanning line driving circuit 104, the vertical conduction terminal 106, and the like. .

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which wiring such as a pixel switching TFT (Thin Film Transistor) as a driving element, a scanning line, and a data line is formed. In the image display area 10a, a pixel electrode 9a is provided in an upper layer of wiring such as a pixel switching TFT, a scanning line, and a data line. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. A counter electrode 21 made of a transparent material such as ITO is formed on the light shielding film 23 so as to face the plurality of pixel electrodes 9a. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Although not shown here, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the TFT array substrate 10 is used for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or at the time of shipment. An inspection circuit, an inspection pattern, or the like may be formed.

  Next, the configuration of the pixel portion of the liquid crystal device according to the present embodiment will be described with reference to FIGS. FIG. 3 is an equivalent circuit of various elements and wirings in a plurality of pixel portions, and FIGS. 4 and 5 are plan views of a plurality of adjacent pixel portions. 4 and 5 respectively show the lower layer portion (FIG. 4) and the upper layer portion (FIG. 5) in the laminated structure described later.

  FIG. 6 is a cross-sectional view taken along line AA ′ when FIGS. 4 and 5 are overlapped. In FIG. 6, the scale of each layer / member is different for each layer / member so that each layer / member can be recognized on the drawing.

  In FIG. 3, a pixel electrode 9a and a TFT 30 for controlling the switching of the pixel electrode 9a are formed in a plurality of pixel portions formed in a matrix in the image display region of the liquid crystal device according to the present embodiment. The data line 6 a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals VS1, VS2,..., VSn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group of a plurality of adjacent data lines 6a. Good.

  Further, the gate electrode 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are pulse-sequentially applied in this order to the scanning line 11a and the gate electrode 3a at a predetermined timing. It is comprised so that it may apply. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal VS1, VS2,..., VSn supplied from the data line 6a is obtained by closing the switch of the TFT 30 as a switching element for a certain period. Write at a predetermined timing.

  Image signals VS1, VS2,..., VSn written to the liquid crystal through the pixel electrode 9a are held for a certain period with the counter electrode formed on the counter substrate. The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to the image signal is emitted from the electro-optical device as a whole.

  Further, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. The storage capacitor 70 is provided side by side with the scanning line 11a, and includes a fixed potential side capacitor electrode and a capacitor electrode 300 fixed to a constant potential.

  Hereinafter, with reference to FIGS. 4 to 6, a specific configuration of the electro-optical device that realizes the above-described circuit operation by the data line 6a, the scanning line 11a, the gate electrode 3a, the TFT 30, and the like will be described. explain.

  First, in FIG. 5, a plurality of pixel electrodes 9 a are provided in a matrix on the TFT array substrate 10 (the outline is indicated by a dotted line portion), and as shown in FIGS. 4 and 5, Data lines 6a and scanning lines 11a are provided along the vertical and horizontal boundaries of the pixel electrode 9a. The data line 6a has a laminated structure including, for example, an aluminum film, and the scanning line 11a has, for example, a conductive polysilicon film. Further, the scanning line 11a is electrically connected to the gate electrode 3a facing the channel region 1a ′ shown by the hatched region rising to the right in FIG. 4 in the semiconductor layer 1a through the contact hole 12cv. The electrode 3a is included in the scanning line 11a. That is, each of the intersections between the gate electrode 3a and the data line 6a is provided with a pixel switching TFT 30 in which the gate electrode 3a included in the scanning line 11a is opposed to the channel region 1a ′. As a result, the TFT 30 (excluding the gate electrode) is configured to exist between the gate electrode 3a and the scanning line 11a.

  Next, as shown in FIG. 6, for example, a TFT array substrate 10 made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and a counter substrate 20 made of, for example, a glass substrate or a quartz substrate are provided to face the TFT array substrate 10. Yes.

  The pixel electrode 9a is provided on the TFT array substrate 10 side, and an alignment film 16 subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive film such as an ITO film. On the other hand, a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 21. . The counter electrode 21 is made of a transparent conductive film such as an ITO film, for example, like the pixel electrode 9a described above.

  Between the TFT array substrate 10 and the counter substrate 20 arranged so as to face each other, an electro-optical material such as liquid crystal is sealed in a space surrounded by the above-described sealing material 52 (see FIGS. 1 and 2). 50 is formed. The liquid crystal layer 50 takes a predetermined alignment state by the alignment films 16 and 22 in a state where an electric field from the pixel electrode 9a is not applied.

  On the other hand, on the TFT array substrate 10, in addition to the pixel electrode 9a and the alignment film 16, various configurations including these are provided in a laminated structure. As shown in FIG. 6, this stacked structure includes a first layer including a scanning line 11a, a second layer including a TFT 30 including a gate electrode 3a, a third layer including a storage capacitor 70, and a data line 6a in order from the bottom. And the like, a fifth layer including the capacitor wiring 400 and the like, and a sixth layer (uppermost layer) including the pixel electrode 9a and the alignment film 16 and the like. Further, the base insulating film 12 is provided between the first layer and the second layer, the first interlayer insulating film 41 is provided between the second layer and the third layer, and the second interlayer insulating film 42 is provided between the third layer and the fourth layer. A third interlayer insulating film 43 is provided between the fourth layer and the fifth layer, and a fourth interlayer insulating film 44 is provided between the fifth layer and the sixth layer, so that the above-described elements are short-circuited. Is preventing. These various insulating films 12, 41, 42, 43, and 44 are also provided with contact holes for electrically connecting the high concentration source region 1d in the semiconductor layer 1a of the TFT 30 and the data line 6a, for example. ing. Hereinafter, each of these elements will be described in order from the bottom. Of the foregoing, the first to third layers are shown in FIG. 4 as the lower layer portion, and the fourth to sixth layers are shown in FIG. 5 as the upper layer portion.

(Laminated structure / Structure of first layer-Scanning line, etc.)
First, for example, the first layer includes at least one of refractory metals such as Ti, Cr, W, Ta, and Mo, a metal simple substance, an alloy, a metal silicide, a polysilicide, and a laminate of these, Alternatively, a scanning line 11a made of conductive polysilicon or the like is provided. The scanning lines 11a are patterned in stripes along the X direction in FIG.

(Laminated structure / Second layer structure-TFT, etc.)
Next, the TFT 30 including the gate electrode 3a is provided as the second layer. As shown in FIG. 6, the TFT 30 has an LDD (Lightly Doped Drain) structure, and includes the above-described gate electrode 3a, for example, a polysilicon film, and a channel formed by an electric field from the gate electrode 3a. The channel region 1a ′ of the semiconductor layer 1a to be formed, the insulating film 2 including a gate insulating film that insulates the gate electrode 3a from the semiconductor layer 1a, the low concentration source region 1b and the low concentration drain region 1c in the semiconductor layer 1a, and the high concentration A source region 1d and a high concentration drain region 1e are provided.

  In addition, a relay electrode 719 is formed on the second layer as the same film as the gate electrode 3a described above. As shown in FIG. 4, the relay electrode 719 is formed in an island shape so as to be positioned approximately at the center of one side extending in the X direction of each pixel electrode 9 a as viewed in a plan view. Since the relay electrode 719 and the gate electrode 3a are formed as the same film, when the latter is made of a conductive polysilicon film or the like, the former is also made of a conductive polysilicon film or the like.

  The TFT 30 described above preferably has an LDD structure as shown in FIG. 6, but may have an offset structure in which no impurity is implanted into the low concentration source region 1b and the low concentration drain region 1c. A self-aligned TFT that implants impurities at a high concentration as a mask and forms a high concentration source region and a high concentration drain region in a self-aligning manner may be used.

(Laminated structure / Structure between first layer and second layer-Underlying insulating film-)
A base insulating film 12 made of, for example, a silicon oxide film is provided on the scanning line 11a described above and below the TFT 30. The base insulating film 12 has a function of insulating the TFT 30 from the scanning line 11a.

  Groove-shaped contact holes 12cv along the channel length direction of the semiconductor layer 1a extending along the data line 6a described later are dug in the base insulating film 12 on both sides of the semiconductor layer 1a in plan view. In correspondence with the contact hole 12cv, the gate electrode 3a stacked above the contact hole 12cv includes a concave portion formed on the lower side. Further, since the gate electrode 3a is formed so as to fill the entire contact hole 12cv, a side wall portion 3b formed integrally with the gate electrode 3a is extended. ing.

(Laminated structure / 3rd layer configuration-storage capacity, etc.)
A storage capacitor 70 is provided in the third layer following the second layer. The storage capacitor 70 includes a lower electrode 71 as a pixel potential side capacitor electrode connected to the high concentration drain region 1e of the TFT 30 and the pixel electrode 9a, and a capacitor electrode 300 as a fixed potential side capacitor electrode. It is formed by arrange | positioning through. According to the storage capacitor 70, it is possible to remarkably improve the potential holding characteristic in the pixel electrode 9a.

  More specifically, the lower electrode 71 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitor electrode. However, the lower electrode 71 may be composed of a single layer film or a multilayer film containing a metal or an alloy. In addition to the function as a pixel potential side capacitor electrode, the lower electrode 71 has a function of relay-connecting the pixel electrode 9a and the high concentration drain region 1e of the TFT 30. The relay connection here is performed through the relay electrode 719.

  The capacitor electrode 300 functions as a fixed potential side capacitor electrode of the storage capacitor 70. The capacitor electrode 300 is electrically connected to a capacitor wiring 400 having a fixed potential described later. Further, the capacitor electrode 300 includes at least one of refractory metals such as Ti, Cr, W, Ta, and Mo, a simple metal, an alloy, a metal silicide, a polysilicide, a laminate of these, or preferably It consists of tungsten silicide.

  As shown in FIG. 6, the dielectric film 75 is, for example, a relatively thin HTO (High Temperature Oxide) film having a film thickness of about 5 to 200 nm, a silicon oxide film such as an LTO (Low Temperature Oxide) film, or a silicon nitride film. Consists of More specifically, the dielectric film 75 has a two-layer structure such that the lower layer is a silicon oxide film 75a and the upper layer is a silicon nitride film 75b. The dielectric film 75 may be configured to have a three-layer structure such as a silicon oxide film, a silicon nitride film, and a silicon oxide film, or a laminated structure of more than that. Of course, a single layer structure may be used.

(Laminated structure, configuration between second layer and third layer—first interlayer insulating film)
On the TFT 30 to the gate electrode 3a and the relay electrode 719 described above and below the storage capacitor 70, for example, NSG (non-silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG ( A silicate glass film such as boron phosphorus silicate glass), a silicon nitride film, a silicon oxide film, or the like, or a first interlayer insulating film 41 preferably made of NSG is formed.

  A contact hole 81 that electrically connects a high-concentration source region 1 d of the TFT 30 and a data line 6 a described later is opened in the first interlayer insulating film 41 while penetrating the second interlayer insulating film 42 described later. . The first interlayer insulating film 41 is provided with a contact hole 83 that electrically connects the high-concentration drain region 1 e of the TFT 30 and the lower electrode 71 constituting the storage capacitor 70. Further, the first interlayer insulating film 41 is provided with a contact hole 881 for electrically connecting the lower electrode 71 as a pixel potential side capacitor electrode constituting the storage capacitor 70 and the relay electrode 719. In addition, a contact hole 882 for electrically connecting the relay electrode 719 and a later-described second relay electrode 6a2 is opened in the first interlayer insulating film 41 while penetrating the second interlayer insulating film 42 described later. It is holed.

(Laminated structure / 4th layer configuration-data lines, etc.)
A data line 6a is provided in the fourth layer following the third layer. As shown in FIG. 6, the data line 6a includes, in order from the lower layer, a layer made of aluminum (see reference numeral 41A in FIG. 6), a layer made of titanium nitride (see reference numeral 41TN in FIG. 6), and a layer made of a silicon nitride film ( 6) (see reference numeral 401 in FIG. 6).

  Further, the fourth layer is formed with the capacitor wiring relay layer 6a1 and the second relay electrode 6a2 as the same film as the data line 6a. As shown in FIG. 5, these are not formed so as to have a planar shape continuous with the data line 6 a when viewed in a plan view, but are formed so as to be separated from each other by patterning. Yes.

(Laminated structure / Structure between third and fourth layers-second interlayer insulating film)
Above the storage capacitor 70 described above and below the data line 6a, for example, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film or a silicon oxide film, or preferably TEOS gas is used. A second interlayer insulating film 42 formed by plasma CVD is formed. The second interlayer insulating film 42 is provided with the contact hole 81 for electrically connecting the high-concentration source region 1d of the TFT 30 and the data line 6a, and the storage layer 6a1 for accumulation with the capacitor wiring. A contact hole 801 is formed to electrically connect the capacitor electrode 300 which is the upper electrode of the capacitor 70. Furthermore, the contact hole 882 is formed in the second interlayer insulating film 42 to electrically connect the second relay electrode 6a2 and the relay electrode 719.

(Laminated structure / Fifth layer structure-capacitor wiring, etc.)
A capacitor wiring 400 is formed in the fifth layer following the fourth layer. When viewed in plan, the capacitor wiring 400 is formed in a lattice shape so as to extend in the X direction and the Y direction in the drawing, as shown in FIG. The portion extending in the Y direction in the figure in the capacitor wiring 400 is formed so as to cover the data line 6a and wider than the data line 6a. In addition, the portion extending in the X direction in the drawing has a notch in the vicinity of the center of one side of each pixel electrode 9a in order to secure a region for forming a third relay electrode 402 described later.

  The capacitor wiring 400 is extended from the image display region 10a where the pixel electrode 9a is disposed to the periphery thereof, and is electrically connected to a constant potential source to have a fixed potential.

  Furthermore, a third relay electrode 402 is formed on the fifth layer as the same film as the capacitor wiring 400. The third relay electrode 402 has a function of relaying an electrical connection between the second relay electrode 6a2 and the pixel electrode 9a through contact holes 804 and 89 described later. As shown in FIG. 5, the space between the capacitor wiring 400 and the third relay electrode 402 is not continuously formed in a planar shape, but is formed so as to be divided for patterning. .

  On the other hand, the capacitor wiring 400 and the third relay electrode 402 described above have a two-layer structure in which a lower layer is made of aluminum and an upper layer is made of titanium nitride.

(Laminated structure / Structure between the 4th and 5th layers-3rd interlayer insulation film)
A silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or preferably TEOS gas is used on the above-described data line 6a and below the capacitor wiring 400. A third interlayer insulating film 43 formed by the plasma CVD method is formed. The third interlayer insulating film 43 includes a contact hole 803 for electrically connecting the capacitor wiring 400 and the capacitor wiring relay layer 6a1, and the third relay electrode 402 and the second relay electrode 6a2. Contact holes 804 for electrical connection are respectively opened.

(Laminated structure, 6th layer, 5th layer and 6th layer configuration-pixel electrode, etc.)
Finally, on the sixth layer, the pixel electrodes 9a are formed in a matrix as described above, and the alignment film 16 is formed on the pixel electrodes 9a. Under the pixel electrode 9a, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or a fourth interlayer insulating film 44 preferably made of NSG is formed. In the fourth interlayer insulating film 44, a contact hole 89 for electrically connecting the pixel electrode 9a and the third relay electrode 402 is opened. Between the pixel electrode 9a and the TFT 30, the contact hole 89, the third relay layer 402 and the contact hole 804, the second relay layer 6a2, the contact hole 882, the relay electrode 719, the contact hole 881, the lower electrode 71, and the contact hole described above. It is electrically connected through 83.

  The configuration in the pixel portion as described above is common to each pixel portion as shown in FIGS. In the image display area 10a described with reference to FIGS. 1 and 2, the configuration of the pixel portion is periodically formed.

  Next, the electrical connection of the data line driving circuit, the sampling circuit, the image signal line, and the data line will be described with reference to FIG. FIG. 7 is an explanatory diagram showing an electrical connection relationship among the data line driving circuit, the sampling circuit, the image signal line, and the data line.

  In FIG. 7, the branch wiring 116 from the image signal line 91 is connected to the source of a sampling switch 7 s composed of a TFT or the like constituting the sampling circuit 7, and the sampling circuit drive signal line 117 from the data line drive circuit 101 is , Connected to the gate of the sampling switch 7s. During the operation of the liquid crystal device, the image signal applied from the external circuit to the external circuit connection terminal 102 for the image signals VID1 to VID6 is supplied to the sampling circuit 7 via the branch wiring 116 from the image signal line 91, where Sampling is performed at a timing according to the sampling circuit driving signal Si supplied from the data line driving circuit 101 via the sampling circuit driving signal line 117. The sampled image signal is supplied to each data line 6a. The data line driving circuit 101 is supplied with an X-side clock signal CLX (and its inverted signal CLX ′) having a predetermined period, a shift register start signal DX, and the like, and based on these, a shift that constitutes the data line driving circuit is provided. Transfer signals Pi (i = 1,..., N) are sequentially output from each stage of the register. These transfer signals Pi are shaped by, for example, a logic circuit constituting the data line driving circuit, and output as a sampling circuit driving signal Si.

  The image signal supplied to the sampling circuit 7 from the image signal line 91 via the branch wiring 116 may be supplied line-sequentially. However, in this embodiment, the image signal is serially / parallel-developed in six phases. Corresponding to each of the received image signals, it is configured to be supplied for each group to a set of six data lines 6a. Note that the number of phase development of the image signal (that is, the number of series of image signals that are serial-parallel-developed) is not limited to six phases, and may be, for example, a plurality of phases such as nine phases, twelve phases, and twenty-four phases. The developed image signal may be supplied to a set of data lines 6a in which the number corresponding to the number of development is set as one set.

  Next, a specific configuration of the image signal line will be described in detail with reference to FIGS. FIG. 8 is a plan view showing a planar layout of image signal lines. 9 is a cross-sectional view taken along line BB ′ in FIG.

  In FIG. 7, the image signal line 91 is routed from the external circuit connection terminal 102 to the sampling circuit 7 on the TFT array substrate 10. Here, in particular, the image signal wiring 91 is provided in the direction in which the sampling switches 7s are arranged in order to supply the image signal to the data lines 6a arranged along one side of the image display area 10a (in the horizontal direction in FIG. 7). In other words, the image display area 10a is configured to include a portion wired in a direction along one side.

  As shown in FIGS. 8 and 9, in the present embodiment, the image signal line 91 particularly includes a first partial wiring 91a and a second partial wiring 91b (see FIG. 9). The first partial wiring 91a is formed of the same film as the conductive film constituting the data line 6a described above with reference to FIG. 6, and the second partial wiring 91b is the capacitive wiring 400 described above with reference to FIG. Is formed from the same film as the conductive film constituting the film. That is, the image signal line 91 is formed from two conductive films located in different layers with the third interlayer insulating film 43 interposed therebetween. Further, the first partial wiring 91 a and the second partial wiring 91 b are electrically connected to each other through a plurality of contact holes 195 opened in the third interlayer insulating film 43. Therefore, compared to the case where the image signal line 91 is formed from one conductive film, the electrical resistance or wiring resistance of the wiring is low. Accordingly, as in the present embodiment, the image signal line 91 includes a portion wired along the direction along one side of the image display area 10a, that is, the left-right direction (see FIG. 7) in the pixel display area 10a. However, the left-right difference in image display performance can be eliminated almost or completely in practice. In other words, due to the difference in time constant between the position corresponding to the left side of the image display area 10a in the image signal line 91 and the position corresponding to the right side, the degree of the round of the image signals VID1 to VID6 or the image signals VID1 to VID1. Since the timing at which the VID 6 is supplied is different, there is a difference in right and left such that the density of the image display varies depending on the left and right, the first partial wiring 91a and the second partial wiring 91b as in this embodiment, etc. This can be reduced or prevented. Such an effect is particularly effective when the image signal line 91 can be routed only from one of the left and right sides due to the arrangement of the external circuit terminals 102 and restrictions from other wirings.

  Further, in FIG. 9, as described above, the first partial wiring 91 and the second partial wiring 92 are each formed from two conductive films located in different layers, so that they are planar on the TFT array substrate 10. It can be wired so as to overlap each other. Therefore, the degree of freedom in designing the first partial wiring 91 and the second partial wiring 92 is high. Therefore, as shown in FIGS. 8 and 9, the first partial wiring 91 and the second partial wiring 92 are wired so that they almost or preferably completely overlap each other when viewed in plan on the TFT array substrate 10. Can do. That is, the resistance of the image signal line 91 can be reduced with little or no increase in the area on the substrate necessary for the wiring of the image signal line 91, in other words, without increasing the substrate size.

  In addition, in FIG. 9, particularly in the present embodiment, the second partial wiring 91 b extends from the external circuit connection terminal 102. Therefore, the second partial wiring 91b is electrically connected to the external circuit connection terminal 102 without passing through the contact hole. Accordingly, since there is no contact resistance or the like, the resistance from the external circuit connection terminal 102 to the second partial wiring 91b can be reduced.

  On the other hand, in FIG. 8 and FIG. 9, particularly in the present embodiment, the first partial wiring 91 a has a plurality of holes opened in a region where the external circuit connection terminal 102 is located in a plan view on the TFT array substrate 10. It is electrically connected to the external circuit connection terminal 102 through the contact hole 191. Therefore, the first partial wiring 91 a formed of a conductive film different from that of the external circuit connection terminal 102 can be formed even in the region where the external circuit connection terminal 102 is located when viewed in plan on the TFT array substrate 10. it can. Therefore, the resistance of the first partial wiring 91a can be lowered by effectively using the region where the external circuit connection terminal 102 is located.

  8 and 9, in the present embodiment, in particular, the first partial wiring 91a and the second partial wiring 91b are arranged via a plurality of contact holes 195 at portions overlapping each other when viewed in plan on the TFT array substrate 10. They are electrically connected to each other. Therefore, the electrical connection between the first partial wiring 91a and the second partial wiring 91b can be ensured, and the resistance of the image signal line 91 can be further reduced.

  8 and 9, in the present embodiment, in particular, the first partial wiring 91a and the second partial wiring 91b are formed so that their wiring widths are aligned with each other when viewed in plan on the TFT array substrate 10. Yes. That is, the wiring widths of the first partial wiring 91a and the second partial wiring 91b are almost or preferably completely matched. Further, the first partial wiring 91a and the second partial wiring 91b are formed so as to overlap each other. That is, the first partial wiring 91a and the second partial wiring 91b are almost or preferably completely overlapped with each other. Therefore, the first partial wiring 91a and the second partial wiring 91b can be wired in a region on the TFT array substrate 10 having almost the same area as the area on the TFT array substrate 10 necessary for wiring one partial wiring. it can. Therefore, the resistance of the image signal line 91 can be lowered with little change in the planar layout in the design.

  8 and 9, particularly in the present embodiment, as described above, the first partial wiring 91a is the same film as the conductive film constituting the data line 6a described above with reference to FIG. 6, that is, the same in the manufacturing process. The second partial wiring 91b is formed from the same film as the conductive film constituting the capacitor wiring 400 described above with reference to FIG. Therefore, the first partial wiring 91a and the second partial wiring 91b can be formed on the same occasion as the data line 6a and the capacitor wiring 400, respectively. That is, the image signal line 91 can be formed from two conductive films without complicating the manufacturing process.

  Next, with reference to FIG. 10 and FIG. 11, a specific configuration regarding electrical connection between the image signal line and the sampling circuit will be described. FIG. 10 is a layout diagram of image signal lines and branch wirings. 11 is a cross-sectional view taken along the line CC ′ in FIG.

  As shown in FIG. 10, on the TFT array substrate 10, the sampling circuit drive signal line 117 is wired in a direction intersecting with the image signal line 91 from the data line drive circuit 101, and further branched for each sampling switch 7s. It is wired in the direction in which the line 6a extends. The branch wiring 116 is wired in the direction in which the data line 6 a extends from one end side electrically connected to the corresponding image signal line 91 via the contact hole 181 opened in the third interlayer insulating film 43. ing. A part of the branch wiring 116 forms a source electrode of the sampling switch 7s, a part of the data line 6a forms a drain electrode of the sampling switch 7s, and a part of the sampling circuit drive signal line 117 forms the sampling switch 7s. A gate electrode is formed. As shown in FIGS. 10 and 11, the branch wiring 116 is electrically connected to the semiconductor layer 1 a in the sampling switch 7 s through the contact hole 183 opened in the first interlayer insulating film 41.

  As shown in FIG. 11, in this embodiment, in particular, the branch wiring 116 is a conductive film located on the lower layer side of the first partial wiring 91a and the second partial wiring 91b, that is, the capacitor electrode 300 described above with reference to FIG. Is formed from the same film as the conductive film constituting the film. If the branch wiring 116 is formed of a conductive film positioned between the first partial wiring 91a and the second partial wiring 91b, the branch wiring 116 is connected to the first partial wiring 91a and the second partial wiring 91 through the interlayer insulating film. A capacitance is formed with each of the two partial wirings 91b. However, according to the present embodiment, the branch wiring 116 forms a capacitance only with the first partial wiring 91a. That is, since the interlayer distance D2 between the branch wiring 116 and the second partial wiring 91b is longer than the interlayer distance D1 between the branch wiring 116 and the first partial wiring 91b, there is no gap between the branch wiring 116 and the second partial wiring 91b. As compared with the branch wiring 116 and the first partial wiring 91a, almost no capacitance is generated. In other words, the branch wiring 116 is formed of a conductive film at a position far enough to reduce or almost eliminate such capacitance on the lower layer side of the first partial wiring 91a and the second partial wiring 91b. Therefore, the fluctuation or fluctuation of the image signals VID1 to VID6 of the branch wiring 116 due to the influence of the image signals of the first partial wiring 91a and the second partial wiring 91b can be reduced.

  As described above, according to the liquid crystal device of the present embodiment, the resistance of the image signal line 91 can be reduced without increasing the area on the TFT array substrate 10 necessary for the wiring of the image signal line 91. Finally, high-quality image display is possible.

(Electronics)
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described.

  First, a projector using this liquid crystal device as a light valve will be described. FIG. 12 is a plan view showing a configuration example of the projector. As shown in FIG. 12, a projector 1100 is provided with a lamp unit 1102 composed of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.

  Note that since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  Next, an example in which the liquid crystal device is applied to a mobile personal computer will be described. FIG. 13 is a perspective view showing the configuration of the personal computer. In FIG. 13, the computer 1200 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal device 1005 described above.

  Further, an example in which the liquid crystal device is applied to a mobile phone will be described. FIG. 14 is a perspective view showing the configuration of this mobile phone. In FIG. 14, a mobile phone 1300 includes a reflective liquid crystal device 1005 together with a plurality of operation buttons 1302. In the reflective liquid crystal device 1005, a front light is provided on the front surface thereof as necessary.

  In addition to the electronic devices described with reference to FIGS. 12 to 14, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Examples include a station, a videophone, a POS terminal, a device equipped with a touch panel and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), It can also be applied to an organic EL display or the like.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. An electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

It is a top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment. It is sectional drawing in the HH 'line in FIG. It is an equivalent circuit of various elements and wirings in a plurality of pixel portions. FIG. 9 is a plan view of a plurality of adjacent pixel portions, and shows only a configuration relating to a lower layer portion (a lower layer portion up to reference numeral 70 (storage capacitor) in FIG. 6). FIG. 9 is a plan view of a plurality of adjacent pixel portions, and shows only the configuration relating to the upper layer portion (the upper layer portion beyond reference numeral 70 (storage capacity) in FIG. 6). It is sectional drawing in the AA 'line at the time of superimposing FIG.4 and FIG.5. It is explanatory drawing which shows the electrical connection relation of a data line drive circuit, a sampling circuit, an image signal line, and a data line. It is a top view which shows the planar layout of an image signal line. It is sectional drawing in the BB 'line in FIG. It is a layout diagram of an image signal line and branch wiring. It is sectional drawing in the CC 'line in FIG. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied. 1 is a perspective view showing a configuration of a personal computer as an example of an electronic apparatus to which an electro-optical device is applied. It is a perspective view which shows the structure of the mobile telephone which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 9a ... Pixel electrode, 6a ... Data line, 7 ... Sampling circuit, 7s ... Sampling switch, 10 ... TFT array substrate, 10a ... Image display area, 11a ... Scanning line, 20 ... Counter substrate, 21 ... Counter electrode, 30 ... Pixel Switching TFT, 41, 42, 43, 44 ... interlayer insulating film, 50 ... liquid crystal layer, 91 ... image signal line, 91a, 91b ... partial wiring, 101 ... data line driving circuit, 102 ... external circuit connection terminal, 104 ... Scan line drive circuit

Claims (7)

A data line; a transistor electrically connected to the data line; a pixel electrode provided corresponding to the transistor; one electrode electrically connected to the capacitor line; and the other electrode being a pixel electrode A storage capacitor electrically connected to the data line; an image signal line for supplying an image signal to the data line; and an external circuit connection terminal electrically connected to the image signal line.
The capacitor line is provided between a layer in which the data line is provided and a layer in which the pixel electrode is provided,
The image signal line includes a first partial wiring formed from the same film as the conductive film forming the data line, and a second partial wiring formed from the same film as the conductive film forming the capacitor line. Connected through a first contact hole provided in an insulating film between the first partial wiring and the second partial wiring;
The electro-optical device, wherein the second partial wiring extends from the external circuit connection terminal. A branch wiring branching from the image signal line, a sampling switch connected between the branch wiring and the data line, and a sampling circuit driving for supplying a sampling circuit driving signal from a data line driving circuit to the gate of the sampling switch A signal line;
The electro-optical device according to claim 1, wherein the branch wiring is formed of a conductive film located on a lower layer side of the first partial wiring and the second partial wiring. The one electrode is formed of a conductive film located on a lower layer side of the layer provided with the data line,
The electro-optical device according to claim 2, wherein the branch wiring is formed of the same film as the one electrode.   The first partial wiring is electrically connected to each of the external circuit connection terminals through a contact hole opened in a region where the external circuit connection terminal is located in a plan view on the substrate. The electro-optical device according to any one of claims 1 to 3.   The first partial wiring and the second partial wiring include a portion that overlaps at least partially when viewed in plan on the substrate, and is electrically connected to each other through at least one contact hole in the overlapping portion. 5. The electro-optical device according to claim 1, wherein the electro-optical device is provided.   2. The first partial wiring and the second partial wiring are formed so that each wiring width is aligned with each other and overlaps each other when viewed in plan on the substrate. The electro-optical device according to claim 5.   An electronic apparatus comprising the electro-optical device according to claim 1.

Images