JP4935326B2 - ELECTRO-OPTICAL DEVICE AND ELECTRONIC DEVICE HAVING THE SAME - Google Patents

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  In this type of electro-optical device, in the pixel region on the substrate, a plurality of data lines and a plurality of scanning lines arranged so as to cross each other, and these wirings are electrically connected corresponding to the intersection of the data lines and the scanning lines. Connected pixel portions are formed. In addition, in a peripheral region located around the pixel region on the substrate, a scanning line driving circuit for driving each scanning line and an image signal supply circuit for supplying an image signal to each data line are provided.

  When driving the electro-optical device, each scanning line is selected by supplying a scanning signal from the scanning line driving circuit, and each pixel line corresponding to the selected scanning line is connected to each pixel via each data line. The image signal is supplied. In such an electro-optical device, the image signal supply circuit is driven by a signal having a higher frequency than the scanning line driving circuit.

  More specifically, in the image signal supply circuit, a transfer signal is sequentially generated from the shift register at a timing based on a relatively high frequency clock signal and an inverted clock signal that is an inverted signal thereof, and the transfer signal is also generated in the buffer circuit. Based on this, buffer signals are sequentially generated, and image signals are supplied to a plurality of data lines at a timing based on the buffer signals.

  In addition, the image signal supply circuit is driven by a plurality of power sources including a pair of a high potential power source and a low potential power source having a lower potential than the high potential power source. The plurality of power sources are supplied from, for example, an external circuit via a plurality of power supply wires.

JP 2004-126551 A

  Here, when the electro-optical device as described above is downsized, it is necessary to reduce the arrangement area of the scanning line driving circuit and the image signal supply circuit in the peripheral region, and accordingly, the plurality of power supply wirings are also thinned. May be. If each power supply wiring is thinned in this way, the wiring capacity is also reduced, so that the potential of the power supply wiring tends to fluctuate, that is, may become unstable. For example, if a signal line serving as a supply path for a clock signal or the like to the image signal supply circuit is arranged close to the power supply wiring, the potential of the power supply wiring is likely to fluctuate due to interference from a relatively high frequency clock signal. This causes problems.

  Along with this, when the power supply potential becomes unstable particularly in each stage of the buffer circuit in the image signal supply circuit, the waveform of the buffer signal is disturbed, and such disturbance is caused in the pixel portion corresponding to each data line. By affecting the image display, it is visually recognized as a strip-shaped display unevenness along the extending direction of the data lines on the display screen, resulting in a problem that the quality of the image display is deteriorated.

  The present invention has been made in view of the above-described problems, for example, and provides an electro-optical device capable of performing high-quality image display and miniaturization, and an electronic apparatus including the electro-optical device. Let it be an issue.

  In order to solve the above-described problem, an electro-optical device according to an aspect of the invention includes a plurality of pixel portions and a plurality of scanning lines wired on the substrate so as to cross a pixel region where the plurality of pixel portions are provided. A plurality of data lines, and a peripheral circuit located in the periphery of the pixel area, including a buffer circuit that is arranged along an arrangement direction of the plurality of data lines and outputs a sampling signal, and is output from the buffer circuit A power supply that has an image signal supply circuit that supplies an image signal to the plurality of data lines according to a sampling signal and a first wiring portion that extends along the arrangement direction, and supplies a power supply potential to the buffer circuit And at least a portion when viewed in plan on the substrate with respect to the buffer circuit, and disposed on a layer different from the first wiring portion on the upper layer side of the buffer circuit To have a wired second wiring portion so as to overlap, and includes and electrically connected to the power supply redundancy line to the power line.

  According to the electro-optical device of the present invention, during the operation, each scanning line is selected based on the scanning signal supplied from the scanning line driving circuit, and the pixel portion corresponding to the selected scanning line has an image. An image signal is supplied from the signal supply circuit via each data line. In the image signal supply circuit, the supply timing of the image signal to the data line is defined based on buffer signals sequentially generated from the buffer circuit.

  Also, the image signal supply circuit is supplied with a plurality of systems of power via, for example, a plurality of power lines, and a plurality of inverters are electrically connected with two or more systems of power sources, for example, a pair of a high potential power source and a low potential power source. A buffer circuit configured to be connected to each other is driven. More specifically, the power supply line has a first wiring portion extending along the arrangement direction of the data lines, and each stage of the buffer circuit is supplied with power via the first wiring portion. The transfer signal is buffered to generate a buffer signal. The “arrangement direction of a plurality of data lines” according to the present invention means a direction in which a plurality of data lines are arranged along one side of the pixel region or a direction intersecting with a direction in which the data lines extend. In other words, it can be called the “X direction”, which is the direction in which the line extends.

  In the electro-optical device of the present invention, the power supply redundant wiring electrically connected to the power supply line is formed in the peripheral region on the substrate. More specifically, the power supply redundant wiring is disposed on a layer higher than the buffer circuit and different from the first wiring portion, and at least partially viewed in plan on the substrate with respect to the buffer circuit. It is wired so as to be superimposed on.

  Therefore, in the electro-optical device of the present invention, the redundant wiring for the power supply is provided for the power supply line, and the second wiring portion is formed so as to run in parallel on the substrate with respect to the first wiring portion. In addition, the wiring capacity in the power supply path to the buffer circuit can be increased. Therefore, even when it is necessary to reduce the power supply redundant wiring in addition to the power supply line, it is possible to prevent the wiring capacity in the power supply path to the buffer circuit due to the thinning from being significantly reduced. As a result, it is possible to prevent the potential from changing significantly in the first wiring portion of the power supply line, that is, to stabilize the potential, and to stabilize the power supply potential of each stage of the buffer circuit.

  Further, by arranging the second wiring portion in the power supply redundant wiring in a layer different from the first wiring portion of the power supply line, the wiring shape of the first wiring portion of the power supply line is not significantly changed. However, redundant power supply wiring can be provided for the power supply line. Therefore, the redundant power supply wiring can be easily formed when the electro-optical device is manufactured.

  In addition, in the redundant wiring for power supply, the second wiring portion is disposed on the upper layer side of the buffer circuit on the substrate, and is formed so as to at least partially overlap the buffer circuit when viewed in plan on the substrate. . Therefore, by providing the power supply redundant wiring in the peripheral region on the substrate, it is possible to prevent an increase in the layout area required for arranging the buffer circuit, the power supply wiring, and the power supply redundant wiring. Further, when the second wiring portion is disposed so as to overlap with the buffer circuit as viewed in plan on the substrate, the buffer circuit is electromagnetically separated from the wiring formed on the upper layer side from the second wiring portion. Can be shielded. Thereby, the operation of each stage of the buffer circuit can be further stabilized.

  According to the electro-optical device of the present invention as described above, it is possible to prevent the waveform of the sampling signal from being significantly disturbed by the unstable operation of each stage of the buffer circuit as the size is reduced. It becomes. Therefore, in the image signal supply circuit, it is possible to prevent the supply timing of the image signal from being disturbed according to the sampling signal, and to prevent the occurrence of display defects such as strip-shaped display unevenness on the display screen of the electro-optical device. . Therefore, the electro-optical device can be easily downsized and high-quality image display can be performed even if the electro-optical device is downsized.

  In one aspect of the electro-optical device of the present invention, a plurality of signal lines arranged on the substrate in the peripheral region along the arrangement direction and outputting the sampling signal in the image signal supply circuit; A plurality of redundant wirings for sampling signals that are electrically connected to the plurality of signal lines and arranged along the arrangement direction are provided.

  According to this aspect, the wiring capacity of the output path of the sampling signal output from each stage of the buffer circuit can be substantially increased, and the potential of the output path can be stabilized. As a result, even if the signal line through which the sampling signal is output is thinned, it is possible to prevent the wiring capacity in the sampling signal output path from being significantly reduced. It is possible to prevent the disturbance of the signal waveform.

  In the aspect including the redundant wiring for sampling signal described above, the plurality of redundant wirings for sampling signal are arranged in different layers from the first wiring portion, and the first wiring portion is viewed in plan on the substrate. You may comprise so that it may be wired so that it may overlap at least partially with respect to one wiring part.

  In this case, it is possible to prevent the arrangement area on the substrate required for arranging the plurality of redundant wirings for sampling signals in addition to the first wiring portion of the power supply line from being increased. Furthermore, a plurality of redundant wirings for sampling signals can be provided without making a significant change in the wiring shape or the like of the first wiring portion of the power supply line.

  In the aspect including the redundant wiring for sampling signal described above, the second wiring portion is arranged in the same layer as the plurality of redundant wirings for sampling signal, and is configured to be wired along the arrangement direction. May be.

  In this case, the second wiring portion of the power supply redundant wiring is arranged in the same layer as the sampling signal redundant wiring, and the second wiring portion of the power supply redundant wiring is connected to the power supply line in an area vacant with respect to the arrangement of each sampling signal redundant wiring. It is formed in parallel with the first wiring portion. Therefore, when the second wiring portion of each of the sampling signal redundant wiring and the power supply redundant wiring is provided in addition to one, the same pattern on the substrate is not changed without significant design change. It becomes possible to form each one layer.

  In the above aspect in which the second wiring portion and the sampling signal redundant wiring are arranged in the same layer, the power supply redundant wiring corresponds to each stage of the buffer circuit from the second wiring portion. You may comprise so that it may have a some contact part extended along the direction which cross | intersects an arrangement | sequence direction, and the 1st wiring part overlapped.

  In this case, when the second wiring portion is formed in the power supply redundant wiring by avoiding the arrangement of each sampling signal redundant wiring in the same layer as the sampling signal redundant wiring, By continuously forming the contact portion, it is possible to substantially expand the arrangement area of the second wiring portion with respect to the region overlapping with the first wiring portion in plan view on the substrate. Become. Therefore, the wiring capacity of the second wiring portion of the power supply redundant wiring can be further increased.

  In the aspect having the plurality of contact portions described above, each of the plurality of contact portions has two sampling signal redundancy lines adjacent to each other among the plurality of sampling signal redundancy wirings when viewed in plan on the substrate. It may be formed between the wirings and may be formed so as to extend in the arrangement direction so as to approach each of the two sampling signal redundant wirings.

  In this case, it is possible to further expand the arrangement area of the second wiring portion substantially with respect to the region overlapping the first wiring portion on the substrate when viewed in plan. Therefore, the wiring capacity of the second wiring portion of the power supply redundant wiring can be further increased. Furthermore, since stable power is supplied near each of the redundant wirings for sampling signals, the potential of the sampling signal can be further stabilized.

  In another aspect of the electro-optical device of the present invention, each of the plurality of pixel portions includes a storage capacitor electrically connected to the data line, and the first wiring portion is formed of the same film as the data line. The second wiring portion is formed of the same film as the capacitor line that is disposed in a different layer from the data line and is electrically connected to the storage capacitor.

  According to this aspect, in the manufacturing process of the electro-optical device, the first wiring portion of the power supply wiring and the second wiring portion of the power supply redundant wiring in the peripheral region on the substrate are replaced with the storage capacitor in the data line or each pixel unit. By forming together, the number of steps can be simplified. Here, the “same film” means films formed on the same occasion in the manufacturing process, and means the same kind of film.

  In order to solve the above-described problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  Since the electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention, the projection display device, the television, the mobile phone, and the electronic notebook that can display a high-quality image and can be miniaturized. Various electronic devices such as a word processor, a viewfinder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. Further, as the electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper, a display device using an electron emission device (Field Emission Display and Conduction Electron-Emitter Display), or the like can be realized.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line H-H 'in FIG.

  1 and 2, the liquid crystal device is composed of a TFT array substrate 10 and a counter substrate 20 which are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are included in an image display region 10a as an example of the “pixel region” according to the present invention. They are bonded to each other by a sealing material 52 provided in a surrounding sealing region.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates, and is applied on the TFT array substrate 10 in the manufacturing process and then cured by ultraviolet irradiation, heating, or the like. It is. Further, in the sealing material 52, a gap material such as glass fiber or glass beads for dispersing the distance (inter-substrate gap) between the TFT array substrate 10 and the counter substrate 20 to a predetermined value is dispersed.

  A light-shielding frame light-shielding film 53 that defines the frame area of the image display area 10a is provided on the counter substrate 20 side in parallel with the inside of the seal area where the sealing material 52 is disposed. However, part or all of the frame light shielding film 53 may be provided as a built-in light shielding film on the TFT array substrate 10 side.

  In the peripheral region located around the image display region 10 a on the TFT array substrate 10, the data line driving circuit 101 and the external circuit connection terminal 102 are provided along one side of the TFT array substrate 10. Further, a region located on the inner side of the seal region in the peripheral region on the TFT array substrate 10 is covered with the frame light shielding film 53 along one side of the image display region 10 a along one side of the TFT array substrate 10. Thus, the sampling circuit 7 is arranged. In the peripheral region on the TFT array substrate 10, the “image signal supply circuit” according to the present invention includes the data line driving circuit 101 and the sampling circuit 7.

  The scanning line driving circuit 104 is provided along two sides adjacent to one side of the TFT array substrate 10 so as to be covered with the frame light shielding film 53. Further, in order to electrically connect the two scanning line driving circuits 104 provided on both sides of the image display region 10a in this way, the TFT array substrate 10 is covered with the frame light shielding film 53 along the remaining side. A plurality of wirings 105 are provided.

  On the TFT array substrate 10, vertical conduction terminals 106 for electrically connecting the two substrates with a vertical conduction material are disposed in regions facing the four corner portions of the counter substrate 20.

  In FIG. 2, on a TFT array substrate 10, a pixel electrode 9a is formed on a TFT (Thin Film Transistor) as a pixel switching element, a wiring such as a scanning line, a data line, and an alignment film (see FIG. 2). Are omitted). In the present embodiment, the pixel switching element may be constituted by various transistors, TFD, or the like in addition to the TFT.

  On the other hand, a lattice-shaped or stripe-shaped light shielding film 23 is formed in the image display region 10a on the counter substrate 20, and a liquid crystal layer 50 is interposed on the light shielding film 23 (below the light shielding film 23 in FIG. 2). Thus, a counter electrode 21 is formed to face the plurality of pixel electrodes 9a. Further, an alignment film (not shown) is formed in the drawing.

  The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films. A liquid crystal storage capacitor is formed between the pixel electrode 9 a and the counter electrode 21 by applying a voltage to each of the liquid crystal devices during driving.

  Although not shown here, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the TFT array substrate 10 is used for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or at the time of shipment. An inspection circuit or the like may be formed.

  Next, an electrical configuration of the liquid crystal device will be described with reference to FIGS. FIG. 3 is a block diagram schematically showing the arrangement of various drive circuits in the peripheral region on the TFT array substrate, the electrical connection relationship, and the like. FIG. 4 shows various elements in a plurality of pixel portions. It is a circuit diagram which shows equivalent circuits, such as wiring.

  3, in the pixel display region 10a on the TFT array substrate 10, a plurality of pixel electrodes 9a arranged in a matrix and a plurality of scanning lines 11a and data lines 6a arranged so as to cross each other are formed. A pixel portion corresponding to the pixel is constructed corresponding to the intersection of the scanning line 11a and the data line 6a.

  In the peripheral region on the TFT array substrate 10, a data line driving circuit 101, a sampling circuit 7 and a scanning line driving circuit 104 constituting the “image signal supply circuit” according to the present invention are provided.

  For example, the scanning line driving circuit 104 receives an Y clock signal CLY, an inverted Y clock signal CLYinv, a Y start pulse DY, and Y-side high potential power supplies VDDY and Y from an external circuit (not shown) via the external circuit connection terminal 102. Side low potential power supply VSSY is supplied. When the Y start pulse DY is input, the scanning line driving circuit 104 sequentially generates and outputs a scanning signal at a timing based on the Y clock signal CLY and the inverted Y clock signal CLYinv.

  In the present embodiment, the data line driving circuit 101 includes a shift register 101a and a buffer circuit 101b.

  The shift register 101a receives, for example, an X clock signal CLX, an inverted X clock signal CLXinv, an X start pulse DX, an X side high potential power supply VDDX, and an X side low potential power supply VSSX from an external circuit via the external circuit connection terminal 102. Supplied.

  The shift register 101a sequentially outputs the transfer signal SRi (i = 1,..., N) from each stage based on the X-side clock signal CLX, the inverted X clock signal CLXinv, and the X start pulse DX having a predetermined period. It is configured.

  The buffer circuit 101b is configured by electrically connecting a plurality of inverters, and outputs the sampling circuit drive signal Si based on the transfer signal SRi sequentially output from the shift register 101b. The sampling circuit drive signal Si is an example of the “sampling signal” according to the present invention.

  Since the transfer signal SRi passes through the buffer circuit 101b, the driving capability of the later-described sampling circuit 7 by the sampling circuit driving signal Si is improved.

  Here, the X-side high-potential power supply VDDX and the X-side low-potential power supply VSSX are supplied to the shift register 101a and the buffer circuit 101b in the data line driving circuit 101 via the corresponding power supply wirings 601 and 602. Further, for example, the power supply lines 601 and 602 are arranged close to each other in the vicinity of a signal line for supplying the X clock signal CLX and the inverted X clock signal CLXinv to the shift register 101a, and an external circuit connection terminal together with these signal lines. From 102, the shift register 101a and the buffer circuit 101b are routed around each of the shift register 101a and the buffer circuit 101b to be connected to the shift register 101a and the buffer circuit 101b.

  The image signals VID <b> 1 to VID <b> 6 are serial-parallel converted into, for example, six phases, that is, phase-expanded, for example, by an external circuit, and are supplied to the sampling circuit 7 via the six image signal lines 6. The six image signal lines 6 are connected to external circuits by bypassing the periphery of the shift register 101a and the buffer circuit 101b from the opposite sides of the shift register 101a and the buffer circuit 101b with respect to the power supply lines 601 and 602, respectively. It is routed from the terminal 102 and wired along the arrangement direction of the sampling switches 71 in the sampling circuit 7 (that is, the arrangement direction of the data lines 6a in FIG. 3 or the X direction). By wiring the six image signal lines 6 in this way, the X clock signal CLX and the inverted X clock which are higher in frequency than the Y clock signal CLY and the inverted Y clock signal CLYinv supplied to the scanning line driving circuit 104. It is possible to prevent electromagnetic signal interference from the signal line serving as the signal CLXinv supply path to each image signal line 6.

  The sampling circuit 7 includes a sampling switch 71 composed of a P-channel or N-channel single-channel TFT or a complementary TFT. A signal output from the buffer circuit 101b of the data line driving circuit 101 is supplied to each sampling switch 71 through the signal line 114 as the sampling circuit driving signal Si.

  Each sampling switch 7a supplies the image signals VID1 to VID6 for each data line group including six data lines 6a as a group in accordance with the sampling circuit drive signal Si. Therefore, in the present embodiment, since the plurality of data lines 6a are driven for each data line group, the driving frequency can be suppressed.

  Various timing signals such as the clock signals CLX and CLY are generated by, for example, a timing generator formed in an external circuit (not shown) and supplied to each circuit on the TFT array substrate 10 via the external circuit connection terminal 102. . Further, the power necessary for driving each drive circuit is also supplied from an external circuit, for example. Further, the counter electrode potential LCC is supplied to the signal line drawn from the vertical conduction terminal 106 from, for example, an external circuit. The counter electrode potential LCC is supplied to the counter electrode 21 through the vertical conduction terminal 106. The counter electrode potential LCC is a reference potential of the counter electrode 21 for appropriately holding the potential difference from the pixel electrode 9a and forming a liquid crystal storage capacitor.

  In FIG. 4, each of a plurality of pixels formed in a matrix that forms the image display region 10 a of the liquid crystal device has a pixel electrode 9 a and a TFT 30 for controlling the switching of the pixel electrode 9 a. A data line 6 a to which an image signal VIDk (where k = 1, 2, 3,..., 6) is supplied is electrically connected to the source of the TFT 30. Further, the gate electrode 3 a is electrically connected to the gate of the TFT 30, and the pixel electrode 9 a is electrically connected to the drain of the TFT 30.

  Each scanning line 11a is selected line-sequentially by scanning signals G1,..., Gm output from the scanning line driving circuit 104. When the scanning signal Gj (j = 1, 2, 3,..., M) is supplied to the TFT 30 via the gate electrode 3a in the pixel portion corresponding to the selected scanning line 11a, the TFT 30 is turned on. The pixel electrode 9a is supplied with the image signal VIDk from the data line 6a at a predetermined timing by closing the switch of the TFT 30 for a certain period. As a result, an applied voltage defined by the potentials of the pixel electrode 9a and the counter electrode 21 is applied to the liquid crystal. The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to the image signals VID1 to VID6 is emitted from the liquid crystal device as a whole.

  In order to prevent the image signal held here from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. The storage capacitor 70 is provided side by side along the scanning line 11a, and includes a capacitor electrode 300 including a fixed potential side capacitor electrode and fixed at a constant potential.

  Next, a specific configuration of the pixel portion that realizes the above-described operation will be described with reference to FIG. FIG. 5 is a cross-sectional view showing the configuration of the cross-sectional portion of the pixel portion. In FIG. 5, the scale of each layer / member is different for each layer / member to have a size that can be recognized on the drawing. About this point, it is the same also about each figure of FIG.7 and FIG.8 mentioned later, and it may mutually differ about each scale about this scale.

  In FIG. 5, for example, a TFT array substrate 10 made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and a counter substrate 20 made of, for example, a glass substrate or a quartz substrate are provided so as to face each other.

  A pixel electrode 9a is provided on the TFT array substrate 10 side, and an alignment film 16 subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive film such as an ITO film. On the other hand, a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 21. . The counter electrode 21 is made of a transparent conductive film such as an ITO film, for example, like the pixel electrode 9a described above.

  Between the TFT array substrate 10 and the counter substrate 20 arranged so as to face each other, liquid crystal is sealed in a space surrounded by a sealing material 52 (see FIGS. 1 and 2), and a liquid crystal layer 50 is formed. The liquid crystal layer 50 takes a predetermined alignment state by the alignment films 16 and 22 in a state where an electric field from the pixel electrode 9a is not applied.

  On the other hand, on the TFT array substrate 10, in addition to the pixel electrode 9a and the alignment film 16, various configurations including these are provided in a laminated structure. Below, this laminated structure is demonstrated in order from the bottom.

  First, on the TFT array substrate 10, a scanning line 11a is provided in the first layer, and a base insulating film 12 is provided on the upper layer side of the scanning line 11a.

  A TFT 30 including the gate electrode 3a is provided in the second layer above the base insulating film 12. The TFT 30 has, for example, an LDD (Lightly Doped Drain) structure, and includes, as its constituent elements, a gate electrode 3a, a channel region 1a ′ of the semiconductor layer 1a in which a channel is formed by an electric field from the gate electrode 3a, a gate electrode An insulating film 2 including a gate insulating film that insulates 3a from the semiconductor layer 1a, a low concentration source region 1b and a low concentration drain region 1c in the semiconductor layer 1a, and a high concentration source region 1d and a high concentration drain region 1e. In addition, a relay electrode 719 is formed on the second layer as the same film as the gate electrode 3a described above.

  Here, a contact hole 12cv is dug in the base insulating film 12, and the gate electrode 3a is formed so as to fill the entire contact hole 12cv, whereby the gate electrode 3a is integrally formed therewith. Side wall portions 3b formed in the above are extended.

  On the TFT array substrate 10, a first interlayer insulating film 41 is formed on the upper layer side from the TFT 30 to the gate electrode 3 a and the relay electrode 719. A contact hole 81 for electrically connecting the high-concentration source region 1d of the TFT 30 and a data line 6a described later is opened in the first interlayer insulating film 41 while penetrating the second interlayer insulating film 42 described later. Yes. Further, the first interlayer insulating film 41 is provided with a contact hole 83 for electrically connecting the high concentration drain region 1e of the TFT 30 and the lower electrode 71 constituting the storage capacitor 70. In addition, the first interlayer insulating film 41 is provided with a contact hole 881 for electrically connecting the lower electrode 71 serving as a pixel potential side capacitor electrode constituting the storage capacitor 70 and the relay electrode 719. . In addition, a contact hole 882 for electrically connecting the relay electrode 719 and a second relay electrode 6a2 described later passes through the second interlayer insulating film 42 described later in the first interlayer insulating film 41. It is open.

  A storage capacitor 70 is provided in the third layer above the first interlayer insulating film 41. The storage capacitor 70 includes a lower electrode 71 as a pixel potential side capacitor electrode connected to the high concentration drain region 1e of the TFT 30 and the pixel electrode 9a, and a capacitor electrode 300 as a fixed potential side capacitor electrode. It is formed by arrange | positioning through.

  The lower electrode 71 has a function of relaying and connecting the pixel electrode 9a and the high concentration drain region 1e of the TFT 30 in addition to a function as a pixel potential side capacitor electrode. The capacitor electrode 300 is electrically connected to a capacitor line 400 having a fixed potential described later. The dielectric film 75 has a two-layer structure, for example, a silicon oxide film 75a in the lower layer and a silicon nitride film 75b in the upper layer.

  A second interlayer insulating film 42 is formed above the storage capacitor 70. The second interlayer insulating film 42 is provided with the contact hole 81 for electrically connecting the high-concentration source region 1d of the TFT 30 and the data line 6a, and the capacitor line relay layer 6a1 and the storage. A contact hole 801 is formed to electrically connect the capacitor electrode 300 which is the upper electrode of the capacitor 70. Further, the contact hole 882 described above for electrically connecting the second relay electrode 6a2 and the relay electrode 719 is formed in the second interlayer insulating film.

  A data line 6 a is provided in the fourth layer above the second interlayer insulating film 42. For example, the data line 6a includes, in order from the lower layer, a layer made of aluminum (see reference numeral 41A in FIG. 5), a layer made of titanium nitride (see reference numeral 41TN in FIG. 5), and a layer made of a silicon nitride film (reference numeral 401 in FIG. 5). Reference) is formed as a film having a three-layer structure. Further, a capacitor line relay layer 6a1 and a second relay electrode 6a2 are formed on the fourth layer as the same film as the data line 6a.

  A third interlayer insulating film 43 is formed above the data line 6a. The third interlayer insulating film 43 includes a contact hole 803 for electrically connecting the capacitor line 400 and the capacitor line relay layer 6a1, and a third relay electrode 402 and a second relay electrode 6a2. Contact holes 804 for electrical connection are respectively opened.

  In the fifth layer above the third interlayer insulating film 43, the capacitor line 400 is formed, and the third relay electrode 402 is formed as the same film as the capacitor line 400. The third relay electrode 402 has a function of relaying an electrical connection between the second relay electrode 6a2 and the pixel electrode 9a through contact holes 804 and 89 described later. Here, the capacitor line 400 and the third relay electrode 402 have a two-layer structure in which a lower layer is made of aluminum and an upper layer is made of titanium nitride.

  Finally, on the sixth layer, the pixel electrodes 9a are formed in a matrix as described above, and the alignment film 16 is formed on the pixel electrodes 9a. A fourth interlayer insulating film 44 is formed under the pixel electrode 9a. In the fourth interlayer insulating film 44, a contact hole 89 for electrically connecting the pixel electrode 9a and the third relay electrode 402 is opened. Between the pixel electrode 9a and the TFT 30, the contact hole 89, the third relay layer 402 and the contact hole 804, the second relay layer 6a2, the contact hole 882, the relay electrode 719, the contact hole 881, the lower electrode 71, and the contact hole described above. It is electrically connected through 83.

  The configuration in the pixel portion as described above is common to each pixel portion, and the configuration in the pixel portion is periodically formed in the image display region 10a described with reference to FIGS. .

  Next, the configuration on the image signal supply circuit side that is characteristic in the present embodiment will be described in more detail with reference to FIGS.

  FIG. 6 schematically shows the arrangement relationship of the data line driving circuit, the sampling circuit, and other various signal lines, and their electrical connection relationship. In FIG. 6, as described with reference to FIG. 3, the transfer signal SRi sequentially output from the shift register 101a is input to the buffer unit circuit 500 of each stage of the buffer circuit 101b.

  As shown in FIG. 6, in the buffer circuit 101b, the buffer unit circuit 500 at each stage is arranged along the X direction (that is, the arrangement direction of the data lines 6a). Further, each of the power supply wirings 601 and 602 has a first wiring part 601a and 602a extending along the X direction. The X-side low potential power supply VSSX and the X-side high potential power supply VDDX are Each buffer unit circuit 500 is supplied via the first wiring portions 601a and 602a. As a result, each buffer unit circuit 500 is driven to buffer the input transfer signal SRi to generate a buffer output signal, which is output to the signal line 114 as a sampling circuit drive signal Si.

  Of the power supply wirings 601 and 602, the power supply redundant wiring 603 is formed by being electrically connected to one power supply wiring 601 that supplies the X-side low potential power supply VSSX. The redundant wiring for power supply 603 includes a second wiring portion 603a arranged in parallel with the first wiring portion 601a on the TFT array substrate 10 along the first wiring portion 601a of the corresponding power supply wiring 601. Have. The redundant power supply wiring 603 is electrically connected to the first wiring portion 601a in the second wiring portion 603a, for example, for each stage of the buffer circuit 101b.

  In this embodiment, as described with reference to FIG. 3 or FIG. 6, the shift register 101a and the buffer circuit 101b of the data line driving circuit 101 share the X-side high potential power supply VDDX and the X-side low potential, respectively. The configuration is not limited to the configuration driven by the power supply VSSX, and may be driven by different power supplies. In this case, different systems of power are supplied to the shift register 101a and the buffer circuit 101b through different power supply lines. With this configuration, it is possible to reduce the influence of the electromagnetic signal interference of the high-frequency X clock signal CLX and the inverted X clock signal CLXinv on the operation of each stage of the buffer circuit 101b via the power supply. Become.

  Further, in the image signal supply circuit according to the present invention, the data line driving circuit 101 may further include, for example, a level shifter circuit for shifting the potential of the output signal of the buffer circuit 101b, or the data line driving circuit 101. In addition, a phase difference correction circuit or the like may be provided that corrects the phase difference between the X clock signal CLX and the inverted X clock signal CLXinv to mutually invert signals.

  Next, the configuration of the first wiring portion and the second wiring portion will be described in more detail with reference to FIGS. FIG. 7 is a plan view showing the configuration and arrangement relationship of the first wiring portion, the second wiring portion, and the redundant wiring for the buffer output signal. FIG. 8 is a cross-sectional view taken along the line AA ′ of FIG. FIG. In FIG. 7, regarding the buffer unit circuits 500 adjacent to each other in the buffer circuit 101b, these buffer unit circuits 500, the first wiring portion 601a, the second wiring portion 603a, and further the redundant wiring for the buffer output signal The arrangement relationship with each of 114a is shown.

  In the present embodiment, as shown in FIG. 8, in the power supply wiring 601, at least the first wiring portion 601a is preferably arranged in the same layer as the data line 6a described with reference to FIG. It is formed by the same film. In this case, the first wiring portion 601 a is disposed on the second interlayer insulating film 42 in the peripheral region on the TFT array substrate 10.

  Further, in the power supply redundant wiring 603, at least the second wiring portion 603a is a layer different from the first wiring portion 601a, and preferably in the same layer as the capacitor line 400 described with reference to FIG. It is formed by the same film. In this case, the second wiring portion 603 a is disposed on the third interlayer insulating film 43 in the peripheral region on the TFT array substrate 10.

  Here, various electronic elements such as transistors constituting each buffer unit circuit 500 are not shown in detail in FIG. 7 or FIG. 8, but the pixel described with reference to FIG. It is formed in the same layer as the switching TFT 30. A specific configuration of the buffer unit circuit 500 will be described later with reference to FIGS.

  In FIG. 7, at least the second wiring portion 603 a in the redundant power supply wiring 603 is planar on the TFT array substrate 10 with respect to the buffer unit circuit 500 on the TFT array substrate 10 and on the upper layer side of the buffer unit circuit 500. And at least partially overlap. Therefore, in FIG. 8, the buffer unit circuit 500 is constructed in a region located on the lower layer side of the second wiring portion 603a. In addition, the first wiring portion 601a is electrically connected to the electronic elements constituting each buffer unit circuit 500 on the lower layer side.

  In the second wiring portion 603a, a contact portion 603b is formed corresponding to each buffer unit circuit 500 continuously and in the same layer as the second wiring portion 603a. That is, the power supply redundant wiring 603 has a contact portion 603b extending in the Y direction from the second wiring portion 603a extending in the X direction for each buffer unit circuit 500. The contact portion 603b is electrically connected to the first wiring portion 601a through a contact hole 610 formed through the third interlayer insulating film 43.

  Therefore, in the present embodiment, since the second wiring portion 603a of the redundant power supply wiring 603 is provided for the first wiring portion 601a of the power supply wiring 601, the power supply to the buffer circuit 101b is substantially reduced. It is possible to increase the wiring capacity in the supply path. Therefore, even when the first wiring portion 601a in the power supply wiring 601 and the second wiring portion 603a in the power redundant wiring 603 need to be thinned, the X-side low potential power supply VSSX for the buffer circuit 101b accompanying the thinning is required. It is possible to prevent the wiring capacitance in the supply path from being significantly reduced.

  For example, as described with reference to FIG. 3, in the peripheral region on the TFT array substrate 10, a signal line for supplying a relatively high frequency X clock signal CLX and an inverted X clock signal CLXinv, and a power supply wiring 601 When the power supply wirings 601 and 602 are thinned, the potential of the power supply wiring 601 becomes unstable due to electromagnetic interference between the X clock signal CLX and the inverted X clock signal CLXinv. As a result, the potential of the first wiring portion 601a may become unstable.

  On the other hand, in this embodiment, in the first wiring portion 601a of the power supply wiring 601, it is possible to secure the wiring capacity and stabilize the potential, and the power supply potential of each buffer unit circuit 500 of the buffer circuit 101b is set. Can be stabilized.

  Further, by forming the power supply redundant wiring 603 so that the second wiring portion 603a in the power supply redundant wiring 603 overlaps the buffer unit circuit 500 when viewed in plan on the TFT array substrate 10, the buffer circuit 101b is formed. Therefore, it is possible to prevent an increase in the layout area required for the layout of the power supply wiring 601 and the power supply redundant wiring 603. In addition, when configured in this manner, each buffer unit circuit 500 can be electromagnetically shielded from the wiring formed on the upper layer side of the second wiring portion 603a in the peripheral region on the TFT array substrate 10. It becomes possible. Thereby, the operation of each buffer unit circuit 500 can be further stabilized.

  Further, by arranging the second wiring portion 603a in a different layer from the first wiring portion 601a, the power wiring 601 can be made without any significant change in the wiring shape or the like of the first wiring portion 601a. Thus, the redundant power supply wiring 603 can be provided. Therefore, the redundant power supply wiring 603 can be easily formed when the liquid crystal device is manufactured.

  In addition, in FIG. 7, the signal line 114 from which the buffer output signal as the sampling circuit drive signal Si is output from each stage of the buffer circuit 101b is the same as the gate electrode 3a of the TFT 30 described with reference to FIG. One layer is formed. A buffer output as an example of the “redundant wiring for sampling signal” according to the present invention is formed on the upper layer side of each signal line 114 in a pattern shape that overlaps with and corresponds to the signal line 114 in plan view. Redundant signal wiring 114a is formed. Therefore, the buffer output signal redundant wiring 114a is arranged along the X direction in FIG. 7 (that is, the same direction as the arrangement direction of the data lines 6a in FIG. 3), that is, along the first wiring portion 601a. A plurality are formed.

  Further, each of the plurality of buffer output signal redundant wirings 114a is preferably disposed in the same layer as the second wiring part 603a and is formed in the same film as the second wiring part 603a, as shown in FIG. That is, it is formed of the same film as the capacitor line 400. Further, each buffer output signal redundant wiring 114a is electrically connected to a corresponding signal line 114 disposed on the lower layer side.

  Therefore, by substantially increasing the wiring capacity of the output path of the sampling circuit drive signal Si output from each buffer unit circuit 500, the power supply potential of this output path can be stabilized. As a result, even if each signal line 114 is thinned, it is possible to prevent the wiring capacity in the output path of the sampling circuit drive signal Si from being significantly reduced, so that the waveform of the sampling circuit drive signal Si can be more reliably detected. Disturbance can be prevented.

  Here, in FIG. 7 or FIG. 8, if attention is paid to the positional relationship between each buffer output signal redundant wiring 114 a and the first wiring portion 601 a, each buffer output signal redundant wiring 114 a is arranged on the TFT array substrate 10. The first wiring portion 601a is formed so as to at least partially overlap when viewed in a plan view. Therefore, providing each buffer output signal redundant wiring 114a prevents an increase in the layout area required for the buffer output signal redundant wiring 114a in addition to the first wiring portion 601a on the TFT array substrate 10. It becomes possible to do. Further, in this case, a plurality of buffer output signal redundant wirings 114a can be provided without significant changes to the wiring shape or the like of the first wiring portion 601a.

  Further, regarding the arrangement relationship between each buffer output signal redundant wiring 114a and the second wiring portion 603a, the second wiring portion 603a is arranged with respect to each buffer output signal redundant wiring 114a (see FIG. 7 in the X direction).

  In FIG. 7, focusing on the pattern shape of each buffer output signal redundant wiring 114 a, the first wiring portion 601 a on the third interlayer insulating film 43 overlaps with the pattern shape of the signal line 114. An empty area is defined in the area, and the buffer output signal redundant wiring 114a is formed so that a part thereof overlaps a portion extending along the X direction in the signal line 114. . As a result, on the portion extending along the X direction in one signal line 114, between the two buffer output signal redundant wirings 114 a electrically connected to this one signal line 114, the TFT array substrate 10. In plan view above, they are not formed continuously but separated from each other.

  The contact portion 603b is formed continuously with the second wiring portion 603a on the first wiring portion 601a in such a vacant region defined between the two buffer output signal redundant wirings 114a. The

  Therefore, in this embodiment, it is possible to form the buffer output signal redundant wiring 114a and the second wiring portion 603a in the same layer without significant design changes in the pattern shape and arrangement. Become. In this case, by forming the contact portion 603b continuously with the second wiring portion 603a, the region overlapping the first wiring portion 601a and the TFT array substrate 10 in a plan view It becomes possible to substantially expand the arrangement area of the second wiring portion 603a. Therefore, the wiring capacity of the second wiring portion 603a can be secured larger.

  In addition, in FIG. 7, each of the plurality of contact portions 603 b is formed between two buffer output signal redundant wirings 114 a adjacent to each other (in other words, adjacent to each other 2 in plan view on the TFT array substrate 10). Are formed between the two signal lines 114) and extended in the X direction so as to approach each of the two buffer output signal redundant wirings 114a. In other words, each of the plurality of contact portions 603b is formed so as to fill a vacant region between two adjacent buffer output signal redundant wires 114a in a region overlapping with the first wiring portion 601a. . Therefore, it is possible to substantially further expand the arrangement area of the second wiring portion 603a with respect to the region overlapping the first wiring portion 601a and the TFT array substrate 10 in plan view. Become. Therefore, the wiring capacity of the second wiring portion 603a of the power supply redundant wiring 603 can be ensured to be larger. Further, since stable power is supplied near each of the buffer output signal redundant wirings 114a, the potential of the buffer signal can be further stabilized.

  Therefore, according to the present embodiment as described above, the operation of the buffer unit circuit 500 at each stage of the buffer circuit 101b becomes unstable as the size of the buffer circuit 101b is reduced. It is possible to prevent the waveform of the signal Si) from being significantly disturbed. Therefore, in the sampling circuit 7, the supply timing of the image signal VIDk is prevented from being disturbed in accordance with the sampling circuit drive signal Si, and the occurrence of display defects such as strip-shaped display unevenness on the display screen of the liquid crystal device is prevented. Can do. Therefore, the liquid crystal device can be easily downsized, and high-quality image display can be performed even if the liquid crystal device is downsized.

  Further, when providing the power supply redundant wiring 603, the power supply wiring 601, and further the buffer output signal redundant wiring 114a, each pattern shape and arrangement can be easily formed without requiring a significant design change. Can do. Further, at the time of manufacturing the liquid crystal device, at least a part of each of the power supply redundant wiring 603, the power supply wiring 601 and the buffer output signal redundant wiring 114a, more specifically, the first wiring part 601a, At least part of the second wiring portion 603a and the buffer output signal redundant wiring 114a can be formed together with the data line 6a and the capacitor line 400, and the number of steps in the manufacturing process can be simplified.

  Next, a specific configuration of the buffer unit circuit of the liquid crystal device according to the present embodiment will be described with reference to FIGS. FIG. 9 is an equivalent circuit diagram showing a configuration of the buffer unit circuit, and FIG. 10 is a plan view showing a specific configuration of the buffer unit circuit and the power supply wiring.

  As shown in FIGS. 9 and 10, the buffer unit circuit 500 includes four inverters 511 to 514 connected in parallel in the direction along the scanning line 11a (that is, the arrangement direction of the data lines 6a or the Y direction). Has been. As a result, the driving capability of the buffer unit circuit 500 is enhanced.

  Further, as shown in FIG. 10, each of the inverters 511 to 514 is configured as a complementary TFT in which a P-channel TFT and an N-channel TFT having a channel width direction formed in the Y direction are combined. That is, each of the inverters 511 to 514 has a P between the lead wire 601b drawn from the first wire portion 601a of the power wire 601 and the lead wire 602b drawn from the first wire portion 602a of the power wire 602. A channel type TFT and an N channel type TFT are connected in series.

  More specifically, the inverter 511 includes a P-channel TFT 511a and an N-channel TFT 511b.

  The TFT 511a includes a semiconductor layer formed from the same film as the semiconductor layer 1a (see FIG. 5) in the pixel portion, a gate electrode 511ag formed from the same film as the gate electrode 3a (see FIG. 5) in the pixel portion, and a gate electrode 511ag. A P-type channel region in a semiconductor layer in which a channel is formed by the electric field, and a source region 511as and a drain region 511ad in the semiconductor layer.

  The source region 511as is electrically connected to the lead-out wiring 601b formed from the same film as the data line 6a through the contact hole 8as opened through the first interlayer insulating film 41 and the second interlayer insulating film 42. It is connected. As described above, the extraction wiring 601b is extracted from the first wiring portion 601a of the power supply wiring 601 and supplied with the X-side low potential power supply VSSX.

  The drain region 511ad is electrically connected to the output wiring 550 formed of the same film as the data line 6a through the contact hole 8ad opened through the first interlayer insulating film 41 and the second interlayer insulating film 42. It is connected.

  The TFT 511b includes a semiconductor layer formed from the same film as the semiconductor layer 1a in the pixel portion, a gate electrode 511bg formed from the same film as the gate electrode 3a in the pixel portion, and a semiconductor layer in which a channel is formed by an electric field from the gate electrode 511bg. And the source region 511bs and the drain region 511bd in the semiconductor layer.

  The source region 511bs is electrically connected to the lead wiring 602b formed of the same film as the data line 6a through the contact hole 8bs opened through the first interlayer insulating film 41 and the second interlayer insulating film 42. Has been. As described above, the extraction wiring 602b is extracted from the first wiring portion 602a of the power supply wiring 602 and supplied with the X-side high potential power supply VDDX.

  The drain region 511bd is electrically connected to the output wiring 550 through a contact hole 8bd opened through the first interlayer insulating film 41 and the second interlayer insulating film. Therefore, the drain region 511bd is electrically connected to the drain region 511ad through the output wiring 550.

  The output wiring 550 is electrically connected to the signal line 114 made of the same film as the gate electrode 3a in the pixel portion through a contact hole 808 opened through the first interlayer insulating film 41 and the second interlayer insulating film 42. It is connected to the. Further, the output wiring 550 is a buffer signal redundant wiring 114a made of the same film as the capacitor line 400 in the pixel portion through a contact hole 807 opened in the third interlayer insulating film 43 (see also FIGS. 7 and 8). ) And are electrically connected.

  The inverters 512, 513, and 514 are configured in substantially the same manner as the inverter 511. Note that the gate electrodes of the P-channel TFT and the N-channel TFT constituting the inverter 511 are electrically connected to the signal line 404 to which the transfer signal SRi is supplied from the shift register 101b.

  As shown in FIG. 10, in this embodiment, the signal line 114 is wired on both sides of the contact part 603b (see also FIG. 7) extending from the second wiring part 603a along the Y direction. A plurality of dummy wirings 910 formed of the same film as the gate electrode 3a in the pixel portion (in other words, the same film as the signal line 114) is provided between the wiring portions. The plurality of dummy wirings 910 are wired so as to extend along the direction in which the data lines 6a extend (that is, the Y direction), and are arranged along the arrangement direction of the data lines 6a (that is, the X direction). They are arranged at substantially the same arrangement pitch as the pitch. Therefore, the unevenness that may be generated on the surface of the TFT array substrate 10 in the region where the wiring portions on both sides of the contact portion 603b are formed by the dummy wiring 910, and the surface of the TFT array substrate 10 in the region where the wiring portion is not formed It is possible to reduce the difference from the unevenness that can occur in the case. In other words, the irregularities on the surface of the TFT array substrate 10 can be generated almost or completely uniformly by the dummy wiring 910. Therefore, CMP (Chemical Mechanical Polishing) is applied to the unevenness generated on the surface of the TFT array substrate 10 (more precisely, the surface of the interlayer insulating film below the pixel electrode 9a laminated on the TFT array substrate 10). The flatness of the surface of the TFT array substrate 10 after removing the irregularities can be improved by performing a flattening process such as mechanical polishing. Thereby, for example, due to surface irregularities in the seal region 52a on the TFT array substrate 10, it becomes difficult to hold the TFT array substrate 10 and the counter substrate 20 at a predetermined interval by the seal material 52. Can be avoided.

  Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described. Here, a projector using this liquid crystal device as a light valve will be described. FIG. 11 is a plan view showing a configuration example of the projector.

  As shown in FIG. 11, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.

  Since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic apparatus described with reference to FIG. 11, a mobile personal computer, a mobile phone, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, Examples include a calculator, a word processor, a workstation, a videophone, a POS terminal, a device equipped with a touch panel, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), The present invention can also be applied to an organic EL display, a digital micromirror device (DMD), an electrophoresis apparatus, and the like.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. An electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

It is a top view which shows the structure of the liquid crystal device which concerns on this embodiment. It is sectional drawing in the HH 'line of FIG. It is a block diagram which shows roughly the structure of the arrangement | positioning relationship, electrical connection relationship, etc. of various drive circuits in the peripheral region on a TFT array substrate. It is a circuit diagram which shows equivalent circuits, such as various elements and wiring in a some pixel part. It is sectional drawing which shows the structure of the cross-sectional part of a pixel part. The arrangement relationship of the data line driving circuit, the sampling circuit, and other various signal lines and their electrical connection relationship are schematically shown. It is a top view which shows the structure and arrangement | positioning relationship of the 1st wiring part and the 2nd wiring part, and also the redundant wiring for buffer output signals. It is AA 'sectional drawing of FIG. It is an equivalent circuit diagram showing the configuration of the buffer unit circuit. It is a top view which shows the specific structure of a buffer unit circuit and power supply wiring. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  6a ... data line, 7 ... sampling circuit, 10 ... TFT array substrate, 10a ... pixel area, 11a ... scanning line, 101a ... shift register, 101b ... buffer circuit, 601, 602 ... power supply wiring, 601a ... first wiring part , 603 ... Redundant wiring for power supply, 603a ... Second wiring portion

Claims (8)

On the board
A plurality of pixel portions;
A plurality of scanning lines and a plurality of data lines wired so as to intersect with a pixel region provided with the plurality of pixel portions;
In a peripheral region located around the pixel region, a buffer circuit arranged along the arrangement direction of the plurality of data lines and outputting a sampling signal is output, and an image is output according to the sampling signal output from the buffer circuit An image signal supply circuit for supplying a signal to the plurality of data lines;
A power supply line having a first wiring portion extending along the arrangement direction and supplying a power supply potential to the buffer circuit;
Arranged on a layer higher than the buffer circuit and different from the first wiring portion, and wired so as to at least partially overlap the buffer circuit when viewed in plan on the substrate. An electro-optical device, comprising: a power supply redundant wiring having a second wiring portion and electrically connected to the power supply line. On the substrate,
In the peripheral region, a plurality of signal lines arranged along the arrangement direction and outputting the sampling signal in the image signal supply circuit;
2. The electro-optical device according to claim 1, further comprising: a plurality of redundant wirings for sampling signals that are electrically connected to the plurality of signal lines and arranged along the arrangement direction.   Each of the plurality of redundant wirings for sampling signal is arranged in a layer different from the first wiring part, and at least partially overlaps the first wiring part when viewed in plan on the substrate. The electro-optical device according to claim 2, wherein the electro-optical device is wired as described above.   4. The electro-optical device according to claim 2, wherein the second wiring portion is arranged in the same layer as the plurality of redundant wirings for sampling signal and is wired along the arrangement direction. 5. .   The power supply redundant wiring extends from the second wiring portion along the direction intersecting the arrangement direction corresponding to each stage of the buffer circuit, and is formed so as to overlap with the first wiring portion. The electro-optical device according to claim 4, further comprising a plurality of contact portions.   Each of the plurality of contact portions is formed between two of the plurality of sampling signal redundant wirings adjacent to each other among the plurality of sampling signal redundant wirings when viewed in plan on the substrate. 6. The electro-optical device according to claim 5, wherein the electro-optical device is formed so as to extend in the arrangement direction so as to approach each of the sampling signal redundant wirings. Each of the plurality of pixel portions includes a storage capacitor electrically connected to the data line,
The first wiring part is formed of the same film as the data line, and the second wiring part is disposed on a layer different from the data line and electrically connected to the storage capacitor. The electro-optical device according to claim 1, wherein the electro-optical device is formed of the same film.   An electronic apparatus comprising the electro-optical device according to claim 1.

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