JP4517576B2 - Electro-optic device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electro-optical device having a function of precharging a data line before supplying a data voltage to the data line.
[0002]
[Background]
In recent years, an electro-optical device, for example, an active matrix liquid crystal device using a liquid crystal as an electro-optical element has become widespread. For example, in a thin film transistor (TFT) as a switching element, miniaturization of an active matrix panel and an increase in driving speed have progressed, and the current driving capability of a small size TFT cannot follow the increase in driving speed.
[0003]
Therefore, a method of precharging a data line connected to a pixel immediately before writing a data voltage to the pixel via a switching element such as a TFT is employed (Patent Document 1).
[0004]
Thus, by precharging the data line to the precharge voltage before writing the original data voltage to the pixel, the data line is charged from the precharge voltage to the data voltage even within a short selection time. It can be discharged. Therefore, even if the capability of a switching element such as a TFT is low, an original data voltage can be written to the pixel.
[0005]
Also, in order to reduce the vertical stroke and vertical stripes, which are in a trade-off relationship, in the active matrix TFT panel of the dot sequential driving method, the black level is precharged in the first half of the precharge period, and the gray is displayed in the second half. Some are precharged to a level (Patent Document 2).
[0006]
[Patent Document 1]
JP-A-10-97224 (FIGS. 1 and 2)
[Patent Document 2]
JP 2000-267067 A (FIGS. 1 to 4)
[0007]
[Problems to be solved by the invention]
However, in any of the precharge driving in Patent Documents 1 and 2 described above, since the precharge voltage is set to a fixed DC level, the occurrence of vertical stripes cannot be completely prevented when the image signal is halftone. . This is because, during the selection period, charging / discharging occurs in the data line until the voltage of a certain data line is changed from the fixed precharge voltage to the original data voltage, resulting in voltage fluctuation. A data line that is adjacent to a data line that is being charged / discharged during the selection period and is already set to a data voltage is affected by voltage fluctuations of the data line that is being charged / discharged. This is because these two data lines are capacitively coupled.
[0008]
Further, in Patent Document 2, a switch for switching the precharge voltage to two levels becomes indispensable, which complicates the configuration of the driver and leads to an increase in circuit scale and power consumption.
[0009]
An object of the present invention is to provide an electro-optical device capable of reducing the occurrence of vertical stripes even in the case of halftone display.
[0010]
[Means for Solving the Problems]
The present invention provides two substrates, a plurality of scanning lines provided on one of the two substrates, a plurality of data lines provided on one of the two substrates, and the 2 And an electro-optic material provided between a plurality of substrates, and an electro-optic device having a plurality of electro-optic elements made of the electro-optic material at positions corresponding to a plurality of pixels.
[0011]
The polarity inversion circuit provided in the electro-optical device inverts the polarity of the voltage applied to each of the plurality of electro-optical elements at a predetermined period equal to or longer than the one horizontal scanning period. The scanning line driving circuit selects a plurality of previous scanning lines for each horizontal scanning period. The data line driving circuit sequentially selects one of a plurality of blocks obtained by dividing the plurality of data lines into one or more data lines in each of a plurality of block selection periods obtained by time-dividing one horizontal scanning period. A data voltage based on an image signal is supplied to the data line in the selected block. The minimum unit of the block is one pixel in the horizontal scanning direction, and in this case, dot sequential driving is performed. When k (k ≧ 2) pixels are arranged in one block, the image signal can be preliminarily developed in the k phase.
[0012]
The precharge circuit supplies a precharge voltage to each of the plurality of data lines in at least one precharge period before the plurality of block selection periods in the one horizontal scanning period. The precharge period may be provided before each of a plurality of block selection periods in one horizontal scanning period in addition to one provided in one horizontal scanning period. The precharge voltage generation circuit generates the precharge voltage supplied to the plurality of data lines during the at least one precharge period based on the level of the image signal.
[0013]
As described above, the precharge voltage is not fixed but can be changed according to the level of the image signal. Therefore, the precharge voltage supplied in at least one precharge period before the plurality of block selection periods is originally supplied to the data line in the subsequent block selection period as compared with the conventional fixed precharge voltage. The voltage is closer to the data voltage. For this reason, in the block selection period, almost no charging / discharging occurs until the original data voltage is reached from the precharge voltage, and the voltage fluctuation on the data line is minimized. If the voltage variation of the data line during the block selection period is small, the adverse effect (voltage variation) on other data lines capacitively coupled with the data line is also reduced, thereby reducing the occurrence of vertical stripes.
[0014]
The polarity inversion circuit used in the present invention can invert the polarity of the voltage applied to the electro-optic element for each horizontal scanning period. Alternatively, the polarity inversion circuit may invert the polarity of the voltage applied to the electro-optic element every vertical scanning period.
[0015]
As an example of the precharge voltage generation circuit, a line memory for storing the image signal in the one horizontal scanning period, and a level of the image signal in the one horizontal scanning period based on information stored in the line memory. A precharge voltage generation unit configured to calculate the absolute value of the average value and generate the precharge voltage. Thereby, the average value of the image signal level in one horizontal scanning period becomes the precharge voltage.
[0016]
As another example of the precharge voltage generation circuit, a plurality of line memories that store the image signals in a plurality of horizontal scanning periods, and information stored in the plurality of line memories, based on information stored in the plurality of line scanning periods. A precharge voltage generation unit that calculates an absolute value of an average value of the image signal levels and generates the precharge voltage. Here, when the polarity of the voltage to the electro-optic element is inverted every horizontal scanning period, the precharge voltage generated based on the storage information of the plurality of line memories is also positive every horizontal scanning period, It may be generated as a negative voltage. When the polarity of the voltage to the electro-optic element is inverted every vertical scanning period, it is simple because the precharge voltage having the same polarity may be used during the vertical scanning period.
[0017]
As still another example of the precharge voltage generation circuit, a frame memory that stores the image signal in one vertical scanning period, and a level of the image signal in the one vertical scanning period based on information stored in the frame memory And a precharge voltage generator that generates the precharge voltage by calculating an absolute value of the average value. Here, when the polarity of the voltage to the electro-optic element is inverted every horizontal scanning period, the precharge voltage generated based on the storage information of the frame memory is also positive, negative and negative every horizontal scanning period. May be generated as a voltage. When the polarity of the voltage to the electro-optic element is inverted every vertical scanning period, it is simple because the precharge voltage having the same polarity may be used during the vertical scanning period.
[0018]
As still another example of the precharge voltage generation circuit, based on block memory that stores image signals having the number of pixels corresponding to the number of data lines belonging to one of the plurality of blocks, and information stored in the block memory A precharge voltage generation unit that calculates an absolute value of an average value of the levels of the image signals simultaneously supplied to the data lines belonging to the one block and generates the precharge voltage. In this case, it is preferable that the image signal is preliminarily developed in the k phase. For example, when three-phase development is performed, the number of data lines belonging to one block is three, and an image signal of at least three pixels is stored in the block memory, and an average value of the image signals of the three pixels is calculated. The calculated common precharge voltage is supplied to the three data lines in one block.
[0019]
The precharge voltage generation unit of each example described above can generate the precharge voltage based on an average value of halftone levels within a predetermined range in the stored information. Since vertical stripes are conspicuous at intermediate gray levels, the generation of vertical stripes can be further reduced by obtaining the average of halftone level image signals as the precharge voltage.
[0020]
The precharge voltage generation unit further includes a histogram calculation unit that calculates the occurrence frequency of the image signal level based on the stored information, and can correct the precharge voltage based on the calculation result. By correcting the average value based on not only the average value of the image signal but also the peak gradation value, the occurrence of vertical stripes can be further reduced.
[0021]
The electro-optical device of the present invention includes a plurality of switching elements respectively connected to the plurality of scanning lines and the plurality of data lines, and a plurality of pixel electrodes respectively connected to the plurality of switching elements. And a common electrode facing the plurality of pixel electrodes, and a voltage setting circuit for setting a voltage of the common electrode. This is a so-called active matrix type electro-optical device.
[0022]
In this active matrix type electro-optical device, the voltage applied to the electro-optical element during the at least one precharge period is corrected by changing the common voltage by the voltage setting circuit based on the level of the image signal. can do. As will be described in detail later, there is an optimum common electrode in accordance with the potential applied to the pixel electrode, and therefore the common voltage changes based on the image signal (preferably an average value during one vertical scanning period). By doing so, the precharge voltage can also be optimized. However, the change of the common voltage is performed only when the polarity of the voltage to the electro-optic element is reversed every vertical scanning period.
[0023]
The electro-optical device of the present invention switches the plurality of data / precharge voltage supply lines equal to the number of the data lines in one block, the data voltage and the precharge voltage, and switches the plurality of data lines. And a switch for supplying the data / precharge voltage supply line. Thus, the supply path for the data signal and the precharge voltage can be shared.
[0024]
In this case, the precharge voltage generation unit generates a precharge voltage for each of a plurality of precharge periods respectively provided before the plurality of block selection periods based on the level of the image signal. Become.
[0025]
In the electro-optical device of the present invention, the data line driving circuit sequentially selects blocks along the block selection direction. In this case, the precharge voltage generation circuit can generate first and second precharge voltages as the precharge voltages for each of the plurality of blocks. The first precharge voltage is generated based on the level of the image signal corresponding to the block, and the second precharge voltage is the image signal corresponding to a block one upstream side of the block. Is generated based on The precharge voltage generation circuit supplies the second precharge voltage to a data line located at least at an upstream end in the block selection direction in each of the plurality of blocks, and supplies the second data line to another data line in the block. The first precharge voltage is supplied.
[0026]
In each block, a second precharge voltage close to the data voltage supplied to the block upstream by one is supplied to the data line at the upstream end in the block selection direction that affects the occurrence of vertical stripes. As a result, voltage fluctuations in the data line capacitively coupled thereto can be reduced, and the occurrence of vertical stripes can be reduced. As described above, the first precharge voltage based on the level of the image signal corresponding to the block may be supplied to the other data lines in the block. Note that the second precharge voltage can be a data voltage supplied to a block one upstream side of the block, an average value thereof, or an average value + ΔV thereof. By setting the second precharge voltage to the average value + ΔV, the operation of writing the original data voltage to the pixels of the block becomes easy.
[0027]
When the present invention is applied to a projector, the projector can include a plurality of panels each provided with color filters of different colors and a plurality of precharge voltage generation circuits. In this case, the precharge voltage supplied to each of the plurality of panels is generated by each of the plurality of precharge voltage generation circuits.
[0028]
As another example of the projector, the precharge voltage supplied to one panel having a color filter having the highest visibility among the plurality of panels is generated based on the precharge voltage generation circuit. Also good.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an electro-optical device, such as a liquid crystal display device, according to an embodiment of the present invention will be described with reference to the drawings. Note that the liquid crystal display device to which the present invention is applied is not limited to the active matrix liquid crystal display device described below, and scanning lines (also referred to as common lines) on one of the two substrates and data lines ( A passive matrix liquid crystal display device including a segment line).
[0030]
<First Embodiment>
FIG. 1 is a block diagram of a peripheral circuit connected to a liquid crystal panel such as a TFT (thin film transistor) panel 10, and FIG. 2 is a schematic explanatory diagram of the TFT panel 10.
[0031]
(Active matrix panel)
FIG. 2 shows an example of an active matrix panel, for example, a TFT panel 10 according to the present embodiment. In the pixel portion 12 of the TFT panel 10, M scanning lines such as gate lines 20 and N data lines such as source lines 22 are provided so as to intersect each other.
[0032]
Each of the (M × N) pixels 30 is provided with a switching element, for example, a TFT 32 connected to the gate line 20 and the source line 22, and a total of (M × N) TFTs 32 are provided in the pixel unit 12. ing. The gates of the N TFTs 32 arranged in the horizontal direction are commonly connected to one gate line 20. The sources of the M TFTs 32 arranged in the vertical direction are commonly connected to one source line 22.
[0033]
The drain of the TFT 32 of each pixel 30 is connected to the pixel electrode 34. A common electrode 40 is provided so as to face the pixel electrode 34 of each pixel 30, and an electro-optical material is disposed therebetween, whereby an electro-optical element, for example, a liquid crystal 50 is disposed in each pixel 30. Although not shown, a storage capacitor may be arranged in parallel with the liquid crystal 50 in each pixel 30.
[0034]
Here, in the TFT panel 10 of the present embodiment, the common electrode 40 is provided on one of the two substrates, and the scanning line 20, the signal line 22, the TFT 32, and the pixel electrode 34 are provided on the other side. A liquid crystal 50 is sealed between the substrates. The TFT panel 10 can be a color panel. In this case, a color filter is formed on one of the two substrates.
[0035]
With the above configuration, by controlling the voltage applied to the liquid crystal 50 of each pixel 30, the gradation value of each pixel 30 is determined, and an image can be formed on the pixel portion 12 of the TFT panel 10.
[0036]
The active matrix panel of the present embodiment is not limited to the TFT panel 10 described above, and any switching element and electric element can be used as long as the electro-optic element can be energized from the data line via the switching element selected by the scanning line. The kind of optical element is not ask | required.
[0037]
As shown in FIG. 2, the active matrix panel 10 of the present embodiment includes a scanning line driving circuit 60, a data line driving circuit (block selection circuit) 70, and a precharge circuit 80.
[0038]
The scanning line driving circuit 60 sequentially selects and drives the M scanning lines 20 for each horizontal scanning period based on the vertical timing signals CLY and DY.
[0039]
The data line driving circuit 70 functioning as a block selection circuit applies one to N data lines 22 based on horizontal timing signals CLX and DX and input image signals (VID 1 to 3 in this embodiment). During the horizontal scanning period, data voltages are supplied in a time-sharing manner by K lines (K ≧ 1, in this embodiment, K = 3).
[0040]
Here, K = 1 is a so-called dot sequential driving method. Since K ≧ 2 is set in the present embodiment, as will be described later, a serial image signal on one signal line is transferred onto K image signal lines by the phase expansion circuit 106 (see FIG. 2). Parallel conversion (also referred to as phase expansion) is performed. In this embodiment, since the number of phase expansion K = 3, three image signal lines VD1 to VD3 are provided. In the case of dot sequential driving with K = 1, phase expansion is not necessary, and only one image signal line is provided.
[0041]
The data line driving circuit 70 of the present embodiment includes a sampling circuit 72 that samples data on the three parallel image signal lines V1 to V3, and a shift register 74 that determines the sampling timing based on the horizontal timing signals CLX and DX. And have.
[0042]
The sampling circuit 72 includes a total of N sampling switches, for example, sampling transistors 74A, each connected between any one of the N data lines 22 and any one of the three image signal lines V1 to V3. Have
[0043]
Here, the N data lines 22 are divided into blocks by the number K of phase expansions. In this embodiment where K = 3, one block is formed by the three data lines 22 and the total (N / K) It is divided into blocks. A total (N / K) of output lines S1, S2,... Of the shift register 74 are also provided. The output lines S1, S2,... Of the shift register circuit 74 are commonly connected to the gates of K = 3 sampling transistors 72A belonging to one block and connected to the three image signal lines V1 to V3, respectively. ing.
[0044]
The output lines S1, S2,... Of the shift register circuit 74 are sequentially activated (for example, HIGH) within one horizontal scanning period. Then, K = 3 switching transistors 72A belonging to each block are simultaneously turned on simultaneously along the block selection direction (in this embodiment, the direction from left to right in FIG. 2).
[0045]
The precharge circuit 80 includes N precharge voltage supply lines 82 that supply a precharge voltage NRS, a precharge timing supply line 84 that supplies a precharge timing signal NRG, and N data lines 22 connected to the N data lines 22, respectively. Precharge switch 86. The precharge switch 86 is formed of, for example, a TFT, the precharge timing supply line 84 is connected to the gate, the precharge voltage supply line 82 is connected to the source, and the data line 22 is connected to the drain.
[0046]
(Panel peripheral circuit)
In FIG. 1, an image signal processing unit 100 that processes an image signal (for example, R, G, B) includes a gamma correction unit 102, a polarity inversion circuit 104A, a phase expansion circuit 106, and a D / A (digital-analog) conversion circuit 108. And have. The gamma correction circuit 102 performs correction based on the voltage-transmittance characteristics of the liquid crystal 50. The polarity inversion circuit 104A inverts the polarity of the voltage applied to the liquid crystal 50 in a predetermined cycle, in this embodiment, every horizontal scanning period. As described above, the phase expansion circuit 106 performs parallel conversion (phase expansion) of serial image signals on one signal line on K (in this embodiment, K = 3) image signal lines. A serial image signal on one signal line is parallel-converted (phase development) on K image signal lines (VID1 to VIDK).
[0047]
In the present embodiment, a precharge voltage generation circuit 110 for generating a precharge voltage every horizontal scanning period is provided. The precharge voltage generation circuit 110 includes a 1H memory (line memory) 112, a video average calculation unit 114, a lookup table (LUT) 116, and a D / A converter 118.
[0048]
The 1H memory 112 sequentially stores image signals for one horizontal scanning period. The video average calculation unit 114 calculates an average, for example, an average of image signals within one horizontal scanning period, based on information stored in the 1H memory 112. The lookup table 116 outputs a precharge voltage index value (digital value) according to the calculation result from the video average calculation unit 114. The D / A converter 118 generates a precharge voltage NRS corresponding to the output from the lookup table 118. Note that the look-up table 118 stores the video average value and the precharge voltage index value on a one-to-one basis, and the stored value can be changed based on an external input. Eventually, the lookup table 118 functions as a correction table for correcting the precharge voltage, which has been fixed in the past, based on the video average value.
[0049]
As shown in FIG. 1, the timing circuit 120 generates horizontal / vertical timing signals DX, CLX, DY, and CLY based on the dot clock (DotCLK), horizontal synchronization signal (HSYNC), and vertical synchronization signal (VSYNC). Generate. Further, the precharge timing circuit 130 generates a precharge timing signal NRG based on the signal from the timing circuit 120.
[0050]
(Precharge operation)
FIG. 3 is a timing chart for explaining the precharge operation of the embodiment shown in FIG. As shown in FIG. 3, a horizontal synchronization signal (HSYNC) indicating one horizontal scanning period (1H) is input to the timing circuit 120 of FIG. Based on the signal from the timing circuit 120, the precharge timing circuit 130 is a precharge timing signal NRG that becomes active (HIGH) for a predetermined period at an initial stage of one horizontal scanning period (1H), as shown in FIG. Is generated.
[0051]
Here, it is assumed that the image signal VID before polarity inversion by the polarity inversion circuit 104A in FIG. 1 is as shown in FIG. The image signal VID is stored in the 1H memory 112 for each horizontal scanning period, and the video average calculation unit 114 calculates the video average value for each horizontal scanning period.
[0052]
As a result of calculation by the video average calculation unit 114, the video signal VID shown in FIG. 3 has substantially the same video average value in the first and second horizontal scanning periods (1H). In the third horizontal scanning period, the video average value is lower by Va than the video average values in the first and second horizontal scanning periods. In the fourth horizontal scanning period, the video average value is higher by Vb than the video average value in the first and second horizontal scanning periods.
[0053]
Based on this video average value, a precharge voltage index value (digital value) is output from the lookup table 116 of FIG. Further, based on the precharge voltage index value, the D / A converter 118 generates a precharge voltage NRS, and a precharge voltage NRS corresponding to the video average value is generated for each horizontal scanning period. Here, as shown in FIG. 3, the relationship between the absolute values (voltages before polarity inversion) V1, V2, V3, and V4 of the precharge voltage NRS in each horizontal scanning period is as follows: V1 = V2, V1> V3, V1 < V4.
[0054]
As shown in FIG. 3, the precharge voltage NRS actually obtained is based on the signal from the timing circuit 120. The precharge voltage NRS generated by the D / A converter 118 is alternately changed every horizontal scanning period. Set to plus or minus. Thus, the precharge voltages V1, V2, V3, V4... For each horizontal scanning period are alternately inverted in voltage polarity with respect to the video center (the potential of the common electrode 40), and coincide with 1H inversion driving of the image signal. Become.
[0055]
Here, in the precharge period (period in which the precharge timing signal NRG is HIGH) for each horizontal scanning period shown in FIG. 3, the output lines S1, S2,. _{N / K} Is set before the block selection period in which the potential becomes high.
[0056]
As a result, each data signal line 20 has a precharge voltage (within one horizontal scanning period) substantially equal to the data voltage applied during the block selection period in which the potentials of the signal lines S1, S2,. Is averaged) before the block selection period. Therefore, before the data voltage is supplied to the data signal line 20 in each block selection period, each data signal line has a precharge voltage that is substantially equal to the data voltage in advance, so that the data line 20 within the selection period. The change in potential (that is, change in voltage across the liquid crystal) is extremely small. For this reason, the adverse effect on the liquid crystal 50 connected to the data line in the middle of the data voltage supply and the other liquid crystal 50 adjacent in the horizontal direction (the data voltage has already been determined) is reduced. This is the principle that vertical stripes can be reduced in this embodiment.
[0057]
In the prior art, the precharge voltage is set to (1) a normally white mode with a black level and (2) a halftone level. However, in all cases, the precharge voltage was a fixed level regardless of the change in the signal level. Therefore, the potential change of the data line 20 within the selection period (that is, the voltage change across the liquid crystal) may be larger than that of the above-described embodiment, and vertical stripes still occur when the potential change is large.
[0058]
In the first embodiment, the video average value is calculated for each horizontal scanning period. However, the present invention is not limited to this, and the video average value is obtained once for each period longer than one horizontal scanning period. May be. For example, a plurality of line memories may be provided, and the video average value may be obtained once every a plurality of horizontal scanning periods. In this case, in a plurality of horizontal scanning periods, the absolute value of one precharge voltage calculated based on the gradation values of the pixels in the plurality of horizontal scanning periods is repeatedly used as the precharge voltage of each block. Alternatively, a frame memory may be provided instead of one or a plurality of line memories, and a video average value for one frame may be obtained. In this case, in one vertical scanning period, the absolute value of one precharge voltage calculated based on the gradation value of the pixel in the one vertical scanning period is repeatedly used as the precharge voltage of each block. However, when the video average value is obtained for each of a plurality of horizontal scanning periods or one vertical scanning period, the precharge voltage set based on the absolute value of the video average value has a polarity with respect to the video center of one horizontal scanning period. Inverted alternately every scanning period.
[0059]
<Second Embodiment>
FIG. 4 shows a second embodiment of the present invention in which some of the circuits in FIG. 1 are modified. In the second embodiment, instead of the IH inversion driving in which the polarity is inverted every horizontal scanning period of the first embodiment, the IV inversion that reverses the polarity every vertical period is adopted.
[0060]
The image signal processing unit 101 shown in FIG. 4 is different from the image signal processing unit 100 of FIG. 1 only in that the polarity inversion circuit 104B is driven by 1V inversion. In FIG. 4, the precharge voltage generation circuit 111 further includes a frame memory 113 instead of the line memory 112 of the precharge voltage generation circuit 110 in FIG. 1. The video average calculation unit 114 calculates the average value of the image signals in one frame.
[0061]
In FIG. 4, a common voltage generation unit 140 that generates the common voltage LCCOM to the common electrode 40 shown in FIG. 2 is further added. In the first embodiment, the common voltage LCCOM is a constant voltage, but in the present embodiment, the common voltage LDCOM is variable based on the video average value. For this purpose, the common voltage generation unit 140 selects a common voltage index value based on the output from the video average calculation unit 114, and generates a common voltage LDCOM based on the common voltage index value. And a converter 144.
[0062]
FIG. 5 is a timing chart showing the precharge operation of the second embodiment shown in FIG. One of the differences between FIG. 5 and FIG. 3 is that the precharge voltage NRS is set not for each horizontal scanning period but for each vertical scanning period. That is, the video average values V1 to V4 in FIG. 5 are generated by the video average calculation unit 114 based on the storage information of the frame memory 113 for each vertical period. Further, the precharge voltage NRS has the voltage polarity with respect to the video center LDCOM inverted every vertical scanning period.
[0063]
Another difference between FIG. 5 and FIG. 3 is that the precharge timing signal NRG becomes HIGH once in one vertical scanning period, and this period becomes the precharge period, and one horizontal scanning period as shown in FIG. One precharge period is set for each time. In the second embodiment, the precharge voltage NRS is supplied to all the data lines 20 through the precharge switch 86 of FIG. 1 within the precharge period set once in the initial stage of one vertical scanning period.
[0064]
As described above, in the second embodiment, instead of the fixed precharge voltage, the video average value obtained for each vertical scanning period is used as the precharge voltage. Can be reduced.
[0065]
In the second embodiment in which the polarity is inverted every vertical scanning period, one or more 1H memories 112 shown in FIG. 1 may be provided instead of the frame memory 113 shown in FIG. In this case, the precharge voltage is obtained based on the video average calculated every horizontal scanning period or every plural horizontal scanning periods, and the precharge voltage becomes a value closer to the original data voltage. At this time, it is not necessary to reverse the polarity of the precharge voltage with respect to the video center every horizontal scanning period as in the first embodiment, and the same polarity may be used in one vertical scanning period.
[0066]
Next, the reason why the video center voltage LDCOM is varied based on the video average value in the present embodiment is as follows. First, when positive and negative data potentials having the same absolute value are applied to the liquid crystal 50, the effective potentials actually applied to the liquid crystal differ between positive and negative, and the amount of difference depends on the magnitude of the absolute value of the data potential. Because it is different. Therefore, when positive and negative data voltages having the same absolute value are applied to the liquid crystal, the intermediate potential between the positive and negative potentials differs depending on the absolute value of the data voltage and a deviation from the preset common voltage LDCOM occurs. One of the reasons why a potential different from the actual data potential is applied to the liquid crystal 50 is that when the TFT 32 provided in the pixel 30 is turned off, it is stored in the pixel 40 due to its gate-source capacitance Cgs component. This is because the generated charge leaks. This is because the TFT 32 has different current drive capability (write capability) depending on the positive and negative voltages of the source line 22, and in the case of an N-type TFT, the positive voltage write capability is lower than the negative voltage write capability. The positive / negative write capability difference differs depending on the absolute value of the data voltage.
[0067]
Therefore, the potential of the common electrode 40 is also variable for each vertical scanning period only in IV inversion driving for inverting the voltage applied to the liquid crystal every vertical period. This variable amount is obtained by the average level of the image signal within one vertical scanning period. In this embodiment, based on the calculation result from the video average calculation unit 114, the common voltage generation unit 140 including the lookup table 142 and the A / D converter 144 generates the common voltage LDCOM for each vertical scanning period. . Thus, when a positive and negative data voltage having the same absolute value is applied to the liquid crystal, the common voltage LDCOM can always be set to a value close to the intermediate potential of the positive and negative voltages, and the positive and negative voltages of the same gradation can be made equal. Can be applied to the liquid crystal 50.
[0068]
<Third Embodiment>
FIG. 6 shows a modification of the precharge voltage generation circuits 110 and 111 of FIG. 1 or FIG. Therefore, in FIG. 6, either the image signal processing unit 100 shown in FIG. 1 or the image signal processing unit 101 shown in FIG. 4 is arranged. A precharge voltage generation circuit 200 shown in FIG. 6 includes a memory 202 configured by either the 1H memory 112 of FIG. 1 or the frame memory 113 of FIG. A precharge voltage generation circuit 200 shown in FIG. 6 generates a precharge voltage based on an average value of a predetermined range of halftone levels in the stored information of the memory 202. For this purpose, the precharge voltage generation circuit 200 can include a video average calculation unit 204, a histogram calculation unit 206, a video average correction unit 208, and a lookup table 210.
[0069]
The vertical stripes described above are inconspicuous if the signal level is black or white, but are conspicuous if the signal level is a halftone level. Therefore, in the third embodiment, the precharge voltage is generated based on the signal level in the halftone area. It is.
[0070]
The video average calculation unit 204 and the lookup table 210 in FIG. 6 have the same functions as the video average calculation unit 114 and the lookup table 116 shown in FIGS. 1 and 4, respectively. That is, the video average calculation unit 204 calculates the video average value a shown in FIG. 7A from the image signal stored in the memory 202 within one horizontal scanning period or one vertical scanning period. The histogram calculation unit 204 calculates the occurrence frequency of the image signal level based on the information stored in the memory 202, and calculates, for example, a histogram as shown in FIG. In FIG. 7B, the frequency of occurrence of the video signal level on the horizontal axis is shown on the vertical axis.
[0071]
FIG. 7C shows a state in which the video average value a (see FIG. 7A) obtained by the video average calculation unit 204 is corrected based on halftone region data within a predetermined range. That is, in FIG. 7C, since the peak of the intermediate region in the predetermined range is at a higher gradation level (for example, a white level), the average value b is corrected to be higher than the average value a. This correction may be performed by the video average correction unit 208 to which the video average a from the video average calculation unit 204 and information from the histogram calculation unit 206 are input, or is performed by the video average calculation unit 204 as described later. May be. Based on the information from the video average correction unit 208, the precharge voltage NRS is determined by the lookup table 210 and the D / A conversion circuit 118.
[0072]
The corrected video average value b may be obtained by calculating the video average only in a predetermined halftone area. In this case, the video average calculation unit 204 reads only data in a predetermined halftone area from the memory 202 and calculates an average value. Therefore, it is not always necessary to use the histogram calculation unit 206 and the video average correction unit 208 in obtaining the average value b of the signal level in the halftone area.
[0073]
FIG. 7D shows another method for correcting the video average value a by using the histogram calculation unit 206 as an essential component. In FIG. 7D, for example, when the black level is set to 0% and the white level is set to 100%, a halftone region of m% to n% (0 <m, n <100) is further represented in accordance with the signal level. For example, it is divided into a low region, a middle region, and a high region.
[0074]
In FIG. 7D, the peak value is higher than the video average value Av (equal to the above-described average value b) in the halftone region of m% to n%. Thus, when there is a bias in the frequency of occurrence of the histogram, it is preferable to obtain an optimum value by weighting or the like between the most frequent peak gradation and the level average Av.
[0075]
The video average correction unit 208 in FIG. 6 calculates, for example, corrected average value = (peak gradation value + video average value) / 2 in order to obtain such an optimum value. For example, if the video average value Av = 60% and the peak gradation = 70%, the average value after correction = (60% + 70%) / 2 = 65%. In addition, the average value after correction = (peak gradation value + coefficient α × video average value) / 2 may be used. The coefficient K can be set to α> 1 if the video average value Av is emphasized, and α <1 if the peak gradation value is emphasized. Such a coefficient α may be multiplied by the peak gradation value. Alternatively, the video average value may be multiplied by a coefficient α1, and the peak gradation value may be multiplied by a coefficient α2 to perform weighting.
[0076]
<Fourth Embodiment>
In the fourth embodiment of the present invention, a precharge voltage that is simultaneously supplied to the same number of pixels as the number K of phase expansion is generated based on the signal level of K pixels. In the present embodiment, for example, the number of phase expansion K is 3, so that three data signal supply lines 301, 302, and 303 are provided as shown in FIG. The three data signal supply lines 301 to 303 are connected to the data line 22 (not shown in FIG. 8) of the pixel unit 12 through a sampling switch 72A controlled by signals SS1, SS2,. Has been.
[0077]
At the ends of the three data signal lines 301 to 303, switches 311, 312, and 313 for selecting one of the image signals VID 1 to 3 and the precharge voltage NRS are provided. These switches 311 to 313 are switched by a switch switching signal VNG. The drive circuit 310 including the switches 311 to 313 may be an external circuit of the TFT panel 10 or may be disposed in the TFT panel 10.
[0078]
FIG. 9 is a timing chart showing the operation timing of the apparatus shown in FIG. As shown in FIG. 9, within one horizontal scanning period (1H) in which the horizontal synchronization signal HSYNC is HIGH, the signals SS1 and SS2 from the shift register 300 are sequentially HIGH and the number of phase expansions in the horizontal scanning direction. The blocks are sequentially selected for each block composed of the same number of three pixels as K = 3. Here, the signal SS1 for selecting the first block becomes HIGH, for example, in two periods, the first is a precharge period, and the next is a data charge period, that is, a selection period. The other signals SS2 and the subsequent signals are the same as the signals SS1 except that the timing of going to HIGH is sequentially shifted. Thus, the precharge period is provided before the selection period of each block. The timing of the switching signal VNG for switching the switches 311 to 313 to the video signal VID1 to VID3 side or the precharge voltage NRS side is determined in accordance with the signals SS1 and SS2.
[0079]
On the other hand, the precharge voltage NRS is determined for each block. For this purpose, the same circuit as the precharge voltage generation circuit 110 shown in FIG. 1 can be used. However, in FIG. 1, a 1H memory that stores data for one horizontal scanning period (1H) is essential. However, the present invention is not limited to this. It ’s fine. The video average calculation unit 114 can generate a precharge voltage for each block by calculating an average value of the signal level for each K pixel.
[0080]
The configuration shown in FIG. 8 is not necessarily limited to that used in the fourth embodiment, and can also be used in the first to third embodiments. In this case, the precharge circuit 80 shown in FIG. 2 is unnecessary.
[0081]
<Fifth Embodiment>
The fifth embodiment of the present invention is, for example, a combination of the first embodiment of the present invention and the technique of Japanese Patent Application Laid-Open No. 2000-212476. 10 is different from the circuit of FIG. 2 used in the first embodiment in that a precharge circuit 81 is provided instead of the precharge circuit 80 of FIG. The precharge circuit 81 of FIG. 10 has a total of two first and second precharge voltage supplies, whereas the precharge circuit 80 of FIG. 2 has only one precharge voltage supply line 82. It has lines 82A and 82B. The first precharge voltage supply line 82A is supplied with the first precharge voltage NRS1, which is the same voltage as the precharge voltage NRS used in the first embodiment. For example, when the first precharge voltage NRS1 is supplied to the block 2, the first precharge voltage NRS1 is generated based on the level of the image signal corresponding to the block 2. A second precharge voltage NRS2 is supplied to the second precharge voltage supply line. For example, when the second precharge voltage NRS2 is supplied to the block 2, the second precharge voltage NRS2 is generated based on the level of the image signal corresponding to the block 1 on the upstream side of the block 2. At this time, the second precharge voltage is a data voltage supplied to the data line 22 (3) of the block 1, an average value of a plurality of data voltages supplied to the block 1, or an average value + ΔV, or the like. be able to. Note that since there is no block located upstream of the block 1, only the block 1 needs to have the first precharge voltage NRS1 = the second precharge voltage NRS2.
[0082]
As shown in FIG. 10, in each block, the second precharge voltage supply line 82B is one of the three precharge switches 86A to 86C connected to the three data signal lines 22 in one block. Is connected to one precharge switch 86A located at the upstream end in the block selection direction A shown in FIG. The first precharge voltage supply line 82A is connected to the remaining two precharge switches 86B and 86C of each block.
[0083]
Here, for example, the block 1 is first set to precharge voltage → data voltage, and then the block 2 is set to precharge voltage → data voltage. At this time, if the precharge voltage of the data line 22 (4) of the block 2 is different from the data voltage being applied to the data line 22 (3) of the block 1, vertical stripes are generated. This is because the data voltage of the data line 22 (3) of the block 1 is shifted due to the influence of the precharge voltage of the data line 22 (4) of the block 2.
[0084]
Therefore, in the present embodiment, the second precharge voltage NRS2 is supplied to the data line at the left end (upstream end in the block selection direction A) that affects the occurrence of vertical stripes among the blocks after the block 2. ing. For example, the second precharge voltage NRS2 supplied to the leftmost data line 22 (4) of the block 2 is generated based on the level of the image signal corresponding to the block 1. Therefore, the second precharge voltage NRS2 to the data line 22 (4) of the block 2 is a voltage close to the data voltage of the data line 22 (3) of the block 1. For this reason, the shift of the data voltage of the data line 22 (3) of the block 1 is suppressed, and the occurrence of the vertical stripes described above can be reduced.
[0085]
FIG. 11 shows a case where the block selection direction is set to the B direction opposite to the A direction shown in FIG. 10 in the same apparatus as FIG. In this case, unlike FIG. 10, the second precharge voltage NRS2 is supplied to the first precharge voltage supply line 82A, and the first precharge voltage NRS1 is supplied to the second precharge voltage supply line 82B. . Thus, the supply destinations of the first and second precharge voltages NRS1 and NRS2 can be switched by the switch provided outside the TFT panel 10 in accordance with the block selection direction.
[0086]
Also in FIG. 11, for example, in the block 1, the second precharge voltage NRS2 supplied to the data line 22 (3) at the right end (upstream end in the block selection direction B) that affects the occurrence of vertical stripes is Since it is close to the data voltage of the data line 22 (4), the occurrence of vertical stripes can be reduced in the same manner. In FIG. 11, for example, in block 1, the second precharge voltage NRS2 is supplied only to the two upstream data lines 22 (2) and 22 (3), and the remaining data lines 22 (1) are supplied to the remaining data lines 22 (1). Is supplied with the first precharge voltage NRS1.
[0087]
The fifth embodiment described above can be applied to the second to fourth embodiments in addition to the first embodiment.
[0088]
<Sixth Embodiment>
The sixth embodiment of the present invention relates to a color projector. In FIG. 12, a color projector 400A includes a liquid crystal panel 401 having a red (R) filter, a liquid crystal panel 402 having a green (G) filter, and a liquid crystal panel 403 having a blue (B) filter. The color projector 400A uses these liquid crystal panels 401 to 403 as light valves and displays their projection images on a screen in an overlapping manner.
[0089]
Here, for example, precharge voltage generation circuits 110R, 110G, and 110B having the same functions as the precharge voltage generation circuit 110 shown in FIG. 1 are connected to the liquid crystal panels 401 to 403, respectively. The precharge voltage generation circuits 110R, 110G, and 110B generate precharge voltages based on the red signal R, the green signal G, and the blue signal B, respectively.
[0090]
FIG. 13 shows another projector 400B. In FIG. 13, only the liquid crystal panel 402 having the color filter having the highest visibility among the liquid crystal panels 401 to 403, that is, the green (G) filter, has the same function as the precharge voltage generation circuit 110 shown in FIG. A precharge voltage generation circuit 110G is connected. A precharge power source 410 is connected to the other liquid crystal panels 401 and 403, and for example, a positive positive precharge voltage and a negative precharge voltage are generated in a positive polarity and a negative polarity, respectively, as in the conventional case. Thus, the effect of reducing the vertical stripes can be expected only by reducing the occurrence of vertical stripes in the green image having the highest visibility.
[0091]
The present invention is not limited to the various embodiments described above, and various modifications can be made within the scope of the gist of the present invention.
[Brief description of the drawings]
FIG. 1 is a block diagram of a liquid crystal display device according to a first embodiment of the present invention.
2 is a schematic explanatory diagram of an active matrix panel used in the liquid crystal display device of FIG.
3 is a timing chart for explaining a precharge operation in the liquid crystal display device of FIG. 1; FIG.
FIG. 4 is a block diagram of a liquid crystal display device according to a second embodiment of the present invention.
5 is a timing chart for explaining a precharge operation in the liquid crystal display device of FIG. 4;
FIG. 6 is a block diagram showing a precharge voltage generation circuit of a liquid crystal display device according to a third embodiment of the present invention.
7A to 7D are schematic explanatory diagrams for explaining the operation of the precharge voltage generation circuit shown in FIG.
FIG. 8 is a circuit diagram showing a part of a liquid crystal display device according to a fourth embodiment of the present invention.
9 is a timing chart for explaining the operation of the apparatus shown in FIG.
FIG. 10 is a circuit diagram showing a part of a liquid crystal display device according to a fifth embodiment of the present invention.
11 is a circuit diagram showing a state in which the block selection direction is set in the reverse direction in the apparatus of FIG.
FIG. 12 is a schematic explanatory diagram of a sixth embodiment in which the present invention is applied to a projector.
FIG. 13 is a schematic explanatory view showing a projector according to an embodiment different from FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Active matrix panel, 12 pixel part, 20 scanning line (gate line), 22 data line (source line), 30 pixel, 32 drain, 34 pixel electrode, 40 common electrode, 50 electro-optic element (liquid crystal), 60 scanning line Drive circuit, 70 data line drive circuit, 72 phase expansion circuit, 74 polarity inversion circuit (amplification / inversion circuit), 70 block selection circuit, 72 sampling circuit, 72A sampling switch, 74 shift register, 80 precharge circuit, 100, 101 Image signal processing unit, 102 gamma correction unit, 104A, 104B polarity inversion unit, 106 phase expansion circuit, 108 D / A converter, 110, 200 precharge voltage generation circuit, 112 1H memory, 113 frame memory, 118 D / A Conversion circuit, 120 timing circuit, 130 precharge timing Circuit, 140 common voltage generation unit, 202 memory, 114, 204 video average calculation unit, 206 histogram calculation unit, 208 video average correction unit, 116, 210 lookup table, 300 shift register, 301-303 data signal / precharge Voltage supply line, 310 drive circuit, 311 to 313 switch, 400A, 400B projector, 401 to 403 liquid crystal panel (light valve), 410 precharge power supply

Claims (7)

Two substrates, a plurality of scanning lines provided on one of the two substrates, a plurality of data lines provided on one of the two substrates, and the space between the two substrates And an electro-optical device having a plurality of electro-optical elements made of the electro-optical material at positions corresponding to a plurality of pixels.
A polarity inversion circuit that inverts the polarity of the voltage applied to each of the plurality of electro-optic elements at a predetermined cycle of the one horizontal scanning period or more;
A scanning line driving circuit for selecting the plurality of scanning lines for each horizontal scanning period;
In each of a plurality of block selection periods obtained by time-dividing one horizontal scanning period, one of a plurality of blocks obtained by dividing the plurality of data lines into two or more data lines is sequentially selected, and within the selected block A data line driving circuit for supplying a data voltage based on an image signal to the data line;
A precharge circuit for supplying a precharge voltage to each data line in the selected block during a precharge period set before each of the plurality of block selection periods in the one horizontal scanning period;
A precharge voltage generation circuit for generating the precharge voltage supplied to the data line in the selected block based on the level of the image signal;
The data line driving circuit sequentially selects blocks along a block selection direction that can be switched between forward and reverse directions .
The precharge voltage generation circuit generates first and second precharge voltages as the precharge voltages for each of the plurality of blocks, and the first precharge voltage corresponds to the image corresponding to the block. The second precharge voltage is generated based on the image signal corresponding to the block one upstream side of the block, and the block selection direction is a positive direction. In the reverse direction, the first and second precharge voltages are switched and supplied to the data lines in the selected block, and are always upstream ends in the block selection direction in each of the plurality of blocks. Supplying the second precharge voltage to the data line located on the side, and supplying the first precharge voltage to the other data lines in the block. Electro-optical apparatus according to symptoms. In claim 1,
The electro-optical device, wherein the polarity inversion circuit inverts the polarity of a voltage applied to the electro-optical element every horizontal scanning period. In claim 1,
The electro-optical device, wherein the polarity inversion circuit inverts the polarity of a voltage applied to the electro-optical element every vertical scanning period. In claim 3,
A plurality of switching elements respectively connected to each of the plurality of scanning lines and each of the plurality of data lines; a plurality of pixel electrodes respectively connected to each of the plurality of switching elements; and An opposing common electrode; and a voltage setting circuit for setting a voltage of the common electrode;
An electro-optical device that corrects a voltage applied to the electro-optical element during the at least one precharge period by changing the common voltage by the voltage setting circuit based on a level of the image signal. . In any one of Claims 1 thru | or 4,
A plurality of data / precharge voltage supply lines equal in number to the number of the data lines in one block;
A switch that switches between the data voltage and the precharge voltage and supplies the plurality of data / precharge voltage supply lines;
Have
The precharge voltage generation unit generates a precharge voltage for each of a plurality of precharge periods provided before the plurality of block selection periods based on the level of the image signal. Electro-optic device. In any one of Claims 1 thru | or 5,
A plurality of panels each having a color filter of a different color; and a plurality of precharge voltage generation circuits, wherein the precharge voltage supplied to each of the plurality of panels is converted into the plurality of precharge voltage generations. An electro-optical device generated by each of the circuits. In any one of Claims 1 thru | or 6.
A plurality of panels each having a color filter of a different color, and the precharge voltage supplied to one panel having a color filter having the highest visual sensitivity among the plurality of panels, An electro-optical device, which is generated based on a charge voltage generation circuit.

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