JPH11327486A - Driving circuit for matrix type display panel and evaluating method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To develop and design a driving circuit optimum to a display panel efficiently, easily and at low cost by deciding the output resistance of the driving circuit so as to optimally drive an equivalent circuit consisting of a resistance and a capacitance and moreover a wiring capacitance. SOLUTION: A signal line is regarded as the serial circuit of a resistance RL=2α.X.rs/π and a capacitance CL=2β.X.cs/π by defining α, β as constants, a wiring resistance per one pixel of the signal line as rs, and a capacitance per one pixel of the signal line as cs. Then, when the wiring capacitance between the driving terminal of the signal line and the driving output terminal of a signal line driving circuit 11 is defined as Cd, the wiring capacitance Cd is connected in parallel with the serial circuit of the resistance RL and the capacitance CL. The terminal of the side of the resistance RL of the serial circuit is connected to the driving output terminal of the circuit 11 and the terminal of the side of the capacitance CL of the serial circuit is connected to a reference potential. A serial and parallel circuit consisting of the Cd, the RL and the CL is dummy load and the output resistance of the driving circuit 11 is set so as to be able to drive the dummy load optimully.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a matrix type display device such as a liquid crystal display device, a plasma display device, and an EL display device, which is useful as a display of information equipment, and particularly has an optimum output resistance for driving. The present invention relates to a driving circuit and an evaluation method thereof.

[0002]

2. Description of the Related Art In a matrix type display device, a plurality of signal lines and a plurality of scanning lines are arranged in a matrix, and a matrix type liquid crystal panel having pixels at intersections thereof is provided with a signal line driving circuit for driving the signal lines. And a scanning line driving circuit for driving the scanning lines are indispensable basic components. In the following description, the signal line and the scanning line driving circuit are collectively referred to as a driving circuit.

In order to realize a high-quality matrix type display device, a driving circuit for optimally driving the matrix type display panel is required. That is, in order for the output circuit constituting the drive circuit to supply the drive voltage to the signal line or the scan line and drive the signal line or the scan line, it is necessary to set the output resistance of the output circuit to an optimum value. In the following description, the optimal design of a driving circuit that optimally drives a signal line or a scanning line means that the output resistance of the driving circuit is set to an optimal value. Except for special cases, a matrix-type display panel is simply called a display panel, and a matrix-type display device is simply called a display device.

A method of designing a driving circuit capable of optimal driving by expressing signal lines or scanning lines by an equivalent circuit and applying driving conditions of a matrix type display panel is considered. A case where a signal line or a scanning line is set as an actual load of a driving circuit, a load expressed by an equivalent circuit is set as a dummy load, and a case where the signal line or the scanning line is driven is referred to as an actual driving. Therefore, in designing a drive circuit capable of optimally driving a display panel, appropriate dummy loads and drive conditions must be determined.

FIGS. 15A and 15B show a conventional signal line and scanning line dummy load circuit. The signal line is
As shown on the left side of (a), the signal line is represented by a ladder circuit in which the wiring resistance per pixel is rs and the capacitance is cs. This circuit, as shown on the right side of FIG.
It can be approximated by a series circuit of the resistor RL2 and the capacitance CL2. However, when the number of scanning lines is X, the resistance RL2 and the capacitance CL2 are approximated by the following equation (Equation 1).

[0006]

RL2 = X · rs CL2 = X · cs Similarly, as shown on the right side of FIG. 15B, the scanning line has a wiring resistance per pixel of the scanning line of r and a capacitance of c. 15B, and is approximated by a series circuit of a resistor RL2 and a capacitance CL2 shown on the right side of FIG. 15B. In this case, if the number of signal lines is Y, the resistance RL2 and the capacitance CL2 are approximated by the following equation (Equation 2).

[0007]

RL2 = Y · r CL2 = Y · c The above values can be easily obtained from the design values of the display panel. As described above, the signal line and the scanning line are defined by the resistance RL2 and the capacitance C obtained by the equations (1) and (2).
The drive circuit is designed to approximate the dummy load represented by the RC series circuit composed of L2 and drive the dummy load optimally.

FIG. 16 shows an equivalent circuit of an output circuit of a drive circuit and a dummy load. The plurality of switches sw and the output resistance Ro represent an output circuit of the drive circuit. FIG. 16 shows a quaternary output drive circuit. TP represents a test point. If the output resistance Ro is determined so that a predetermined voltage is obtained at TP of the equivalent circuit in FIG. 16, a drive circuit that optimally drives the display panel can be designed.

FIG. 14 shows a conventional evaluation method of the drive circuit designed as described above. In the figure, reference numeral 91 denotes a drive circuit, o1 to on are n drive output terminals, Vo is a drive power input terminal, Vdd is a signal power input terminal, Ck is a clock input terminal, Data is a data input terminal, and Dref is a data input terminal. Is a reference voltage input terminal. The above-described series circuit of RL2 and CL2 is connected as a load to each of the drive output terminals o1 to on. However, FIG. 14 shows only a load connected to one drive output terminal o1 for simplicity.
One end of RL2 is connected to the drive output terminal (for example, o1), and one end of CL2 is grounded. A test point TP is provided at a connection point between RL2 and CL2.

In FIG. 14, reference numeral 92 denotes a power supply circuit.
The drive power supply input terminal Vo and the ground terminal GN of the drive circuit 91
A power supply voltage for driving is supplied between D and D. Reference numeral 93 denotes a control circuit which supplies a control signal such as a signal power supply voltage and a clock and data to the drive circuit 91 and controls the power supply circuit 92.

With the above configuration, the driving circuit 91 is operated by the driving power supply voltage supplied by the power supply circuit 92, the signal power supply voltage supplied by the control circuit 93, and the control signals such as clock and data. And a dummy load consisting of CL2. And the power supply current of the drive circuit,
The electrical characteristics such as the operating power supply voltage range, the timing margin of the control signal, and the delay time of the drive voltage at the drive output terminal are obtained, and it is evaluated whether the drive circuit 91 is optimally designed.

[0012]

However, in the above-described conventional driving circuit and the evaluation method thereof, the driving circuit is determined based on the dummy load obtained from the equations (1) and (2). Even when optimally designed and required and sufficient performance is obtained in the evaluation method of the configuration shown in FIG.
When the actual display panel was driven, the result sometimes did not match the evaluation result by the evaluation method of the configuration shown in FIG. This may be due to the improper dummy load. In this case, it is necessary to redesign the drive circuit or select another drive circuit so as to optimally drive the display panel. As a result, the development cost is increased, or the cost is increased by using an over-performance drive circuit.

In view of the above-mentioned conventional problems, the present invention provides a driving circuit for a display panel which can be optimally driven at a low cost, and a display in which a performance evaluation result using a dummy load matches an actual driving evaluation result. It is an object to provide a method for evaluating a panel drive circuit.

[0014]

A first configuration of a drive circuit for a matrix type display panel according to the present invention is that α and β are constants, a wiring resistance per pixel of a signal line is rs, and a signal resistance per pixel of a signal line is rs. The capacitance is cs, and the signal line is a resistor RL = 2
α · X · rs / π and capacitance CL = 2β · X · cs / π
When a wiring capacitance between the driving end of the signal line and the driving output terminal of the signal line driving circuit is represented by Cd,
The wiring capacitance Cd is connected in parallel to a series circuit of the resistor RL and the capacitance CL, and the resistor RL side terminal of the series circuit is connected to the drive output terminal of the signal line driving circuit, and the capacitance C of the series circuit is connected.
The L-side terminal is connected to a reference potential or a ground potential, and has an output resistance such that the voltage across the capacitance CL becomes a predetermined drive voltage when the signal line drive circuit operates under predetermined conditions. And

In a second configuration of the driving circuit for a matrix type display panel according to the present invention, α and β are constants, the wiring resistance per pixel of the scanning line is r, and the capacitance per pixel of the scanning line is r. c, and the scanning line has a resistance RL = 2α · Y · r /
Considering a series circuit of π and the capacitance CL = 2β · Y · c / π, and assuming that the wiring capacitance between the driving end of the scanning line and the driving output terminal of the scanning line driving circuit is Cd, the wiring capacitance Cd Are connected in parallel to a series circuit of the resistor RL and the capacitance CL, the resistor RL side terminal of the series circuit is connected to the drive output terminal of the scanning line driving circuit, and the capacitance CL side terminal of the series circuit is connected to the reference potential or It is connected to a ground potential and has an output resistance such that the voltage across the capacitance CL becomes a predetermined drive voltage when the scanning line drive circuit is operated under predetermined conditions.

According to the above configuration, a drive circuit that can optimally drive a matrix type display panel can be designed easily and at low cost. In the first configuration of the method for evaluating a matrix-type display panel driving circuit according to the present invention, α and β are constants, the wiring resistance per signal line pixel is rs, and the capacitance per signal line pixel is cs. , The signal line is regarded as a series circuit of a resistor RL = 2α × X · rs / π and a capacitance CL = 2β × X · cs / π, and the drive end of the signal line and the drive output terminal of the signal line drive circuit are connected. The wiring capacitance between the capacitors is defined as Cd, and a series connection of a resistor having a resistance value RL and a capacitor having a capacitance CL and a capacitor having a capacitance Cd connected in parallel is used as a dummy load of the signal line driving circuit, and the resistance of the series circuit is reduced. The terminal is connected to the drive output terminal of the signal line drive circuit, the capacitor side terminal of the series circuit is connected to the reference potential or the ground potential, and the signal line drive circuit is operated under predetermined conditions for evaluation. .

In a second configuration of the method for evaluating a matrix-type display panel drive circuit according to the present invention, α and β are constants, the wiring resistance per pixel of a scanning line is r, and
The capacitance per pixel is c, and the scanning line is resistance RL = 2α ·
Considering a series circuit of Y · r / π and capacitance CL = 2β · Y · c / π, the wiring capacitance between the driving end of the scanning line and the driving output terminal of the scanning line driving circuit is Cd, and the resistance is Cd. A series connection of a resistor having a value RL and a capacitor having a capacitance CL and a capacitor having a capacitance Cd connected in parallel is used as a dummy load of the scanning line driving circuit, and the resistance side terminal of the series circuit is used to drive the scanning line driving circuit. It is connected to the output terminal, the capacitor side terminal of the series circuit is connected to the reference potential or the ground potential, and the scanning line driving circuit is operated under predetermined conditions for evaluation.

According to the above configuration, a drive circuit capable of optimally driving a matrix type display panel can be designed easily and at low cost, and the evaluation of the drive circuit can be easily performed by connecting a dummy load. And it can be performed accurately.

In each of the above-described configurations of the drive circuit and its evaluation method, the drive output terminal of the signal line drive circuit is connected to only one end of the signal line, or the drive output terminal of the scan line drive circuit is connected to the scan line. When both are connected to only one end, it is preferable that both of the constants α and β be 1.

When the drive output terminal of the first signal line drive circuit is connected to one end of the signal line and the drive output terminal of the second signal line drive circuit is connected to the other end of the signal line, or When the drive output terminal of the first scan line drive circuit is connected to one end of the scan line and the drive output terminal of the second scan line drive circuit is connected to the other end of the scan line, the above constant α And β are both preferably 0.5.

The wiring capacitance Cd in each of the above structures is
Is set to 0 (zero), the number of circuit elements of the dummy load of the signal line or the scanning line can be reduced.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) The signal lines and scanning lines in this embodiment are represented by equivalent circuits shown in FIGS. 2 (a) and 2 (b). In FIG. 2A, rs indicates the wiring resistance per signal line pixel, and cs indicates the capacitance per signal line pixel. In FIG. 2B, r indicates the wiring resistance per scanning line pixel, and c indicates the capacitance per scanning line pixel. cs and c are capacitance values for the operation reference terminal. The voltage applied to the operation reference terminal is defined as the operation reference voltage. 2A and 2B, the operation reference terminal is shown as a common terminal.

The ladder circuits on the left side of FIGS. 2A and 2B can be approximated by RC series circuits on the right side. That is, as shown in FIG. 2A, the signal line is accurately approximated by a series circuit of the resistor RL1 and the capacitor CL1 obtained from the equation (Equation 3), and the scanning line is as shown in FIG. 2B. , Is accurately approximated by a series circuit of the resistor RL1 and the capacitor CL1 obtained from the equation (Equation 4). An accurate approximation cannot be obtained with Expression (Equation 1) and Expression (Equation 2) used in the description of the conventional example.

[0024]

RL1 = 2X · rs / π CL1 = 2X ·
cs / π

[0025]

RL1 = 2Y · r / π CL1 = 2Y ·
The c / π equation (Equation 3) is a resistance and a capacitor (capacitance) constituting an equivalent circuit when driven from one end of the signal line, and the equation (Equation 4) is an equivalent circuit when driven from one end of the scanning line. The constituent resistors and capacitors are shown.

Based on the above considerations, in the present invention, the signal line is represented by a series circuit of the resistor RL and the capacitor CL obtained from the equation (Equation 5), using α and β as constants, and the scanning line is represented by the equation (Equation 5). It is represented by a series circuit of the resistor RL and the capacitor CL obtained from 6). Here, the number of scanning lines of the matrix type display panel is X and the number of signal lines is Y.

[0027]

RL = 2α · X · rs / π CL = 2β ·
X · cs / π

[0028]

RL = 2α · Y · r / π CL = 2β ·
Y · c / π α and β are constants determined in consideration of an error between a driving condition, a margin of driving capability, and a design value. For example, consideration is given to the case where the wiring resistances rs and r, the manufacturing variations of the capacitances cs and c, the case where matrix type display panels having different screen sizes are driven by the same drive circuit, and the like.

In driving from one end, 0.7 ≦ α ≦ 1.
3, and α and β are determined so as to satisfy 0.7 ≦ β ≦ 1.3, and α = β = 1 when the margin or variation in the driving ability is small. On the other hand, in driving from both ends, 0.35 ≦ α ≦ 0.65 and 0.35 ≦ β ≦
Α and β are determined so as to satisfy 0.65, and α = β = 0.5 when the margin or variation in the driving ability is small.

The wiring between the driving circuit and the signal line or the scanning line has a wiring capacitance. Further, an output terminal capacitance is generated at a drive output terminal of the drive circuit. Therefore, in the evaluation method of the present invention, the wiring capacitance generated between the wiring between the drive output terminal of the drive circuit and the signal line or the scanning line and the operation reference terminal is represented by Cd
And the resistance RL obtained from the equation (Equation 5) or the equation (Equation 6)
A circuit in which a capacitor corresponding to the wiring capacitance Cd is connected in parallel to a series circuit of a resistor having a capacitance and a capacitor having a capacitance CL is used as a dummy load. The wiring capacitance Cd is determined based on an actually measured value.

FIG. 1 is a block diagram showing a method for evaluating a drive circuit of a matrix type display panel. In FIG. 1, C
A series-parallel circuit composed of d, RL, and CL is a dummy load that represents a signal line or a scanning line by an equivalent circuit. If the output resistance of the drive circuit is set so that the dummy load thus determined can be optimally driven, the driving capability in actual driving is optimized in the same manner as when the dummy load is driven. That is,
A drive circuit having an optimum drive capability can be easily and efficiently designed using the above-described equivalent circuit (that is, a dummy load), and its evaluation can be accurately performed using the dummy load.

In FIG. 1, Vref represents an operation reference voltage. The operation reference voltage is for determining an operation point of the matrix type display panel. In the conventional evaluation method shown in FIG. 14, one end of the dummy load is connected to the ground potential, but in FIG. 1, one end of the dummy load is connected to the operation reference voltage. The operation reference voltage may be a value close to the ground potential in some cases, but the configuration of FIG. 14 increases errors. In the evaluation method of the present invention, as shown in FIG. 1, one end of the dummy load, that is, a connection point between the capacitors Cd and CL is connected to the operation reference voltage Vref. Of course, when the operation reference voltage is 0 V in actual driving, it may be connected to the ground potential.

In FIG. 1, reference numeral 11 denotes a drive circuit optimally designed using the above-described equivalent circuit (ie, dummy load). O1 to on of the drive circuit 11 are drive output terminals, Vo
Is the input terminal of the drive power supply, Vdd is the power supply terminal for signal, C
.., Dref indicate input terminals for control signals such as clock, data, and reference voltage.
The number of output terminals of the drive circuit 11 is n. A dummy load including Cd, RL, and CL is connected to the drive output terminal o1. TP indicates a test point. Reference numeral 12 denotes a drive power supply circuit that supplies a drive power supply voltage to the drive circuit 11. A control circuit 13 supplies a reference voltage and a control signal to the drive circuit 11 and controls the drive power supply circuit 12.

According to the above configuration, the drive circuit 11 operates by the control signals such as the clock and data supplied from the control circuit 13 and the drive power supply voltage supplied from the drive power supply circuit 12 to drive the dummy load. At this time, the drive circuit 11 operates under conditions close to actual driving of the matrix type display panel. In this way, the performance evaluation is performed by obtaining the electrical characteristics such as the timing margin of the drive circuit 11, the power supply current, the operating power supply voltage range, and the delay time of the drive voltage at the drive output terminal. The driving capability can be accurately evaluated by measuring the waveform (waveform at TP) of the capacitor CL of the dummy load.

Since the dummy load can accurately approximate the signal line or the scanning line, the measurement result based on the evaluation method of FIG. 1 matches the measurement result of the actual driving, and the performance evaluation of the driving circuit can be accurately performed in advance. it can.

FIG. 3 shows an example of a configuration diagram of a display device. The number of signal lines of the matrix type display panel 34 is Y, the number of scanning lines is X, and COM indicates an operation reference terminal. 3
1 indicates a scanning line, 32 indicates a signal line, and 33 indicates a pixel. Reference numeral 35 denotes a signal line driving IC, 36 denotes a scanning line driving IC, and 37 denotes a control circuit for controlling the signal line driving IC 35 and the scanning line driving IC 36. The combination (Y, X) of the number of signal lines and the number of scanning lines is (640 * 3, 480), (800 * 3,
600), (1024 * 3,768), (1240 *)
3,1024) and (1600 * 3,1200) are often used. In any case, since the number of signal lines and scanning lines is large, the driving circuit is generally composed of a plurality of driving ICs. Therefore, the design or evaluation of the drive circuit specifically means the design or evaluation of the drive IC.

FIG. 4 is a block diagram of the signal line driving circuit. 41 is an output circuit, 42 is a level shift circuit.
The control circuit mainly includes a shift register group and a logic circuit.
FIG. 5 is a block diagram of a scanning line driving circuit. FIG.
Similarly to the above, 51 is an output circuit, 52 is a level shift circuit, and the control circuit mainly comprises a shift register group and a logic circuit.

FIG. 6 shows an example of the output circuit of the drive circuit and its equivalent circuit. The output circuit of FIG. 6 includes four analog switches, and is represented by an equivalent circuit of switches sw1 to sw4 and four resistors Ro. FIG. 7 is a diagram showing an output circuit of the drive circuit and a dummy load in an equivalent circuit. As can be seen from FIG. 7, the drive circuit can be easily and accurately designed by expressing the signal lines or scan lines of the display panel by an equivalent circuit (ie, a dummy load) including Cd, RL, and CL as described above. Can be. That is, by accurately simulating the voltage appearing at the test point TP under predetermined driving conditions based on the equivalent circuit of FIG.
The optimum output resistance Ro for driving can be determined. Thus, the drive circuit 11 for optimally driving the display panel can be easily and efficiently designed at low cost.

FIGS. 8A to 8C show an example of the voltage waveform at the drive output terminal. 8A and 8B show the voltage waveforms of the scanning lines, and FIG. 8C shows the voltage waveforms of the signal lines.
V1 to V8 indicate the amplitude of the drive voltage (operation reference voltage Vr
ef). FIG. 8A shows an example of the output voltage of the output circuit including the four analog switches shown in FIG.
FIG. 8B shows a case where there are three analog switches. FIG. 8C shows a case of a signal line driving circuit having an output circuit including two analog switches. 8 (a) to 8 (c)
An optimal drive circuit can be designed based on the condition setting for driving the dummy load composed of Cd, RL, and CL with the drive waveform shown in FIG. In addition, it is possible to perform an evaluation capable of obtaining a performance evaluation close to actual driving.

An example of numerical values obtained from Expressions (3) and (4) is shown below. Screen size is 12.1 inches and Y =
The signal lines of the STN liquid crystal panel of 800 * 3 and X = 600 have RL1 = 860Ω and CL1 = 50 pF, and the scanning lines have RL1 = 2.3 KΩ and CL1 = 480 pF. Also, if the screen size is 10.4 inches, Y = 800 * 3, X
= 600, the signal line of the TFT type liquid crystal panel is RL1 = 2.
7KΩ, CL1 = 29 pF, and the scanning line is RL1 = 9
60Ω, CL1 = 407 pF. The value of Cd varies depending on the screen size of the display panel and the shape of the wiring on the printed circuit board, but is usually about several tens of pF.

Although the capacitance of the signal line is relatively small,
In the evaluation of the drive circuit, when measuring the voltage waveform at both ends of the CL, it is affected by the capacitance of the measuring instrument (for example, the terminal capacitance of the oscilloscope probe). In that case, the capacity obtained by subtracting the capacity of the measuring instrument from the value of CL in Expressions (5) and (6) may be used as CL. In this way, the influence of the measuring instrument can be reduced.

As described above, the equations (Equation 5) and (Equation 6)
By obtaining the output resistance of the drive circuit so as to optimally drive an equivalent circuit (that is, a dummy load) composed of the resistor RL, the capacitor CL, and the capacitor Cd, an optimum drive circuit for a display panel can be efficiently, easily, and at low cost. Can be developed and designed. In addition, according to the evaluation method of the present invention using the above-described dummy load, the performance of the drive circuit can be accurately evaluated without actual driving, and a problem occurring in actual driving can be grasped in advance. This can contribute to cost reduction of the display device.

(Embodiment 2) FIG. 9 is a block diagram showing a second embodiment of the method for evaluating a drive circuit for a matrix type display panel according to the present invention. FIG. 9 shows the operation reference voltage Vr of FIG.
This corresponds to the case where ef is set to 0V. Other configurations are shown in FIG.
Is the same as This embodiment is suitable when the operation reference voltage is close to 0V. Since the operation reference voltage is not required, there is an advantage that the parameters of the simulation for obtaining the output resistance of the drive circuit for optimal driving can be reduced, and the design of the drive circuit and the evaluation circuit are simplified.

(Embodiment 3) FIG. 10 is a block diagram showing a third embodiment of the method for evaluating a drive circuit for a matrix type display panel according to the present invention. FIG. 10 shows RL, CL and Cd.
Is connected to the drive output terminal o1 of the drive circuit 11.
This is the case where all the connections of ~ on are connected. As in FIG.
An operation reference voltage is connected to the dummy load. This embodiment has the same effect as the embodiment of FIG. 1, and also connects the dummy loads to all the drive output terminals of the drive circuit 11 and operates the drive circuit 11 under conditions closer to the actual drive. It is possible to accurately obtain operating characteristics such as the driving current, driving capability, power consumption, operating power supply voltage range, operating frequency, and timing of the eleventh embodiment. In particular, there is an advantage that the consumption current and the drive current of the drive circuit can be accurately obtained before mounting on the display panel.

(Embodiment 4) FIG. 11 is a block diagram showing a fourth embodiment of the method for evaluating a matrix-type display panel drive circuit according to the present invention. FIG. 11 shows a case where the operation reference voltage Vref in FIG. 10 is set to 0V. Other configurations are the same as those in FIG. This embodiment is suitable when the operation reference voltage is close to 0V. Since the operation reference voltage is unnecessary, the number of simulation parameters for obtaining the output resistance of the drive circuit for optimal driving can be reduced, and there is an advantage that the design of the drive circuit and the evaluation circuit are simplified.

(Embodiment 5) FIG. 12 is a block diagram showing a fifth embodiment of the method for evaluating a drive circuit of a matrix type display panel according to the present invention. FIG. 12 shows the case where the wiring capacitance Cd generated between the wiring between the drive output terminal of the drive circuit and the signal line or the scanning line and the operation reference terminal in FIG. 1 is set to 0. This embodiment is suitable when the wiring capacitance Cd is negligibly small compared to the load capacitance CL. In this case, the same effect as that of FIG. 1 can be obtained with the configuration of FIG.
The present invention can be applied to a case where a drive IC is mounted on a display panel by a COG (Chip on glass) method or a case where the drive IC is formed outside an image display area of the display panel.

Since the wiring capacitance Cd is set to 0, the number of circuit elements of the dummy load can be reduced, and there is an advantage that the simulation in the design of the drive circuit becomes easy. Furthermore,
When the operation reference voltage Vref can be approximated to 0 V, FIG.
Similarly, one terminal of the capacitor CL can be grounded.

(Embodiment 6) FIG. 13 is a block diagram showing a sixth embodiment of the method for evaluating a drive circuit of a matrix type display panel according to the present invention. FIG. 13 shows the case where the wiring capacitance Cd generated between the wiring between the driving output terminal of the driving circuit and the signal line or the scanning line and the operation reference terminal in FIG. 10 is set to 0. This embodiment is suitable when the wiring capacitance Cd is negligibly small compared to the load capacitance CL. The present invention can be applied to a case where a driving IC is mounted on a display panel by a COG (Chip on glass) manufacturing method or a case where the driving IC is formed outside an image display area of the display panel.

Since the wiring capacitance Cd is set to 0, the number of circuit elements of the dummy load can be reduced, and there is an advantage that the simulation in the design of the drive circuit becomes easy. Furthermore,
When the operation reference voltage Vref can be approximated to 0 V, FIG.
Similarly to 1, one terminal of the capacitor CL can be grounded.

[0050]

As described above, according to the present invention, an equivalent circuit (dummy load) composed of the resistor RL and the capacitor CL, which are obtained from the equations (5) and (6), and the wiring capacitance Cd can be optimized. By determining the output resistance of the drive circuit so as to drive, a drive circuit optimal for a display panel can be efficiently and easily developed and designed at low cost.

Further, according to the evaluation method of the present invention in which the driving circuit is operated under conditions close to actual driving using the above-described dummy load, the performance of the driving circuit can be accurately evaluated.
Since troubles occurring in actual driving can be grasped in advance, it is possible to contribute to cost reduction of the display device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a method for evaluating a matrix type display panel drive circuit according to the present invention.

FIG. 2 is a diagram illustrating a signal line and a scanning line in an equivalent circuit.

FIG. 3 is a block diagram illustrating an example of a matrix display device.

FIG. 4 is a block diagram illustrating an example of a signal line driver circuit.

FIG. 5 is a block diagram illustrating an example of a scanning line driving circuit.

FIG. 6 is a diagram showing a configuration and an equivalent circuit of an output circuit of a drive circuit.

FIG. 7 is a diagram showing an output circuit of a drive circuit and a dummy load in an equivalent circuit.

FIG. 8 illustrates an example of a drive output voltage of a drive circuit.

FIG. 9 is a block diagram showing Embodiment 2 of a method for evaluating a matrix type display panel drive circuit according to the present invention.

FIG. 10 is a block diagram showing a third embodiment of a method for evaluating a matrix type display panel drive circuit according to the present invention.

FIG. 11 is a block diagram showing a fourth embodiment of a method for evaluating a matrix type display panel drive circuit according to the present invention.

FIG. 12 is a block diagram showing Embodiment 5 of a method for evaluating a matrix type display panel drive circuit according to the present invention.

FIG. 13 is a block diagram showing a sixth embodiment of a method for evaluating a matrix type display panel drive circuit according to the present invention.

FIG. 14 is a block diagram showing an evaluation method of a conventional matrix type display panel drive circuit.

FIG. 15 is a diagram showing signal lines and scanning lines in FIG. 14 in an equivalent circuit.

FIG. 16 is a diagram showing an output circuit of a drive circuit and a dummy load in FIG. 14 by an equivalent circuit;

[Explanation of symbols]

 Reference Signs List 11 signal line drive circuit 12 drive power supply circuit 13 control circuit 31 scan line 32 signal line 33 pixel 34 matrix type display panel 35 signal line drive IC 36 scan line drive IC 37 control circuit 41 output circuit of signal line drive IC 42 signal line drive Level shift circuit of IC 51 Output circuit of scan line drive IC 52 Level shift circuit of scan line drive IC 91 Drive circuit 92 Drive power supply circuit 93 Control circuit RL Resistance of dummy load CL Capacity of dummy load Cd Capacity Ro Output resistance of drive circuit sw, sw1 to sw4 Switch RL1 Equivalent resistance of signal line or scanning line CL1 Equivalent capacitance of signal line or scanning line RL2 Resistance of conventional dummy load CL2 Capacity of conventional dummy load Vref Operating reference voltage rs Per pixel of signal line Wiring resistance r Wiring resistance per pixel of scanning line cs Capacitance per pixel of signal line c c Capacitance per pixel of scanning line o1 to on Drive output terminal of drive circuit TP Test point X Number of scanning lines of matrix type display panel Y Number of signal lines of matrix type display panel com Operation Reference terminal

Claims (14)

[Claims] 1. A driving circuit for a matrix type display panel in which X scanning lines and Y signal lines are arranged in a matrix, and each intersection of the signal lines and the scanning lines is a pixel. Let α and β be constants, the wiring resistance per pixel of the signal line be rs, and the capacitance per pixel of the signal line be cs
The signal line is regarded as a series circuit of a resistor RL = 2α · X · rs / π and a capacitance CL = 2β · X · cs / π, and the driving end of the signal line and the driving output of the signal line driving circuit are considered. When a wiring capacitance between the terminal and the terminal is Cd, the wiring capacitance Cd is connected in parallel to a series circuit of the resistor RL and the electrostatic capacitance CL, and a resistor RL side terminal of the series circuit drives a signal line driving circuit. An output terminal connected to a capacitance CL side terminal of the series circuit connected to a reference potential or a ground potential, and a voltage across the capacitance CL when the signal line driving circuit is operated under predetermined conditions. Having an output resistance such that a predetermined driving voltage is obtained. 2. The drive circuit for a matrix display panel according to claim 1, wherein when the drive output terminal of the signal line drive circuit is connected to only one end of the signal line, both the constants α and β are set to 1. 3. When the drive output terminal of the first signal line drive circuit is connected to one end of the signal line and the drive output terminal of the second signal line drive circuit is connected to the other end of the signal line, 2. The driving circuit according to claim 1, wherein the constants α and β are both set to 0.5. 4. A driving circuit for a matrix type display panel, wherein X scanning lines and Y signal lines are arranged in a matrix, and each intersection of the signal line and the scanning line is a pixel. α and β are constants, the wiring resistance per pixel of the scanning line is r, the capacitance per pixel of the scanning line is c, and the resistance of the scanning line is RL = 2α · Y · r / π and the capacitance is Capacity CL
= 2β · Y · c / π, and when the wiring capacitance between the driving end of the scanning line and the driving output terminal of the scanning line driving circuit is Cd, the wiring capacitance Cd is equal to the resistance RL. And a capacitor CL are connected in parallel to a series circuit, a resistor RL side terminal of the series circuit is connected to a drive output terminal of a scanning line driving circuit, and a capacitor CL side terminal of the series circuit is connected to a reference potential or ground. A matrix-type display having an output resistance connected to a potential so that a voltage at both ends of the capacitance CL becomes a predetermined driving voltage when the scanning line driving circuit is operated under a predetermined condition. Panel drive circuit. 5. The driving circuit for a matrix type display panel according to claim 4, wherein when the driving output terminal of the scanning line driving circuit is connected to only one end of the scanning line, both the constants α and β are set to 1. 6. When the drive output terminal of the first scan line drive circuit is connected to one end of a scan line and the drive output terminal of the second scan line drive circuit is connected to the other end of the scan line, 5. The driving circuit for a matrix type display panel according to claim 4, wherein the constants α and β are both set to 0.5. 7. The semiconductor device according to claim 1, wherein the wiring capacitance Cd is set to 0.
7. The driving circuit for a matrix type display panel according to any one of items 6 to 6. 8. A method for evaluating a driving circuit for driving a matrix type display panel in which X scanning lines and Y signal lines are arranged in a matrix, and each intersection of the signal lines and the scanning lines is a pixel. Where α and β are constants, the wiring resistance per pixel of the signal line is rs, the capacitance per pixel of the signal line is cs, and the resistance of the signal line is RL = 2α · X · rs / Considering a series circuit of π and capacitance CL = 2β · X · cs / π,
The wiring capacitance between the driving end of the signal line and the driving output terminal of the signal line driving circuit is Cd, and a capacitor having a capacitance Cd is connected in parallel with a series circuit of a resistance having a resistance RL and a capacitor having a capacitance CL. The connected one is used as a dummy load of the signal line drive circuit, the resistor side terminal of the series circuit is connected to the drive output terminal of the signal line drive circuit, the capacitor side terminal of the series circuit is connected to the reference potential or the ground potential, A method for evaluating a matrix-type display panel driving circuit, wherein the evaluation is performed by operating the signal line driving circuit under predetermined conditions. 9. The matrix type display panel driving circuit according to claim 8, wherein when the driving output terminal of the signal line driving circuit is connected to only one end of the signal line, both the constants α and β are set to 1. Evaluation methods. 10. When the drive output terminal of the first signal line drive circuit is connected to one end of a signal line and the drive output terminal of the second signal line drive circuit is connected to the other end of the signal line,
9. The method according to claim 8, wherein the constants α and β are both set to 0.5. 11. A method of evaluating a driving circuit for driving a matrix display panel in which X scanning lines and Y signal lines are arranged in a matrix and each intersection of the signal lines and the scanning lines is a pixel. Where α and β are constants, the wiring resistance per pixel of the scanning line is r, the capacitance per pixel of the scanning line is c, and the scanning line has a resistance RL = 2α · Y · r / π and capacitance CL
= 2β · Y · c / π, the wiring capacitance between the driving end of the scanning line and the driving output terminal of the scanning line driving circuit is Cd, and the resistance of the resistance RL and the capacitance CL A capacitor having a capacitance of Cd connected in parallel to a series circuit with a capacitor is used as a dummy load of the scanning line driving circuit, and the resistor side terminal of the series circuit is connected to the driving output terminal of the scanning line driving circuit. A method for evaluating a matrix-type display panel drive circuit, comprising: connecting a capacitor side terminal of a circuit to a reference potential or a ground potential; and operating the scanning line drive circuit under predetermined conditions for evaluation. 12. The matrix display panel driving circuit according to claim 11, wherein when the driving output terminal of the scanning line driving circuit is connected to only one end of the scanning line, both the constants α and β are set to 1. Evaluation methods. 13. When the drive output terminal of the first scan line drive circuit is connected to one end of a scan line and the drive output terminal of the second scan line drive circuit is connected to the other end of the scan line,
The evaluation method for a matrix-type display panel drive circuit according to claim 11, wherein both the constants α and β are set to 0.5. 14. The wiring capacitance Cd is set to 0.
14. The method for evaluating a matrix-type display panel drive circuit according to any one of items 13 to 13.