JP2003008424A - Noise reduction circuit for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a noise reduction circuit for a semiconductor device that can reduce a high level noise caused by concentrated flowing of a momentary transient current (peak current) through power lines of IO buffers when many outputs are inverted in each semiconductor, using the IO buffer with an output in a plurality of bits and capable of a high output current capability, such as a data control circuit for plasma display and liquid crystal display. SOLUTION: The noise reduction circuit is configured such that a delay circuit is inserted to each bit of each semiconductor to individually shift an inversion timing of output data so as to deviate a peak timing of the transient current momentarily flowing through the output IO buffer thereby reducing a noise due to a sudden change in a power supply voltage and a GND voltage in the inside of each semiconductor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise reduction circuit for a semiconductor device, and more particularly to a multi-bit output which outputs image data in accordance with a display timing signal of a PDP (plasma display panel) or a liquid crystal panel of a large panel. The present invention relates to a display data control circuit, such as a load-applied display data control circuit, which reduces noise caused by concentrated output transient current flow of a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal display panel LCD has about 600 to 2000 horizontal lines due to high definition and large screen.
While approximately 500 to 1000 signal lines are provided in the vertical direction, a liquid crystal drive circuit formed of a semiconductor integrated circuit can have only about 80 to 160 output terminals. Therefore, in order to drive one liquid crystal display panel LCD, a large number of liquid crystal drive circuits are used respectively from the left and right poles of the liquid crystal display panel, and a liquid crystal display data control circuit that outputs image data in accordance with display timing is used. The output is input in parallel to a large number of liquid crystal drive circuits.

[0003]

Liquid crystal display panel LCD
The output of the liquid crystal display data control circuit which outputs the image data in accordance with the display timing is input to a large number of liquid crystal drive circuits of the left and right poles of the liquid crystal display panel through the signal lines formed on the mounting substrate. Therefore, the external load applied to the output of the liquid crystal display data control circuit is the sum of the wiring capacitance of the signal line formed on the mounting substrate and the input capacitance of a large number of liquid crystal drive circuits. The input load capacitance of one terminal of a normal semiconductor is 10 pF to 15 pF, and when 10 liquid crystal driving semiconductors are mounted on one liquid crystal display panel LCD, the liquid crystal display data control circuit has 100 pF to 150 pF per terminal.
External load capacity of. When a high external load such as a liquid crystal display data control circuit is applied, it is necessary to use an output IO buffer with a high output current capacity in order to suppress signal blunting. Momentarily large transient current (peak current)
Flows. Further, since the liquid crystal display data control circuit outputs a plurality of bits of image display data, when a large number of outputs of the liquid crystal display data control circuit are inverted from H → L or L → H, a large number are synchronized with the clock pulse. The signals of are inverted at the same time. An instantaneous transient current (peak current) continues to flow in the output IO buffer by the number of signal bits inverted for each cycle of the clock pulse. For this reason, an instantaneous transient current (peak current) is generated inside the semiconductor of the liquid crystal display data control circuit.
However, there is a problem in that a large amount of noise is generated by intensively flowing into the power supply line. At the same time, when noise is generated in each clock pulse cycle, if the clock frequency of the liquid crystal display data control circuit is high frequency, the high frequency noise also affects semiconductors other than the display data control circuit in the liquid crystal display panel LCD and causes noise. There was a problem of causing.

As described above, the present invention has been made in order to solve the above problems, and also in a semiconductor having an output IO buffer having a plurality of bits of output and having a high output current capability. An object of the present invention is to provide a noise reduction circuit for a semiconductor device that can reduce the noise by shifting the peak timing of the instantaneous transient current (peak current) flowing in the output IO buffer.

[0005]

In order to solve the above problems, in a noise reduction circuit for a semiconductor device according to claim 1 of the present invention, transient currents of a plurality of signal outputs of the semiconductor device simultaneously flow. A noise reduction circuit of a semiconductor device for reducing noise generated thereby, which is characterized by comprising an output phase shift means for shifting the phases of the plurality of signal outputs from each other.

A semiconductor device noise reduction circuit according to a second aspect of the present invention is the semiconductor device noise reduction circuit according to the first aspect, wherein the output phase shift means includes a combination circuit for receiving each data input, and A circuit set having a flip-flop having an output of the combination circuit as a data input and a clock of a predetermined frequency as a clock input, and a delay circuit having an output of the flip-flop as an input is provided with different delay amounts by the delay circuits. N pieces are provided.

A semiconductor device noise reduction circuit according to a third aspect of the present invention is the semiconductor device noise reduction circuit according to the first aspect, wherein the output phase shift means includes a combinational circuit for receiving each data input, and A flip-flop that receives the output of the combinational circuit as a data input and a clock of a predetermined frequency as a clock input, and a delay amount that receives and outputs the output of the flip-flop becomes 1
Delay circuits and (M-1) delay circuits each having a different delay value and each having an output of the flip-flop and having different delay amounts, and an input and an output of the flip-flop. And are input, and data is H → L or L → before and after the input / output of the flip-flop.
An inversion detection circuit for detecting whether or not it is inverted to H,
N circuit sets are provided, each of which has an M input selector that receives an output of the M delay circuits and selects one of the M outputs, and each of the N inversion detection circuits. Is used as an input, the optimum delay value of the delay amounts of the M kinds of delay circuits in the N circuit sets is calculated from the detection results of the inversion detection circuits, and a selector control signal is supplied to the M input selector. And an optimum delay value calculation circuit for outputting as.

According to a fourth aspect of the present invention, there is provided a semiconductor device noise reduction circuit according to the first aspect, wherein the output phase shift means adjusts the clock phase by each adjustment amount. A clock phase adjustment circuit, a first flip-flop that receives each data input and uses a common clock as a clock input, a combination circuit that receives the output of the first flip-flop as an input, and an output of the clock phase adjustment circuit Is used as a clock input, and a second flip-flop having the output of the combinational circuit as a data input is provided, and N circuit sets are provided.

[0009]

(First Embodiment) A noise reduction circuit for a semiconductor device according to a first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a noise reduction circuit of a semiconductor device according to the first embodiment.

In FIG. 1, 100 is a combinational circuit which receives the signal S1 and outputs the signal S2, and 101 is S.
2 is a data input, a clock CLK1 having a frequency fclk is a clock input, a flip-flop having a signal S3 as a Q output, a delay circuit 102 having S3 as an input and a signal S4 as an output, and 103 having a signal S4 as an input, a semiconductor An output IO buffer that outputs the output signal A. The combinational circuit 100, the flip-flop 101, the delay circuit 102, and the output IO buffer 103 constitute one circuit set X, and N circuit sets X are provided. Also,
In the N circuit sets X, the combination circuits are 100, 110, 120, 130, ..., The inputs of the combination circuits 100, 110, 120, 130 are S01, S11, S21, S31 ,. , S02, S12, S22, S32, ..., Flip-flops 101, 111, 121, 131, ...
.., flip-flops 101, 111, 121, 131
Q output of S03, S13, S23, S33.
.... Delay circuits 102, 112, 122, and 1 respectively
32 ..., Delay circuits 102, 112, 122, 132
The output of S04, S14, S24, S34 ...
.., output IO buffers 103, 113, 12 respectively
3 and 133, and the outputs of the output IO buffers are semiconductor output signals A, B, C, D ,. The clock inputs of the flip-flops 101, 111, 121 ... Are all clocks CLK1 having a frequency fclk, and the delay circuits 102, 112, 122 ... Can set different delay values.

The operation of the noise reduction circuit of the semiconductor device configured as described above will be described below with reference to FIG. Combination circuits 100, 110, 120
.. Since the circuit contents of each are different, its output S0
The phases of the signal changes of 2, S12, S22, ... Are different, but the flip-flops 101, 111,
The Q outputs S03, S13, S23, ... Of 121 ... Are output in synchronization with the rising edge of the clock CLK1, and therefore the phases of signal changes are the same. Delay circuit 10
2, 112, 122, ... Can set different delay values, for example, the delay circuit 102 sets the input S03 to 1 ns.
The delay circuit 112 delays and outputs the delayed signal.
Different delay values are set in the respective delay circuits by delaying output by ns and outputting. P1 and P in FIG.
2 and P3 indicate delay values of the delay circuits 102, 103 and 104, respectively. Furthermore, the output IO buffers 103 and 11
If the buffer capacity of 3, 123 ... Is equal, the data change point of the semiconductor output B as shown in FIG.
1 ns delay with respect to the data change point of 1), the data change point of the semiconductor output C with 2 ns delay with respect to the data change point of the semiconductor output A, etc. are output at different data change timings.

As described above, in the noise reduction circuit for the semiconductor device according to the first embodiment, a plurality of set circuits X each having a combinational circuit, a flip-flop, and a delay circuit are provided, and the delay values of the delay circuits are individually set. By doing so, even if the semiconductor has an output IO buffer with a high output current capability, such as a liquid crystal display data control circuit, the semiconductor output is H → L, L →.
When inverted to H, the peak timing of the transient current that instantaneously flows in the output IO buffer can be shifted, and as a result, multiple bit outputs are inverted at the same time and the transient currents overlap and flow intensively to the power supply line. It is possible to reduce noise caused by a sudden change in the power supply voltage and the GND voltage inside the semiconductor, which occurs at a change point of the output signal.

(Second Embodiment) Hereinafter, a noise reduction circuit for a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 3 and 4. FIG. 3 shows noise of the semiconductor device according to the second embodiment. It is a block diagram which shows the structure of a reduction circuit.

In FIG. 3, reference numeral 200 denotes a combinational circuit which receives the signal T1 and outputs the signal T2, and 201 denotes T.
2 is a data input, a clock CLK2 having a frequency fclk is a clock input, and a flip-flop 202, 203, 204, ... Having a signal T3 as a Q output is a signal T3 as an input, and signals T4, T5, T6 ... , M-1 delay circuits having an output of 210, the input signal T2 and the output signal T3 of the flip-flop are input, and T2 and T3
And an inversion detection circuit that detects whether two signals are inverted and outputs a detection result T11. Reference numeral 211 denotes an output T3 of the flip-flop 201 and outputs T4, T5, T6 of M-1 delay circuits. ... and the signal T1
An M input selector that outputs 0, and 212 is an output IO buffer that receives T10 as an input and outputs the semiconductor output signal A ′. The combination circuit 200, the flip-flop 201, and M−1 delay circuits 202 and 203,
.., the inversion detection circuit 210, the M input selector 211, and the output IO buffer 212 into one circuit set Y, and N circuit sets Y are provided.

Further, in the N circuit sets Y, the combination circuits are respectively 200, 300, 40.
0, 500 ..., Combination circuits 200, 300, 4
Inputs of 00 and 500 are T1, U1, V1 and W1 respectively.
..., outputs are T2, U2, V2, W2 ..., and flip-flops are 201, 301, 401, 501, respectively.
..., flip-flops 201, 301, 401, 5
01 ... Q output to T3, U3, V3, W3 respectively
..., 20 M-1 delay circuits in the circuit set Y
2, 203, 204 ..., 302, 303, 304 ...
..., 402, 403, 404 ..., Delay circuit 20
2, 203, 204 ..., 302, 303, 304 ...
.., 402, 403, 404 ... Outputs are respectively T4, T5, T6 ..., U4, U5, U6 ..., V
4, V5, V6 ... Inversion detection circuits 210, 310, 410, 510 ... In the circuit set Y, respectively, and outputs of the inversion detection circuits 210, 310, 410, 510. , V11, W11 ...
The M input selectors in the circuit set Y are set to 211 and 3 respectively.
11, 411, 511, ..., M input selector 211,
The outputs of 311, 411, 511, ...
0, U10, V10, W10 ..., Output IO buffers in the circuit set Y 212, 312, 412, 512.
・ ・Flip-flops 201, 301, 401
The clock CLK2 having the frequency fclk is input to all clock inputs of ... Further, 213 is the inversion detection circuit 210, 310, 410 ... In the circuit set Y.
Is an optimum delay value calculation circuit that inputs L outputs T11, U11, V11 ... Of L and outputs L signals T12, U12, V12.
2 ... are input as select control signals of the M input selectors 211, 311, and 411, respectively.

The operation of the noise reduction circuit of the semiconductor device configured as described above will be described below with reference to FIG. Combination circuits 200, 300, 400 ...
Since the circuit contents of each are different, its output T2, U
The phases of the signal changes of 2, V2 ... Are different, but the flip-flops 201, 301, 401 ...
・ Q output T3, U3, V3 ... Is clock CLK2
Since the signals are output in synchronization with the rising edge of, the phases of signal changes are the same. (M-1) × N delay circuits 20
2, 203, 204 ... 302, 303, 304 ...
In 402, 403, 404, ..., the delay circuit 2
02, 302, 402 ... Have the same delay value, delay circuit 2
03, 303, 403 ... Have the same delay value, 204, 3
04, 404 ... Have the same delay value. The inversion detection circuits 210, 310, 410 ... Compare the signals before and after the input / output of the flip-flops 201, 301, 401 ... And detect whether the two signals are inverted and detect the detection result T11, It outputs U11 and V11.

The optimum delay value calculation circuit 213 detects the detection results T11, U2 of the inversion detection circuits 210, 310, 410, ....
1, M21 selector 21 calculated from V21 ...
1, 311, 411 ... Select control signals T12,
It outputs U12, V12 ... The select control signals T12, U12, V12, ... Select the input signals T3, U3, V3, ... Output the code, and for the inverted bit, calculate the optimum delay value so that the overlap of the transient current at the time of output inversion can be sufficiently widened within the output AC timing, and set it to that delay value. The code that selects the output of the delay circuit having the existing delay element is output. As a result, only the inverted bits of the outputs T10, U10, V10 ... Of the M input selector have different data change timings. Q1 in FIG. 4 represents the delay value of the bit with the largest delay amount, and if the signal inversion bit is 2 bits, the delay value of the inverted bit is Q1 /
2 and Q1, and if the signal inversion bit is 3 bits, the delay value of the inverted bit is Q1 / 3, 2 × Q1 /
3 and Q1. That is, if the signal inversion bit is N bits, the delay value of the inverted bit is Q1 /
N, 2 x Q1 / N, 3 x Q1 / N ... (N-1) x Q1 /
N and Q1.

As described above, the noise reduction circuit for the semiconductor device according to the present embodiment is provided with the combination circuit, the flip-flop, the inversion detection circuit, the delay circuit, and N set circuits Y each having the M input selector, and the optimum delay is further provided. By providing the value detection circuit, only the bit whose output data is inverted will be output through the delay circuit with the optimum delay value, and the overlap of the transient current at the time of output inversion can be widened sufficiently. It is possible to reduce noise caused by a sudden change in the power supply voltage and the GND voltage inside the semiconductor, which occurs at a change point of the output signal, which is caused by a large current in which the currents overlap each other intensively flow in the power supply line.

(Third Embodiment) A third embodiment of the present invention will be described below with reference to FIGS. 5 and 6. FIG. 5 is a block diagram showing the configuration of the noise reduction circuit of the semiconductor device according to the third embodiment.

In FIG. 5, 1000 is a frequency fclk
Of the clock phase adjusting circuit A, which receives the clock CLK3 of
The clock CLK3 is input to 001, and the frequency fclk
Of the clock phase adjusting circuit B and 1002 which outputs the clock CLK05 of the first, the first flip-flop 1003 which receives the signal SS01 as the data input, the clock CLK4 as the clock input and the signal SS02 as the Q output, and 1003 the signal SS02.
Is a combinational circuit that inputs the signal SS03 and outputs the signal SS03.
A second flip-flop 1005 receives LK05 as a clock input and outputs a signal SS04 as a Q output.
Is an input IO buffer that receives the input and outputs the semiconductor output A ″. This clock phase adjustment circuit B1001
, The first flip-flop 1002, the combinational circuit 1003, the second flip-flop 1004, and the output IO buffer 1005 into one circuit set Z,
N circuit sets Z are provided.

Further, in the N circuit sets Z,
The clock adjustment circuit B is 1001, 1011, and 1 respectively.
021, 1031 ..., Clock adjustment circuit B100
The outputs of 1, 1011, 1021, 1031, ... Are respectively CLK05, CLK15, CLK25, CLK35.
..., first flip-flops 1002,
1012, 1022, 1032, ..., First flip-flops 1002, 1012, 1022, 1032.
The data input of ... is SS01, SS11, SS21,
SS31 ..., Q output is SS02, SS12, SS2
2, SS32 ..., 1003 for combination circuits,
1013, 1023, 1033, ..., Outputs of combination circuits 1003, 1013, 1023, 1033, ... Are respectively SS03, SS13, SS23, SS33.
.... Second flip-flops 1004 and 1 respectively
014, 1024, 1034, ..., Output IO buffers 1005, 1015, 1025, 1035, respectively.
, And the outputs of the output IO buffers are semiconductor output signals A ″, B ″, C ″, D ″, ...
First flip-flops 1002, 1012, 1022
Clock inputs are all clock phase adjustment circuits A
Output clock CLK4, the second flip-flops 1004, 1014, 1024 ...
K15, CLK25 ... Are input respectively. It is assumed that different adjustment values can be set for the phase adjustments of the clock phase adjustments B1001, 1011, 1021 ...

The operation of the noise reduction circuit of the semiconductor device configured as described above will be described below with reference to FIG. First flip-flops 1002, 101
Since the clock inputs of 2, 1022, ... Are all CLK4, the Q outputs SS02, S of the first flip-flop
S12, SS22, ... Are output in synchronization with the rising edge of the clock CLK4, and the phases of signal changes match. Combination circuits 1003, 1013, 1023
Since the circuit contents of ... are different, the output SS
The phases of signal changes of 03, SS13, SS23 ... Second flip-flop 100
Clock phase adjusting circuits B1001, 1011, 1021 ...
Outputs CLK05, CLK15, CLK25 ... Are input to the clock adjusting circuit B100.
.. can be set to different arbitrary adjustment values, the Q outputs SS04, SS14, SS24 ... Of the second flip-flops 1004, 1014, 1024 ... It is output in synchronization with any rising edge of the clock. For example, assuming that the clock delay adjustment value of the clock phase adjustment circuit B1001 is 0.1 ns, the clock delay adjustment value of the clock phase adjustment circuit B1011 is 0.2 ns, and the clock delay adjustment value of the clock phase adjustment circuit B1021 is 0.3 ns.
Second flip-flops 1004, 1014, 1024
Q outputs SS04, SS14, SS24 ... Are also delayed by 0.1 ns and output. Furthermore, the output I
If the buffer capabilities of the O buffers 1005, 1015, 1025, ... Are equal, the semiconductor outputs A ″, B ″, C ″, ... As shown in FIG. 6 are output at different data change timings. .

As described above, the noise reducing circuit for the semiconductor device according to the third embodiment includes the first clock phase adjusting circuit A, and further includes the second clock phase adjusting circuit B and the first flip-flop. N set circuits Z each having a circuit and a second flip-flop are provided,
By setting the number of clock phase adjustment values of the clock phase adjustment circuit B to be shifted, and driving the clock phase adjustment circuits B of a plurality of flip-flops by one clock phase adjustment circuit A, a small gate scale and a small chip can be obtained. Even in the case of a semiconductor that uses an IO buffer having a large output current capability and having a plurality of bits of output, such as a liquid crystal display data control circuit, the semiconductor output is H → L,
When inverted from L to H, the peak timing of the transient current instantaneously flowing in the output IO buffer can be shifted,
As a result, multiple bit outputs are inverted at the same time, transient currents overlap each other, and the currents intensively flow in the power supply line, so that the power supply voltage inside the semiconductor and the GND occur at the change point of the output signal.
Noise due to a sudden change in voltage can be reduced.

[0024]

As described above, according to the noise reducing circuit of the semiconductor device of the first aspect, the noise of the semiconductor device for reducing the noise generated by the transient currents of a plurality of signal outputs of the semiconductor device simultaneously flowing. Since it is a reduction circuit, it is equipped with an output phase shift means that shifts the phases of the plurality of signal outputs from each other, so that it has a plurality of bits of output like a display data control circuit of a PDP or a liquid crystal panel, and has an output current capability. Even if the semiconductor uses a high IO buffer, if the semiconductor output is inverted from H to L or L to H at the same time, the phase of the signal output is shifted from each other, and the multiple bit output is inverted for cleaning. The noise due to the sudden change of the power supply voltage and the GND voltage inside the semiconductor that occurs at the change point of the output signal caused by the transient current overlapping and flowing intensively in the power supply line is reduced. There is an effect that it is Rukoto.

As described above, according to the noise reduction circuit of the semiconductor device of the second aspect, in the noise reduction circuit of the semiconductor device of the first aspect, the output phase shift means is a combination that receives each data input. Circuit, a flip-flop having the output of the combination circuit as a data input and a clock of a predetermined frequency as a clock input, and a delay circuit having an output of the flip-flop as an input, Since N pieces are provided with different amounts, even if the semiconductor has a multi-bit output like a liquid crystal display data control circuit and uses an IO buffer having a high output current capability, the semiconductor output is H → By shifting the peak timing of the transient current that instantaneously flows in the output IO buffer when it is inverted from L to L → H, Tsu bets output of the semiconductor inside occurs with a change point of the output signal produced to flow concentratedly to the power supply line overlaps the transient current reverses to clean the supply voltage and G
There is an effect that noise due to a sudden change in the ND voltage can be reduced.

According to a third aspect of the noise reduction circuit of the semiconductor device, in the noise reduction circuit of the first aspect of the semiconductor device, the output phase shift means includes a combinational circuit for receiving each data input, A flip-flop having the output of the combination circuit as a data input and a clock of a predetermined frequency as a clock input, and one delay circuit having an output of the flip-flop as an input and an output and a delay amount of zero are different from each other. Delay circuits having different delay values, each having an output of the flip-flop as an input, and having different delay amounts (M-1),
An inversion detection circuit that receives inputs and outputs of the flip-flop and detects whether data is inverted from H to L or L to H before and after the input and output of the flip-flop, and the M delays. And N inputs of the output of the circuit and an M input selector that selects one of the M outputs, and further inputs the outputs of the N inversion detection circuits. The optimum delay value of the delay amounts of the M kinds of delay circuits in the N circuit sets is calculated from the detection results of the inversion detection circuits, and is output to the M input selector as a selector control signal. Since the delay value calculation circuit is provided, even if the semiconductor has a plurality of bits of output such as a liquid crystal display data control circuit, when the semiconductor output is inverted from H → L or L → H, the The output IO buffer can shift the peak timing of the transient current that flows instantaneously, and the overlap of the transient current at the time of output reversal can be sufficiently widened, so a large current with overlapping transient current concentrates on the power supply line. There is an effect that it is possible to reduce noise caused by a sudden change in the power supply voltage and the GND voltage inside the semiconductor, which occurs at the change point of the output signal caused by the dynamic flow.

According to a fourth aspect of the noise reduction circuit of the semiconductor device of the present invention, in the noise reduction circuit of the first aspect of the semiconductor device, the output phase shifting means adjusts the phase of the clock by each adjustment amount. A phase adjustment circuit, a first flip-flop that receives each data input and uses a common clock as a clock input, a combination circuit that receives the output of the first flip-flop as an input, and an output of the clock phase adjustment circuit. Since there are provided N circuit sets each having a clock input and a second flip-flop which receives the output of the combinational circuit as a data input, the clock phase adjustment value of the clock phase adjustment circuit B is shifted in phase. Set as many as desired, and one clock phase adjustment circuit A can be used for multiple clock phase adjustment circuits B of flip-flops. Even if the semiconductor has a small gate scale and a small chip area and has an output of multiple bits like a liquid crystal display data control circuit and uses an IO buffer having a high output current capability, the semiconductor output can be improved. It is possible to shift the peak timing of the transient current that instantaneously flows in the output IO buffer when it is reversed from H to L or L to H, and as a result, the multiple bit outputs are reversed for cleaning and the transient current overlaps and the power supply line is overlapped. There is an effect that it is possible to reduce noise caused by a sudden change in the power supply voltage and the GND voltage inside the semiconductor, which occurs at the change point of the output signal due to the concentrated flow.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a noise reduction circuit of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing signal levels of respective parts of the noise reduction circuit of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a noise reduction circuit of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing signal levels of respective parts of the noise reduction circuit of the semiconductor device according to the second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a noise reduction circuit of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing signal levels of respective parts of the noise reduction circuit of the semiconductor device according to the third embodiment of the present invention.

[Explanation of symbols]

100, 110, 120, 130, 200, 300, 4
00,500,1003,1013,1023,103
3 Combination circuits 101, 111, 121, 131, 201, 301, 4
01,501 Flip-flops 102, 112, 122, 132, 202, 203, 2
04, 302, 303, 304, 402, 403, 40
4,502,503,504 Delay circuits 103, 113, 123, 133, 212, 312, 4
12,512,1005,1015,1025,103
5 output IO buffer 210,310,410,510 inversion detection circuit 211,311,411,511 M input selector 213 optimum delay value detection circuit 1000 clock phase adjustment circuit A 1001,1011,1021,1031 clock phase adjustment circuit B 1002 1012, 1022, 1032 First flip-flops 1004, 1014, 1024, 1034 Second flip-flops

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/36 G09G 3/28 HF term (reference) 2H093 NA31 NA36 NA79 ND40 5C006 AF71 BB11 BC16 BF49 FA32 5C080 AA05 AA10 BB05 CC06 DD12 JJ02 JJ04 5J056 AA04 BB24 BB25 CC00 CC05 CC14 FF01 FF10 GG03 KK01

Claims (4)

[Claims] 1. A noise reduction circuit of a semiconductor device for reducing noise generated by transient currents of a plurality of signal outputs of a semiconductor device simultaneously flowing, wherein an output phase shift for shifting phases of the plurality of signal outputs from each other. A noise reduction circuit for a semiconductor device, comprising: 2. The noise reduction circuit for a semiconductor device according to claim 1, wherein the output phase shift means has a combination circuit for receiving each data input, and an output of the combination circuit as a data input, and a clock of a predetermined frequency. A flip-flop that receives a clock; a delay circuit that receives the output of the flip-flop;
A noise reduction circuit for a semiconductor device, characterized in that N circuit sets each having the above are provided with different delay amounts by the delay circuit. 3. The noise reduction circuit for a semiconductor device according to claim 1, wherein the output phase shift means has a combination circuit for receiving each data input, and an output of the combination circuit as a data input, and a clock of a predetermined frequency. A flip-flop that is used as a clock input, one delay circuit that receives and outputs the output of the flip-flop and that has a delay amount of zero, and has different delay values, and the output of the flip-flop is input to each. And (M-1) delay circuits having different delay amounts, and the input and output of the flip-flop are input, and data is H → L or L → before and after the input / output of the flip-flop. An inversion detection circuit for detecting whether or not the signal is inverted to H and an output of the M delay circuits are input, and one of the M outputs is selected. M input selectors, each of which has an M input selector, and further has N outputs of each of the N inversion detection circuits as an input, and outputs an output from each of the N inversion detection circuits. An optimum delay value calculation circuit that calculates an optimum delay value of the delay amounts of the M kinds of delay circuits and outputs the optimum delay value to the M input selector as a selector control signal. Noise reduction circuit for semiconductor devices. 4. The noise reduction circuit for a semiconductor device according to claim 1, wherein said output phase shift means receives a clock phase adjustment circuit for adjusting the phase of the clock by each adjustment amount, and receives each data input in common. A first flip-flop having a clock as a clock input; a combinational circuit having an output of the first flip-flop as an input; and an output of the clock phase adjusting circuit having a clock input,
A noise reduction circuit for a semiconductor device, comprising: a second flip-flop whose data input is an output of the combinational circuit; and N circuit sets.