KR100728472B1 - Output driver of semiconductor device - Google Patents

Abstract

An output driver of a semiconductor device is provided to reduce skew and switching noise of a chip, by using a deskewing output driver. A clock oscillator(100) outputs a clock signal. A first output buffer(400) drives a first output signal at a first timing according to a first load value. A first delay line(200) enables the first output driver by delaying the clock signal output from the clock oscillator by a first delay time. A second output buffer drives a second output signal at a second timing according to a second load value. A second delay line enables the second output buffer by delaying the clock signal output from the clock oscillator by a second delay time. A delay detector(500) compares output timing of the first output signal and the second output signal, and outputs a corresponding delay value. A control part(300) controls the first delay time of the first delay line and the second delay time of the second delay line in correspondence to the delay value output from the delay detector.

Description

Output driver of semiconductor device {OUTPUT DRIVER OF SEMICONDUCTOR DEVICE}

1 is a block diagram showing a delay detector according to a preferred embodiment of the present invention.

Figure 2 is a flow chart for explaining the operation of the control unit according to an embodiment of the present invention.

3 is a block diagram showing an output driver according to a preferred embodiment of the present invention.

Fig. 4 is a block diagram when the number of output drivers is varied.

FIG. 5 is a diagram illustrating power noise and transmission delays according to various output drivers shown in FIG. 4; FIG.

Explanation of symbols on the main parts of the drawings

100: oscillator 200: delay line

300: control unit 400: delay detector

The present invention relates to a semiconductor device, and more particularly to a data output driver of a semiconductor device for outputting data.

Semiconductor devices using CMOS have many tapered buffer types. The buffer is used to reduce single delay and improve operation speed in a large capacitance load or a large fan-out circuit such as off chip capacitance or on chip capacitance of a clock line.

On the other hand, noise is generated in the power supply voltage supply terminal that provides power due to the large skew delay of the current generated when the output signal is converted. This noise increases as the number of output buffers switching at the same time increases, and this negative switching noise (SSN) can adversely affect other circuits on the power line.

To reduce this SSN, the number of output buffers switched at the same time must be reduced. To do this, you can think about how to operate with different delays for each output driver. However, this method has disadvantages of increasing the propagation delay delay and skew of the circuit.

It is an object of the present invention to provide an output driver of a semiconductor device which can reduce switching noise while reducing delay delay and skew.

The present invention provides a clock oscillator for outputting a clock signal, a first output buffer for driving a first output signal at a first timing according to a first load value, and a first delay time for the clock signal output from the clock oscillator. A first delay line for enabling the first output buffer by a delay, a second output buffer for driving a second output signal at a second timing according to a second load value, and the output from the clock oscillator Comparing a second delay line for enabling the second output buffer by delaying a clock signal by a second delay time, and output timings of the first output signal and the second output signal, and comparing a corresponding delay value. A delay detector for outputting the first delay time of the first delay line and a second delay line of the second delay line in response to a delay value output from the delay detector; An output driver of a semiconductor device having a control unit for controlling the time periods is provided.

In addition, the present invention is characterized in that the control unit controls the value of the second delay time.

The delay detector may further include: a first flip-flop configured to receive the first output signal at a clock input terminal and the second output signal at a signal input terminal; A delay unit configured to receive the first output signal and delay the output signal by a predetermined value; A second flip-flop which receives the output of the delay unit at a clock input terminal and the second output signal at a signal input terminal; An or gate for receiving and outputting the positive output terminal of the first flip-flop and the positive output terminal of the second flip-flop; And a NOR gate for receiving and outputting the positive output terminal of the first flip-flop and the sub-output terminal of the second flip-flop.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. do.

1 is a block diagram illustrating a delay detector according to a preferred embodiment of the present invention.

Referring to FIG. 1, the delay detector includes a first flip-flop 10 that receives a first output signal clk2 at a clock input terminal and a second output signal clk1 at a signal input terminal, and a first output signal clk2. Delay unit 30 for receiving and delaying the output by a predetermined value, and the second flip-flop 20 for receiving the second output signal clk1 to the signal input terminal from the output of the delay unit 30 to the clock input terminal; Or gate 40 for receiving and outputting the positive output terminal of the first flip-flop 10 and the positive output terminal of the second flip-flop 20, and the positive output terminal and the second flip-flop of the first flip-flop 10. A NOR gate 50 for receiving and outputting the sub output terminal 20 is provided.

2 is a flowchart illustrating an operation of a controller according to a preferred embodiment of the present invention.

Referring to Figure 2, the control unit determines the size of the delay output buffer. Figure 2 illustrates the operation principle of the controller, which is designed to select a delay in the range of 0 to 32.

When the start signal is input, the 5-bit output is set to '10000' and the comparison starts at the 16 times delay, which is the median delay of the circuit. We set the starting value as the middle value to minimize the time to find the desired delay.

Two control signals received from the delay detector select a delay one step higher if the delay is large, and a delay one step larger if the delay is small. When the delay detector detects a delay of an appropriate magnitude and the delay is within the locking gap defined by the delay detector, the lock signal becomes 1 or exceeds the range that can be adjusted by the controller. It will keep the signal.

The delay given to each output buffer is determined by the signal output from the controller, thereby correcting the skew generated by the interconnection line.

3 is a block diagram showing an output driver according to a preferred embodiment of the present invention.

According to an embodiment of the present invention, an output driver includes a clock oscillator 100, a first output buffer 400 for driving a first output signal at a first timing according to a first load value, and a clock oscillator 100. A first delay line 200 for enabling the first output buffer 400 by delaying the clock signal by a first delay time, and a second drive for driving the second output signal at a second timing according to the second load value. A second output buffer (not shown), a second delay line (not shown) for enabling the second output buffer by delaying the clock signal output from the clock oscillator 100 by a second delay time, Delay detector 500 for comparing the output timing of the first output signal and the second output signal and outputting a delay value corresponding thereto, and the first delay in response to the delay value output from the delay detector 200. To control the first delay time of the line 200 The control unit 300 is provided.

In addition, the present invention is characterized in that the control unit 300 controls the value of the second delay time.

Hereinafter will be described the operation and operation of the output driver of the present invention.

In order to reduce the number of buffers that are simultaneously switched in a way to reduce the SSN, when the different delays are driven to each switch, a problem arises in that the transfer delay of the circuit increases. On the other hand, when several output drivers are connected to one chip by a load, a conventional method of adjusting the length of the line is used to reduce skew caused by the difference in the length of the interconnection line. However, such a method is not always possible, and there is a disadvantage in that compensation for skew generated due to various factors cannot be compensated.

Up to now, the above two problems were considered separate and tried to solve. However, by using the deskew output driver provided by the present invention, the SSN problem and the skew problem can be solved at the same time.

When using the deskew output driver, the skew of each load is reduced, which reduces the skew of the chip. In addition, since the output driver switches with different delays, the effect of reducing the SSN can be expected. Therefore, it can be expected that by using the deskewing output driver, a separate effect of reducing the SSN can be obtained while sufficiently satisfying the original purpose of reducing the skew of the chip caused by the difference in the length of the interconnect shut line.

The time delay caused by the difference in the length of the interconnect lines connected to different loads is equal to Flying time = Line Length / c * e _r . Commercially available circuits use the same length of interconnection lines to prevent this delay. However, there are cases where the length of interconnection lines cannot be matched.

Therefore, in order to prevent time skew between loads due to the difference in the length of the interconnect line, an appropriate delay is added from the beginning to send a signal.

In other words, by detecting the delay difference caused by the length of each interconnection line and adding a different delay to each signal, the signal is adjusted so that the time to reach the load is the same.

As shown in Fig. 1, when the reset signal is input, the signals shown on the output side enter the delay detector. The delay detector compares the delay difference between the two signals to determine whether the signal is locked within a predetermined locking gap and outputs two output signals. If the delay of the other signal is smaller based on one signal, comp = 1, if the delay is large, comp = 0, and the lock signal is 1 when the delay difference between the two signals falls within a desired gap.

3 is an overall block diagram of the deskewing output driver according to the present invention as described above.

Included are the delay detectors and controls described above, an oscillator that controls their timing, and an output driver designed with delay chains and tapered buffers with values from 0 to 32.

The proposed deskew output driver reduces the time skew caused by the interconnection line, and reduces the size of the SSN by switching the output drivers with different delays.

FIG. 4 is a block diagram when the number of output drivers is varied, and FIG. 5 is a diagram showing power noise and transmission delays according to various output drivers shown in FIG.

Referring to Figure 4, in order to find out the relationship between the number of output drivers that are simultaneously switched and the size of the generated SSN, the setup is divided into three cases by eight tapered extraction drivers, each case as shown in Figure 4 Simulation results in the same result as in FIG.

In the first case (Case A) is a case in which eight output buffers are switched at the same time, in the second case (Case B) four output buffers are switched at the same time, the other four are to be switched at the same time after a unit delay. In the third case (Case C), it is configured to include a case in which no delay is divided into two and a case in which a switch has a delay of three times the unit delay.

As shown in FIG. 5, as can be seen from the relationship between the SSN and the propagation delay, the SSN decreases as the number of drivers switched simultaneously from the first case to the third case decreases.

As described above, the output driver according to the present invention includes a plurality of output buffers, and optimizes operation timing of each output buffer provided according to a corresponding load, thereby eliminating skew problems of all output signals. do. At the same time, since all the output buffers operate at different timings, switching noise can be reduced.

In other words, the SSN can be reduced by differently timing each output buffer turned on while performing skew correction according to the load.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

By using the deskewing output driver according to the present invention, the problem of chip skew and switching noise can be solved at the same time.

Claims (3)

A clock oscillator for outputting a clock signal; A first output buffer for driving the first output signal at a first timing according to the first load value; A first delay line for enabling the first output buffer by delaying the clock signal output from the clock oscillator by a first delay time; A second output buffer for driving the second output signal at a second timing according to the second load value; A second delay line for enabling the second output buffer by delaying the clock signal output from the clock oscillator by a second delay time; A delay detector for comparing output timings of the first output signal and the second output signal and outputting a corresponding delay value; And Control unit for controlling the first delay time of the first delay line and the second delay time of the second delay line, respectively, in response to the delay value output from the delay detector An output driver of the semiconductor device having a. delete The method of claim 1, The delay detector is A first flip-flop receiving the first output signal at a clock input terminal and the second output signal at a signal input terminal; A delay unit configured to receive the first output signal and delay the output signal by a predetermined value; A second flip-flop which receives the output of the delay unit at a clock input terminal and the second output signal at a signal input terminal; An or gate for receiving and outputting the positive output terminal of the first flip-flop and the positive output terminal of the second flip-flop; And NOR gate for receiving and outputting the positive output terminal of the first flip-flop and the sub-output terminal of the second flip-flop An output driver of the semiconductor device having a.

Images