JP2003076321A - Plasma display panel display device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PDP display device in which reactive power loss does not increase even though the pitch of sustaining pulses applied to display electrodes during a sustaining period while driving is reduced and high speed driving is conducted for a PDP display device having a highly precise PDP section such as a high vision and the device is driven with relatively low power consumption without increasing useless electric power loss. SOLUTION: In a pair of display electrodes, a driving waveform process is conducted in a sustaining period to timely superimpose from the rising interval of one of the electrode to the falling interval of the other electrode. Thus, without reducing the lengths of tr and tf (i.e., without making the gradients of the rising/falling of pulse waveforms steep), the intervals of sustaining pulses to be applied to the pair of display electrodes are made short.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel display device and a driving method thereof.

[0002]

2. Description of the Related Art A plasma display panel (PDP) display device has a pair of thin front panel glass and back panel glass that are opposed to each other through a plurality of partition walls, and red (R) and green are respectively disposed between the plurality of partition walls. (G), blue (B)
It has a phosphor layer of each color, and has a PDP part in which a discharge gas is enclosed in a discharge space which is a gap between both glass plates. A plurality of pairs of display electrodes each having a pair of scan electrodes (scan electrodes) and sustain electrodes (sustain electrodes) are formed on the front panel glass side. On the back panel glass side, a plurality of address electrodes (data electrodes) are arranged in parallel so as to be orthogonal to the display electrodes across the discharge space. After forming the electrodes, a dielectric layer is formed on the surface of the panel glass so as to cover the electrodes. A PDP drive unit is connected to the PDP unit as a drive device for driving the PDP unit, and becomes a PDP display device.

In the PD section, for the video data input from the external video equipment, the built-in preprocessor sets the display electrodes and address electrodes in the initialization period based on the drive waveform process.
Each pulse corresponding to the writing period, the sustaining period, and the erasing period is applied, and fluorescence is emitted by the discharge generated in the discharge gas. Has such a configuration
Even if the PDP display device has a large screen, the CRT of the conventional display
It is excellent in that the depth dimension and weight are unlikely to increase and the viewing angle is not limited. Currently PD
P-display devices are required to have large screens and high definition, and 50-inch and larger devices have been commercialized. It should be noted that as the screen of the PDP section becomes larger, the panel capacity also increases proportionately. Therefore, a PDP display device that consumes as little power as possible is desired.

In a general AC type PDP display device, a dielectric layer formed on the front panel surface so as to cover the display electrodes forms a capacitor having a relatively large capacitance in each region corresponding to the pair of display electrodes. (The capacitance of the capacitor is hereinafter referred to as "panel capacitance"). Therefore, when a drive voltage is applied to any pair of display electrodes, it simply moves back and forth between the capacitor and the power supply (just charges and discharges the dielectric layer).
The load is not consumed and reactive power loss occurs.

The reactive power P _{1 which} does not contribute to the discharge for display and which is required by the power source only to charge and discharge the capacitors of each panel capacitance is given by the following formula: C _p is the panel capacitance and V _s is the voltage of the applied pulse.

[0006]

[Equation 1] It is expressed as. This reactive power is
When a sustain pulse is repeatedly applied to each of the pair of display electrodes, a power loss of a non-negligible amount appears. Therefore, as the size of the PDP increases, the panel capacity also increases, and the power consumption due to reactive power increases significantly.

As a countermeasure example for reducing the power consumption of such an AC PDP display device and improving the display efficiency, Japanese Patent Publication No. 7-10
Japanese Patent Laid-Open No. 9542 discloses sustain pulse generation circuits 112a and 112b as reactive power recovery circuits using an LC resonance circuit which is a tank circuit as shown in FIG. The circuit 112a,
In 112b, a pair of display electrodes (scan electrode 19a _N , sustain electrode 19a _N
b _N ), the panel area (shown as “panel” in the figure) facing each other in the dielectric layer is equivalently a capacitor, and a coil is provided for each of the scan electrode 19a _N and the sustain electrode 19b _N. 310, 311 and capacitors 308, 309 are connected in series to form a reactance circuit. The circuit 112a, 11
Switching elements 300 to 307 are arranged in 2b, and PDs are connected to these.
Control signal 5 from the preprocessor which is the main control unit of the P drive unit
0-57 is transmitted. While the control signals 50 to 57 are outputting a high level, the target switching element
300 to 307 are turned on, scan electrode 19a _N , sustain electrode 19b _N
Power from external power supply Vsus or capacitor against 30
The power due to 8,309 is supplied. Diode 312-3
Reference numeral 15 has a rectifying function when a current flows through the circuits 112a and 112b.

Such sustain pulse generation circuits 112a and 112b
, The drive waveform is as shown in Fig. 24 (a).
This is a process in which pulses having a slightly gentler shape in the rising period and the falling period are alternately applied. This circuit
At 112a and 112b, the reactive power is recovered during the falling period of this pulse, and the recovered reactive power is supplied to the scan electrodes 19a _N and sustain electrodes 19b _N during the rising period of the pulse. In the conventional drive waveform process, as shown in FIG. 24 (a), in the sustain period, after the sustain pulse to one of the scan electrode 19a _N and the sustain electrode 19b _N is completed, the sustain pulse is applied to the other electrode. It is like this.

The operation based on the sustain pulse in FIG.
An example of road operation will be described. First, display electrode 19a_NOf sustaining pulse
During the rising period, the switching elements 303, 304
Is turned on, and the capacitor already stored in the capacitor 308 is invalid.
Power display electrode 19a_NApply to. Switching at this time
The element 307 is also turned on. Then, next, the switching element 300,
Turn on 303, display electrode 19a_NSustain voltage V_sApply and display
Electrode 19b_NGround. Then switching elements 303, 30
Turn ON 5,307 and display electrode 19a again _NTo capacitor 309
It accumulates electric charge and recovers reactive power. This series of operations
The display electrode 19b_NThe same applies to.

In this way, the sustain pulse generating circuit 112a,
In 112b, the recovered reactive power is applied to the display electrodes 19a _N and 19b _N during the rising period of the sustain pulse during the falling period of the sustain pulse, and the reactive power is effectively used to reduce power loss and display efficiency. To improve. Here, the reactive power loss of sustain pulse generating circuits 112a and 112b will be considered. Now, the rising period of the sustain pulse P _s is t _r ,
Assuming that the series resistance of the sustain pulse generating circuit 112a (or 112b) and the panel resistance is R and the inductance of the coil 310 is L, the reactive power loss P ₂ per sustain pulse is

[0011]

[Equation 2] become that way. In this case, t _r and L are correlated, so only one of them cannot be changed. Therefore, this equation shows that when the reactive power recovery is performed using the sustain pulse generation circuits 112a and 112b, the power loss is reduced by (t _r R / 4L) compared to the case where the reactive power recovery is not performed at all. Shows.

The above (Formula 2) holds even _{if the} falling period t _f is substituted for the rising period t _r . Further, generally, there is a relation of the following equation between the rising period t _r or the falling period t _f (here, t _s ) of the pulse and the inductance L of the coil 310 and the panel capacitance C _p .

[0013]

[Equation 3] Substituting this (Equation 3) into (Equation 2)

[0014]

[Equation 4] Becomes Therefore, the sustain pulse generating circuits 112a and 112b are
When using, the reactive power loss increases as the rising period t _r or the falling period t _{f of} the pulse decreases.

[0015]

In recent years, there has been a demand for higher definition of the PDP section and larger screen. In order to increase the definition of the PDP section, it is required to increase the number of scanning lines and to narrow the pitch of the sustain pulse applied to the display electrodes during driving to drive the PDP section at high speed.

However, if the width of the top of the pulse is made too narrow, the rising period t _r or the falling period t _f of the pulse tends to be shortened accordingly. As described above, this can cause an increase in reactive power loss of the PDP display device, and is not desirable in reducing power consumption. The present invention has been made in view of the above problems,
The purpose is a PDP that has a high-definition PDP unit such as HDTV.
Even in the case of a display device, even if the pitch of the sustain pulse applied to the display electrode during the sustain period at the time of driving is shortened and driven at high speed, it is driven with relatively low power consumption without causing an increase in reactive power loss. An object of the present invention is to provide a PDP display device and a driving method thereof that can be performed.

[0017]

In order to solve the above problems, the present invention is directed to a second substrate with respect to a surface of a first substrate on which a plurality of pairs of display electrodes and a dielectric layer for covering the display electrodes are formed. And a PDP part arranged opposite to each other, and an LC resonance circuit for driving based on the time-division gray scale display method in the field and recovering the reactive power of the power supplied to each display electrode during driving. A driving method of a PDP display device having a PDP driving unit, wherein during a sustain period during driving, the PDP driving unit collects reactive power in an LC resonant circuit during a period when the sustain pulse falls and the sustain pulse rises. In the period, a cycle in which the collected reactive power is supplied to the display electrode as new power is executed, and in each cycle, a period in which the sustain pulse applied to the first electrode of the pair of display electrodes falls. The driving is performed so as to have a portion where the period in which the sustain pulse applied to the second electrode rises overlaps.

According to such a driving method, in the pair of display electrodes, the rising period of one electrode is overlapped with the falling period of the other electrode in terms of time.
Even if the rising period and the falling period of the sustain pulse (that is, the rising / falling gradient of the pulse waveform) are not made steep, the interval of the sustain pulses alternately applied to the pair of display electrodes can be shortened. Therefore, in the present invention, even if the PDP display device is, for example, a high-definition high-definition type and employs an intra-field time-division gray scale display method of high speed driving with a short subfield period, the sustain pulse width is not shortened as much as the conventional one. Therefore, it is possible to satisfactorily avoid an increase in reactive power loss, and it is possible to exhibit extremely efficient display performance.

In the present invention, when the period during which the sustain pulse applied to the first electrode falls is tf and the period during which the sustain pulse applied to the second electrode rises is t _r , t _f and t _r Have the highest effect in the case where all of them overlap temporally, that is, when the sustain pulses alternately applied by the pair of display electrodes are closest to each other. Further, in the present invention, even if the rising period t _r or the falling period t _f of the sustain pulse is slightly shortened, the effect of reducing the reactive power loss can be satisfactorily maintained, so that the power consumption can be effectively suppressed while performing high-speed driving. You can

Further, according to the present invention, a PDP portion in which a second substrate is disposed so as to face a first substrate surface on which a plurality of pairs of display electrodes and a dielectric layer for covering the display electrodes are formed, and in a field. A PDP display device having a PDP drive unit that is driven based on a time-division gray scale display method and has an LC resonant circuit for recovering reactive power of power supplied to each display electrode during driving. PDP during the maintenance period
The drive unit performs a cycle in which the LC resonant circuit recovers the reactive power in the period in which the sustain pulse falls, and supplies the collected reactive power as new power to the display electrode in the period in which the sustain pulse rises. Yes, and
In each cycle, a part of the pair of display electrodes may have a portion in which the period in which the sustain pulse applied to the first electrode falls and the period in which the sustain pulse applied to the second electrode rises overlap. .

In this case, when the sustain pulse applied to one electrode falls during the period t _f and the sustain pulse applied to the other electrode rises during the period t _r , the PDP driving unit defines t _f and t. _It is also possible to adopt a configuration in which the _r's are driven so that they are completely overlapped in time. Further, the PDP section may include individual LC resonance circuits connected to each display electrode.

Further, according to the present invention, the PDP section in which the second substrate is arranged so as to face the surface of the first substrate on which a plurality of display electrode pairs is formed is driven by an in-field time division gradation display system to display an image. In addition to displaying it, the reactive power is recovered from the power supplied to the PDP section to improve the display efficiency.
A PDP drive device, of the display electrode pair, a first reactive power recovery circuit that recovers reactive power from power supplied to the first electrode, and a reactive power recovery from power supplied to the second electrode. The second reactive power recovery circuit is electrically connected in series via the display electrode pair at one time in each subfield, and the reactive power recovered by one reactive power recovery circuit is transferred to the other reactive power recovery circuit. It is also possible to adopt a configuration in which a configuration for transferring via the display electrode pair is established.

In this case, one period in the subfield is a period in which the rising period of the sustain pulse applied to the first electrode and the falling period of the sustain pulse at the end of the sustain discharge of the second electrode overlap. Is desirable. Further, in the present invention, a voltage application circuit and a ground circuit are arranged in parallel in the first and second reactive power recovery circuits, respectively, during the sustain discharge, each reactive power recovery circuit is separated from the corresponding display electrode, Alternatively, the voltage application circuit may be connected to one of the display electrodes and the ground circuit may be connected to the other electrode.

In this case, the reactive power recovery circuit may be a reactance circuit. Specifically, it is desirable that the reactance circuit is an LC resonance circuit. Further, in the present invention, a first switch means for connecting and disconnecting the first electrode and the first reactive power recovery circuit, and a second switch means for connecting and disconnecting the second electrode and the second reactive power recovery circuit. ,
It is also possible to provide a control means for simultaneously turning on the first and second switch means in one period of each subfield.

Further, according to the present invention, a PDP portion in which a second substrate is arranged so as to face a first substrate surface on which a plurality of pairs of display electrodes and a dielectric layer for covering the display electrodes are formed, and the PDP portion. Part is driven based on the time division gray scale display method in the field
The PDP drive unit has a first reactive power recovery circuit for recovering the reactive power from the power supplied to the first electrode of each pair of display electrodes by the PDP drive unit, and the power supply to the second electrode. PDP display device having a second reactive power recovery circuit for recovering reactive power from the power, the first and second reactive power recovery circuit, the display electrode pair at one time of each subfield PDP display characterized in that it is electrically connected in series via the display electrode pair and the reactive power recovered by one reactive power recovery circuit is transferred to the other reactive power recovery circuit via the display electrode pair. Provide a device.

With the structure of such a PDP display device, the above-described driving method of the present invention can be realized. The reactive power recovery circuit may be a reactance circuit. Specifically, it is desirable that the reactance circuit is an LC resonance circuit. The present invention further includes first and second switch means for connecting / disconnecting each reactive power recovery circuit and the corresponding display electrode, and control means for connecting / disconnecting each switch means in each subfield. Can also be controlled such that there is a period in which the first and second switch means are simultaneously turned on.

In this case, one period in the subfield is a period in which the rising period of the sustain pulse applied to the first electrode and the falling period of the sustain pulse at the end of the sustain discharge of the second electrode overlap. . Furthermore, a voltage application circuit and a ground circuit are arranged in parallel in the first and second reactive power recovery circuits, respectively, and at the time of sustain discharge,
Each reactive power recovery circuit is separated from the corresponding display electrode, and instead the voltage application circuit is applied to one of the display electrodes.
The grounding circuit may be connected to the other electrode.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described with reference to the following preferred embodiments for carrying out the invention and the accompanying drawings, which are for the purpose of illustration and are not limited thereto. Should not be done. 1. Configuration of PDP Display Device Common to Each Embodiment 1-1. Configuration of PDP First, the overall configuration of the PDP display device according to the embodiment will be described.

This PDP display device is an AC surface discharge type (AC
Type) PDP section 10 (Fig. 1) and its driving device, PDP drive section 1
It consists of 00 (Fig. 5). In this PDP section 10, a front panel glass 11 and a back panel glass 12 are arranged parallel to each other and facing each other, and their outer peripheral portions are sealed. Stripe-shaped scanning electrode groups 19a _{1 to} 19a _N are provided as display electrodes on the facing surface of the front panel glass 11.
Further, the sustain electrode groups 19b _{1 to} 19b _N are arranged in parallel so as to form pairs alternately. The electrode group 19a _{1 to} 19a _N , 19b _{1 to} 19
The b _N is covered with a dielectric layer 17, and the surface of the dielectric layer 17 is covered with a protective layer 18 (made of, for example, MgO). On the opposite surface of the back panel glass 12, stripe-shaped data electrode groups 14 _{1 to} 14 _M and a dielectric layer 13 (for example,
(Composed of MgO) is provided on the data electrode group 141.
A partition wall 15 is arranged in parallel with 14M. The gap between the front panel glass 11 and the back panel glass 12 is a partition wall 15.
It is partitioned by and is filled with discharge gas. The filling pressure of the discharge gas is usually about 100 to 500 Torr (1 x 1 Torr so that the inside of the panel is a negative pressure against the outside pressure (atmospheric pressure).
The pressure is set in the range of 0 ^{4 to} 7 × 10 ⁴ Pa), but it is advantageous to set a high pressure of 8 × 10 ⁴ Pa or higher to obtain high luminous efficiency.

FIG. 2 is a diagram showing an electrode matrix of the PDP section 10. The electrode groups 19a _{1 to} 19a _N , 19b _{1 to} 19b _N and the data electrode groups 14 _{1 to} 14 _M are arranged orthogonal to each other,
In the space between the front panel glass 11 and the back panel glass 12, discharge cells are formed at the intersections of the electrodes. Partitions 15 are provided between adjacent discharge cells to block discharge diffusion to the adjacent discharge cells, so that high-resolution display can be performed.

In the PDP section 10 for single color display, a mixed gas centered on neon is used as the discharge gas, and the display is made by emitting light in the visible region during discharge. In the PDP, a phosphor layer 16 made of phosphors of three primary colors of red (R), green (G) and blue (B) is formed on the inner wall of the discharge cell. The discharge gas includes, for example, a mixed gas centered on xenon (neon-xenon or helium-xenon), and color display is performed by converting ultraviolet rays generated by discharge into visible light of each color in the phosphor layer 16. I do.

The PDP section 10 is driven by using the in-frame time division gray scale display method. FIG. 3 is a diagram showing a method of dividing one frame in the case of expressing 256 gradations,
The horizontal direction indicates time, and the shaded area indicates the maintenance period. For example, in the example of the division method shown in FIG. 3, one frame has 8
This sub-field consists of 8 sub-fields, and the ratio of the sustain period of each sub-field is set to 1, 2, 4, 8, 16, 32, 64, 128.
Can express 56 gradations. It should be noted that in an NTSC television image, since the image is composed of 60 frames per second, the time for one frame is set to 16.7 ms.

Each subfield is composed of a series of sequences of an initialization period, a writing period, a sustaining period and an erasing period. FIG. 4 is a timing chart when a pulse is applied to each electrode in one subfield in the present embodiment. During the initialization period, the scan electrode group 19
The charge state of all discharge cells is initialized by applying an initialization pulse to all of a _{1 to} 19 a _N at once.

In the writing period, by applying the data pulse to the selected electrode in the data electrode groups 14 _{1 to} 14 _M while sequentially applying the scan pulse to the scan electrode groups 19 a _{1 to} 19 a _N , lighting is performed. Accumulates wall charges in the discharge cells that are about to
Write image information for the screen. In the sustain period, by applying sustain pulses while switching the polarities collectively between the scan electrode groups 19a _{1 to} 19a _N and the sustain electrode groups 19b _{1 to} 19b _N , the discharge cells in which the wall charges are accumulated are discharged. And emit light for a predetermined time.

Although the sustain pulse is shown as a simple rectangular wave in FIG. 4 for the sake of convenience, in the concrete embodiment of the present invention, as shown in FIG. 9, in the rising period of the pulse and the falling period of the pulse, the sustain pulse is gentle. It has a waveform that gradually increases or decreases. The formation of this waveform will be described later in detail. In the erase period, a narrow erase pulse is collectively applied to the scan electrode groups 19a _{1 to} 19a _N to erase the wall charges of the discharge cells.

1-2. Basic Driving Method of PDP Display Device FIG. 5 is a block diagram showing the configuration of the PDP driving unit 100.
The PDP driving unit 100 includes a preprocessor 101 that processes video data input from an external video output device, a frame memory 102 that stores the processed video data, and a synchronization that generates a synchronization pulse for each frame and subfield. A pulse generator 103, a scan driver 104 that applies a pulse to the scan electrode groups 19a _{1 to} 19a _N , a sustain driver 105 that applies a pulse to the sustain electrode groups 19b _{1 to} 19b _N, and a pulse to the data electrode groups 141 to 14M. It comprises a data driver 106.

The preprocessor 101 extracts video data for each frame (frame video data) from the input video data and creates video data for each subfield (subfield video data) from the extracted frame video data. It is stored in the frame memory 102. Also,
Data is output to the data driver 106 line by line from the current subfield video data stored in the frame memory 102, and a sync pulse such as a horizontal sync signal or a vertical sync signal is detected from the input video data to generate a sync pulse. A synchronization signal is also sent to the generation unit 103 for each frame and each subfield. Also, control signals 50 to 57 (Fig. 9) are sent to the switching devices 300 to 307 (Fig. 8) in the sustain pulse generation circuits 112a and 112b to turn these elements ON / OFF.
Is controlled to form a sustain pulse having a predetermined shape.

The frame memory 102 is capable of dividing and storing each sub-field video data for each frame. Specifically, the frame memory 102 is a 2-port frame memory having two memory areas for one frame (for example, 8 subfield images are stored in the example of FIG. 3), and one of the memory areas is used. While writing the frame video data, the operation of reading the frame video data written in the other memory area can be alternately performed.

The sync pulse generator 103 includes a preprocessor 1
With reference to the sync signal sent from 01 for each frame and subfield, initialization pulse, scan pulse,
A trigger signal for instructing the timing of raising the sustain pulse and the erase pulse is generated and sent to each of the drivers 104 to 106. The scan driver 104 responds to the trigger signal sent from the synchronization pulse generation unit 103, in response to the initialization pulse,
A scan pulse, a sustain pulse, and an erase pulse are generated and applied to any of the scan electrodes 19a _{1 to} 19a _N.

FIG. 6 is a block diagram showing the configuration of the scan driver 104. The reset pulse, the sustain pulse, and the erase pulse are commonly applied to all the scan electrodes 19a _{1 to} 19a _N. Therefore, as shown in FIG. 6, scan driver 104 is provided with three pulse generation circuits (initialization pulse generation circuit 111, sustain pulse generation circuit 112a, erase pulse generation circuit 113) for generating each pulse. ing. Then, these three pulse generation circuits 111, 112a, 11
3 is connected in series by a floating ground method and operates in response to a trigger signal from the synchronization pulse generation unit 103, so that an initialization pulse, a sustain pulse, and an erase pulse are selectively generated, and the scan electrode group 19a ₁ ~. It is designed to be applied to 19a _N.

Further, the scan driver 104 includes the scan electrodes 19a.
_In order to apply the scan pulse to ₁ , 19a ₂ , ..., 19a _N in order, as shown in FIG.
And a multiplexer 115 connected thereto, and a method is adopted in which a pulse is generated by the scanning pulse generation circuit 114 and is switched and output by the multiplexer 115 in accordance with the trigger signal from the synchronization pulse generator 103. It is also possible to adopt a configuration in which a scan pulse generation circuit is provided individually for each scan electrode 19a.

Then, the above three pulse generation circuits 111 to 113
The switches SW1 and SW2 are provided to selectively apply the output from the scan pulse generating circuit 114 and the output from the scan pulse generating circuit 114 to the scan electrode groups 19a1 to 19aN. The sustain driver 105 (FIG. 5) includes a sustain pulse generation circuit 112b, generates a sustain pulse in response to the trigger signal from the synchronization pulse generator 103, and applies the sustain pulse to the sustain electrode groups 19b _{1 to} 19b _N.

The sustain pulse generating circuit 112a and the sustain pulse generating circuit 112b respectively have coils 310 and 311 as will be described later.
And as a tank circuit with capacitors 308, 309
It is an LC resonance circuit, and has a pair of scan electrodes 19a _N and sustain electrodes 19b _N.
It acts as a reactive power recovery circuit for recovering the reactive power of the power supplied during the period and improving the display efficiency.

The data driver 106 (FIG. 5), based on the sub-field information corresponding to one line is input serially, and outputs a data pulse to the data electrodes 14 ₁ to 14 _M in parallel. FIG. 7 is a block diagram showing the configuration of the data driver 106. The data driver 106
A first latch circuit 121 that takes in sub-field video data for each scanning line, and a second latch circuit 12 that stores it
2, data pulse generation circuit 123 for generating data pulses,
AND gate 124 provided at the entrance of each data electrode 14 _{1 to} 14 _M
It is composed of _{1 to} 124 _M.

In the first latch circuit 121, the preprocessor 10
CLK the subfield video data sent in sequence from 1
Several bits are sequentially captured in synchronization with the signal, and sub-field image data for one scanning line (data electrodes 14 _{1 to} 14 _M
Information indicating whether or not to apply the data pulse for each of the above) is latched, and the data is collectively moved to the second latch circuit 122. The second latch circuit 122 is a sync pulse generator.
In response to the trigger signal sent from 103, AND gate
Data electrode for applying data pulse in 124 _{1 to} 124 _M 14
Open those corresponding to _{1 ~14 M.} Then, the data pulse generation circuit 123 generates a data pulse in synchronization with this. As a result, the data pulse is applied to the data electrodes 14 _{1 to} 14 _M corresponding to the ones in which the AND gates are opened.

In such a PDP driving section 100, as shown below, the operation for one sub-field constituted by a series of sequences of an initialization period, a writing period, a sustaining period and an erasing period is shown in FIG. In the example, the image display of one frame is performed by repeating eight times. During the initialization period, the switch SW1 of the scan driver 104
Is turned on and SW2 is turned off, and by applying an initialization pulse to all scan electrodes 19a collectively by the initialization pulse generation circuit 111, initialization discharge is performed in all discharge cells, and wall charges are generated in each discharge cell. Accumulate. Here, by applying a certain wall voltage to each discharge cell, the rise of the write discharge in the next write period can be accelerated.

In the writing period, the scan driver 10
The switch SW2 of 4 is turned on and the switch SW1 is turned off (FIG. 6), and the scan pulse of the negative voltage generated by the scan pulse generation circuit 114 is applied to the scan electrode 19a _{1 of the first} row to the scan electrode 19a _{N of the} last row. Applied in order. Then, this timed, data driver 106, the one that corresponds to the lighting try to discharge cells in the data electrodes 14 ₁ to 14 _M, a write discharge by applying a data pulse of the positive voltage Then, wall charges are accumulated in the discharge cell. In this way, by accumulating wall charges on the surface of the dielectric layer 17 of the discharge cell to be lit, one screen of image information is written.

The pulse width (writing pulse width) of the scan pulse and the data pulse is usually set to about 1.25 μsec or more. In the sustain period, the switch SW1 of the scan driver 104 is turned on and the switch SW2 is turned off, and the sustain pulse generation circuit 112 is turned on.
The operation of applying a sustain pulse of a constant length (for example, 1 to 5 μsec) collectively to the scan electrode groups 19a _{1 to} 19a _{N at a} , and the sustain electrode group 19b _{1 to} 19b at the sustain pulse generation circuit 112b of the sustain driver 105. _{The operation} of collectively applying a sustain pulse of a constant length to _N is alternately repeated.

As a result, in the discharge cell in which the wall charges have been accumulated during the writing period, discharge occurs when the potential of the surface of the dielectric layer 17 exceeds the discharge start voltage, and this sustain discharge is generated in the discharge cell. Along with this, ultraviolet light is emitted, and this is converted into visible light in the phosphor layer, so that visible light corresponding to the color of the phosphor layer is emitted. During the erase period, the switch SW1 of the scan driver 104 is ON and SW
2 is turned off, and a narrow erase pulse is collectively applied to the scan electrode groups 19a _{1 to} 19a _N from the erase pulse generation circuit 113 to generate incomplete discharge, thereby erasing the wall charge in each discharge cell. To do.

In the present invention, the waveform of the sustain pulse applied between the scan electrode groups 19a _{1 to} 19a _N and the sustain electrode groups 19b _{1 to} 19b _N and its effect during the sustain period during driving of the PDP display device. Since these are the main features, these will be described in detail in Embodiments 1 and 2 below. 2.Embodiment 12-1.
Detailed Configuration of Sustain Pulse Generation Circuit FIG. 8 is a diagram showing configurations of sustain pulse generation circuits 112a and 112b included in scan driver 104 and sustain driver 105, respectively. As shown in the figure, the sustain pulse generating circuits 112a and 112b
Is a tank circuit (LC resonance circuit), and a coil 310, 311 and capacitors 308, 309 are arranged in series to form a reactance circuit, and an arbitrary pair of display electrodes 19a _N , 19b _N
Rising period of sustain pulse during sustain period
In the fall period, each operates as a reactive power recovery circuit.

In the sustain pulse generating circuits 112a and 112b, the panel sandwiching the pair of display electrodes 19a _N and 19b _N is equivalently a capacitor, and the display electrodes 19a _N and 19b _N are respectively coiled.
310, 311 and capacitors 308, 309 are connected to each other so that electric power (voltage value Vsus) is supplied from an external power source. The switching elements 300 to 307 are included in the circuits 112a and 112b.
Are arranged, and control signals 50 to 57 are transmitted to them from the preprocessor which is the main control unit of the PDP drive unit. While the control signals 50 to 57 are outputting a high level, the target switching elements 300 to 307 are in the ON state, and the power from the external power source Vsus or the capacitor is supplied to the scan electrodes 19a _N and the sustain electrodes 19b _N. Electric power due to 308 and 309 is supplied. The diodes 312 to 315 serve to rectify the current in the circuits 112a and 112b. According to such circuits 112a and 112b, the reactive power is collected in the capacitors 308 and 309 at the fall of the sustain pulse, and the collected reactive power is displayed electrode 19a _N in the rising period of the sustain pulse. It can be applied to 19b _N to reduce power loss due to reactive power.

2-2. Operation by Sustain Pulse Generation Circuit Here, in the first embodiment, as shown in the timing chart of the sustain pulse for the display electrode of FIG. 9, in the pair of display electrodes 19a _N and 19b _N , Rise of pulse
It has the feature that the waveforms are set so that the respective periods required for the fall are completely overlapped in time. Due to this feature, in the PDP display device of the first embodiment, it is possible to perform high-speed driving with good power consumption without causing a significant increase in loss of reactive power.

Sustain pulse generation circuit 112 of the first embodiment
During period A during the maintenance period, the reactive power recovery operation by a and 112b is performed.
(Rising pulse to the scan electrodes, the pulse fall of the sustain electrodes), period B (V _s voltage applied to the scanning electrodes, grounding the sustain electrode), falling pulse falling to the period C (scanning electrodes,
The pulse rise to the sustain electrode) and the period D (scan electrode is grounded, Vs voltage is applied to the sustain electrode) will be described with reference to FIGS. 10 to 13. FIG. 9 shows ON / OFF (High / Low) states of the control signals 50 to 57 for the switching elements 300 to 307. P _s in FIG. 9 shows a sustain pulse applied to the panel by the display electrodes 19a _N, 19b _N. Figure 10 (a) ~ Figure 13
In (a), the flow of current is indicated by an arrow for easy understanding.

* Period A (pulse rising to scan electrode,
Pulse falling to sustain electrode). Each waveform of the pair of display electrodes 19aN and 19bN at this time is the region shown in FIG. 10 (a). In the first embodiment, as a main characteristic, a pair of display electrodes 19a _N, a waveform rising period t _r and fall period t _f overlap completely in the sustain pulse waveform to 19b _N, one electrode The total time t _{e r} from the rising period of the applied sustain pulse to the end of the falling period of the sustain pulse applied to the other electrode is t _r = t _f = t
_er .

At the beginning of the period A in FIG. 10A, the scanning electrodes 19a _N
Is the ground potential, and the sustain electrode 19b _N is the sustain voltage Vs. In the beginning of this period A, the switching elements 301, 302, 305, 306 are turned on in the sustain pulse generating circuits 112a, 112b,
The reactive power resulting from the previous sustain pulse is stored in the capacitor 308. Switching element 30 in this state
Turn off 1, 302, 305, 306, and control signals 5 to 304, 307 at the same time.
Send 4, 57 to turn them on. At this time, the capacitors 308 and 309 in the sustain pulse generation circuits 112a and 112b are connected to the coil 31.
It is in a state of being electrically connected with 0, 311 and the panel sandwiched therebetween. With this, in the circuit 112a, as shown in FIG. 10A, the reactive power accumulated in the capacitor 308 charges the panel side by the LC resonance effect, and the voltage of the scan electrode is changed from the ground potential.
Pull up to V ₁ . At the same time, in the sustain pulse generation circuit 112b, the charge generated by charging the panel side is stored in the capacitor 309 by the LC resonance effect of the circuit 112b, and the voltage of the sustain electrode 19b _N is changed from V _s to V ₂ . Can be lowered.

<Reason and effect of temporally overlapping the rising period and the falling period of each sustain pulse applied to the pair of display electrodes 19a _N , 19b _N > In recent PDP display devices, high definition display performance such as high definition Therefore, with the increase in the number of scanning lines, the driving time is required to be shortened in the general PDP display method which adopts the time division gray scale display method in the field.

Due to such a background, it is desired to cope with the speedup of the maintenance period, but in the case of the PDP display device having the reactive power recovery circuit, the purpose is to shorten the maintenance period as described above (Formula 4). If care is taken to reduce t _r and t _f , the reactive power loss will increase.
FIG. 24 (a) shows a waveform example of a conventional sustain pulse applied to scan electrode 19a _N and sustain electrode 19b _N. Conventionally figure
As shown in FIG. 24 (b), the total time t _f0 of the rising and falling periods of the pair of display electrodes is shortened from the state of the waveform of 24 (a), and the pulse width is narrowed to t _f1 to reduce the pulse width. Attempting to shorten the whole leads to a significant increase in reactive power.

Then, as a result of intensive investigations by the present inventors,
In the pair of display electrodes, a drive waveform process is used in which the rising period of one electrode and the falling period of the other electrode are temporally overlapped in the sustain period. This gives t _r , t _f
Without shortening (that is, the rising edge of the pulse waveform
It is possible to shorten the interval between the sustain pulses applied to the pair of display electrodes (without making the falling slope steep). Therefore, in the first embodiment, even if the PDP is a high-definition high-definition high-speed drive system, the sustain pulse width does not need to be as short as in the conventional case, so that an increase in reactive power loss is satisfactorily avoided. Therefore, it is possible to exhibit extremely efficient display performance.

In period A, a slight power loss occurs due to the circuit included in the PDP display device, so that the scan electrode 19
The voltage between a _N and sustain electrode 19b _N is not completely reversed from the initial voltage.
This potential difference is compensated for in the next period B. * Period B (V _s voltage applied to scan electrode, sustain electrode grounded). By simultaneously turning on switching elements 300 and 303, the voltage of the scan electrode is raised from V ₁ to sustain voltage V _s . At the same time, the voltage on the sustain electrode drops from V ₂ to ground voltage.

* Period C (falling pulse to scan electrode,
Next, the switching elements 300, 303, 304, 307 are turned off at the same time, and then the switching elements 305, 306 are turned on at the same time, so that the capacitors in the sustain pulse generation circuits 112a, 112b are turned on again. 308, 3
09 is in a state of being electrically connected to the coils 310 and 311 via the panel. As a result, in the sustain pulse generation circuit 112a, as shown in FIG. 12 (a), the charge stored in the panel is recovered in the capacitor 308 by the LC resonance effect, and the voltage of the scan electrode 19a _N is changed from the sustain voltage V _s to V ₂ Down to. At the same time, in the sustain pulse generation circuit 112b, the capacitor 309
The electric power stored in the panel is charged to the panel side by the LC resonance effect, and the voltage of the sustain electrode 19bN is raised from the ground voltage to V ₁ . The voltage change of the display electrodes 19a _N and 19b _N in the period C is completely opposite to the operation in the period A.

* Period D (scan electrode is grounded, V _s voltage is applied to sustain electrode). Next, switching elements 301 and 302 are simultaneously turned on to lower scan electrode 19a _N from V ₂ to the ground voltage. At the same time, the voltage of the sustain electrode is raised from V ₁ to V _s . The voltage change of the display electrodes 19a _N and 19b _N in the period D is completely opposite to the operation in the period B. In this way, in the first embodiment, the series of operations from the period A to the period D is repeatedly performed to perform the reactive power recovery operation.

As is clear from the flow of the above period A to period D, in the present embodiment 1, while the reactive power is recovered from one electrode of the pair of display electrodes 19a _N , 19b _N , the other electrode is previously collected. The accumulated reactive power is supplied as new power. Therefore, it is faster than the conventional drive waveform process, and power consumption can be suppressed at the same time.
2-3. For PDP display device according to the first performance measurement experiment present, was examined the relationship of the reactive power loss and duration t _r, t _f. The measurement results are shown in the graph of FIG. 23 (a) and the measurement value table of FIG. 23 (b).

As is apparent from this figure, the first embodiment
It was found that in the PDP display device of the present invention, the loss of the reactive power can be suppressed better than that of the conventional PDP display device in the approximate range of the time required to collect the reactive power.
Especially among period t _r, t _f is from 600ns to 1000 ns, that loss dramatically reactive power than a conventional PDP display device can be suppressed revealed.

Therefore, from this data, the present invention has an effect that the loss of the reactive power does not increase so much even _{if the} periods t _r and t _f are slightly shortened. That is, there is a possibility that the drive speed can be dramatically increased as compared with the conventional case with the reactive power loss value that is approximately the same as the conventional case. However, when actually setting the periods t _r and t _f , it is desirable to determine the reactive power loss values at that time while measuring and comparing them. 3. Second Embodiment In the second embodiment, the configuration of the PDP display device is the same as in the first embodiment.
Is the same as.

In the first embodiment, the sustain pulse waveforms for the scan electrodes and the sustain electrodes have respective rising periods _tr.
The pulse waveforms in which the falling periods t _f are completely overlapped with each other, and the total time t _er from the rising of one electrode to the falling of the other electrode is t _r = t _f = t _er is shown in the example. However, in the present invention, any effect can be expected as long as it is a sustain pulse waveform having a time taken for the rising of the one electrode to overlap with the time taken for the falling of the other electrode for at least one hour.

As an example thereof, the second embodiment is shown in FIG.
Shown in the timing chart of sustain pulse for display electrode
To the sustain electrode as compared to the waveform at the scan electrode.
Waveforms in the rising and falling periods
Example of overlapping by 1/3, that is, t _er= (t_r+ t_f) -t_fIn case of / 3
This is disclosed. Here, in the second embodiment,
Separate the sustain pulse waveform by the period ABCD
There is a rising period and a falling period of
And period B is further divided into a1 to a3 and c1 to c3, and FIGS.
It will be explained using 8. In Figures 15 (a) to 18 (a), the arrow
Therefore, the flow of current is shown. 14 switching
ON / OFF state of control signals 50-57 for elements 300-307 (Hi
gh / Low state).

[0067] 3-1. Operation according to the sustain pulse generating circuit * period A-a1 (ground scan electrodes, the pulse fall of the sustain electrodes). First, as shown in FIG. 15 (b), the scanning electrodes 19a _N is The switching elements 301, 302, 305, and 306 are turned off at the same time from the state where only the switching elements 301, 302, 305, and 306 are turned on at the ground potential and the sustain electrode 19b _N is at the sustain voltage V _s . After that, by turning on the switching element 307, the sustain pulse generating circuit 112b on the sustain electrode 19b _N side in FIG.
As shown in (a), the reactive power stored in the panel is recovered and stored in the capacitor 309.

* Period A-a2 (pulse rise to scan electrode, pulse fall to sustain electrode). Period A during period a2
When the switching element 14 is turned on at a time point corresponding to 1/3 of the power recovery time t _er from the start of, the capacitors 308 and 309 are electrically connected to the coils 310 and 311 via the panel. As a result, as shown in FIG. 16 (a), in the circuit 112a, the panel side is started to be charged with the reactive power stored in the capacitor 308. At the same time, in the circuit 112b, the reactive power is recovered from the panel side to the capacitor 309, the reactive power is started to be accumulated, and the sustain electrode 19bN is pulled down to V2.

* Period A-a3 (pulse rising to scan electrode, sustain electrode grounded). In period a3, switching element 13 is _{activated at} the time corresponding to 2/3 of the power recovery time t _er from the start of period A.
By turning on, as shown in FIG. 17 (a), the electric power stored in the capacitor 308 is continuously charged to the panel side,
Finally, the potential of the scan electrode 19a _N is raised to V ₁ . At the same time, the sustain electrode 19b _N is grounded from V ₂ .

* Period B (sustaining voltage Vs is applied to the scan electrode, sustaining electrode is grounded) In period B, as shown in FIG. 18 (a), switching element 300 is turned on and scan electrode 19a _N is switched from V ₁ to V ₁ Raise to the sustain voltage Vs. The sustain electrode 19b _N is kept at the ground voltage. * Period C-c1 (falling pulse to scan electrode, sustain electrode grounded). First, as shown in FIG. 19 (b), scan electrode 19a _N is sustain voltage V _s and sustain electrode 19b _N is ground voltage. From the state,
The switching elements 300, 303, 304, 307 are turned off at the same time. After that, by turning on the switching element 305, the sustain pulse generating circuit 112a on the sustain electrode a _N side is turned on.
As shown in 19 (a), the electric power stored in the panel is recovered and stored in the capacitor 308.

* Period C-c2 (pulse fall to scan electrode, pulse rise to sustain electrode). * Period during period c2
When the switching elements 305, 306 are turned on at a time corresponding to 1/3 of the power recovery time t _er from the start of C, the capacitors 308, 3
09 is in a state of being electrically connected to the coils 310 and 311 via the panel. This results in the circuit 1 as shown in Figure 20 (a).
In 12b, the panel side is started to be charged with the electric power stored in the capacitor 309. At the same time, in the circuit 112a, electric power is recovered from the panel side to the capacitor 308 and starts to store the electric power, and the scan electrode 19a _N is _{pulled down} from V _s to V ₂ .

* Period C-c3 (scan electrode is grounded, pulse rises to sustain electrode). In period c3, switching element 30 is _{activated at} the time corresponding to 2/3 of power recovery time t _er from the start of period C.
By turning on 6, the electric power stored in the capacitor 309 is continuously charged to the panel side as shown in FIG.
The potential of sustain electrode 19b _N is finally raised to V ₁ . At the same time, the scan electrode 19a _N is grounded from V ₂ .

* Period D (scan electrode is grounded, sustain electrode is maintained
Voltage V_sIn period D, as shown in Figure 22 (a), the
Turning on the switching element 301, the sustain electrode 19b_NTo V₁Maintained from
Voltage V_sUp to. Keep scan electrodes at ground voltage
One. As described above, in the second embodiment, in the maintenance period
Scanning electrode 19a_NAnd sustain electrode 19b _NIn the pulse waveform of
Rising period t_r・ Falling period t_fIf partially overlap
Even in the same manner as in the first embodiment,
Only rising period t _r・ Falling period t_fCan be shortened
It is possible to suppress the increase of reactive power while
High-speed driving even in high-definition PDP display devices such as
It can be realized with low power consumption. 4. Other matters In addition, the sustain pulse generating circuits 112a and 112b are arranged in the scan electrode group 19a.₁
~ 19a_NAnd sustain electrode group 19b₁~ 19b_NOne for each electrode of
Or divide these electrodes into smaller groups
You may arrange | position one by one.

[0074]

As is apparent from the above, according to the present invention, the second substrate is opposed to the surface of the first substrate on which a plurality of pairs of display electrodes and the dielectric layer for covering the display electrodes are formed. A PDP drive unit equipped with an installed PDP unit and an LC resonant circuit that drives based on the time-division gray scale display method in the field and recovers the reactive power of the power supplied to each display electrode during driving. A method of driving a PDP display device having, wherein the PDP driving unit includes:
In the period when the sustain pulse falls, the reactive power is recovered by the LC resonant circuit, and in the period when the sustain pulse rises, a cycle of supplying the recovered reactive power to the display electrode as new power is executed, and in each cycle. , Of the pair of display electrodes, the sustain pulse applied to the first electrode falls and the sustain pulse applied to the second electrode rises so as to have an overlapping portion. Even if the display device is, for example, a high-definition high-definition display and adopts a high-speed drive intra-field time-division gray scale display method with a short subfield period, it is not necessary to shorten the sustain pulse width as in the conventional case, so reactive power loss Can be satisfactorily avoided, and extremely efficient display performance can be exhibited.

[Brief description of drawings]

FIG. 1 is a partial perspective view showing a configuration of a PDP section.

FIG. 2 is a diagram showing a matrix of display electrodes and data electrodes of a PDP section.

FIG. 3 is a diagram illustrating a frame division method when driving a PDP display device.

FIG. 4 is a timing chart when a pulse is applied to a display electrode and a data electrode in one subfield.

FIG. 5 is a block diagram showing a configuration of a PDP display device.

FIG. 6 is a block diagram showing a configuration of a scan driver.

FIG. 7 is a block diagram showing a configuration of a data driver.

FIG. 8 is a diagram showing a configuration of each sustain pulse generation circuit of a scan driver and a sustain driver.

FIG. 9 is a detailed waveform of a sustain pulse in the sustain period of the first embodiment and a timing chart of ON / OFF of a control signal for a switching element in each sustain pulse generation circuit.

FIG. 10 is a diagram showing a detailed waveform of a sustain pulse and a current flow in each sustain pulse generating circuit in a period A.

FIG. 11 is a diagram showing a detailed waveform of a sustain pulse and a current flow in each sustain pulse generating circuit in a period B.

FIG. 12 is a diagram showing a detailed waveform of a sustain pulse and a current flow in each sustain pulse generating circuit in a period C.

FIG. 13 is a diagram showing a detailed waveform of a sustain pulse and a current flow in each sustain pulse generating circuit in a period D.

FIG. 14 is a detailed waveform of a sustain pulse in the sustain period of the second embodiment and a timing chart of ON / OFF of a control signal for a switching element in each sustain pulse generation circuit.

FIG. 15 is a diagram showing a detailed waveform of a sustain pulse and a current flow in each sustain pulse generation circuit during a period a1.

FIG. 16 is a diagram showing a detailed waveform of a sustain pulse and a current flow in each sustain pulse generation circuit in a period a2.

FIG. 17 is a diagram showing a detailed waveform of a sustain pulse and a current flow in each sustain pulse generation circuit in a period a3.

FIG. 18 is a diagram showing a detailed waveform of a sustain pulse and a current flow in each sustain pulse generating circuit in a period B.

FIG. 19 is a diagram showing a detailed waveform of a sustain pulse and a current flow in each sustain pulse generating circuit in a period c1.

FIG. 20 is a diagram showing a detailed waveform of a sustain pulse and a current flow in each sustain pulse generation circuit in a period c2.

FIG. 21 is a diagram showing a detailed waveform of a sustain pulse and a current flow in each sustain pulse generation circuit in a period c3.

FIG. 22 is a diagram showing a detailed waveform of a sustain pulse and a current flow in each sustain pulse generation circuit in a period D.

FIG. 23 is a diagram showing the relationship between the magnitude of reactive power and the reactive power recovery time in a conventional PDP display device and a PDP display device of the present invention.

FIG. 24 is a sustain pulse waveform in a conventional PDP display device provided with a sustain pulse generation circuit that is a reactive power recovery circuit (LC resonance circuit) in a scan driver and a sustain driver.

[Explanation of symbols]

19a _{1 to} 19a _N , 19b _{1 to} 19b _N Display electrode 14 _{1 to} 14 _M Data electrode 50 to 57 Control signal 100 PDP driver 112a, 112b Sustain pulse generation circuit 300 to 307 Switching element 308, 309 Capacitor 310, 311 Coil 312 ~ 315 diode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 641 G09G 3/28 HE

Claims (17)

[Claims] 1. A PDP section in which a second substrate is arranged so as to face a first substrate surface on which a plurality of pairs of display electrodes and a dielectric layer for covering the display electrodes are formed, and a time division floor in the field. A driving method of a PDP display device having a PDP driving unit equipped with an LC resonant circuit for driving based on a gradation display method and recovering reactive power of power supplied to each display electrode during driving. In the sustain period of time, the PDP drive unit collects the reactive power by the LC resonance circuit during the period when the sustain pulse falls, and supplies the collected reactive power as new power to the display electrode during the period when the sustain pulse rises. And a period in which the sustain pulse applied to the first electrode of the pair of display electrodes falls and a period in which the sustain pulse applied to the second electrode rises in each cycle. The driving method of the PDP display apparatus, characterized in that the drive so as to have a portion overlapping. 2. When t _{f is} a period during which the sustain pulse applied to the first electrode falls and t _r is a period during which the sustain pulse applied to the second electrode rises, t _f and t _r are time. 2. The method for driving a PDP display device according to claim 1, wherein the PDP display devices overlap each other. 3. A PDP section in which a second substrate is arranged so as to face a first substrate surface on which a plurality of pairs of display electrodes and a dielectric layer for covering the display electrodes are formed, and an intra-field time division floor. A PDP display device that has a PDP drive unit that is driven based on a gradation display method and that has a LC resonance circuit for recovering the reactive power of the power that is supplied to each display electrode during driving. In the period, the PDP drive unit recovers the reactive power by the LC resonance circuit in the period in which the sustain pulse falls, and the cycle in which the recovered reactive power is supplied to the display electrode as new power in the period in which the sustain pulse rises. The period during which the sustain pulse applied to the first electrode of the pair of display electrodes falls and the period during which the sustain pulse applied to the second electrode rises in each cycle. PDP display device characterized by a configuration in which the presence of a portion overlapping. 4. The PDP driving unit, when the period during which the sustain pulse applied to one electrode falls is t _f and the period during which the sustain pulse applied to the other electrode rises is t _r , t _f and t _r 4. The PDP display device according to claim 3, wherein the PDP display device is driven so as to be completely overlapped in terms of time. 5. The PDP unit includes an individual LC resonance circuit connected to each display electrode.
PDP display device described in. 6. A PDP section, in which a second substrate is arranged to face the surface of a first substrate on which a plurality of display electrode pairs are formed,
A PDP driving device that is driven by an in-field time division gray scale display method to display an image and that recovers reactive power from power supplied to the PDP section to improve display efficiency. Of the pair, a first reactive power recovery circuit that recovers the reactive power from the power supplied to the first electrode and a second reactive power recovery circuit that recovers the reactive power from the power supplied to the second electrode A configuration in which the reactive power recovered by one reactive power recovery circuit is transferred to the other reactive power recovery circuit via the display electrode pair at one time in each subfield and electrically connected in series via the display electrode pair. The PDP drive device is characterized in that 7. The one period in the subfield is a period in which the rising period of the sustain pulse applied to the first electrode and the falling period of the sustain pulse at the end of the sustain discharge of the second electrode overlap. 7. The PDP drive device according to claim 6. 8. The first and second reactive power recovery circuits are respectively provided with a voltage application circuit and a ground circuit in parallel, and at the time of sustain discharge, each reactive power recovery circuit is separated from the corresponding display electrode, 7. The PDP drive device according to claim 6, wherein the voltage application circuit is connected to one electrode of the display electrode and the ground circuit is connected to the other electrode instead. 9. The PDP drive device according to claim 6, wherein the reactive power recovery circuit is a reactance circuit. 10. The PDP drive device according to claim 9, wherein the reactance circuit is an LC resonance circuit. 11. The first switch means for connecting and disconnecting the first electrode and the first reactive power recovery circuit, and the second switch for connecting and disconnecting the second electrode and the second reactive power recovery circuit. 7. The PDP drive device according to claim 6, further comprising: means and a control means for simultaneously turning on the first and second switch means in one time period of each subfield. 12. A PDP section, in which a second substrate is arranged to face a first substrate surface on which a plurality of pairs of display electrodes and a dielectric layer for covering the display electrodes are formed, and the PDP section. A PDP drive unit that is driven based on the internal time division gray scale display method, and the PDP drive unit is a first for recovering reactive power from the power supplied to the first electrode of each pair of display electrodes. A PDP display device having a reactive power recovery circuit and a second reactive power recovery circuit for recovering reactive power from power supplied to a second electrode, wherein the first and second reactive power recovery circuits Is electrically connected in series via the display electrode pair at one time in each subfield, and transfers the reactive power recovered by one reactive power recovery circuit to the other reactive power recovery circuit via the display electrode pair. A PDP display device characterized in that a configuration is established. 13. The PDP display device according to claim 12, wherein the reactive power recovery circuit is a reactance circuit. 14. The PDP display device according to claim 13, wherein the reactance circuit is an LC resonance circuit. 15. Further comprising: first and second switch means for connecting / disconnecting each reactive power recovery circuit and the corresponding display electrode; and control means for connecting / disconnecting each switch means in each subfield, 13. The PDP display device according to claim 12, wherein the control means controls such that there is a period in which the first and second switch means are simultaneously turned on. 16. The one time period in the subfield is a time period in which the rising period of the sustain pulse applied to the first electrode and the falling period of the sustain pulse at the end of the sustain discharge of the second electrode overlap. Claim 12 characterized in that
PDP drive device described in. 17. The first and second reactive power recovery circuits are respectively provided with a voltage application circuit and a ground circuit in parallel, and at the time of sustain discharge, each reactive power recovery circuit is separated from the corresponding display electrode, 13. The PDP drive device according to claim 12, wherein the voltage application circuit is instead connected to one electrode of the display electrode and the ground circuit is connected to the other electrode.