JP2002351395A - Driving device of plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plasma display panel(a PDP) that has a high picture quality and is manufactured at a low cost, by realizing a low voltage driving of data electrodes in a writing interval. SOLUTION: The plasma display panel is provided with a plurality of opposing first and second display electrodes located between a pair of parallel substrates and data electrodes that are arranged orthogonal to the first display electrodes. The panel has at least an initializing period, a writing period, a maintaining period and an erasing period. The time constant of a falling applied voltage in the initializing period is made longer than the time constant of priming attenuation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel, particularly, a facing three-electrode surface discharge type AC plasma display panel, and more particularly to a low-voltage driving for high definition.

[0002]

2. Description of the Related Art A plasma display panel is a display that excites and emits a phosphor by ultraviolet rays generated by gas discharge to display an image. The discharge can be classified into an alternating current (AC) type and a direct current (DC) type based on the method of forming the discharge. The AC type is characterized by being superior to the DC type in luminance, luminous efficiency, and life. Furthermore, among the AC types, the reflection type surface discharge type is the most common because it is particularly outstanding in terms of luminance and luminous efficiency.

FIG. 2 is a perspective view schematically showing an AC type plasma display panel (hereinafter, referred to as a PDP) as an example of the related art. Thus, the PDP has R (red), G
A large number of cells that emit light of each color (green) and B (blue) are arranged.

[0004] The structure and operation will be described below. First, the description will be made from the front panel FP side. A plurality of transparent electrodes 34 (ITO or SnO ₂ is used) are formed on the front panel glass 21 (most commonly, a glass plate is used). However, this transparent electrode 3
No. 4 has a high sheet resistance and cannot supply sufficient power to all the pixels in a large panel. Therefore, a silver thick film, an aluminum thin film, chromium / copper / chromium (Cr / Cu / Cr) 3) Bus electrode 3 with laminated thin film
5 are formed. The bus electrode 35 apparently lowers the sheet resistance of the transparent electrode 34. A transparent dielectric layer 24 (low melting glass is used) on these electrodes
And protection layer 25 made of magnesium oxide (MgO)
Are formed. The dielectric layer 24 has a current limiting function peculiar to the AC type plasma display, and is a factor that can make the life longer than that of the DC type. Protective layer 25
Is used to protect the dielectric layer 24 from being sputtered by electric discharge so that the dielectric layer 24 has excellent sputter resistance, has a high secondary electron emission coefficient (γ), and reduces the discharge starting voltage. With.

The other back panel BP will be described. On the back panel glass 26, a data electrode 27 for writing image data, a base dielectric layer 33, a partition wall 28, and phosphor layers 30 (R), 31 (G), 32 (B) are formed. Here, the data electrode 27 and the partition 28
Are disposed so as to be orthogonal to the transparent electrode 34, and form a discharge space 29 by a space surrounded by two partition walls 28. In the discharge space 29, neon (Ne) is used as a discharge gas. And a mixed gas of xenon (Xe) at a pressure of about 66.5 kPa (500 Torr). Further, the partition wall 28 partitions the adjacent discharge cells to prevent erroneous discharge and optical crosstalk.

An AC voltage of several tens of kHz to several hundreds of kHz is applied between the transparent electrodes 34 to generate a discharge in the discharge space 29, and the fluorescent layers 30, 31, 32 are excited by ultraviolet rays from the excited Xe atoms. To generate visible light to perform a display operation.

Next, FIG. 3 shows an electrode arrangement diagram of this panel. The electrodes have an m × n matrix configuration, m columns of data electrodes D1 to Dm are arranged in the column direction, and n rows of scan electrodes SCN1 to SCNn and sustain electrodes SUS1 to SUSn are arranged in the row direction. ing.

FIG. 4 shows an operation drive timing chart of a driving method for driving this panel.

As shown in FIG. 4, one field period is
It is composed of first to n-th subfields having at least a writing period and a sustaining period. In each subfield, the number of sustaining pulses is different, and gradation is displayed by a combination of the subfields. It is assumed that one field includes at least one subfield having an initialization period or an erasing period. As an example, FIG. 4 shows a subfield having both the initialization period and the erasing period as an example.

Next, each period will be described.

First, an initialization pulse is applied to the scan electrodes SCN1 to SCNn in FIG. 3 to initialize wall charges in the discharge cells of the panel. Next, in the writing period, in order to perform display on the first row, a scan pulse voltage is applied to the scan electrodes SCN1 on the first row, and the data electrode groups D1 to D1 corresponding to the discharge cells are applied.
Dm, a write pulse voltage is applied to the data electrode group D1.
A write discharge (address discharge) is caused between .about.Dm and the scan electrode SCN1 in the first row, a wall charge is accumulated on the surface of the dielectric layer, and a write operation (address operation) in the first row is performed. The above operations are sequentially performed, and the writing operation of the Nth row is completed, and a latent image for one screen is written. Next, in the sustain period, the data electrode groups D1 to Dm are grounded, a sustain pulse voltage is first applied to all the sustain electrode groups SUS1 to SUSn, and then all the scan electrode groups SCN1 to SCN
By applying the sustain pulse voltage to n and subsequently applying the sustain pulse voltage alternately, the sustain discharge is continuously emitted in the discharge cells where the write operation has been performed in the write period. Is displayed on the screen. Thereafter, in the erasing period, a discharge is generated by applying a narrow erasing pulse, and the wall charges disappear, so that an erasing operation is performed.

As described above, image display is performed by a series of driving methods of the initialization period, the writing period, the sustaining period, and the erasing period.

[0013]

In the above conventional driving method, the write pulse voltage applied during the write period is limited by the withstand voltage of the output driver IC of the data electrode drive circuit, and the write pulse voltage cannot be sufficiently high. ,
In a panel having a high firing voltage, there is a problem that stable data writing is not performed, and image quality is deteriorated such as flickering or non-lighting of an image.

In particular, in driving a high-definition panel, it is necessary to end the discharge within a short write pulse time, and for that purpose, the data electrode drive voltage becomes higher than that in the case of VGA screen display. was there.

As a method for solving this problem, it is conceivable to use an IC having a high withstand voltage as the output driver IC. However, such a driver IC generally causes a large increase in the cost of a drive circuit. Had.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-quality and low-cost PDP by solving the above-mentioned conventional problems and realizing low-voltage driving of a data electrode during a writing period.

[0017]

In order to achieve the above object,
In the driving method of the plasma display panel according to the first aspect of the present invention, a plurality of first and second display electrodes facing each other are disposed between a pair of parallel substrates, and are arranged so as to be orthogonal to the first display electrodes. In a plasma display panel including a data electrode and including at least an initializing period, a writing period, a sustaining period, and an erasing period, a time constant of a fall of an applied voltage in the initializing period is longer than a time constant of priming decay. It is characterized by. A weak discharge occurs at the fall of the applied voltage during the initialization period, and the wall charges on the electrodes are erased. The voltage in the cell is equal to the discharge start voltage in the cell. At that time, if there is an influence of priming, the discharge start voltage further drops, and the wall charges are erased. At the writing time, the priming attenuates and the discharge start voltage returns to the original level, and the difference causes the data voltage to rise. In the present invention, the effect of priming is eliminated by erasing wall charges at the first sudden fall to the extent that a strong discharge does not occur, and gradually approaching the end point during initialization, thereby eliminating the effects of priming. In this case, the difference in the discharge start voltage can be eliminated, and the drive voltage at the time of writing can be reduced.

A driving method of a plasma display panel according to a second aspect of the present invention is characterized in that the time constant of the fall of the applied voltage during the initialization period is 3 μs to 20 μs.

According to a third aspect of the present invention, there is provided a driving method of a plasma display panel, wherein a plurality of first and second display electrodes opposed to each other are interposed between a pair of parallel substrates so as to be orthogonal to the first display electrodes. And a data electrode disposed therein, wherein in a plasma display panel including at least an initialization period, a writing period, a sustain period, and an erasing period, a plurality of gradients are provided for falling of the applied voltage in the initialization period. I do. In the case where a strong discharge occurs in the first aspect of the invention, by providing a plurality of gradients, a weak discharge is caused in a stepwise manner, and the absolute amount of priming can be reduced. This eliminates the difference between the discharge start voltage in the cell at the end of the initialization and that at the time of writing, and makes it possible to reduce the driving voltage at the time of writing.

A driving method of a plasma display panel according to a fourth aspect of the present invention is characterized in that a falling gradient of an applied voltage in the initialization period is 0.1 V / μs to 30 V / μs.

According to a fifth aspect of the present invention, there is provided a driving method of a plasma display panel, wherein a plurality of first and second display electrodes opposed to each other between a pair of parallel substrates are orthogonal to the first display electrodes. And a data electrode disposed therein, wherein in a plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, a fall of an applied voltage in the initializing period is changed in a subfield. . By changing in the sub-field, variations between a period in which priming is large and a period in which priming is small can be reduced, and low-voltage driving can be realized.

According to a sixth aspect of the present invention, in the method for driving a plasma display panel, a plurality of opposed first and second display electrodes are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. A plasma display panel comprising at least an initializing period, a writing period, a sustaining period, and an erasing period, wherein the falling of the applied voltage during the initializing period is a subfield having a rising edge of the initializing period. It is characterized in that it is changed in subfields that do not exist.

According to a seventh aspect of the present invention, in the method of driving a plasma display panel, a plurality of first and second display electrodes opposed to each other between a pair of parallel substrates so as to be orthogonal to the first display electrodes. In the plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, the falling of the applied voltage in the initializing period is set to the immediately preceding subfield in the erasing period. It is characterized by changing between subfields with and without subfields.

In a driving method of a plasma display panel according to an eighth aspect of the present invention, a plurality of opposed first and second display electrodes are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. In the plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, the falling of the applied voltage in the initializing period is turned on by the immediately preceding subfield. It is characterized in that it is changed between a subfield that has been turned on and a subfield that is not lit.

According to a ninth aspect of the present invention, in the method of driving a plasma display panel, a plurality of opposed first and second display electrodes are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. A plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, wherein a fall of an applied voltage during the initializing period is controlled by a subfield having a low discharge probability and a subfield having a high discharge probability. It is characterized by changing in the field.

The driving method of the plasma display panel according to the present invention is characterized in that the time constant of the fall of the applied voltage during the initialization period is longer than the time constant of the priming decay.

The driving method of a plasma display panel according to the present invention is characterized in that the time constant of the fall of the applied voltage during the initialization period is 3 μs to 20 μs.

A driving method of a plasma display panel according to a twelfth aspect of the present invention is characterized in that the fall of the applied voltage during the initialization period is lowered at a plurality of gradients.

A driving method of a plasma display panel according to a thirteenth aspect of the present invention is characterized in that the falling gradient of the applied voltage during the initialization period is 0.1 V / μs to 30 V / μs.

In a driving method of a plasma display panel according to a fourteenth aspect of the present invention, a plurality of opposed first and second display electrodes are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. In the plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, a final potential in the initializing period is changed in a subfield. By changing in the sub-field, variations between a period in which priming is large and a period in which priming is small can be reduced, and low-voltage driving can be realized.

According to a fifteenth aspect of the present invention, there is provided a driving method for a plasma display panel, wherein a plurality of first and second display electrodes opposed to each other between a pair of parallel substrates are orthogonal to the first display electrodes. In a plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, a final potential of the initializing period is changed between a subfield with initialization and a subfield without initialization. It is characterized by the following.

In a driving method of a plasma display panel according to a sixteenth aspect of the present invention, a plurality of opposed first and second display electrodes are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. A plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, and setting the final potential of the initializing period to a sub-field having an erasing period in the immediately preceding subfield. It is characterized by changing between a field and a non-subfield.

In a driving method of a plasma display panel according to a seventeenth aspect of the present invention, a plurality of opposed first and second display electrodes are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. In a plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, a final potential of the initializing period is set to a sub-field in which a previous sub-field was lit. It is characterized by changing between a field and a subfield that is not lit.

In the driving method of a plasma display panel according to the present invention, a plurality of opposed first and second display electrodes are provided between a pair of parallel substrates so as to be orthogonal to the first display electrodes. A plasma display panel including at least an initializing period, a writing period, a sustaining period, and an erasing period, wherein a final potential in the initializing period is changed between a subfield having a low discharge probability and a subfield having a high discharge probability. It is characterized by the following.

In a driving method of a plasma display panel according to a nineteenth aspect of the present invention, a plurality of first and second display electrodes opposed to each other between a pair of parallel substrates so as to be orthogonal to the first display electrodes. A plasma display panel comprising at least an initializing period, a writing period, a sustaining period, and an erasing period, wherein the final potential of the initializing period is changed between red, green, and blue of the phosphor. Features.

In the driving method for a plasma display panel according to the present invention, the final potential during the initialization period is -100.
V to + 50V.

[0037]

Embodiments of the present invention will be described below. Hereinafter, a method of driving the AC plasma display panel according to the present embodiment will be described with reference to FIGS.

Embodiment 1 A plasma display panel according to an embodiment of the present invention has the same components as a conventional plasma display panel. Figure 2 below
The production method will be described along the line.

(Overall Manufacturing Method of PDP) (Fabrication of Front Panel) The front panel FP has a transparent electrode 34 made of a transparent conductive material such as ITO or tin oxide (SnO ₂ ) and a silver ( Ag) thick film (thickness: 2 μm to 10 μm), aluminum (Al)
Thin film (thickness: 0.1 μm to 1 μm) or Cr / Cu /
Bus electrodes 35 composed of a Cr laminated thin film (thickness: 0.1 μm to 1 μm) are sequentially laminated, and further, lead oxide (PbO), bismuth oxide (Bi ₂ O ₃ ), or phosphorus oxide (PO ₄ )
As a main component (for example, 70% by weight of lead oxide (PbO),
15% by weight of boron oxide (B ₂ O ₃ ), silicon oxide (SiO ₂ )
Low melting point glass (thickness: 20 μm to 50%)
μm) is formed by screen printing (which can also be formed by die coat printing or film lamination). For example, in the case of a silver electrode, an ink for a silver electrode containing an ultraviolet-sensitive resin is uniformly applied onto the front glass panel 21 by a screen printing method, dried, and then formed by patterning and baking by exposure and development. Next, a protective layer 25 (thickness: 100 n) made of MgO that protects the dielectric layer 24 from being damaged by plasma.
m to 1000 nm) are formed and stacked by an electron beam evaporation method or a sputtering method.

(Preparation of Back Panel) On the back panel BP side, a silver (Ag) thick film (thickness: 2 μm to 10 μm) and an aluminum (Al) thin film (thickness: 0.1 μm to 1 μm) are formed on the back panel glass 26. ) Or Cr / Cu / C
The data electrode 27 made of a laminated thin film (thickness: 0.1 μm to 1 μm), lead oxide (PbO) or bismuth oxide (B
A base dielectric layer 33 made of low-melting glass (thickness: 5 μm to 20 μm) containing i ₂ O ₃ ) or phosphorus oxide (PO ₄ ) as a main component is formed. Further, partition walls 2 mainly composed of glass
8 are formed at a predetermined pitch, and phosphor layers 30, 31, and 32 made of a red phosphor, a green phosphor, and a blue phosphor are formed in each space sandwiched by the partition walls 28, thereby forming the back panel BP side. Have been. Here, the base dielectric layer 33 is for improving the adhesion to the partition wall 28, and does not mean that the plasma display panel does not operate without it. The phosphor is a red phosphor,
The phosphor layers 30, 31, and 32 are formed by applying a green phosphor and a blue phosphor, respectively, by an ink ejection method. As the phosphor of each color, phosphor materials generally used for a plasma display panel are shown below. Here, these phosphors are used.

Red phosphor: (Y _X Gd _{1 -X} ) BO ₃ : Eu
³⁺ or YBO ₃ : Eu ³⁺ green phosphor: BaAl ₁₂ O ₁₉ : Mn or Zn ₂ Si
O ₄ : Mn Blue phosphor: BaMgAl ₁₀ O ₁₇ : Eu ²⁺ Each color phosphor is produced as follows.

The blue phosphor is prepared by using barium carbonate (BaCO ₃ ), magnesium carbonate (MgCO ₃ ),
Aluminum oxide (α-Al ₂ O ₃ ) is mixed at a molar ratio of 1: 1 to 5: 1. Next, a predetermined amount of europium oxide (Eu ₂ O ₃ ) is added to the mixture. Then, the mixture is mixed with an appropriate amount of flux (AlF ₂ , BaCl ₂ ) in a ball mill, and calcined at 1000 ° C. to 1200 ° C. for a predetermined time (for example, 5 hours) in a weak reducing atmosphere (in H ₂ , N ₂ ). To obtain.

The red phosphor is prepared by mixing yttrium oxide (Y ₂ O ₃ ) and boric acid (H ₃ BO ₃ ) in a molar ratio of 0.5 to 1 as raw materials. Next, a predetermined amount of europium oxide (Eu ₂ O ₃ ) was added to the mixture, and the mixture was mixed with a proper amount of a flux by a ball mill.
After firing at 0 ° C. for a predetermined time (for example, 5 hours), this is sieved to obtain the powder.

The green phosphor is made of zinc oxide (Zn) as a raw material.
O), silicon oxide (SiO_Two) In a molar ratio of 2: 1
You. Next, a predetermined amount of manganese oxide is added to the mixture.
(Mn _TwoO_Three) Was added and mixed in a ball mill.
Firing at 50 ° C to 1200 ° C for a predetermined time (for example, 5 hours)
And sifting this to get it. After that, the ink ejection method
Red, green and blue phosphors (30, 3
1, 32) are formed.

(Preparation of PDP by Panel Lamination)
Next, the front panel and the back panel thus manufactured are attached to each other using sealing glass,
A high vacuum (1 × 1)
After exhausting to 0 ^-4 Pa), a plasma display panel is manufactured by filling a discharge gas having a predetermined composition at a predetermined pressure. As an example, the mixed gas of neon gas and xenon gas is 95% and 5% by volume, respectively, and the pressure is 66.5 kPa (500 Torr).

(Driving Method of PDP) The driving method of the plasma display panel according to the embodiment of the present invention has the same set values as those of the conventional driving method except for the Vb voltage and the downward slope portion of the initialization.

In a panel for VGA display (853 × 480 pixels), as an example, the pitch between partition walls is 360 μm, the thickness of the dielectric layer 24 is 42 μm, the thickness of the MgO protective layer 25 is 0.8 μm, and the scanning electrode 22 is formed. In a panel having a structure in which the gap between the electrode and the sustain electrode 23 is 80 μm and the height of the partition 28 is 120 μm, the voltage setting values in FIG.
-100V, Vc = -20V, Vd = 140V, Ve =
Reference is made to 150 V, Vs = 180 V, and Vdat = 67 V.

In a panel of a 42 inch class XGA display (1024 × 768 pixels), as an example, the pitch between partition walls is 300 μm, the thickness of the dielectric layer 24 is 35 μm, and
The thickness of the MgO protective layer 25 is 0.8 μm,
In a panel having a gap of 80 μm between the electrode and the sustain electrode 23 and a height of the partition wall of 120 μm, the voltage setting values in FIG. 4 are set to Va = 400V, Vb = −90V, Vc = −10V, V
d = 140V, Ve = 150V, Vs = 160V, Vd
At is based on 67V.

A method for driving an AC plasma display panel according to claims 1 to 4 of the present invention will be described. FIG. 1 shows an operation drive timing chart. The embodiment 1a in the figure shows claims 1 and 2, and the embodiment 1b shows claims 3 and 4.

The experiment was performed on a VGA panel, and the Vb voltage was 0 V. In the conventional drive, Vdat is 67V
Met. As for a, Vdat dropped to 55 V in the time constant of the voltage falling in the range of 3 μs to 20 μs. When the time constant was shorter than 3 μs, a strong discharge occurred and the amount of wall charge erased was large, so that Vdat was as high as 75 V or more.

A weak discharge occurs at the fall of the applied voltage for initialization, and the wall charges on the electrodes are erased. The voltage in the cell is equal to the discharge start voltage in the cell. At that time, if there is an influence of priming, the discharge start voltage further drops, and the wall charges are erased. At the writing time, the priming attenuates and the discharge start voltage returns to the original level, and the difference causes the data voltage to rise. In the present invention, to the extent that a strong discharge does not occur, the wall charge is erased at the first sharp fall, and gradually approaches the end point near the end point of initialization, thereby eliminating the influence of priming, and The discharge start voltage difference in the cell at the time of writing can be eliminated, and the drive voltage at the time of writing can be reduced.

The time constant of priming attenuation is 3 μs to 5 μm.
s, a longer time constant of 3 μs to 20 μ
By reducing the applied voltage at s, the rapid increase in the discharge scale is suppressed,
Maintains a weak discharge. Therefore, the time constant of the fall of the applied voltage is larger than the time constant of the priming decay, and
A range of 20 μs is desirable.

Regarding b, the falling gradient is 30 V
/ D, 1 V / μs, and 0.1 V / μs, and the slope is divided into three equal parts.
Descended. For the same reason as above, the slope range is
0.1 V / μs to 30 V / μs is desirable,
It is desirable that the later gradient is gentler.

Further, the same effect was obtained even if it was further subdivided or divided into two stages.

(Embodiment 2) Claims 5 to 13 of the present invention
A method of driving the AC plasma display panel will be described. FIG. 5 shows an operation drive timing chart. One field period includes an initialization period, a writing period,
It is composed of first to n-th subfields having a sustain period and an erase period. The structure of the panel is the first embodiment.
The description is omitted because it is the same as.

An example of a subfield in which the immediately preceding subfield is lit and a subfield that is not lit are shown as (m) subfield and (m + 2) subfield, respectively. In the case of a cell that was lit, the influence of priming and the like may remain, so in a, in the subfield that is not lit, a long time constant is set in the range of 3 μs to 20 μs, and in the subfield that was lit, The time constant is long in the range of 5 μs to 20 μs. b
Then, in the unlit subfield, 0.1V /
In the subfield that is set in the range of μs to 30 V / μs and is lit, the gradient is gently set in the range of 0.1 V / μs to 20 V / μs. As a result, the variation in Vdat of each subfield can be reduced from 7 V to 3 V, and low-voltage driving can be realized.

As an example of changing the fall of the applied voltage in the initialization period between a subfield having a rise in the initialization period and a subfield having no rise, the (m) subfield and the (m + 1) subfield are shown, respectively. . Here, in the subfield having the rise of the initialization period, the time constant is set to be longer in the range of 5 μs to 20 μs in a, and 0.1 V / μs to 20 V in b.
/ Μs in the range. As a result, the variation of Vdat of each subfield is reduced by 7 V
From 5 V to 5 V, and low-voltage driving was realized. This means that, in a subfield where the initializing period rises, the amount of wall charges to be erased in the initializing downstream is large, so that the priming amount is large. Therefore, it is effective to lengthen the time constant and make the gradient gentle.

As an example of a case where the fall of the applied voltage in the initialization period is changed between a subfield having an erasing period and a subfield having no erasing period in the immediately preceding subfield, (m + 1) subfield and (m + 2) Show as a subfield. Here, for the subfield having no erasing period in the immediately preceding subfield, in a, the time constant is set longer in the range of 5 μs to 20 μs, and b
Has a gentle gradient in the range of 0.1 V / μs to 20 V / μs. As a result, the variation in Vdat of each subfield can be reduced from 7 V to 5 V, and low-voltage driving can be realized. This means that in a subfield in which there is no erasing period in the immediately preceding subfield, the amount of wall charges to be erased in the initialization downflow is large, so that the priming amount is large. Therefore, it is effective to lengthen the time constant and make the gradient gentle.

As an example of the case where the fall of the applied voltage in the initialization period is changed between a subfield having a low discharge probability and a subfield having a high discharge probability, the (m + 1) subfield and the (m + 2) subfield are shown, respectively. Here, for the subfield having a higher discharge probability, the time constant is set longer in the range of 5 μs to 20 μs for a, and b
Has a gentle gradient in the range of 0.1 V / μs to 20 V / μs. As a result, the variation in Vdat of each subfield can be reduced from 7 V to 5 V, and low-voltage driving can be realized. This means that, in the subfield having a high discharge probability, the amount of wall charges to be erased at the time of initialization is large, so that the priming amount is large. Therefore, it is effective to lengthen the time constant and make the gradient gentle.

Incidentally, it is also effective to combine a and b.

(Embodiment 3) Claims 14 and 2 of the present invention
A method of driving the AC type plasma display panel for 0 will be described. FIG. 6 shows an operation drive timing chart. Since the configuration of the panel is the same as that of the first embodiment, the description is omitted.

As an example of a subfield in which the immediately preceding subfield is lit and a subfield which is not lit, the subfield is shown as (m) subfield and (m + 2) subfield, respectively. Unlit cells are not affected by priming or the like and tend to have a low discharge probability, so the final potential is set high to leave wall charges. As a result, the variation in Vdat of each subfield can be reduced from 7 V to 4 V, and low-voltage driving can be realized. This means that the priming amount increases in the subfield in which the previous subfield was lit. Therefore, by lowering the final potential, the amount of priming can be reduced and low voltage driving can be realized. Final potential is -100V
There was an effect in the range of + 50V.

Further, as an example of a subfield having a rise period of initialization and a subfield having no rise period, an (m) subfield and an (m + 1) subfield are shown, respectively. Here, a subfield having a rising period of initialization is set low.

As a result, the V of each subfield is
The variation in dat could be reduced from 7V to 5V, and low voltage driving was realized. This means that, in a subfield where the initializing period rises, the amount of wall charges to be erased in the initializing downstream is large, so that the priming amount is large. Therefore, by lowering the final potential, the amount of priming can be reduced and low voltage driving can be realized. Final potential is -100V
There was an effect in the range of + 50V.

As an example of a subfield having an erasing period and a subfield having no erasing period in the immediately preceding subfield, (m + 1) subfield and (m + 2) subfield are shown, respectively. Here, a subfield having no erasing period in the immediately preceding subfield is set low. As a result, the variation in Vdat of each subfield can be reduced from 7 V to 5 V, and low-voltage driving can be realized. This means that in a subfield in which there is no erasing period in the immediately preceding subfield, the amount of wall charges to be erased in the initialization downflow is large, so that the priming amount is large. Therefore, by lowering the final potential, the amount of priming can be reduced and low voltage driving can be realized. Final potential is -100V
There was an effect in the range of + 50V.

As an example of the case where the fall of the applied voltage in the initialization period is changed between a subfield having a low discharge probability and a subfield having a high discharge probability, (m + 1) subfield and (m + 2) subfield are shown, respectively. Here, a subfield having a high discharge probability is set low. As a result, the variation in Vdat of each subfield can be reduced from 7 V to 4 V, and low-voltage driving can be realized. This means that, in the subfield having a high discharge probability, the amount of wall charges to be erased at the time of initialization is large, so that the priming amount is large. Therefore, by lowering the final potential, the amount of priming can be reduced and low voltage driving can be realized. An effect was obtained when the final potential was in the range of -100V to + 50V.

Note that combining a and b is also effective.

[0068]

As described above, the effect of priming at the end of the initialization is eliminated, and the driving of the data electrode at a low voltage during the writing period can be realized.

[Brief description of the drawings]

FIG. 1 is an operation drive timing chart showing a method for driving an AC plasma display panel according to a first embodiment of the present invention;

FIG. 2 is a perspective view schematically showing an AC type plasma display panel.

FIG. 3 is an electrode arrangement diagram

FIG. 4 is a timing chart of a conventional drive waveform.

FIG. 5 is an operation drive timing chart showing a method for driving an AC plasma display panel according to a second embodiment of the present invention;

FIG. 6 is an operation drive timing chart showing a method for driving an AC plasma display panel according to a third embodiment of the present invention;

[Explanation of symbols]

 FP front panel BP back panel 21 front panel glass 22 scan electrode 23 sustain electrode 24 dielectric layer 25 protective layer 26 back panel glass 27 data electrode 28 partition wall 29 discharge space 30 phosphor (R) 31 phosphor (G) 32 phosphor (B) 33 dielectric layer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/66 101 G09G 3/28 BE (72) Inventor Ryuji Kurata 1006 Kadoma, Oji, Kadoma, Osaka Matsushita (72) Inventor Noriaki Nagao 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Ryuichi Murai 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. Reference) 5C058 AA11 BA02 BA04 5C080 AA05 BB05 CC03 DD03 DD24 DD27 EE29 HH02 HH04 HH06 HH07

Claims (20)

[Claims] 1. A plurality of first and second display electrodes facing each other between a pair of parallel substrates, and a data electrode arranged to be orthogonal to the first display electrodes, and at least initialization is performed. A plasma display panel comprising a period, a writing period, a sustain period, and an erasing period, wherein the time constant of the fall of the applied voltage in the initialization period is longer than the time constant of the priming decay. Method. 2. The method of driving a plasma display panel according to claim 1, wherein the time constant of the fall of the applied voltage during the initialization period is 3 μs to 20 μs. 3. A plurality of first and second display electrodes facing each other between a pair of parallel substrates and a data electrode arranged so as to be orthogonal to the first display electrodes, and at least initialization is performed. A plasma display panel comprising a period, a writing period, a sustaining period, and an erasing period, wherein the falling of the applied voltage in the initialization period is provided with a plurality of gradients. 4. The method of driving a plasma display panel according to claim 3, wherein the slope of the fall of the applied voltage during the initialization period is 0.1 V / μs to 30 V / μs. 5. A plurality of first and second display electrodes facing each other between a pair of parallel substrates and a data electrode arranged to be orthogonal to the first display electrodes, and at least initialization is performed. A method for driving a plasma display panel comprising a period, a writing period, a sustaining period, and an erasing period, wherein a fall of an applied voltage in the initialization period is changed in a subfield. 6. A plurality of first and second display electrodes opposed to each other between a pair of parallel substrates, and a data electrode arranged to be orthogonal to the first display electrodes, and at least initialization is performed. A plasma display panel comprising a period, a writing period, a sustaining period, and an erasing period, wherein the fall of the applied voltage in the initialization period is changed between a subfield having a rise of the initialization period and a subfield having no rise. Display panel driving method. 7. A plurality of opposed first and second display electrodes between a pair of parallel substrates and a data electrode arranged to be orthogonal to the first display electrode, and at least initialization is performed. Period, a writing period, a sustaining period, and an erasing period.In the plasma display panel, the fall of the applied voltage in the initialization period is changed between a subfield having an erasing period and a subfield having no erasing period in the immediately preceding subfield. Characteristic driving method of a plasma display panel. 8. A plurality of first and second display electrodes facing each other between a pair of parallel substrates, and a data electrode arranged to be orthogonal to the first display electrodes, and at least initialization is performed. Period, a writing period, a sustaining period, and an erasing period.In the plasma display panel, the fall of the applied voltage in the initialization period is divided into a subfield where the previous subfield was lit and a subfield which was not lit. A method for driving a plasma display panel, characterized by changing. 9. A plurality of first and second display electrodes facing each other between a pair of parallel substrates and a data electrode arranged so as to be orthogonal to the first display electrode, and at least initialization is performed. Period, a writing period, a sustaining period, and an erasing period. In the plasma display panel, the fall of the applied voltage in the initialization period is changed between a subfield having a low discharge probability and a subfield having a high discharge probability. Drive method. 10. The method of driving a plasma display panel according to claim 5, wherein the time constant of the fall of the applied voltage during the initialization period is longer than the time constant of the priming decay. 11. The driving method for a plasma display panel according to claim 10, wherein the time constant of the fall of the applied voltage during the initialization period is 3 μs to 20 μs. 12. The method according to claim 5, wherein the fall of the applied voltage during the initialization period is reduced by a plurality of gradients.
The method for driving a plasma display panel according to any one of the above. 13. The method of driving a plasma display panel according to claim 12, wherein the slope of the fall of the applied voltage during the initialization period is 0.1 V / μs to 30 V / μs. 14. A plurality of first and second display electrodes facing each other between a pair of parallel substrates, and a data electrode arranged so as to be orthogonal to the first display electrodes, and at least initialization is performed. In a plasma display panel including a period, a writing period, a sustaining period, and an erasing period, a final potential in the initialization period is changed in a subfield. 15. A plurality of first and second display electrodes facing each other between a pair of parallel substrates, and a data electrode arranged to be orthogonal to the first display electrodes, and at least initialization is performed. A plasma display panel comprising a period, a writing period, a sustaining period, and an erasing period, wherein a final potential in the initialization period is changed between a subfield with initialization and a subfield without initialization. 16. A plurality of first and second display electrodes facing each other between a pair of parallel substrates and a data electrode arranged so as to be orthogonal to the first display electrode, and at least initialization is performed. In a plasma display panel including a period, a writing period, a sustaining period, and an erasing period, the final potential of the initialization period is changed between a subfield having an erasing period and a subfield having no erasing period in the immediately preceding subfield. A method for driving a plasma display panel. 17. A method comprising: providing a plurality of opposed first and second display electrodes between a pair of parallel substrates; and a data electrode disposed so as to be orthogonal to the first display electrodes, and at least initializing the display electrodes. Period, a writing period, a sustaining period, and an erasing period.In the plasma display panel, the final potential of the initialization period is changed between a subfield where the previous subfield was lit and a subfield which was not lit. Characteristic driving method of a plasma display panel. 18. A plurality of first and second display electrodes opposed to each other between a pair of parallel substrates, and data electrodes arranged to be orthogonal to the first display electrodes, and at least initialization is performed. A plasma display panel comprising a period, a writing period, a sustaining period, and an erasing period, wherein a final potential in the initialization period is changed between a subfield having a low discharge probability and a subfield having a high discharge probability. 19. A plurality of first and second display electrodes facing each other between a pair of parallel substrates, and a data electrode arranged to be orthogonal to the first display electrode, and at least initialization is performed. A plasma display panel comprising a period, a writing period, a sustaining period, and an erasing period, wherein the final potential in the initialization period is changed between red, green, and blue phosphors. 20. The final potential in the initialization period is from -100 V to
The driving method of a plasma display panel according to any one of claims 14 to 19, wherein the driving voltage is + 50V.