KR100599728B1 - Driving apparatus and method of plasma display panel - Google Patents

Abstract

The present invention relates to a driving apparatus of a plasma display panel (PDP) and a driving method thereof. The plasma display driving method of the present invention reduces the ramp down period by dividing the ramp down period during the reset period into a first ramp down period in which the descending speed is high and a second ramp down period in which the descending speed is slow. At this time, the first ramp falling period makes the falling speed faster by using LC resonance. In this way, the brightness can be increased by shortening the reset period and using the remaining time in the sustain discharge section.

PDP, power recovery circuit, reset period, lamp, maintenance discharge

Description

Driving device of plasma display panel and driving method thereof {DRIVING APPARATUS AND METHOD OF PLASMA DISPLAY PANEL}

1 is a partial perspective view of a plasma display panel.

2 shows an electrode arrangement diagram of the plasma display panel.

3 is a driving waveform diagram of a conventional plasma display panel.

4 is a driving waveform diagram of a plasma display panel according to an exemplary embodiment of the present invention.

5 is a schematic circuit diagram of a plasma display panel driving circuit according to an embodiment of the present invention.

6A to 6D are diagrams showing current paths in respective modes of a reset period according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus for a plasma display panel (PDP) and a driving method thereof, and more particularly to a driving apparatus for a plasma display panel for reducing a reset time and a driving method thereof.

Recently, flat display devices such as a liquid crystal display (LCD), a field emission display (FED), and a PDP have been actively developed. Among these flat panel display devices, PDPs have advantages of high luminance and luminous efficiency and high viewing angles compared to other flat panel display devices. Therefore, the PDP is in the spotlight as a display device to replace the conventional cathode ray tube (CRT) in a large display device of 40 inches or more.

PDPs are flat display devices that display characters or images using plasma generated by gas discharge, and dozens to millions or more of pixels are arranged in a matrix form according to their size. Such PDPs are classified into a direct current type (DC type) and an alternating current type (AC type) according to the shape of the driving voltage waveform applied and the structure of the discharge cell.

The DC-type PDP is exposed to the discharge space, so that the current is exposed to the discharge space while the voltage is applied, so that the current flows in the discharge space while the voltage is applied. There are disadvantages to be given. On the other hand, in the AC PDP, the dielectric layer covers the electrode, so that the current is limited by the formation of a natural capacitance component, and the electrode is protected from the impact of ions during discharge.

1 is a partial perspective view of an AC plasma display panel.

As shown in FIG. 1, a scan electrode 4 and a sustain electrode 5 covered with a dielectric layer 2 and a protective film 3 are arranged in parallel on the first glass substrate 1. A plurality of address electrodes 8 covered with the insulator layer 7 are provided on the second glass substrate 6. A partition 9 is formed on the insulator layer 7 between the address electrodes 8 in parallel with the address electrode 8. The first glass substrate 1 and the second glass substrate 6 have a discharge space 11 therebetween so that the scan electrode 4 and the address electrode 8 and the sustain electrode 5 and the address electrode 8 are orthogonal to each other. They are arranged to face each other. The discharge space 11 at the intersection of the address electrode 8 and the pair of the scanning electrode 4 and the sustain electrode 5 forms a discharge cell 12.

2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 2, the electrodes of the plasma display panel are arranged in a matrix of m × n. Specifically, the address electrodes A1 -Am are arranged in the column direction and n rows of scan electrodes in the row direction. Y1-Yn and sustain electrodes X1-Xn are arranged in a zigzag. Hereinafter, the scanning electrode will be referred to as "Y electrode" and the sustain electrode as "X electrode". The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG.

In general, a driving method of an AC plasma display panel includes a reset period, an addressing period, and a sustain discharge period.

3 is a view showing the waveform of the X, Y electrodes according to the prior art.

As shown in Fig. 3, each subfield consists of a reset period, an address period, and a sustain period. In the rising period of the reset period, a weak discharge is generated in all the cells by applying a voltage slowly rising to the voltage Vset to the scan electrodes Y1-Yn. Next, in the falling period of the reset period, the wall charge is erased by applying a voltage falling gently to the negative level Vnf voltage while the sustain electrodes X1-Xn are biased to a constant voltage Ve. This initializes the wall charge state of each cell. In the address period, pulse voltages Vscl are sequentially applied to the lines of the scan electrodes while the scan electrodes Y1-Yn are biased at a constant voltage Vsch. At this time, the address voltage Va is applied to the discharge cells to be selected to the address electrodes A1-An. In the sustain discharge period, the sustain discharge voltage Vs is alternately applied to the scan electrodes Y1-Yn and the sustain electrodes X1-Xn to generate a discharge for actually displaying an image in the addressed cell.

That is, all the cells are initialized in the reset period, the cells to be discharged in the sustain discharge period are selected in the address period, and light emission is generated by the sustain discharge of the selected cells in the sustain discharge period. Therefore, the reset period during which light emission does not occur is short, and the sustain discharge period during which light emission occurs is long to display a bright image. In addition, a clear image can be displayed when light emission due to a wrong discharge does not occur in the reset period.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a driving apparatus and a driving method of a plasma display panel capable of reducing the time of a reset period without erroneous light emission and allocating the remaining time to a sustain discharge period to increase luminance.

In order to achieve the above technical problem, a driving apparatus of a plasma display panel according to an aspect of the present invention applies a voltage to a first electrode and a second electrode and a panel capacitor formed between the first electrode and the second electrode. A drive device for a plasma display panel

An inductor having a first terminal electrically connected to the first electrode of the panel capacitor; A first switch electrically connected between the second terminal of the inductor and a first power supply for supplying a first voltage; A second switch electrically connected between the first terminal of the inductor and a second power supply for supplying a second voltage; And a third switch electrically connected between the first electrode of the panel capacitor and a third power supply for supplying a third voltage to gradually lower the voltage.

In a reset period, the second switch is turned on to apply the second voltage to the voltage of the first electrode, the second switch is turned off, and the first switch is turned on to turn on the first power source, the inductor, and the panel capacitor. After generating an LC resonance in between to lower the first electrode from the second voltage to the fourth voltage, turn off the first switch and turn on the third switch to turn the voltage of the first electrode to the fourth voltage. The voltage is gradually lowered from the voltage to the third voltage.

A driving method of a plasma display panel according to another aspect of the present invention,

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In the reset period, lowering the voltage of the first electrode from the first voltage to the second voltage by the first slope by LC resonance generated in the panel capacitor and the inductor electrically connected to the first electrode; And lowering the voltage of the first electrode from the second voltage to a third voltage with a second slope smaller than the first slope.

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DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

Now, a driving apparatus and a driving method of a plasma display panel according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Looking at the reset period shown in Figure 3, the time taken by the ramp up or ramp down period is long. However, a slight discharge does not occur between the ramp up or ramp down periods, but little discharge occurs in the range of the initial rise or the initial fall.

The present invention has been made in view of this, and provides a method of reducing the time of the reset period by increasing the slope of the fall in the initial ramp down for a period of time.

4 is a driving waveform according to an embodiment of the present invention consists of a reset period, an address period and a sustain discharge period. The plasma display panel is driven by a scan / hold driving circuit (not shown) and an address electrode A1-Am for applying driving voltages to the Y electrodes Y1-Yn and the X electrodes X1-Xn in each period. An address driving circuit (not shown) for applying a voltage is connected. The driving circuit and the plasma display panel are connected to form one plasma display device.

As shown in FIG. 4, the driving waveform diagram of the plasma display panel according to the exemplary embodiment of the present invention is similar to the conventional driving waveform diagram of FIG. 3, but has a first ramp falling period M3 having a different ramp falling period. And the second ramp falling period M4. In particular, the slope of the first ramp falling period M3 is greater than the slope of the second ramp falling period M4.

During the reset period, in the ramp rising period M2, the address electrode and the X electrode are held at 0 V, and the Y electrode gradually rises from the voltage Vs below the discharge start voltage to the V electrode, which is a voltage above the discharge start voltage. Apply lamp voltage. While this ramp voltage is rising, the first weak reset discharge occurs in each of the discharge cells from the Y electrode to the address electrode and the X electrode, respectively. As a result, negative wall charges are accumulated at the Y electrode, and positive wall charges are accumulated at the address electrode and the X electrode.

In the first ramp falling period M3, the voltage is lowered to the voltage of Vs / 2 at the Y electrode while the Ve voltage is biased at the X electrode. In this embodiment, the voltage of Vs / 2 is specified, but if strong discharge does not occur between the electrodes, it may be lowered to another voltage (for example, voltage higher or lower than Vs / 2).

According to an embodiment of the present invention, the first ramp falling period uses LC resonance of the power recovery circuit. Detailed description thereof will be given below.

In the second ramp falling period M4, while the X electrode is maintained at the constant voltage Ve, the Y electrode has a ramp voltage that falls gently from the voltage Vs / 2 to the Vnf (V) beyond the discharge start voltage with respect to the X electrode. Is authorized. While this ramp voltage falls, the second weak reset discharge occurs again in all the discharge cells. As a result, the negative wall charges of the Y electrode are reduced, and the polarity of the X electrode is inverted so that a weak negative charge is accumulated. In addition, the positive wall charge of the address electrode is adjusted to a value suitable for the address operation.

In the embodiment of the present invention, the lamp type voltage is applied to the Y electrode in the reset period, but the other type of voltage capable of controlling the wall charge while causing weak discharge other than the lamp type is applied to the Y electrode. May be authorized. This type of voltage is a voltage whose voltage level changes gradually over time.

FIG. 5 is a schematic circuit diagram of a driving circuit for applying the waveform shown in FIG. 4, and FIGS. 6A to 6D are diagrams showing current paths of a ramp up and ramp down mode in a drive circuit according to the present invention.

The circuit shown in FIG. 5 is a schematic Y electrode driving circuit, where the first terminal of the panel capacitor Cp is the Y electrode, and the second terminal represents the X electrode. However, the drive circuit of the X electrode and the A electrode is omitted here.

The Y electrode driving circuit 100 is largely divided into a power recovery circuit 120, a sustain discharge circuit 140, and a lamp circuit 160.

The power recovery circuit 120 includes a switch connected in parallel between the inductor L, a power recovery capacitor Ce connected to one end of the ground, and the other end of the power recovery capacitor Ce and one end of the inductor L. (S1, S2).

The sustain discharge circuit 140 includes switches S3 and S4 having one end connected to the other end of the inductor L included in the power recovery circuit 120, and the other ends of the switches S3 and S4 respectively having a voltage ( Vs) and ground.

The lamp circuit 160 includes switches S5 and S6 connected in series between the other end of the inductor L and the Y electrode of the panel capacitor Cp, the other end of the inductor L and the contact point of the switch S5. A ramp-up switch connected between a capacitor Cset connected between a voltage Vset-Vs and a contact of the capacitor Cset and the voltage Vset-Vs and a contact of the switches S5 and S6 connected in series Yrr, a ramp down switch Yfr coupled between the switch S6 and the contact of the Y electrode and the voltage Vnf. Here, the switches S4 to S6 are MOSFET switches including body diodes, and when the voltage Vnf is a negative voltage, the switch S6 is required to cut off the current flowing through the body diodes of the switches S4 and S5. do.

However, although this circuit is represented by the switches S1 to S6, a MOSFET is generally used. In the present invention, the switch is not limited to a MOSFET or a switch. The lamp switches Yrr and Yfr briefly indicate a circuit for lamp operation. The switches S1 to S6 and the lamp switches Yrr and Yfr are controlled by a controller not shown in the figure.

When the power recovery circuit 120 and the sustain discharge circuit 140 alternately apply a voltage of Vs and 0 to the Y electrode in the sustain discharge period, the power recovery circuit 120 and the sustain discharge circuit 140 store some of the power consumed in the power recovery capacitor Ce. Emissions reduce overall power consumption. That is, when the lamp switches Yrr and Yfr are open, and the switches S1 to S4 are closed one by one in the order of S1-S3-S2-S4 with the switches S5 and S6 closed, the Y electrode has Vs. And a voltage of 0 are applied alternately. Here, when the S2 switch is closed, electric current flows through the power recovery capacitor Cer, and when the S1 switch is closed, a voltage is applied to the Y electrode due to the charged charge.

The ramp circuit 160 applies the setup voltage Vset and the setdown voltage Vnf to the Y electrode in a predetermined order in the reset period. When the ramp up switch Yrr and the switch S6 are turned on while the switch S5 is open, the setup voltage Vset is gradually applied to the Y electrode. In addition, when the switch S6 is turned off and the lamp lowering switch Yfr is turned on, the setdown voltage Vnf is gradually applied to the Y electrode.

In the embodiment according to the present invention, the lamp lowering is divided into a first ramp lowering and a second ramp lowering period, and the operation change of the Y electrode driving circuit 100 is divided into four modes with reference to FIGS. 6A to 6D. do.

① Mode 1 (M1)

In the mode 1 period M1 of FIG. 4, the switches S1, S2, S4 and the lamp switches Yrr, Yfr are in an off state, and the switches S3, S5, S6 are in an on state. Then, as illustrated in FIG. 6A, a current path is formed by the switch S3, the switch S5, the switch S6, and the panel capacitor Cp. Therefore, a voltage of Vs is applied to the Y electrode.

② Mode 2 (M2)-(Lamp Rise)

In the mode 2 period M2 of FIG. 4, while the switch S3 is turned on, the switch S5 is turned off and the lamp switch Yrr is turned on. Here, the capacitor Cset is precharged with a voltage of Vset-Vs. Then, as shown in FIG. 6B, a current path is formed by the switch S3, the lamp switch Yrr, the switch S6, and the panel capacitor Cp, so that the voltage of the Y electrode (the first electrode of the panel capacitor) is increased. It gradually rises from Vs voltage to Vset voltage.

③ Mode 3 (M3)-(1st lamp down)

In the mode 3 period M3 of FIG. 4, the lamp switch Yrr is turned off, the switches S3 and S5 are turned on, and a voltage of Vs is applied to the Y electrode. After that, the switch S3 is turned off again, and the switch S2 is turned on. Then, as illustrated in FIG. 6C, a current path is formed by the panel capacitor Cp, the switch S6, the switch S5, the coil L, the switch S2, and the power recovery capacitor Ce, thereby providing power. Resonance occurs between the recovery capacitor Ce, the inductor L, and the panel capacitor Cp. Due to this resonance, electric charge is charged in the power recovery capacitor Ce, and the voltage of the Y electrode drops rapidly to about Vs / 2. In this case, the voltage applied to the Y electrode may be adjusted to be higher or lower than Vs / 2 by adjusting the switching timing of the switch S2.

④ Mode 4 (M4)-(2nd ramp down)

In the mode 4 period M4 of FIG. 4, the switch S6 is turned off and the lamp switch Yfr is turned on. Then, a current path is formed from the panel capacitor Cp to the lamp switch Yfr as shown in FIG. 6D. Therefore, the voltage applied to the Y electrode gradually falls from Vs / 2 to Vnf by the lamp switch Yfr.

This operation causes the length of the entire ramp down period to be reduced by Z as compared to the ramp down period of the prior art. For example, if there are eight subfields in one frame, a length as long as Z × 8 is secured. This secured time can be used for maintenance discharge.

In the embodiment according to the present invention, the time taken for the reset period can be reduced by simply controlling the switches S1 to S6 and the lamp switches Yrr and Yfr without changing the existing circuit.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, it is possible to reduce the time of the reset period without erroneous discharge by simply operating the switch and to increase the luminance by allocating the remaining time to the sustain discharge period.

Claims (10)

In the driving apparatus of the plasma display panel for applying a voltage to the first electrode and the second electrode, and a panel capacitor formed between the first electrode and the second electrode, An inductor having a first terminal electrically connected to the first electrode of the panel capacitor; A first switch electrically connected between the second terminal of the inductor and a first power supply for supplying a first voltage; A second switch electrically connected between the first terminal of the inductor and a second power supply for supplying a second voltage; And A third switch electrically connected between the first electrode of the panel capacitor and a third power supply for supplying a third voltage to gradually lower the voltage; In the reset period, Turn on the second switch to apply the second voltage to the first electrode; The second switch is turned off and the first switch is turned on to generate LC resonance between the first power source, the inductor, and the panel capacitor so that the voltage of the first electrode is changed from the second voltage to the fourth voltage by the first slope. Down to Turning off the first switch and turning on the third switch to gradually lower the voltage of the first electrode from the fourth voltage to the third voltage with a second slope smaller than the first slope; Drive of display panel. delete The method of claim 1, A fourth switch electrically connected between the first terminal of the inductor and the first electrode of the panel capacitor; A capacitor electrically connected between the fourth switch and a contact of the inductor and a fourth power supply for supplying a fifth voltage; And A fifth switch electrically connected between the first electrode of the panel capacitor and the fourth power source to gradually increase a voltage; And turning on the fifth switch in a state where the fourth switch is turned off to gradually raise the first electrode from the sixth voltage to the seventh voltage. The method of claim 1, And the first voltage is 1/2 of the second voltage. The method of claim 1, And the third voltage is a negative value. The method of claim 1, And the first switch and the second switch are transistors each having a body diode. A method of driving a plasma display panel for applying a voltage to a first electrode and a second electrode and a panel capacitor formed between the first electrode and the second electrode, In the reset period, (a) decreasing the voltage of the first electrode from the first voltage to the second voltage by a first slope by LC resonance generated between the inductor electrically connected to the first electrode and the panel capacitor; And (b) lowering the voltage of the first electrode from the second voltage to a third voltage with a second slope smaller than the first slope; Method of driving a plasma display panel comprising a. The method of claim 7, wherein Before step (a), And applying a slowly rising voltage from the fourth voltage to the fifth voltage to the first electrode. The method according to claim 7 or 8, And the second voltage is 1/2 of the first voltage. The method according to claim 7 or 8, And the third voltage is a negative value.

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