JP2003157042A - Method of driving ac-type plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of driving an AC-type plasma display panel capable of obtaining a favorable contrast characteristic by suppressing black brightness without generating strong discharge in a non-lighting pixel in an AC-type plasma display panel from which a non-discharge gap between a scanning electrode and a common electrode is eliminated. SOLUTION: In a sub-field 1, a maintenance eliminating sustained period 2, a write priming period 3, a scanning period 4, a wall voltage returning period 5, a wall charge inverting period 6, a maintenance eliminating period 7, a write priming period 8, a scanning period 9, a wall voltage returning period 10, and a maintaining period 11 are time-sequentially arranged in this order. In the maintenance eliminating period 2, negative wall charges are formed on the scanning electrodes S and common electrodes C1 of the pixels in the odd- numbered lines, and in the scanning period 4, the pixels in the odd-numbered lines are excited to generate write discharges. Similarly, in the maintenance eliminating period 7, negative wall charges are formed on the scanning electrodes S and common electrodes C1 of the pixels in the even-numbered lines, and in the scanning period 9, the pixels in the even-numbered lines are excited to generate write discharges.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method of an AC type plasma display panel in which a scanning electrode and a common electrode are commonly used in adjacent pixels, and particularly, an AC type plasma display panel for reducing black luminance. Driving method.

[0002]

2. Description of the Related Art Generally, a plasma display panel (hereinafter, also referred to as PDP) has many features such as being thin and capable of relatively easily displaying a large screen, having a wide viewing angle, and having a fast response speed. ing. Therefore, it has recently been used as a flat display for wall-mounted televisions, public display boards, and the like. According to its operation method, the PDP exposes the electrodes to the discharge space filled with the discharge gas,
A DC discharge type (DC type) PDP which operates by generating a DC discharge between the electrodes, and an AC discharge which operates in an AC discharge state without directly exposing the electrodes to a discharge gas by covering the electrodes with a dielectric layer. Type (AC type) PDP. In the DC type PDP, the discharge is maintained while the voltage is applied, and in the AC type PDP, the discharge is maintained by reversing the polarity of the voltage. Further, there are AC type PDPs having two electrodes and three electrodes in one cell. A document describing a PDP having such a structure is "Society for Information.
Display 98 digest, pages 279-281,
May 1998 (SID; 98; DIGEST, p279-281, May, 199
8) ”

The structure and driving method of a conventional three-electrode AC plasma display panel will be described below. FIG. 10 is a sectional view showing the structure of a cell in a conventional plasma display panel, and FIG. 11 is a plan view showing an electrode arrangement of this conventional plasma display panel.

As shown in FIG. 10, in this conventional AC3 electrode type plasma display panel, a front substrate 20 and a rear substrate 21 facing the front substrate 20 are provided. The front substrate 20 and the rear substrate 21 are made of glass, for example. Back substrate 21 in front substrate 20
A plurality of scanning electrodes 22 and a common electrode 23 are arranged alternately and in parallel with each other at a predetermined interval on the surface facing each other. The scan electrode 22 and the common electrode 23 are IT
The transparent electrode is made of O and extends in the direction from the back side of the paper surface to the front side in FIG.

A metal electrode 32 is laminated on the scan electrode 22 and the common electrode 23 to reduce the wiring resistance. Further, a transparent dielectric layer 24 is provided so as to cover the scanning electrodes 22 and the common electrode 23, and a protective layer 25 made of MgO or the like is formed on the transparent dielectric layer 24.

On the other hand, the front substrate 20 in the rear substrate 21
A plurality of data electrodes 29 are provided on the surface facing each other. The data electrodes 29 are the scanning electrodes 22 and the common electrode 2.
3 extends in a direction orthogonal to 3 (vertical direction in the drawing). A white dielectric layer 28 and a phosphor layer 27 are provided on the data electrode 29.

A partition wall (not shown) is provided between the front substrate 20 and the rear substrate 21. The partition wall forms a space between the front substrate 20 and the rear substrate 21 in the discharge space 26.
And the discharge space 26 is divided into display cells (pixels). Each display cell has a scan electrode 22.
1 and the closest contact point between the data electrode 29 and the data electrode 29 and the closest contact point between the common electrode 23 and the data electrode 29 are included. The discharge space 26 is filled with a mixed gas of He, Ne, Xe, etc. as a discharge gas.

Further, as shown in FIG.
(Si (i = 1 to m)) and the common electrode 23 (Ci (i =
1 to m)) and the data electrode 29 (Dj (j = 1 to n)).
The display cells 31 are arranged in a matrix so as to include the respective closest portions to and. A discharge gap 37 where a surface discharge is generated is formed between the scan electrode Si and the common electrode Ci, and a non-discharge gap 38 where a surface discharge is not generated is formed between the scan electrode Si and the common electrode Ci-1. .

Next, a method of driving this conventional PDP will be described. Currently, the mainstream method for driving a PDP is a scan sustain separation method (ADS method) in which a scan period and a sustain period are separated. Hereinafter, the driving method of the scan sustain separation method will be described. FIG. 12 shows the conventional 3
FIG. 6 is a drive waveform diagram showing one subfield (hereinafter referred to as SF) of the electrode AC type plasma display panel. 1
The subfield is composed of three periods of a preliminary discharge period 12, a scanning period 13 and a sustain period 11.

First, the preliminary discharge period 12 will be described. In the preliminary discharge period 12, the positive polarity preliminary discharge pulse 14 is applied to the common electrode 23, and the negative polarity preliminary discharge pulse 15 is applied to the scan electrode 22. This resets and initializes the difference in the wall charge state caused by the difference in the light emission state in the previous SF in each pixel, forcibly discharges all the pixels, and the subsequent write discharge is performed at a low voltage. Get the priming effect to wake up.

In FIG. 12, the preliminary discharge pulses 14 and 15 are each once, but after a sustaining erase pulse for resetting the state of the previous SF is applied, a priming pulse that discharges all pixels and causes a priming effect is generated. In some cases, the pulse may be applied by separating the two roles such as applying. At this time, the sustaining erase pulse is not limited to one time, and different pulses may be applied a plurality of times. Further, the priming effect is not always necessary in every SF, and there is a driving method in which the priming pulse is applied only once in several SFs. The priming pulse causes all pixels to emit light irrespective of display, thus increasing the black luminance. Therefore, by reducing the number of times the priming pulse is applied, the brightness during black display can be suppressed low. As in the conventional example shown in FIG. 12, the preliminary discharge pulse 1
When 4 and 15 are applied, in order to make the priming effect of forcibly discharging all the pixels once every several SF, the pre-discharge pulses 14 and 15 are lowered in SFs other than SF shown in FIG. In some cases, only the role of reset is assumed. At this time, in order to perform reset surely,
Instead of each single preliminary discharge pulse 14 and 15, pulses having different voltages may be applied multiple times.

Next, in the scanning period 13, the scanning electrode S
The scanning pulse 16 is sequentially applied to 1 to Sm. A data pulse 18 is applied to the data electrodes D1 to Dn in accordance with the scan pulse 16 based on display data. In the pixel to which the data pulse 18 is applied, the total voltage of the scan pulse 16 and the data pulse 18 is applied between the scan electrode 22 and the data electrode 29, and the total voltage is the discharge between the scan electrode 22 and the data electrode 29. Since the voltage is set to be higher than the start voltage, the scan electrode 22 and the data electrode 29 are
Write discharge occurs during the period. As a result, large positive wall charges are formed on the scan electrode 22 side and negative wall charges are formed on the data electrode 29 side.

On the other hand, in the pixel to which the data pulse 18 is not applied, the applied voltage is only the voltage of the scan pulse 16,
Since it is set so as not to reach the discharge start voltage, no discharge occurs. Therefore, the situation of wall charges does not change in this pixel. Thus, two types of wall charge situations can be created depending on the presence or absence of the data pulse 18. The diagonal lines of the data pulse 18 in the figure indicate that the presence or absence of the data pulse 18 changes depending on the display data.

Scan pulse 13 is applied to all scan electrodes S1 to Sm.
When the application of the voltage is finished, the sustain period 11 starts. Maintenance period 1
In No. 1, the sustain pulse 19 is alternately applied to all the scanning electrodes 22 and all the common electrodes 23. The voltage value of the sustain pulse 19 is set to a voltage at which discharge does not start with its own voltage. Therefore, since the wall charges are small in the pixels in which the writing discharge has not occurred in the scanning period 13, no discharge occurs even if the sustain pulse 19 is applied.

On the other hand, in the pixel in which the writing discharge is generated in the scanning period 13, since a large positive wall charge exists on the scanning electrode 22 side, the first positive sustain pulse 19 applied to the scanning electrode 22 (this is This positive wall charge is superimposed on the first sustain pulse). As a result, a voltage higher than the discharge start voltage is applied between the scan electrode 22 and the common electrode 23,
Sustain discharge occurs. By this sustain discharge, the scan electrode 2
Negative wall charges are accumulated on the 2 side, and positive wall charges are accumulated on the common electrode 23 side. The next sustain pulse 19 (referred to as the second sustain pulse) is applied to the common electrode 23 side. At this time, in the pixel in which the sustain discharge is generated by the first sustain pulse, the wall charges are superimposed on the second sustain pulse to generate the sustain discharge, and the wall having a polarity opposite to that after the sustain discharge by the first sustain pulse is generated. Electric charges are accumulated on the scan electrode 22 side and the common electrode 23 side. After that, discharge is continuously generated according to the same principle. That is, the potential difference due to the wall charges generated by the xth sustain discharge is superimposed on the (x + 1) th sustain pulse 19, and the sustain discharge continues. The amount of light emission is controlled by adjusting the number of sustain discharges.

The above-mentioned preliminary discharge period 12, scanning period 13,
The sustain period 11 is collectively referred to as a subfield. PDP
In the case of displaying an image on one screen, one field, which is a period for displaying image information of one screen, is composed of a plurality of subfields, and the number of sustain pulses in each subfield is made different from each other to light each subfield. By selecting whether to turn on or off and controlling the number of subfields to be turned on, gradation display of an image can be performed.

[0017]

However, the above-mentioned conventional technique has the following problems. In the above-described conventional plasma display panel, unless the wide non-discharge gap 38 (see FIG. 11) is provided between the adjacent scan electrode 22 and common electrode 23 between the upper and lower adjacent pixels, the upper and lower pixels are False discharge will occur. The non-discharge gap 38 needs a certain length even if the size of the pixel is reduced. Therefore, when trying to manufacture a high-definition plasma display panel, the ratio of the non-discharge gap in one pixel becomes large, and the widths of the scanning electrode 22 and the common electrode 23 cannot be sufficiently secured. Therefore, the brightness and the luminous efficiency are lowered.

Further, in the above-described conventional plasma display panel driving method, during the preliminary discharge period 12 shown in FIG. 12, strong discharge is generated by the preliminary discharge pulses 14 and 15 even in non-lighted pixels. As a result, the black brightness increases and the contrast characteristic of the PDP deteriorates.

The present invention has been made in view of the above problems, and in the AC type plasma display panel in which the non-discharge gap between the scanning electrode and the common electrode is eliminated, a strong discharge is generated in the non-lighted pixel. It is an object of the present invention to provide a method for driving an AC type plasma display panel, which can suppress black luminance to a low level and obtain good contrast characteristics.

[0020]

A method for driving an AC type plasma display panel according to the present invention is the same as the method for driving an AC type plasma display panel, wherein the first and second insulating substrates are arranged to face each other. A plurality of scan electrodes and common electrodes that are alternately provided on the surface of the first insulating substrate facing the second insulating substrate and extend in the first direction, and the first insulation of the second insulating substrate. A plurality of data electrodes that are provided on a surface facing the substrate and extend in a second direction orthogonal to the first direction, and a first dielectric layer formed to cover the scan electrodes and the common electrode. And a second dielectric layer formed so as to cover the data electrode, and a partition arranged between the first insulating substrate and the second insulating substrate. , Placed on the center line of the scanning electrode A first portion extending in the first direction, a second portion arranged on the center line of the common electrode and extending in the first direction, and on each region between the data electrodes adjacent to each other. Are arranged so as to form a lattice pattern with the third portion extending in the second direction, and a plurality of pixels are partitioned by the partition walls and arranged in the first direction. Using an AC type plasma display panel in which a first pixel group and a second pixel group composed of a plurality of pixels are alternately arranged, one field displaying one image has one or a plurality of sub-fields. A first scanning period in which wall charges are formed in the pixels in the first pixel group selected based on display data, and the sub-field is temporally separated from the first scanning period for display. Selected based on data Second scan period in which wall charges are formed on pixels in the second pixel group, and first and second pixel groups in which the wall charges are formed by alternately applying voltage to the scan electrodes and the common electrode And a sustain period in which sustain discharge is generated at the same timing in each pixel.

In the present invention, the discharge gap is entirely formed between the scan electrode and the common electrode, and the non-discharge gap is not provided between the scan electrode and the common electrode. It is possible to secure a sufficient width for the electrodes and the common electrode, and prevent the luminance and the luminous efficiency from decreasing. In addition, in the past, only one scanning period was provided in one subfield, and
By dividing the scan period and forming wall charges in the first and second pixels at different timings, the discharges of the first and second pixels can be independently controlled.

In addition, the subfield causes discharge in pixels in the first pixel group, and makes it easier for discharge in pixels in the first pixel group during the first scanning period to be ready for first writing. A period, a second writing preparation period in which discharge occurs in pixels in the second pixel group, and discharge easily occurs in pixels in the second pixel group in the second scanning period; A first wall charge that causes a weak discharge in a pixel in which no wall charge is formed in the pixel in the pixel group in the first scanning period to return the charge state in the pixel to the state immediately before the first writing preparation period. In the return period and in the pixels in the second pixel group, a weak discharge is generated in the pixels in which the wall charges have not been formed in the second scanning period, and the charge state in the pixels is set immediately before the second write preparation period. 2nd wall charge return period to return to the state of When, it is preferable to have a.

Further, the first write preparation period and the second write preparation period
The discharge in the writing preparation period is preferably a surface discharge generated between the scan electrode and the common electrode, and the surface discharge gradually increases the potential difference between the scan electrode and the common electrode. It is preferable that the weak discharge is generated.

As a result, strong discharge does not occur in the non-lighted pixels, and the black luminance can be suppressed to a low level. As a result, the contrast of the image can be improved.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described below with reference to the accompanying drawings. 1 is a schematic plan view showing a three-electrode AC type plasma display panel (PDP) according to a first embodiment of the present invention, and FIG. 2 is a three-electrode AC type plasma display panel according to the first embodiment. FIG. 3 is a schematic plan view showing one cell, and FIG. 3 is a sectional view showing an AA ′ section shown in FIG.

As shown in FIG. 1, the PDP of the first embodiment.
In FIG. 30, a plurality of scan electrodes 22 (scan electrode S1
To Sm) and a plurality of common electrodes 23 (common electrodes C1 to Cm) are provided, and the scanning electrodes 22 and the common electrodes 23 extend in the first direction (lateral direction in the drawing) and are alternately parallel to each other. They are evenly spaced. Further, the data electrodes 29 are provided, extend in the second direction (vertical direction in the drawing) orthogonal to the first direction, and are arranged at equal intervals. Furthermore, a plurality of cells 31 (pixels) are provided in a matrix, and each cell 31 includes a scan electrode 22, a common electrode 23, and a data electrode 29. In addition, in FIG.
Components other than the scan electrode 22, the common electrode 23, and the data electrode 29 are not shown.

As shown in FIG. 2, the cells 31 are rectangular, and the area occupied by each cell 31 in the second direction is the center of the scanning electrode 22 in the width direction and the common electrode 23 adjacent to the scanning electrode 22. Of the data electrodes 29 adjacent to each other and in the first direction between the center of the data electrodes 29 adjacent to each other in the first direction. That is, in the adjacent cell 31, the scan electrode 2
2 and the common electrode 23 are commonly used. In FIG. 2, an upper insulating substrate 20, a lower insulating substrate 21, a transparent dielectric layer 24, a protective layer 25, a phosphor 27, which will be described later,
The white dielectric layer 28 (see FIG. 3 for all) is not shown.

Further, as shown in FIG. 3, in the PDP of the first embodiment, the upper insulating substrate 20 which is a front substrate is used.
And a lower insulating substrate 21 which is a rear substrate is provided so as to face the upper insulating substrate 20.
As the upper insulating substrate 20 and the lower insulating substrate 21, for example, soda lime glass substrates having a thickness of about 2 to 5 mm are used.

On the surface of the upper insulating substrate 20 facing the lower insulating substrate 21, a transparent electrode made of tin oxide or indium oxide and having a film thickness of about 100 to 500 nm is used as the scanning electrode 22 and the common electrode 23. Is provided. When the cell pitch of the cells 31, that is, the length of the cells 31 in the first direction is, for example, 600 μm, the widths of the scan electrodes 22 and the common electrode 23 are 500 to 5
The gap between the two electrodes is 50 to 1
It is about 00 μm. Some areas on each transparent electrode
The film thickness of Ag or the like is 2 to 7 in order to reduce the wiring resistance.
A metal electrode 32 of about μm is provided.

Further, on the surface of the upper insulating substrate 20,
A transparent dielectric layer 24 is provided so as to cover the scanning electrode 22, the common electrode 23, and the metal electrode 32. The transparent dielectric layer 24 is made of PbO-B ₂ having a relative dielectric constant of about 10 to 25.
It is formed using O ₃ —SiO ₂ -based low melting point glass paste to have a thickness of about 10 to 50 μm,
It is baked at a temperature of about to 600 ° C. Furthermore, a protective layer 25 for protecting the transparent dielectric layer 24 is provided on the transparent dielectric layer 24. Protective layer 25
Is formed by depositing MgO to a thickness of about 0.5 to 2 μm. Furthermore, the protective layer 25
In a region corresponding to the upper part of the metal electrode 32, the height is about half (40 to 40 μm) of the cell gap (40 to 130 μm).
Cell separation partition 33 having a width of about 50 to 200 μm and a width of about 50 to 200 μm. In addition, the protective layer 35
A vertical line partition wall 35 (see FIG. 2) is also provided on the top. The vertical line partition wall 35 is formed in a region corresponding to a region between the data electrodes 29 described later, and has a width of 50 to 70 μm.
The height is the same as that of the cell separating partition wall 33. The cell separation partition 33 and the vertical line partition 35 are formed simultaneously by the sandblast method.

On the other hand, on the surface of the lower insulating substrate 21 facing the upper insulating substrate 20, a data electrode 29 made of Ag or the like and having a film thickness of about 2 to 4 μm is formed. A white dielectric layer 28 is provided thereon. The white dielectric layer 28 is made of a white glass paste obtained by mixing PbO—B ₂ O ₃ —SiO ₂ -based low melting point glass paste with a relative dielectric constant of about 10 to 25 and TiO ₂ at a ratio of 10: 1. Of about 5 to 40 μm is formed into a film and baked at a temperature of 500 to 600 ° C. A cell separation partition 34 is formed on the white dielectric layer 28. The cell separation partition 34 is the cell separation partition 3
3 is placed at a position facing 3 and the height is 40 to 50 μm by printing the white glass paste.
It is formed so as to have a thickness of about m and is fired at a temperature of about 500 to 600 ° C.

A vertical line partition 36 (see FIG. 2) is formed on the white dielectric layer 28 at a position corresponding to the vertical line partition 35 on the upper insulating substrate 20 by a sandblast method. The height of the vertical line barrier ribs 36 is about 20 μm higher than the height of the cell separation barrier ribs 34, and the upper insulating substrate 20 is bonded to the lower insulating substrate 21 to form an exhaust path between the cell separation barrier ribs 33 and 34. A gap is formed. Further, on the surface of the white dielectric layer 28, the side surface of the cell separation partition wall 34 and the side surface of the vertical line partition wall 36, a phosphor 27 having a thickness of about 10 to 15 μm is formed by coating. When the type of the phosphor 27 is separately applied to RGB (red, green, blue) for each cell 31, full color display is possible in the PDP 30. For example, an R (red) phosphor is (Y, Gd) BO ₃ : Eu, a G (green) phosphor is Zn ₂ SiO ₄ : Mn, and a B (blue) phosphor is B.
aMgAl ₁₀ O ₁₇ : Eu can be used.

In the PDP of the present embodiment, the above-mentioned upper insulating substrate 20 is bonded to the lower insulating substrate 21, baked at a temperature of 350 to 500 ° C., and then the inside of the cell is evacuated.
As a discharge gas, a mixed gas of He, Ne, and Xe is sealed so as to have a pressure of 2.7 × 10 ^{4 to} 8.0 × 10 ⁴ Pa, and sealed.

Next, a method of driving the PDP according to the first embodiment will be described. FIG. 4 is a PDP according to the first embodiment.
6A to 6D are waveform diagrams showing the driving method of FIG.
6A to 6F are schematic cross-sectional views showing the driving method of the PDP, and show the cross section AA 'in FIG. 5 (a) to 5 (d) and 6 (a) to 6 (f)
In Fig. 1, the amount of wall charges on each electrode is schematically shown by a polygon. Among the wall charges, negative charges are indicated by “−” in the polygon, and positive charges are indicated by “+” in the polygon. The height of this polygon indicates the magnitude of the wall voltage which is the potential difference generated in the dielectric layer by the wall charges. S is a scanning electrode, and C1 and C2 are common electrodes (C
1, C3, ..., C2k-1) and the even-row common electrodes (C2, C4, ..., C2k). D indicates a data electrode. In the PDP of the first embodiment, the surface discharge starting voltage between the scan electrode and the common electrode is about 180 to 210V, and the opposite discharge starting voltage between the scan electrode or the common electrode and the data electrode is 160 to 190V. The cells are designed so that the degree is small.

As shown in FIG. 4, in the driving method according to this embodiment, one field is a plurality of subfields (S
F) 1 and subfield 1 includes a sustain erase period 2, a write preparation period 3, a scan period 4, a wall voltage return period 5, a wall charge inversion period 6, a sustain erase period 7,
A write preparation period 8, a scanning period 9, a wall voltage return period 10 and a sustain period 11 are temporally arranged in this order.

Previous subfield 1 (hereinafter referred to as previous SF1
The arrangement of the wall charges of each cell (pixel) at the final time of () is different depending on whether the cell was lit or not lit in the previous SF1. FIG. 5A shows the previous SF1.
5 shows the odd-row pixels that were in the non-lighted state in FIG.
(B) shows the even-row pixels that were in the non-lighting state in the previous SF1. Further, FIG. 5C shows the odd-row pixels that are in the lighting state in the previous SF1, and FIG. 5D shows the even-row pixels that are in the lighting state in the previous SF1.

In this state, the sustain erase period 2 of subfield 1 is entered. In the maintenance erase period 2,
First, a voltage Ve1 of 230 to 270V is applied to the common electrode C1.
Is applied. Further, by applying the voltage Ve2 to the scan electrode S,
The voltage Vs is applied to the common electrode C2. The voltage Ve2 is 10
In the cell which is set to about 0 to 150 V and which is not lit in the previous SF1, a region corresponding to the common electrode C on the surface of the transparent dielectric layer 24 (hereinafter referred to as the common electrode C1) and a transparent region are transparent. Discharge is prevented from occurring between the surface of the dielectric layer 24 and a region corresponding to the scan electrode S (hereinafter, referred to as the scan electrode S), while the cell that was turned on in the previous SF1 is Discharge is generated. As a result, discharge occurs in the odd-row pixels that are in the lighting state in the previous SF1 as shown in FIG. 5C, and negative wall charges are generated on the common electrode C1 as shown in FIG. 6A. Are formed, negative wall charges smaller than the negative charges on the common electrode C1 are formed on the scan electrode S, and the data electrode D on the surface of the white dielectric layer 27 is formed.
The wall charge arrangement is such that positive wall charges are formed in a region corresponding to the above (hereinafter, referred to as the data electrode D).

After that, the electrode potential of the common electrode C1 is continuously reduced to the ground potential, and a weak opposing discharge (weak discharge) is generated between the common electrode C1 and the data electrode D. As a result, as shown in FIG. 6B, the wall charge between the opposing surfaces is reduced. The wall charge arrangement shown in FIG. 6B is shown in FIG.
This is the same as the wall charge arrangement of the odd-row pixels that were in the non-lighting state in the previous SF1 shown in FIG. That is, the state of the previous SF1 is reset in the sustain erasing period 2. It should be noted that in the sustain erase period 2, discharge is not generated in the even-row pixels, and the wall charge arrangement remains in the state shown in FIG. 5B or 5D.

The write preparation period 3 is composed of a first half priming period 3a and a second half priming erasing period 3b.
In the priming period 3a, a voltage having a ramp waveform that continuously increases from the ground potential to the voltage Vp is applied to the common electrode C1. Further, the scan electrode S is at the ground potential, and the voltage Vs is still applied to the common electrode C2. Voltage Vp
Is, for example, about 360 to 400V. Common electrode C1
By continuously increasing the voltage applied to the electrodes, a weak discharge is generated between the scan electrode S and the common electrode C1, and the wall charges in the vicinity of the surface discharge gap in the odd-row pixels are generated.
It changes as shown in (c). Thus, in the priming period 3a, by generating discharge,
The negative wall voltage can be formed only on the odd-row pixel side on the scan electrode S. This makes it possible to generate the write discharge only in the odd-row pixels in the scanning period 4 described later. In addition, it is possible to generate priming particles in the pixels to facilitate discharge in pixels in odd-numbered rows in the scanning period 4.

In the priming erase period 3b, the potential applied to the common electrode C1 is discontinuously reduced to a certain level of potential, and then continuously reduced to the ground potential. Further, the voltage Vpe is applied to the scan electrode S. The voltage Vs is still applied to the common electrode C2. Voltage Vpe
Is set to a voltage higher than the surface discharge starting voltage, and in this embodiment, is set to about 230 to 250V. As a result, a weak discharge of the surface occurs in the odd-row pixels, and
The wall charges are arranged as shown in (d). In the write preparation period 3, no discharge occurs in the even-numbered pixels, and the wall charge arrangement remains in the state shown in FIG. 5B or 5D.

In the scanning period 4, the voltage Vs is applied to the common electrodes C1 and C2. The common electrodes C1 and C
The voltage applied to 2 may be slightly higher than Vs.
This ensures writing. On the other hand, the potential of the scan electrode S is set to about Vbw = 90 to 120 V, and scan pulses falling to GND are sequentially applied for each scan electrode line.
A data pulse of Vd = 60 to 80 V is applied to the data electrode D based on the display data at the timing when the scan pulse is applied. As a result, the write discharge is generated between the scan electrode S and the data electrode D only in the odd-row pixels in which the large negative wall voltage is formed on the scan electrode S.
In the pixel in which the write discharge has occurred, as shown in FIG. 6E, negative wall charges are formed on the common electrode C1 and positive wall charges are formed on the scan electrode S. The wall charge arrangement of the odd-row pixels in which the write discharge has not occurred remains as shown in FIG. 6 (d). Moreover, the wall charge arrangement of the even-row pixels remains in the state shown in FIG. 5B or 5D.

Next, in the wall charge returning period 5, the potential of the common electrode C1 is continuously decreased from the voltage Vs to the ground potential, and the potential of the scan electrode S is changed from the voltage Vbw to this voltage Vbw.
The voltage Ve3 (= 0 to 20 V) lower than bw is continuously decreased, and the voltage Vd is applied to the data electrode D. The voltage Vs is still applied to the common electrode C2. As a result, a weak discharge is generated between the scan electrode S and the data electrode D in the odd-row pixels in which the write discharge has not been generated in the scan period 4, and the wall charge as shown in FIG. It will be arranged. This is the same as the wall charge arrangement shown in FIG. That is, in the wall charge returning period 5, the wall charge arrangement of the odd-row pixels in which the writing discharge has not occurred in the scanning period 4 can be returned to the last state of the sustaining erasing period 2.

In the wall charge inversion period 6, first, the potential of the common electrode C1 is set to the ground potential, the potential of the common electrode S is set to the voltage Vs, and the potential of the common electrode C2 is set to the ground potential. The potential of the data electrode D is ground potential. As a result, positive wall charges are formed on the scan electrodes S in the odd-row pixels in which the write discharge is generated in the scan period 4,
The voltage due to this positive wall charge is superimposed on the applied voltage Vs, exceeds the surface discharge start voltage, and discharge occurs. on the other hand,
In the odd-row pixels in which the writing discharge has not been generated in the scanning period 4, the positive wall charges are not formed on the scanning electrodes S, so that the discharging is not generated. In the even-row pixels, no discharge is generated from the sustain erase period 2 to the wall charge return period 5, so that the wall charges are arranged as shown in FIG.
The state shown in (b) or (d) remains as it is. For this reason,
In the even-numbered pixels in which the discharge is generated in the previous SF1, the positive wall charges are formed on the scan electrodes S as shown in FIG. Meanwhile, the previous SF
In the even-numbered pixels in which the discharge is not generated in No. 1, the positive wall charges are not formed on the scan electrode S as shown in FIG.

Next, the potential of the common electrode C1 is set to the voltage Vs, the potential of the common electrode S is set to the ground potential, and the potential of the common electrode C2 is set to the voltage Vs. As a result, discharge occurs in the odd-row pixels in which the write discharge has occurred in scan period 4, discharge does not occur in the odd-row pixels in which the write discharge has not occurred, and even discharge that has occurred in the previous SF1. The discharge occurs in the row pixels, and the discharge does not occur in the even-row pixels in which the discharge has not occurred in the previous SF1.

Next, the potential of the common electrode C1 is maintained at the voltage Vs, the potential of the common electrode S is set to the voltage Vs, and the potential of the common electrode C2 is set to the ground potential. As a result, no discharge is generated in the odd-row pixels, discharge is generated in the even-row pixels that have been discharged in the previous SF1, and discharge is not generated in the even-row pixels that have not been discharged in the previous SF1.

As described above, in the wall charge inversion period 6, the odd-numbered pixels in which the writing discharge is generated in the scanning period 4 are discharged twice and the odd-numbered pixels in which the writing discharge is not generated are generated. No discharge is generated, the discharge is generated three times in the even-row pixels that have been discharged in the previous SF1, and no discharge is generated in the even-row pixels that are not discharged in the previous SF1. As a result, at the end of the wall charge inversion period 6, the wall charge state of the odd-row pixels remains at the last state of the wall charge return period 5, that is, the state shown in FIG. 6D or 6F. Further, in the even-row pixels in which the discharge has occurred in the previous SF1, the wall charges on the scan electrode S and the common electrode C2 are inverted. This state is shown in FIG.
This is the same as the state in which the common electrode C1 is replaced with the common electrode C2 in (c). Furthermore, the wall charge state of the even-row pixels in which no discharge has occurred in the previous SF1 remains the state shown in FIG. 5D, and this state changes the common electrode C1 to the common electrode C2 in FIG. 5A. It is the same as the replaced state. That is, in the wall charge inversion period 6, only the wall charge state of the even-row pixels in which the discharge has occurred in the previous SF1 is inverted, and the wall charge state of the even-row pixels is changed to the odd-row pixels at the beginning of the sustaining / erasing period 2. The same state as the wall charge state of. In each period, the ramp waveform width is about 40 to 80 μsec.

Next, the sustain erase period 7, the write preparation period 8,
The scanning period 9 and the wall voltage returning period 10 are passed in this order.
In the sustain / erase period 7, the write preparation period 8, the scanning period 9, and the wall voltage return period 10 (hereinafter, collectively referred to as a later period), the common electrode C1 has the above-described sustain / erase period 2 and the write preparation period. 3, the scanning period 4, the wall voltage return period 5 (hereinafter collectively referred to as the previous period), the waveform applied to the common electrode C2 is applied, the scan electrode S, the waveform applied to the scan electrode S in the previous period. And the waveform applied to the common electrode C1 in the previous period is applied to the common electrode C2.
That is, in the latter period, the common electrode C1 in the former period.
, And the voltage waveforms applied to C2 are replaced with each other. Further, in the scanning period 9, the voltage Vd is applied to the data electrode D based on the display data. Therefore, in the later period, the change in the discharge state and the wall charge is a change in the common electrode C1 and the common electrode C2 with respect to the change in the discharge state and the wall charge in the previous period, and the scan period 9 Is a period for writing to pixels in even-numbered rows. Then, at the end of the wall charge returning period 10, the writing of the image data to the pixels of all the rows is finished.

After that, the maintenance period 11 starts. The driving method of the PDP in the sustain period 11 is the same as the driving method of the PDP in the conventional sustain period 11 shown in FIG. That is, the sustain discharge (surface discharge) is generated only in the pixels in which the write discharge is generated in the scanning periods 4 and 9 shown in FIG. 4, and the sustain discharge causes light emission for image display. In this way, display can be performed for all pixels.

As described above, in this embodiment, the discharge gap is provided between the common electrode and the scan electrode which are adjacent to each other, and the non-discharge gap is not provided. Therefore, the widths of the scan electrode and the common electrode are sufficiently wide. Therefore, the brightness and the luminous efficiency can be improved.

Further, in the present embodiment, the discharges generated in the non-lighted pixels are weak discharges generated by the voltage application of the ramp waveform twice in the write preparation period 3 or 8, and
Only a weak discharge is generated by the voltage application of the ramp waveform in the wall charge returning period 5 or 10, and a strong discharge is not generated. Therefore, the brightness of black display can be suppressed and high contrast can be obtained. For example, the conventional P
In DP, the black luminance was about 10.8 cd / m ² . On the other hand, in the first embodiment, the black luminance could be set to 1.5 cd / m ² or less.

Next, a second embodiment of the present invention will be described. The configuration of the PDP in the second embodiment is the same as the configuration of the PDP according to the first embodiment described above. FIG. 7 is a waveform diagram showing a driving method of the PDP according to the second embodiment. As shown in FIG. 7, in the second embodiment, the common electrode C1 is set to the ground potential in the write preparation period 3c,
A voltage having a ramp waveform that continuously increases from the voltage Ve2 to the voltage Vp is applied to the scan electrode S. The voltage Vp is about 230 to 250V. Further, the potential of the common electrode C2 is maintained at the voltage Vs and the potential of the data electrode D is maintained at the ground potential. Similarly, in the writing preparation period 8c, the common electrode C2 is set to the ground potential, and the voltage of the ramp waveform continuously increasing from the voltage Ve2 to the voltage Vp is applied to the scan electrode S. Further, the potential of the common electrode C1 is maintained at the voltage Vs and the potential of the data electrode D is maintained at the ground potential.
As a result, in the write preparation period 3c, the wall charge arrangement directly changes from the state shown in FIG. 6B to the state shown in FIG. 6D without passing through the state shown in FIG. 6C. . Writing preparation periods 3c and 8c in the driving method according to the second embodiment.
The driving method other than the above is the same as the driving method other than the writing preparation periods 3 and 8 in the first embodiment described above.

In the second embodiment, two kinds of ramp waveforms applied to the common electrode C1 in the priming period 3a and the priming erasing period 3b in the first embodiment are applied to the scan electrode S. Can be replaced with the ramp waveform of. As a result, the weak discharges that occur once in the priming period 3a and the priming erasing period 3b in the above-described first embodiment, that is, twice in total, can be reduced to once in the second embodiment. Similarly, in the writing preparation period 8c, the weak discharge can be made once. Thereby, the black luminance can be further reduced. Further, the lengths of the write preparation periods 3c and 8c can be shortened as compared with the write preparation periods 3 and 8, and the sustain period 11 can be lengthened accordingly. This makes it possible to increase the brightness of the PDP.

Next, a third embodiment of the present invention will be described. The configuration of the PDP in the third embodiment is the same as the configuration of the PDP according to the first embodiment described above. FIG. 8 is a waveform diagram showing a driving method of the PDP according to the third embodiment. In the above-described first embodiment, the sustain erasing period is divided into the sustain erasing period 2 for odd-row pixels and the sustain erasing period 7 for even-row pixels. On the other hand, in the third embodiment, as shown in FIG. 8, the sustain erasing is performed on the pixels in all rows in the sustain erasing period 2a. That is, in the third embodiment, the sustaining and erasing periods 2 and 7 in the first embodiment are shared. Specifically, in the sustain erase period 2a, the voltage Ve1 is applied to the common electrode C2 as in the case of the common electrode C1.
A ramp waveform voltage that continuously decreases from the ground potential to the ground potential is applied. As a result, a discharge is generated between the common electrode C1 and the scan electrode S, and at the same time, a discharge is generated between the common electrode C2 and the scan electrode S. It should be noted that in the sustain erase period 2a of the third embodiment, the common electrode C1 and the scan electrode S are
The voltage applied to the data electrode D and the voltage applied to the data electrode D are the common electrode C1 and the scan electrode S in the sustain erase period 2 of the first embodiment.
And the voltage applied to the data electrode D. Also,
The driving method other than the sustain erasing period 2a in the third embodiment is the same as the driving method other than the sustain erasing period 2 in the first embodiment.

In the third embodiment, the sustain erase period 7 shown in the first embodiment can be omitted. In addition, the final sustain pulse in the sustain period 11 is set to the common electrodes C1 and C2.
And the same, and as a result, the wall charge inversion period 6 can be omitted. As a result, the sustain erase period and the wall charge inversion period can be shortened, and the sustain period 11 can be lengthened accordingly. Therefore, PDP
Higher brightness can be achieved. In the third embodiment, the drive waveforms of the second embodiment described above can be applied to the write preparation periods 3 and 8.

Next, a fourth embodiment of the present invention will be described. FIG. 9 is a sectional view showing one cell of a three-electrode AC type plasma display panel according to the fourth embodiment.
As shown in FIG. 9, in this embodiment, the height of the cell separating partition wall 34 formed on the surface of the lower insulating substrate 21 facing the upper insulating substrate 20 is higher than the surface of the upper insulating substrate 20. The height reaches the protective layer 25 formed on the. The configuration of the PDP of the fourth embodiment other than the above is
The configuration is the same as that of the PDP of the first embodiment described above. The driving method of the PDP in the fourth embodiment is the same as the driving method of the PDP in the first embodiment described above.

In the fourth embodiment, the cell separating partition wall 3
Since 4 is in contact with the protective layer 25, the phosphor layer 27 can be applied to the entire inner surface of the partition wall 34 in the cell 31, and the display of the PDP can have high brightness.

[0057]

As described in detail above, according to the present invention,
In the AC type plasma display panel in which the non-discharge gap between the scanning electrode and the common electrode is eliminated, it is possible to suppress the black luminance to a low level without generating a strong discharge in the non-lighted pixel. Thereby, good contrast characteristics can be realized.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing a three-electrode AC plasma display panel (PDP) according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view showing one cell of a three-electrode AC type plasma display panel according to the first embodiment.

FIG. 3 is a cross-sectional view showing a cross section taken along the line A-A ′ shown in FIG.

FIG. 4 is a waveform diagram showing a driving method of the PDP according to the first embodiment.

5A to 5D are schematic cross-sectional views showing a driving method of the PDP.

6A to 6F are schematic cross-sectional views showing the driving method of the PDP, showing the next step of FIG.

FIG. 7 is a waveform diagram showing a driving method of a PDP according to a second embodiment of the present invention.

FIG. 8 is a waveform diagram showing a driving method of a PDP according to a third embodiment of the present invention.

FIG. 9 is a sectional view showing one cell of a three-electrode AC type plasma display panel according to a fourth embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the structure of a cell in a conventional plasma display panel.

FIG. 11 is a plan view showing an electrode arrangement of a conventional plasma display.

FIG. 12 is a drive waveform diagram showing one subfield of a conventional three-electrode AC type plasma display panel.

[Explanation of symbols]

1; Subfield maintenance period 2, 2a; maintenance erase period 3,3c; Writing preparation period 3a; priming period 3b; priming elimination period 4; scanning period 5; Wall charge return period 6; Wall charge inversion period 7; Maintenance elimination period 8, 8c; Writing preparation period 9; scanning period 10; Wall charge return period 11; maintenance period 12; Pre-discharge period 13; scanning period 14: Positive polarity preliminary discharge pulse 15; Negative polarity preliminary discharge pulse 16; scan pulse 17: Scan base voltage 18; Data pulse 19; Sustain pulse 20; Upper insulating substrate 21; Lower insulating substrate 22; Scan electrode 23; common electrode 24; Transparent dielectric layer 25; Protective layer 26; Discharge space cell 27; Phosphor layer 28; White dielectric layer 29; Data electrode 30; PDP 31; cell 32; Metal electrode 33, 34; Cell partition wall 35, 36; Vertical line bulkhead 37; discharge gap 38; Non-discharge gap C, C1, C2; common electrode S: Scan electrode D: Data electrode

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) H04N 5/66 101 G09G 3/28 E

Claims (16)

[Claims] 1. A method of driving an AC type plasma display panel, comprising: a first and a second insulating substrate arranged to face each other; and a surface of the first insulating substrate facing the second insulating substrate. A plurality of scanning electrodes and common electrodes which are alternately provided and extend in the first direction, and a second insulating substrate which is provided on the side of the surface facing the first insulating substrate and which is orthogonal to the first direction. A plurality of data electrodes extending in the direction 2, a first dielectric layer formed so as to cover the scan electrodes and the common electrode, and a second dielectric layer formed so as to cover the data electrodes. And a partition disposed between the first insulating substrate and the second insulating substrate, the partition being disposed on the center line of the scanning electrode and extending in the first direction. The first portion is disposed on the center line of the common electrode. And a second portion extending in the first direction and a third portion arranged in each region between the data electrodes adjacent to each other and extending in the second direction form a lattice shape. A plurality of pixels are arranged by being surrounded by the partition wall, and a first pixel group and a second pixel group composed of a plurality of pixels arranged in the first direction are alternately arranged. Using the arranged AC type plasma display panel, one field for displaying one image is composed of one or a plurality of subfields, and this subfield is a first pixel group selected based on display data. A first scanning period during which wall charges are formed on pixels within the second pixel group, and a second scanning period during which wall charges are formed on pixels within a second pixel group that is temporally separated from the first scanning period and is selected based on display data. Scanning period, the scanning electrode and the AC type characterized by having a sustain period in which a sustain discharge is generated at the same timing in pixels in the first and second pixel groups in which the wall charges are formed by alternately applying a voltage to the through electrodes. Driving method for plasma display panel. 2. A first write preparation in which the subfield causes discharge in pixels in the first pixel group and discharge in pixels in the first pixel group during the first scanning period is facilitated. A period, and a second writing preparation period during which discharge is generated in the pixels in the second pixel group and discharge is easily generated in the pixels in the second pixel group in the second scanning period,
In the pixels in the first pixel group, weak discharge occurs in the pixels in which the wall charges are not formed in the first scanning period, and the charge state in the pixels is returned to the state immediately before the first writing preparation period. During the first wall charge returning period and the second scanning period in the pixels in the second pixel group, weak discharge is generated in the pixel in which the wall charge is not formed, and the charge state in this pixel is written in the second writing. Second to return to the state just before the preparation period
A wall charge returning period.
7. A method for driving an AC type plasma display panel as described in 1. 3. The discharge in the first writing preparation period and the second writing preparation period is performed by a scan electrode region corresponding to the scan electrode on the first dielectric layer and the first write layer.
3. The method for driving an AC type plasma display panel according to claim 2, wherein the surface discharge is generated between the dielectric layer and the common electrode region corresponding to the common electrode. 4. The AC according to claim 3, wherein the surface discharge is a weak discharge generated by gradually increasing a potential difference between the scan electrode and the common electrode.
Type plasma display panel driving method. 5. Immediately before the first write preparation period and immediately before the second write preparation period, both the wall charges formed in the scan electrode region and the wall charges formed in the common electrode region are The driving method of an AC type plasma display panel according to claim 2, wherein the driving method is an AC type plasma display panel. 6. The AC of claim 5, wherein wall charges generated in the scan electrode region and wall voltages generated in the common electrode region are substantially equal to each other. Type plasma display panel driving method. 7. The method according to claim 5, wherein the amount of wall charges formed in the scan electrode region and the amount of wall charges formed in the common electrode region are substantially equal to each other. Driving method of AC plasma display panel. 8. When the wall charge of the scan electrode region is negative in the first write preparation period and the second write preparation period, the negative wall charge amount is increased to increase the scan electrode region. The method of driving an AC type plasma display panel according to any one of claims 2 to 7, characterized in that when the wall charges of the positive polarity are positive, the amount of the positive wall charges is reduced. 9. In the first write preparation period and the second write preparation period, when the wall charge of the scan electrode region has a negative polarity, the negative wall charge amount is once decreased and then increased. The AC type plasma according to any one of claims 2 to 7, wherein when the wall charge of the scan electrode region has a positive polarity, the positive wall charge amount is once increased and then decreased. Display panel driving method. 10. The first electrodes in which the common electrodes are alternately arranged.
A common electrode and a second common electrode, and a potential difference between the second common electrode and the scan electrode is applied to the second common electrode on the first dielectric layer in the first write preparation period. The potential difference between the corresponding second common electrode region and the corresponding scanning electrode region is set so that no discharge is generated, and the potential difference between the first common electrode and the corresponding scanning electrode during the second writing preparation period is equal to the first difference. 10. The potential difference between the first common electrode region corresponding to the first common electrode on the dielectric layer and the scan electrode region is set so that no discharge is generated. Item 7. A method for driving an AC type plasma display panel according to item. 11. The first write preparation period has a first priming period and a first priming erase period, the second write preparation period has a second priming period and a second priming erase period, and In the first priming period, the scan electrode is set to the ground potential and the potential of the first common electrode is continuously increased to a first positive potential higher than a surface discharge start voltage between the scan electrode region and the common electrode region. And increasing the potential of the scan electrode to a second positive potential lower than the first positive potential and continuously decreasing the potential of the first common electrode in the first priming erase period. In the second priming period, the scan electrode is set to a ground potential and the potential of the second common electrode is connected to a first positive potential higher than the surface discharge inception voltage. And increasing the potential of the scan electrode to a second positive potential lower than the first positive potential and continuously increasing the potential of the second common electrode during the second priming erase period. The method of driving an AC type plasma display panel according to claim 10, further comprising a step of reducing the number. 12. A potential difference between the second common electrode and the scan electrode at the end of the first write preparation period, and the first common electrode and the scan electrode at the end of the second write preparation period. The method of driving an AC type plasma display panel according to claim 10 or 11, wherein the potential difference between the scanning electrode region and the common electrode region is set higher than a surface discharge starting voltage between the scanning electrode region and the common electrode region. 13. A potential difference between the second common electrode and the scan electrode at the end of the first write preparation period, and the first common electrode and the scan electrode at the end of the second write preparation period. 13. The method of driving an AC type plasma display panel according to claim 12, wherein the potential difference between the two is set to be 20 V or more higher than the surface discharge inception voltage. 14. The potential difference between the second common electrode and the scan electrode at the end of the first write preparation period and the first common electrode and the scan electrode at the end of the second write preparation period. The method of driving an AC type plasma display panel according to claim 12 or 13, wherein a potential difference between the two is less than a voltage obtained by adding 80 V to the surface discharge starting voltage. 15. The subfield has a first sustaining erase period before the first write preparation period and a second sustaining erase period before the second write preparation period. In the sustain erase period, the potential of the first common electrode is discharged between the scan electrode in the pixel in which the sustain discharge occurs in the subfield one time before the subfield to which the first write preparation period belongs. In the pixel which has been generated and in which the sustain discharge has not been generated in the previous subfield, the positive potential is set so that discharge is not generated between the pixel and the scan electrode.
After that, the method further includes a step of continuously decreasing the potential to the ground potential and setting the potential of the second common electrode to a potential at which discharge is not generated between the scan electrode and the second common electrode. In the pixel in which the sustain discharge is generated in the subfield one time before the subfield to which the second write preparation period belongs, the discharge is generated between the common electrode and the scan electrode, and In the pixel in which the sustain discharge is not generated in the subfield, the positive potential is set so that the discharge is not generated between the pixel and the scan electrode, and then the positive potential is continuously reduced to the ground potential, and
15. The method of driving an AC type plasma display panel according to claim 2, further comprising the step of setting a potential of the common electrode to a potential at which discharge is not generated between the common electrode and the scan electrode. 16. The first wall charge return period and the second wall charge return period
16. The weak discharge is generated by continuously changing the potential of the common electrode during a wall charge return period. 16. The A according to claim 2, wherein the weak discharge is generated.
Driving method for C-type plasma display panel.