JPH10149133A - Driving method for plasma display panel and plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform high-speed and stable write by executing the pilot effect of residual space charges generated by address time thin width elimination discharge to the entire surface of a panel. SOLUTION: For a cell 1, a front surface glass substrate 2 and a back surface glass substrate 3 are arranged so as to face each other across a discharge space, a first row electrode 4 and a second row electrode 5 are formed on the front surface glass substrate 2 so as to be paired with each other, a dielectric layer 6 is put on the row electrodes 4 and 5 and further, a magnesium oxide 7 is put on the dielectric layer 6. In an address period, a thin width elimination operation is performed by a thin width elimination pulse set to a head. While discharge is generated in all the cells, by providing a period for turning the applied voltage of all the electrodes inside the cell to zero immediately before the extinction of the discharge by the storage of wall charges occurs, the wall charges are neutralized by space charges and the cell is reset. Write discharge is performed following the thin width elimination discharge and the write discharge becomes the discharge of short discharge delay time by the residual space charges generated by the thin width elimination discharge.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AC plasma display panel, and more particularly, to a method for driving a surface discharge AC plasma display panel and a plasma display panel for realizing the driving method.

[0002]

2. Description of the Related Art FIG.
FIG. 1 is a partial perspective view showing a surface discharge type plasma display panel, which is one of the conventional AC type plasma display panels disclosed in Japanese Patent Application Laid-Open No. 7-287548 and Japanese Patent Application Laid-Open No. 7-287548. As shown, the surface discharge type plasma display panel 100 is configured as follows. A front glass substrate 102 and a rear glass substrate 103, which are display surfaces, are opposed to each other with a discharge space interposed therebetween, and the first row electrodes 104 (X1 to Xn) are arranged on the front glass substrate 103 so as to be paired with each other.
And a second row electrode 105 (Y1 to Yn). A dielectric layer 106 is coated on the row electrodes 104 and 105, and an MgO (magnesium oxide) 107 is further coated thereon. On the back glass substrate 103, row electrodes 104,
Column electrode 108 (W1
... Wn) are formed, and a phosphor layer 109 for emitting red, green, and blue light is provided on each column electrode 108 in a striped manner in order. Here, a column electrode 108 orthogonal to the row electrodes 104 and 105 forming a pair.
The three sets of red, green, and blue of the discharge cells at the intersection of constitute one pixel, and a partition 110 that separates these discharge cells and maintains a discharge space is provided. Ne-X is placed in the discharge space between the front glass substrate 102 and the rear glass substrate 103.
A discharge gas mainly containing a rare gas such as an e mixed gas or a He-Xe mixed gas is sealed.

Next, the operation will be described. A voltage pulse is alternately applied between the first row electrode 104 and the second row electrode 105 to generate a discharge whose polarity is inverted every half cycle,
The cell emits light. In color display, the phosphor layer 109 formed in each cell is excited by ultraviolet light from discharge to emit light. The first row electrode 104 and the second
Row electrodes 105 are covered with the dielectric layer 106, so that once a discharge occurs between the electrodes of each cell, the charged particles generated in the discharge space move in the direction of the applied electric field, and To accumulate. These accumulated charged particles are called wall charges. Since the electric field formed by the wall charges has the opposite polarity to the applied electric field, the discharge quickly disappears as the wall charges grow. When the electric field whose polarity is reversed from that of the previous discharge is applied after the discharge is extinguished, the electric field formed by the wall charges and the externally applied electric field are superimposed, so the applied voltage having a smaller absolute value than the previous discharge is applied. Discharge starts. Thereafter, the discharge can be maintained by the alternately inverted applied voltage having a small absolute value with the assistance of the wall charges.
Such a function is called a memory effect. A discharge sustained at a low applied voltage using the memory effect is called a sustain discharge, and the first row electrode 104 and the second row electrode 105 are provided every half cycle.
Is called a sustain pulse. This sustain discharge continues as long as the sustain pulse is applied, as long as the wall charges are not extinguished. The operation of eliminating wall charges is called erasing, and the first formation of wall charges on a dielectric is called writing.

Next, a brief description will be given of a gradation display method of an AC type plasma display panel. FIG. 14 is a diagram showing a configuration in one field showing a gradation display method of a conventional plasma display panel disclosed in, for example, JP-A-7-160218. One field is a time for displaying one picture on a screen, and is about 16.7 ms (60 Hz) in the case of NTSC. In the drawing, a display line is a line in the row direction composed of first and second row electrodes of an AC type plasma display panel, and the horizontal direction in the drawing is a time axis. One field is divided into a plurality of subfields, and each subfield includes a reset period, an address period, and a sustain discharge period. For example, in the case of 256 (2 ⁸ ) gray scale display, one field is divided into eight subfields, and the temporal weight of the sustain discharge period in each subfield is 2 ⁿ (n = 0 to 7).

FIG. 15 shows one of the conventional plasma display panels disclosed in, for example, JP-A-7-160218.
9 is a voltage waveform (timing chart) showing a driving method in a subfield. In this conventional example, the first row electrode X
Are connected in common on the entire surface of the panel, and a common voltage is applied to all the row electrodes X. On the other hand, the second
Row electrode Y and column electrode W can apply an individual voltage for each line. The voltage waveforms in the figure are the voltage waveforms applied to the column electrode Wj, the first electrode X, and the second row electrodes Y1, Y2, Yn in order from the top.

First, the reset period is a period in which all the cells of the AC type plasma display panel are brought into the same state. At the beginning of the reset period, the entire row is written to the first row electrodes X commonly connected to all the screens in FIG. A pulse Pp (priming pulse) is applied. Since the full write pulse Pp is set to be equal to or higher than the discharge start voltage between the first row electrode X and the second row electrode Y, all cells discharge and emit light regardless of whether or not light emission is performed in the previous subfield. At this time, a voltage pulse is also applied to the column electrode W. This is for suppressing the discharge between the first row electrode X and the column electrode W, and the potential difference between the XY electrodes is one. / 2 is set. When the full-surface write pulse Pp is applied, a strong discharge is generated between the X and Y electrodes, and wall charges of opposite polarities are accumulated in each of the X and Y electrodes, and the discharge is terminated. Next, in FIG. 3B, when the full write pulse Pp falls and the voltage applied to the first row electrode X and the second row electrode Y is removed, the rising discharge of the previous full write pulse Pp is applied between the X and Y electrodes. The electric field due to the accumulated wall charges remains. Since the voltage value of the entire-surface write pulse Pp is set so that this electric field is large enough to generate a discharge, an XY discharge occurs again. Since the discharge at this time does not have an externally applied voltage, the charged particles generated by the discharge neutralize the wall charges so that the electric field in the cell becomes zero. In this way, all cells can be written and erase reset regardless of the presence or absence of wall charges due to the lighting state of the previous subfield. A discharge generated by only the voltage of the wall charges without an externally applied voltage when performing the erasing operation is called a self-erasing discharge.

[0007] In the figure c after the reset period has ended, the first
Almost no wall charge remains on the row electrode X and the second row electrode Y. On the other hand, in the discharge cells, neutral particles that have been excited to a metastable level having a long life during the entire writing / erasing discharge remain, and serve as seed particles that lower the firing voltage in the following discharge. do. That is, the full-surface write pulse has two effects of reset and pilot light.

The address period is a period for controlling the presence or absence of wall charges in each cell by selecting an arbitrary cell on the screen in a matrix with row electrodes and column electrodes. In the address period, first, a negative scan pulse PSa is sequentially applied to the second row electrodes Y1 to Yn by scanning. On the other hand, a positive address pulse Pa corresponding to image data is applied to the column electrode W. Second
Pulse P _Sa applied to the row electrode Y and the column electrode W
An arbitrary cell is matrix-selected by the address pulse Pa applied to the cell. The potential difference between YW of the cell selected by the scan pulse P _Sa and the address pulse Pa is Y
The voltage is set to be equal to or higher than the discharge starting voltage of the -W discharge, and the YW discharge occurs only in the cells selected in the matrix. Also,
During the address period, the first row electrode X connected in common is
Is applied with a positive voltage, but the voltage value is set so as not to cause a discharge between the XY electrodes or the XW electrodes. However, when a YW discharge occurs in a cell selected in a matrix by the first row electrode Y and the column electrode W, this discharge triggers an XY discharge. The XY discharge in this address period is called a write sustain discharge, and wall charges are accumulated in the first row electrode X and the second row electrode Y. The duration of the scan pulse P _Sa applied to the second row electrode Y and the address pulse Pa applied to the column electrode W needs a time of about 3 μs in order to reliably perform the write sustain discharge. Therefore, it takes (duration of scan pulse P _Sa ) × (number of lines) time for the address period to complete scanning of scan line P _Sa on all lines of the screen. For example, in the case of the VGA display, the scan pulse P
_Since the duration of _Sa is 3 μs and the number of lines is 480, 1.44 ms is required for the address period.

After the operation of all the screens of the second row electrodes Y1 to Yn is completed, a sustain discharge period continues. In the sustain discharge period, positive sustain discharge pulses are alternately applied to the first row electrodes X and the second row electrodes Y, and only the cells that have accumulated the wall charges in the address period perform the sustain discharge to emit light. The light emission luminance per subfield is determined by the number of sustain discharge pulses Ps. A plurality of subfields having different numbers of sustain discharge pulses Ps are arranged in one field for displaying one screen, and the combination of the subfields allows the plasma display panel to be used. Perform gradation expression. In addition, image quality improvement such as pseudo contour removal is achieved by subfield division.

As described above, the driving method for separating the address period and the sustain discharge period over the entire screen of the AC type plasma display panel is called "address / sustain separation method".

In the "address / sustain separation method", the charged particles generated by the reset discharge almost disappear in the address period, and the effect of the write sustain discharge as a seed particle in the address period cannot be expected, and the long life Only the seed fire effect by the metastable particles of appears. For this reason,
The write discharge generated between the first row electrode X and the column electrode W for performing the matrix selection has a large discharge delay time,
For stable writing, the write sustain pulse requires a duration sufficiently longer than the discharge delay time.

If the potential difference between the first row electrode X and the column electrode W for performing the matrix selection is increased, the discharge delay time of the write discharge is reduced, but this operation is performed by the first row electrode X or the column electrode W. An erroneous discharge occurs in a half-selected cell to which a voltage is applied to any one of the electrodes, and erroneous writing in which display other than the selected cell is performed during the sustain discharge period or a writing defect in which the selected cell is not written occurs. The characteristics are deteriorated. In a plasma display panel having a narrow writing margin, the operating voltage region is significantly limited.

[0013]

In the above-mentioned conventional driving method, in the address period, (the duration of the scan pulse _PSa ) × (the number of scan lines) per subfield.
Time is needed. Further, since the gradation of the plasma display panel is expressed by a combination of a plurality of subfields arranged in one field, the occupation time of the address period per field is (scan pulse P
Sa duration) × (the number of scanning lines) × (the number of subfields). On the other hand, in a plasma display panel aiming at multi-gradation and high image quality, the number of scanning lines of the entire screen and the number of sub-fields in one field tend to increase, and the occupation time of the address period in one field increases. However, there is a problem that the time of the sustain discharge light emission used for the above is shortened, or the number of subfields that can achieve the required gradation and image quality cannot be included in one field.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to surely perform a write sustain discharge while shortening a write sustain discharge time per line,
An object of the present invention is to provide a plasma display panel and a method of driving the panel, which can reduce the occupation time of the address period per subfield.

[0015]

According to the present invention, there is provided a method of driving a plasma display panel, comprising a plurality of first and second electrodes covered with a dielectric, and the first and second electrodes. A plurality of third electrodes arranged so as to form cells at right angles to at least one of the first electrode and the second electrode. A priming period in which a pulse having a voltage value and a pulse width that causes a discharge only in the cell lit in the previous subfield is applied to the first or third electrode or the third electrode to accumulate wall charges; A pulse having a voltage value and a pulse width that causes a discharge by the wall voltage and the applied voltage generated by the wall charges accumulated between the first and second electrodes or the first and third electrodes is applied. A reset discharge in which the post-applied voltage is set to 0 to eliminate wall charges; and a reset discharge between the first electrode or the second electrode and the third electrode within the duration of the discharge pilot particles generated by the reset discharge. A reset address period consisting of a write discharge for accumulating wall charges having a short discharge delay time with the aid of seed particles, and applying an AC voltage to the first electrode and the second electrode; And a sustain discharge period in which a sustain discharge is performed using the wall charges accumulated in the cell.

Further, the present invention specifies that a reset discharge is performed with a time timing shifted for each of one or more cell blocks.

Further, in the reset discharge, all the cells are discharged between the first electrode and the second electrode or between the first electrode and the third electrode, and are accumulated at the time of application of the pulse at the end of the pulse. This specifies that a self-erasing discharge is used to generate a discharge due to wall charges and neutralize the wall charges by the discharge.

Further, in the plasma display panel according to the present invention, the driving method is realized by the driving method according to any one of claims 1 to 3, wherein the writing discharge is performed with the aid of seed particles generated by the reset discharge. And the rows operated by the conventional driving method in which the priming period, the address period, and the sustain discharge period are completely separated from each other are provided alternately or in combination every plural rows. .

Further, a plurality of first and second electrodes covered with a dielectric material and a plurality of such electrodes are formed so as to form cells orthogonal to at least one of the first and second electrodes. In the plasma display panel provided with the third electrode provided, an auxiliary discharge row covered with a light-blocking member is provided between display rows, and an auxiliary discharge is performed prior to an address period of an image display field, and generated by the discharge. Writing for accumulating wall charges having a short discharge delay time between the first electrode or the second electrode and the third electrode within the duration of the discharged discharge pilot particles. This specifies that a discharge is to be performed.

According to the plasma display panel of the present invention, the duration of the write pulse and the scan pulse after the reset discharge or the auxiliary discharge according to the first, second, third and fourth aspects is reduced. The modulation is performed for each scanning line, and the writing discharge is performed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. Embodiment 1 FIG. FIG. 1 is a sectional view of a cell of a surface discharge type plasma display panel to which a method of driving a plasma display panel according to a first embodiment of the present invention is applied.
As shown in the figure, the cell 1 of the surface discharge type plasma display panel is configured as follows. A front glass substrate 2 and a rear glass substrate 3, which are display surfaces, are opposed to each other with a discharge space therebetween, and the first row electrode 4 (Xi) and the second row electrode 4 (Xi) are arranged on the front glass substrate 2 so as to form a pair. Row electrode 5 (Yi)
Are formed, and a dielectric layer 6 is coated on the row electrodes 4 and 5, and further a MgO (magnesium oxide) 7 is coated thereon. A column electrode 8 (Wj) is formed on the rear glass substrate 3 so as to be orthogonal to the row electrodes 4 and 5, and further emits red, green and blue light on the column electrode 8 for each column electrode. Phosphor layers 9 are provided in stripes in order. In addition, the discharge cells are separated by partition walls 10 that maintain a discharge space. In the discharge space sandwiched between the front glass substrate 2 and the rear glass substrate 3, Ne-Xe mixed gas or He
A discharge gas mainly composed of a rare gas such as a -Xe mixed gas is sealed.

FIG. 2 is a voltage waveform (timing chart) showing a method of driving the plasma display panel according to the first embodiment of the present invention. In the figure, the voltage waveforms are row electrodes Xi, row electrodes Yi, This is a voltage waveform applied to the column electrode Wj. The figure shows an example in which XY discharge is used for priming, and a priming pulse Pp
Is set to a voltage value and a pulse width at which self-erasing discharge does not occur although all discharge cells emit light. The priming pulse Pp causes wall charges to accumulate on the X and Y electrodes.

In the address period, a narrow erase operation is performed by the narrow erase pulse Pea set at the head. The narrow erase pulse Pea has a voltage value of about the same level as the sustain voltage pulse for a duration of about 1 μs or less, and causes a discharge in all the cells. By providing a period in which the voltage applied to all the electrodes is set to 0, the wall charges are neutralized by the space charges and the cell is reset.

A write discharge is performed successively to the narrow erase discharge. However, due to the residual space charge generated by the narrow erase discharge, the write discharge is a discharge having a short discharge delay time, and stable and high-speed writing can be realized.

The combination of the electrodes for performing the priming and the reset discharge is arbitrary. FIG. 3 shows an example in which the priming and the reset discharge are used between the Y and W electrodes.

Embodiment 2 FIG. FIG. 4 is a diagram showing a discharge delay time characteristic of a write discharge subjected to a pilot ignition effect by charged particles generated by a preceding discharge, using a time interval between the preceding discharge and the write discharge as a parameter. In other words,
This shows the evaluation of the lifetime of the residual space charge generated by the narrow reset discharge, and the time required for the end of the discharge in which writing is performed stably using the time interval from the preceding discharge to the writing discharge as a parameter. Is read from the emission waveform of the writing discharge. From this, it can be seen that a cell stably written by a write discharge pulse having a duration of 1.5 μs is 9 μs after the preceding discharge is completed. In addition, it can be seen that the shorter the time interval from the preceding discharge, the faster the write discharge is completed.

FIG. 5 is a voltage waveform (timing chart) showing a driving method of the plasma display panel according to the second embodiment of the present invention. All the scanning lines of the plasma display panel are divided into blocks, and the beginning of the address period of each block is shown. Each block is provided with a narrow erase pulse Pea. Since the residual space charge generated by the narrow erase discharge disappears in a certain time, the number of lines for performing the subsequent write discharge is determined by the life of the residual space charge and the total time required for the write discharge of all the lines in the block. . As a result, a pilot effect of the residual space charge generated by the narrow erase discharge at the time of addressing can be applied to the entire panel.

Embodiment 3 FIG. 6 is a voltage waveform (timing chart) showing a driving method of the plasma display panel according to the third embodiment of the present invention.
The voltage waveform is a voltage waveform applied to the row electrode Xi, the row electrode Yi, and the column electrode Wj in order from the top. In the figure, an XY discharge is used for priming, and the voltage value is a voltage value at which all cells discharge and emit light at the rising edge, without depending on the history of the lighting state of all subfields. It is set to a voltage value at which discharge is realized. By increasing the pulse width of the priming pulse Pp and setting the falling edge to the beginning of the address, charged particles generated by the self-erasing discharge can be used as seed particles for the writing discharge. Further, by shifting the timing at which the self-erasing discharge occurs for each of a plurality of divided lines of the screen, a high-speed and stable writing discharge can be realized over all lines with the aid of charged particles generated by the self-erasing discharge.

FIG. 7 is a voltage waveform showing another driving method of the plasma display panel according to the third embodiment of the present invention.
(Timing chart), in which voltage waveforms are voltage waveforms applied to a row electrode Xi, a row electrode Yi, and a column electrode Wj in order from the top. In the figure, an XY discharge is used for priming, a positive voltage is applied to the row electrode X and a negative voltage is applied to the row electrode Y at the same time. The voltage difference depends on the history of the lighting state of all subfields at the time of application. In addition, each cell takes a voltage value at which discharge light emission occurs. In addition, a discharge is not generated at the fall of the X electrode, but is set at a voltage value at which self-erasing discharge is realized at the rise of the Y electrode. . The priming pulse P _XP applied to the X electrode falls on all lines in common, but the priming pulse P _YP applied to the Y electrode is extended by increasing the pulse width so that the rising _edge is at the beginning of the address, causing self-erasing discharge. The generated charged particles can be used as seed particles for writing discharge. Also, by shifting the timing at which the self-erasing discharge occurs for each of a plurality of divided lines of the screen, a high-speed and stable writing discharge can be realized over all lines with the aid of charged particles generated by the self-erasing discharge. In addition, since the X electrode can apply a voltage common to all lines, the driving circuit can be simplified.

Embodiment 4 FIG. 8 is a diagram showing a plasma display panel according to Embodiment 4 of the present invention.
In the figure, three rows constitute one group, the center row operates by the driving method satisfying claims 1 and 3, and the outer two rows do not perform a narrow erase discharge at the time of addressing and apply a normal write pulse. I do.

Next, the operation will be described. FIG. 9 is a voltage waveform (timing chart) showing a method for driving a plasma display panel according to Embodiment 4 of the present invention.
Priming pulses P _XP and P _YP are applied to the center row, and discharge light emission occurs during priming in any of the subfields. Due to the priming discharge generated in the central one row, charged particles or long-lived metastable excited atoms flow into or be generated in the adjacent two outer rows, thereby providing a pilot effect for stabilizing the operation of the plasma display panel. At this time, in the adjacent two outer rows, the narrow erase pulse P _ep is applied during priming and reset is performed, but the narrow erase discharge by the narrow erase pulse P _ep depends on the lighting state of the previous subfield. However, when the previous subfield is not lit, the narrow erasure discharge is not performed, so that background light emission does not occur in cells other than the cell selected by the display information.

Prior to the address period, X
The electrode priming pulse P _XP ends, but no discharge occurs. In the subsequent address period, the Y-electrode priming pulse P _YP ends, and a self-erasing discharge is performed. By this discharge, charged particles are supplied not only to the central one row where the discharge was performed but also to two adjacent outer rows. . With the supplied charged particles, the subsequent writing discharge can be a stable discharge with a short discharge delay time. At this time, in the outer two rows, background light emission does not occur except for cells selected by the display information.

As described above, it is possible to realize a high-contrast plasma display panel in which background light emission other than cells selected by display information is suppressed while performing stable and high-speed writing over the entire screen.

In the example shown in FIG. 8, the group division is fixed within one subfield, but the group division is shifted by one line in the row direction for each subfield,
Background light emission can be uniformly generated over the entire screen.

In the example shown in FIG. 8, three rows are shown as one group, but the amount of charged particles that can be generated in a neighboring cell by cell discharge depending on the size of the cell of the plasma display panel is shown. For example, if three or more rows, for example, five rows are set as one group, and priming is performed, and a row for performing narrow-width erasing at the address is arranged at the center, background light emission is suppressed as compared with the example shown in FIG. A plasma display panel can be realized.

Embodiment 5 FIG. 10 is a view showing a plasma display panel according to a fifth embodiment of the present invention, in which an auxiliary discharge line covered with a light shielding member is provided between each line. FIG. 11 is a voltage waveform (timing chart) showing a driving method of the plasma display panel according to the fifth embodiment of the present invention. The display line is composed of three periods of reset, address, and sustain discharge. Background luminescence is suppressed by using narrow width erasing for discharging. During the address period, charged particles are supplied to the display line by the auxiliary discharge line, and high-speed and stable writing discharge can be realized in the display line.

In FIG. 10, the auxiliary discharge line is provided every other display line. However, the amount of charged particles that can be generated in a neighboring cell by cell discharge varies depending on the size of the cell of the plasma display panel. Therefore, by providing an auxiliary discharge line for every plural display lines, it is possible to simplify a circuit and a manufacturing process and to reduce power consumption.

Embodiment 6 FIG. FIG. 12 is a voltage waveform (timing chart) showing a driving method at the time of addressing the plasma display panel according to the sixth embodiment of the present invention, wherein the reset discharge or the reset discharge according to any one of claims 1 to 4 is performed. 5 an auxiliary discharge after the write pulse P _a and the duration of the scan pulse P _Sa modulates each scan line according to, to shorten the reset P _ea or auxiliary discharge write pulse duration immediately after the write discharge, subsequent subsequent The duration of the write pulse of the write discharge of the line is gradually extended. According to this method, as shown in FIG. 4, the charged particles generated by the reset or auxiliary discharge are attenuated with time, and the effect of increasing the writing discharge speed is reduced if the time interval between the preceding discharge and the writing discharge is widened. Therefore, more lines can be written within the life of the charged particles generated by the reset or auxiliary discharge, the writing time averaged over all lines is reduced, the background light emission is suppressed, and the drive circuit is divided into multiple blocks. Suppression of complication is achieved.

[0039]

Since the present invention is configured as described above, it has the following effects.

According to the method for driving a plasma display panel according to the present invention, a plurality of first and second electrodes covered with a dielectric material and at least one of the first and second electrodes is provided. A plurality of third electrodes arranged so as to form cells in a direction perpendicular to the first and second electrodes or the first and second electrodes or the first and second electrodes. For the three electrodes,
A priming period in which a pulse having a voltage value and a pulse width that causes a discharge to be applied only to the cells lit in the previous subfield and a wall charge is accumulated, and the first and second electrodes or the first and third electrodes A pulse having a voltage value and a pulse width that causes a discharge by the wall voltage and the applied voltage due to the wall charge accumulated in between is applied, and then the applied voltage is set to 0 to erase the wall charge. A method for accumulating wall charges having a short discharge delay time between the first electrode or the second electrode and the third electrode during the lifetime of the generated discharge pilot particles. A reset address period consisting of a write discharge, and an AC voltage applied to the first electrode and the second electrode to perform a sustain discharge utilizing wall charges accumulated on the dielectric. The driving method of a plasma display panel which is composed of a discharge period, stable writing discharge at a high speed is realized, it can be shortened address period of one subfield.

The method of driving a plasma display panel according to claim 1, wherein the time timing of the reset discharge is shifted for every one or more of the plurality of cell blocks. As a result, the address period in one subfield can be shortened.

Further, in the reset discharge, all the cells were discharged between the first electrode and the second electrode or between the first electrode and the third electrode, and accumulated at the time of application of the pulse at the end of the pulse. 3. A driving method for a plasma display panel according to claim 1, wherein an erasing discharge for generating a discharge due to the wall charge and neutralizing the wall charge by the discharge is used. As a result, the address period in one subfield can be shortened.

According to the plasma display panel of the present invention, a row for performing a write discharge assisted by seed particles generated from the reset discharge according to any one of claims 1 to 3, and a reset period High-speed and stable writing discharge by a plasma display panel characterized in that rows driven by the conventional driving method in which the address period and the sustaining discharge period are completely separated are arranged alternately or in combination in a plurality of rows. Is realized, and an address period in one subfield can be shortened, and a high-contrast plasma display panel in which background light emission is suppressed can be realized.

Further, a plurality of first and second electrodes covered with a dielectric and a plurality of such electrodes are formed so as to form a cell orthogonal to at least one of the first and second electrodes. In the plasma display panel having the third electrode provided, an auxiliary discharge electrode covered with a light shielding member is provided between display rows, and an auxiliary discharge is performed prior to an address period of an image display field, and the auxiliary discharge is generated by the discharge. For accumulating wall charges having a short discharge delay time between the first electrode or the second electrode and the third electrode within the duration of the discharged discharge pilot particles. A plasma display panel characterized by performing a write discharge realizes a high-speed and stable write discharge, shortens an address period in one subfield, and reduces background light emission. Plasma display panel can be realized in the example was high contrast.

Also, the duration of the write pulse and the scan pulse after the reset discharge according to any one of claims 1 to 4 or the auxiliary discharge according to claim 5 is modulated for each scan line, and the write discharge is performed. According to the driving method of the plasma display panel, which is performed, high-speed and stable writing discharge is realized, and the address period in one subfield can be shortened.

[Brief description of the drawings]

FIG. 1 is a sectional view of a cell of a surface discharge type plasma display panel to which a driving method of a plasma display panel according to a first embodiment of the present invention is applied;

FIG. 2 is a voltage waveform (timing chart) showing a driving method for reset discharge of XY electrodes of the plasma display panel according to the first embodiment of the present invention.

FIG. 3 is a voltage waveform (timing chart) showing a driving method for reset discharge of a YW electrode of the plasma display panel according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a discharge delay time characteristic of a write discharge subjected to a seeding effect by charged particles generated by a preceding discharge, using a time interval between the preceding discharge and the write discharge as a parameter.

FIG. 5 is a voltage waveform (timing chart) showing a driving method of the plasma display panel according to the second embodiment of the present invention.

FIG. 6 is a voltage waveform (timing chart) showing a driving method of the plasma display panel according to the third embodiment of the present invention.

FIG. 7 is a voltage waveform (timing chart) showing another driving method of the plasma display panel according to the third embodiment of the present invention.

FIG. 8 is a diagram showing a plasma display panel according to a fourth embodiment of the present invention.

FIG. 9 is a voltage waveform (timing chart) illustrating a method for driving a plasma display panel according to a fourth embodiment of the present invention.

FIG. 10 is a diagram showing a plasma display panel according to a fifth embodiment of the present invention.

FIG. 11 is a voltage waveform (timing chart) showing a driving method of a plasma display panel according to a fifth embodiment of the present invention.

FIG. 12 is a voltage waveform (timing chart) showing a driving method at the time of addressing a plasma display panel according to a sixth embodiment of the present invention.

FIG. 13 is a partial perspective view showing a conventional surface discharge type plasma display panel.

FIG. 14 is a diagram showing a configuration in one field showing a gradation display method of a conventional plasma display panel.

FIG. 15 is a voltage waveform (timing chart) showing a driving method in one subfield of the conventional plasma display panel.

[Explanation of symbols]

Reference Signs List 1 Plasma display panel cell, 2 front glass substrate, 3 back glass substrate, 4 first row electrode (X electrode), 5 second row electrode (Y electrode), 6 dielectric layer, 7 M
gO (magnesium oxide), 8 row electrode (W electrode), 9
Phosphor layer, 10 partition wall, 100 the plasma display panel, Pp priming pulse (entire surface write pulse), P _xp X electrodes priming pulse, P _Yp Y electrodes priming pulse, P _e erase pulse, P _ep priming when narrow erase pulses, P _ea address time narrow erase pulse, Pa address pulse, _Psa scan pulse, P
_s sustain pulse.

Claims (6)

[Claims] A plurality of first and second electrodes covered with a dielectric, and a plurality of such electrodes are formed so as to form a cell orthogonal to at least one of the first and second electrodes. In the method for driving a plasma display panel provided with a third electrode provided, the field for image display is the first electrode and the second electrode or the first electrode and the third electrode.
A priming period in which a pulse having a voltage value and a pulse width that causes a discharge to all the cells regardless of the display information of the previous subfield is applied to the electrodes to accumulate wall charges, and the first and second electrodes or the A reset discharge in which a pulse having a voltage value and a pulse width that causes a discharge by the wall voltage and the applied voltage due to the wall charge accumulated between the first and third electrodes and then applying an applied voltage of 0 to erase the wall charge is performed. A wall having a short discharge delay time between the first electrode or the second electrode and the third electrode within the duration of the discharge pilot particles generated by the reset discharge; A reset / address period consisting of a write discharge for accumulating electric charges, and applying an AC voltage to the first and second electrodes to utilize wall charges accumulated on the dielectric. Method of driving a plasma display panel, comprising the sustain discharge period in which sustain discharge Te. 2. The driving method of a plasma display panel according to claim 1, wherein a time timing of the reset discharge is shifted for every one or more cell blocks. 3. During a reset discharge, all cells are discharged between the first electrode and the second electrode or between the first electrode and the third electrode, and accumulated at the end of the pulse when applied. 3. The method of driving a plasma display panel according to claim 1, wherein an erasing discharge for generating a discharge by the wall charge and neutralizing the wall charge by the discharge is used. 4. A row operated by the driving method according to claim 1, wherein a write discharge is performed with the aid of seed particles generated by a reset discharge, and a priming period, an address period, and a maintenance period. A plasma display panel in which rows operated by a conventional driving method in which discharge periods are completely separated are arranged alternately or in combination in a plurality of rows. 5. A plurality of first and second electrodes covered with a dielectric, and a plurality of such electrodes are formed so as to form a cell orthogonal to at least one of the first and second electrodes. In the plasma display panel having the third electrode provided, an auxiliary discharge electrode covered with a light shielding member is provided between display rows, and an auxiliary discharge is performed prior to an address period of an image display field, and the auxiliary discharge is generated by the discharge. For accumulating wall charges having a short discharge delay time between the first electrode or the second electrode and the third electrode within the duration of the discharged discharge pilot particles. A plasma display panel characterized in that a writing discharge is performed. 6. The duration of a write pulse and a scan pulse subsequent to the reset discharge according to any one of claims 1 to 4 or the auxiliary discharge according to claim 5 is modulated for each scan line, and the write discharge is performed. A plasma display panel characterized in that the plasma display panel is configured to perform the following.