JPH1165516A - Method and device for driving plasma display panel - Google Patents

Method and device for driving plasma display panel

Info

Publication number
JPH1165516A
JPH1165516A JP9221530A JP22153097A JPH1165516A JP H1165516 A JPH1165516 A JP H1165516A JP 9221530 A JP9221530 A JP 9221530A JP 22153097 A JP22153097 A JP 22153097A JP H1165516 A JPH1165516 A JP H1165516A
Authority
JP
Japan
Prior art keywords
electrode group
sustain discharge
selecting
discharge
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9221530A
Other languages
Japanese (ja)
Inventor
Takeo Masuda
健夫 増田
Masaharu Ishigaki
正治 石垣
Takashi Sasaki
孝 佐々木
Yuji Sano
勇司 佐野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9221530A priority Critical patent/JPH1165516A/en
Publication of JPH1165516A publication Critical patent/JPH1165516A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/293Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge
    • G09G3/2932Addressed by writing selected cells that are in an OFF state

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Gas-Filled Discharge Tubes (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)

Abstract

PROBLEM TO BE SOLVED: To surely execute address discharge in an entire whole panel, even when a number of cells in the panel is increased by changing a potential difference between an address electrode and a Y-electrode during the addressing period. SOLUTION: By boosting a voltage Va of an addressing pulse APm applied on an address electrode with the lapse of time or lowering a voltage Vysc of a scanning pulse SPm of the Y-electrode with the lapse of time in an addressing period of driving a plasma display panel, the potential difference between the address electrode and the Y-electrode is kept higher than a discharge start voltage and normal addressing discharge is performed, even when an electric charge having polarity opposite to the applied voltage is stored on the address electrode. By further applying a compensating voltage v(t) in accordance with the lapse of time from the starting time of addressing period, the voltage portion canceled by the electric charge stored on the address electrode is compensated, even in a cell whose address discharge is executed in the later time of the addressing period and stable address discharge is executed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、メモリ機能を有す
る気体放電表示素子(セル)の集合によって構成された
マトリクス型表示パネル、特にAC型プラズマ・ディス
プレイ・パネル(Plasma Display Panel;PDP)にお
いて、高品質な画像の表示を可能とする駆動方法および
駆動装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type display panel constituted by a collection of gas discharge display elements (cells) having a memory function, and more particularly to an AC type plasma display panel (PDP). The present invention relates to a driving method and a driving device capable of displaying a high-quality image.

【0002】[0002]

【従来の技術】従来のAC型プラズマディスプレイパネ
ルの一例の構造の一部を図2に分解斜視図で示す。プラ
ズマディスプレイパネルには、背面ガラス基板12と前
面ガラス基板4に挟まれた空間内に所定のガスが封入さ
れている。背面ガラス基板12上には、アドレス電極1
1が複数本並列に配置されており、それらアドレス電極
11を完全に覆う形で誘電体層8bが形成されている。
この誘電体層8b上には、隔壁9がアドレス電極11と
平行に各アドレス電極11の両側に形成されている。紫
外線の照射により、それぞれが赤色、緑色、青色に発光
する螢光体10R、10G、10Bが、隔壁9の壁面お
よび背面ガラス基板12上の誘電体層8b上に塗布され
ている。
2. Description of the Related Art FIG. 2 is an exploded perspective view showing a part of the structure of an example of a conventional AC type plasma display panel. In the plasma display panel, a predetermined gas is sealed in a space between the rear glass substrate 12 and the front glass substrate 4. The address electrode 1 is provided on the rear glass substrate 12.
1 are arranged in parallel, and a dielectric layer 8b is formed so as to completely cover the address electrodes 11.
On the dielectric layer 8b, partition walls 9 are formed on both sides of each address electrode 11 in parallel with the address electrodes 11. Phosphors 10R, 10G, and 10B, which emit red, green, and blue light upon irradiation with ultraviolet light, are applied on the wall surface of the partition wall 9 and the dielectric layer 8b on the rear glass substrate 12.

【0003】一方、前面ガラス基板4上には、背面ガラ
ス基板12上に形成されているアドレス電極11とは直
交する方向に、複数本のX透明電極5aと複数本のY透
明電極6aが平行に形成されている。さらにX透明電極
5a上にはXバス電極5bが、Y透明電極6a上にはYバ
ス電極6bが形成されている。また、これらX透明電極
5aおよびXバス電極5bと、Y透明電極6aおよびYバ
ス電極6bを完全に覆うように誘電体層8aが形成されて
おり、さらに誘電体層8a上には保護膜(MgO等)7
が形成されている。
On the other hand, a plurality of X transparent electrodes 5a and a plurality of Y transparent electrodes 6a are arranged on the front glass substrate 4 in a direction orthogonal to the address electrodes 11 formed on the rear glass substrate 12. Is formed. Further, an X bus electrode 5b is formed on the X transparent electrode 5a, and a Y bus electrode 6b is formed on the Y transparent electrode 6a. Further, a dielectric layer 8a is formed so as to completely cover the X transparent electrode 5a and the X bus electrode 5b and the Y transparent electrode 6a and the Y bus electrode 6b, and a protective film (not shown) is formed on the dielectric layer 8a. MgO, etc.) 7
Are formed.

【0004】これらの背面ガラス基板と前面ガラス基板
が、図2中の矢印の方向に、背面ガラス基板12上の隔
壁9の上に前面ガラス基板4上の保護膜7が接するよう
に合わさっている。バス電極が透明電極上外側にあるよ
うな一対のX電極5およびY電極6間にある隔壁間の溝
が1セルの放電空間13を形成している。
The rear glass substrate and the front glass substrate are joined in the direction of the arrow in FIG. 2 so that the protective film 7 on the front glass substrate 4 contacts the partition wall 9 on the rear glass substrate 12. . The groove between the partition walls between the pair of X electrode 5 and Y electrode 6 such that the bus electrode is on the outer side of the transparent electrode forms a discharge space 13 of one cell.

【0005】アドレス電極11は、維持放電を行うセル
に選択的に放電を行わせる電極である。X透明電極5a
およびXバス電極5bからなるX電極5は、Y電極との
間で維持放電を行う電極として働き、Y透明電極6aお
よびYバス電極6bからなるY電極6は、アドレス電極
11との間で維持放電を行うセルに選択的に放電を行わ
せるとともにX電極5との間で維持放電を行う電極とし
て働く。
[0005] The address electrode 11 is an electrode that selectively causes a cell that performs a sustain discharge to perform a discharge. X transparent electrode 5a
The X electrode 5 including the X bus electrode 5b functions as an electrode for performing sustain discharge with the Y electrode, and the Y electrode 6 including the Y transparent electrode 6a and the Y bus electrode 6b is maintained between the Y electrode 6 and the address electrode 11. The cell that performs the discharge selectively discharges, and also functions as an electrode that performs a sustain discharge with the X electrode 5.

【0006】上記電極の一例の配線図を図3に示す。第
1の電極であるX電極5は、セルの外部においてその一
端が全て共通に接続されるか、あるいは複数のブロック
に分けて共通に接続されており、ブロック毎に共通の駆
動電圧が印加される。第2の電極であるY電極Y1〜Ym
(mはY電極数)および第3の電極であるアドレス電極
A1〜An(nはアドレス電極数)は、一つ一つが独立に
配置されており、各々に異なる駆動波形を印加できる構
成となっている。
FIG. 3 shows a wiring diagram of an example of the above electrode. One end of the X electrode 5, which is the first electrode, is commonly connected to the outside of the cell, or is commonly connected to a plurality of blocks, and a common drive voltage is applied to each block. You. Y electrodes Y1 to Ym as second electrodes
(M is the number of Y electrodes) and address electrodes A1 to An (n is the number of address electrodes), which are third electrodes, are individually arranged one by one, so that different driving waveforms can be applied to each of them. ing.

【0007】一般的なAC型PDPの駆動シーケンス
は、特開平6−186927号公報に示されているよう
に、1フィールドが2つ以上のサブフィールドに分割さ
れており、それらサブフィールドは、リセット期間1
と、アドレス期間2と、維持放電期間3で構成されてい
る。
As shown in Japanese Patent Application Laid-Open No. 6-186927, the driving sequence of a general AC type PDP is such that one field is divided into two or more subfields, and these subfields are reset. Period 1
, An address period 2, and a sustain discharge period 3.

【0008】図4は、従来のサブフィールド駆動方法の
一実施例を示すものである。横軸は時間を、縦軸はY電
極Y1〜Ymを表わしている。ここでは1フィールド15
は、8個のサブフィールドSF1〜SF8と、全サブフィ
ールド分の総和時間と垂直同期信号Vsyncの1周期期間
との差で生じるブランク14で構成される。
FIG. 4 shows an embodiment of a conventional subfield driving method. The horizontal axis represents time, and the vertical axis represents Y electrodes Y1 to Ym. Here, 1 field 15
Is composed of eight subfields SF1 to SF8 and a blank 14 generated by a difference between the total time of all the subfields and one cycle period of the vertical synchronization signal Vsync.

【0009】サブフィールドSFiの構成を図5に示
す。サブフィールドSFiは、リセット期間1と、アド
レス期間2と、維持放電期間3から構成されており、全
てのサブフィールドSFiが同様な構成となっている。
リセット期間1は、リセット放電を行う期間であり、ア
ドレス期間でのアドレス放電をしやすくする励起粒子お
よび荷電粒子を生成する。アドレス期間2は、維持放電
を行うセルを選択してY電極6とアドレス電極11間で
アドレス放電を行わせる期間であり、その後、X電極5
とY電極6との間で維持放電が行われる。
FIG. 5 shows the structure of the subfield SFi. The subfield SFi includes a reset period 1, an address period 2, and a sustain discharge period 3, and all the subfields SFi have the same configuration.
The reset period 1 is a period for performing a reset discharge, and generates excited particles and charged particles that facilitate address discharge in the address period. The address period 2 is a period in which a cell for performing the sustain discharge is selected and the address discharge is performed between the Y electrode 6 and the address electrode 11, and thereafter, the X electrode 5
And a Y-electrode 6 causes a sustain discharge.

【0010】リセット期間1では、全セルにおいて電荷
の均一化もしくは電荷の消去を行なう。アドレス期間2
では、維持放電期間3において画像を表示するための維
持放電を行うセルを水平ライン毎に順次アドレス放電を
行ない、選択していく。維持放電期間3では、X電極お
よびY電極に同電圧同パルス幅の維持放電パルスが時間
的に交互に等間隔で印加される。選択されたセルでは、
各サブフィールドSF1〜SF8に与えられている維持放
電パルス数NSF1〜NSF8の回数だけ、維持放電を行
なう。例えば、サブフィールド数を8個とした場合、こ
の維持放電回数の比を例として2進符号で形成されるN
SF1:〜:NSF8=1:2:4:8:〜:128とす
れば、これらサブフィールドSFnの組合わせで256
階調を表示することが可能である。
In the reset period 1, the charges are made uniform or the charges are erased in all the cells. Address period 2
In the sustain discharge period 3, cells for performing sustain discharge for displaying an image in the sustain discharge period 3 are sequentially subjected to address discharge for each horizontal line and selected. In the sustain discharge period 3, sustain discharge pulses having the same voltage and the same pulse width are applied to the X electrode and the Y electrode alternately at regular intervals. In the selected cell,
Sustain discharge is performed by the number of sustain discharge pulses NSF1 to NSF8 given to each subfield SF1 to SF8. For example, when the number of subfields is eight, the ratio of the number of times of sustain discharge is used as an example, and N formed by a binary code is used.
If SF1 ::: NSF8 = 1: 2: 4: 8 ::: 128, the combination of these subfields SFn is 256.
It is possible to display gradation.

【0011】図6は、従来の駆動方法の一実施例のアド
レス期間2における駆動波形を示す。横軸は時間を、縦
軸は上から順に、(a)はX電極5の印加電圧波形を、
(b)はY電極6のY1電極の印加電圧波形を、(c)
はY電極6のY2電極の印加電圧波形を、(d)はY電
極6のYm電極の印加電圧波形を示している。(e)お
よび(f)はアドレス電極11に印加する電圧波形を表
わしている。なお、(e)は、垂直方向の全セルが選択
される場合を、(f)は、垂直方向の最初のセルと最後
のセルが選択される場合を示している。
FIG. 6 shows a driving waveform in an address period 2 in one embodiment of the conventional driving method. The horizontal axis represents time, the vertical axis from top to bottom, (a) shows the voltage waveform applied to the X electrode 5,
(B) shows the voltage waveform applied to the Y1 electrode of the Y electrode 6, (c)
Shows the applied voltage waveform of the Y2 electrode of the Y electrode 6, and (d) shows the applied voltage waveform of the Ym electrode of the Y electrode 6. (E) and (f) show the voltage waveform applied to the address electrode 11. (E) shows the case where all cells in the vertical direction are selected, and (f) shows the case where the first cell and the last cell in the vertical direction are selected.

【0012】アドレス期間中、図6(a)に示すよう
に、X電極5には電圧Vxsc、例えば60[V]が印加
されている。Y電極6には、図6(b)(c)(d)に
示すように、電圧Vyb、例えば−70[V]が印加され
ているが、維持放電を行なうセルを選択するためのアド
レス放電を行なうラインには水平ライン毎に、例えば1
ライン目には図6(b)に、2ライン目には図6(c)
に、最終ラインには図6(d)に示すように、電圧Vys
c、例えば−150[V]のスキャンパルスSPmが順次
印加される。
During the address period, a voltage Vxsc, for example, 60 [V] is applied to the X electrode 5 as shown in FIG. Although a voltage Vyb, for example, -70 [V] is applied to the Y electrode 6 as shown in FIGS. 6B, 6C and 6D, an address discharge for selecting a cell for performing a sustain discharge is performed. Is performed for each horizontal line, for example, 1
FIG. 6B shows the second line, and FIG. 6C shows the second line.
The voltage Vys is applied to the last line as shown in FIG.
c, for example, a scan pulse SPm of -150 [V] is sequentially applied.

【0013】このとき、図6(e)に示すように、アド
レス電極11に電圧Va、例えば60[V]のアドレス
パルスAPmがアドレス期間2中、全ラインのスキャン
パルスSPmに対応して印加されると、アドレス電極1
1上の垂直方向全セルにおいて、アドレス電極11とY
電極6間で放電開始電圧以上の電位差、例えば210
[V]が生じ、これら電極間で順次放電が行われる。X
電極5とY電極6間の電位差は、放電開始電圧よりやや
低い電位差、例えば210[V]であるので、この直
後、ほぼ同時にアドレス電極11とY電極6間での放電
が、X電極5とY電極6間に移行する。そして、X電極
5とY電極6間で放電を行ない、X電極5およびY電極
6上のMgO膜の表面にそれぞれ維持放電に必要な壁電
荷を順次形成する。以下、前記これら2つの放電を合わ
せてアドレス放電とする。
At this time, as shown in FIG. 6E, a voltage Va, for example, an address pulse APm of 60 [V] is applied to the address electrode 11 during the address period 2 in correspondence with the scan pulse SPm of all the lines. Then, address electrode 1
1 in all vertical cells on the address electrodes 11 and Y
A potential difference between the electrodes 6 equal to or higher than the discharge starting voltage, for example, 210
[V] is generated, and discharge is sequentially performed between these electrodes. X
Since the potential difference between the electrode 5 and the Y electrode 6 is slightly lower than the discharge starting voltage, for example, 210 [V], immediately after this, the discharge between the address electrode 11 and the Y electrode 6 is almost simultaneously performed with the X electrode 5. The transition is made between the Y electrodes 6. Then, a discharge is performed between the X electrode 5 and the Y electrode 6, and wall charges required for the sustain discharge are sequentially formed on the surfaces of the MgO films on the X electrode 5 and the Y electrode 6, respectively. Hereinafter, these two discharges are collectively referred to as an address discharge.

【0014】また、他の例としては、図6(f)のよう
なアドレスパルスAPmが印加された場合、最初のライ
ンと最後のラインに相当するアドレス電極11上のセル
でのみ、アドレス放電が行われる。
As another example, when an address pulse APm as shown in FIG. 6 (f) is applied, address discharge occurs only in cells on the address electrode 11 corresponding to the first line and the last line. Done.

【0015】[0015]

【発明が解決しようとする課題】従来のアドレス期間2
における各電極の印加電圧では、同一SFにてパネル
上、垂直方向にアドレス放電が水平ライン毎に順次多く
行われると、アドレス放電によって発生した電荷がアド
レス電極方向(溝方向)に拡散し、アドレス期間におい
てアドレス放電が行われる時期が遅いセルでは、アドレ
ス電極11の印加電圧により、アドレス電極An上に印
加電圧を打ち消す極性の電荷が蓄積されていく。このた
め、パネルの高精細化に伴い、セル数が増加すると、ア
ドレス期間が長くなったり、アドレス放電回数が増え、
アドレス放電が行われる時期が遅いセルほど蓄積電荷量
が増加し、アドレス電極11とY電極6間の電位差が小
さくなり、アドレス放電が行なわれにくくなる。また、
アドレス期間においてアドレス放電が行われる時期が遅
いセルでは、リセット期間で生成された励起粒子および
荷電粒子は時間経過とともに減衰してしまうため、アド
レス放電が行われにくくなる。その結果、高精細パネル
では、アドレス放電が行われず維持放電が行われなかっ
た非点灯セルが生じ易くなり、パネル全体での駆動時に
おいてアドレス電圧動作マージンが狭くなるといった問
題が発生した。
The conventional address period 2
With the applied voltage of each electrode in (1), when address discharges are sequentially performed in the same SF in the vertical direction on the panel for each horizontal line, the charges generated by the address discharges diffuse in the address electrode direction (groove direction), and In a cell in which the address discharge is performed late in the period, the charge applied to the address electrode 11 causes charges having a polarity that cancels the applied voltage to accumulate on the address electrode An. For this reason, as the number of cells increases as the definition of the panel increases, the address period becomes longer, and the number of address discharges increases.
A cell in which the address discharge is performed later has a larger amount of accumulated charge, a potential difference between the address electrode 11 and the Y electrode 6 becomes smaller, and it becomes difficult to perform the address discharge. Also,
In a cell in which the address discharge is performed late in the address period, the excited particles and the charged particles generated in the reset period attenuate over time, so that it is difficult to perform the address discharge. As a result, in a high-definition panel, non-lighted cells in which address discharge is not performed and sustain discharge is not performed are likely to occur, causing a problem that an address voltage operation margin is narrowed when driving the entire panel.

【0016】本発明の目的は、高精細ディスプレイにお
いてもパネル全体でアドレス放電を確実に行なうことに
よって、非点灯セルを無くし、アドレス動作マージンを
拡大し、パネル全面で均一性の良い、高品質な画像を提
供し得るプラズマディスプレイパネルの駆動方法および
駆動装置を提供することにある。
An object of the present invention is to eliminate the non-lighted cells, expand the address operation margin, and provide high uniformity and high quality over the entire panel by reliably performing address discharge on the entire panel even in a high definition display. An object of the present invention is to provide a driving method and a driving apparatus of a plasma display panel capable of providing an image.

【0017】[0017]

【課題を解決するための手段】上記目的を達成するた
め、本発明は、プラズマディスプレイパネルの駆動方法
におけるアドレス期間において、アドレス電極11に印
加するアドレスパルスAPmの電圧Vaを時間経過ととも
に上昇させるか、もしくはY電極6のスキャンパルスS
Pmの電圧Vyscを時間経過とともに低下させることによ
って、アドレス電極11上に印加電圧とは逆極性の電荷
が蓄積されてもアドレス電極11とY電極6間の電位差
を放電開始電圧以上に維持し、正常なアドレス放電を行
なうものである。
In order to achieve the above object, the present invention relates to a method of driving a plasma display panel, which comprises increasing a voltage Va of an address pulse APm applied to an address electrode 11 with time during an address period. Or the scan pulse S of the Y electrode 6
By lowering the voltage Vysc of Pm with the passage of time, the potential difference between the address electrode 11 and the Y electrode 6 is maintained at or above the discharge starting voltage even if charges having the opposite polarity to the applied voltage are accumulated on the address electrode 11, Normal address discharge is performed.

【0018】本発明は、前面ガラス基板には維持放電用
の第1の電極群と該電極群に平行に配した維持放電用お
よび維持放電セル選択用の第2の電極群を、背面ガラス
基板には前記第1の電極群および前記第2の電極群と交
差する方向に維持放電セル選択用の第3の電極群を有す
るプラズマディスプレイパネルの駆動方法において、維
持放電を行なわせるセルを選択する放電を行なう際の、
第3の電極群と第2の電極群の電位差が、アドレス期間
において変化するようにした。さらに、維持放電を行な
わせるセルを選択する放電を行なう際に、第3の電極群
と第2の電極群の電位差が、アドレス期間において増大
していくようにし、そのために、第3の電極群に印加さ
れる電圧が、アドレス期間において変化するようにする
か、第3の電極群に印加される電圧値が、アドレス期間
において二つ以上の値をとるようにし、もしくは第3の
電極群に印加される電圧が、アドレス期間において徐々
に上昇するようにした。
According to the present invention, a first electrode group for sustain discharge and a second electrode group for sustain discharge and selecting a sustain discharge cell arranged in parallel with the electrode group are provided on the front glass substrate. In the method for driving a plasma display panel having a third electrode group for selecting a sustain discharge cell in a direction intersecting the first electrode group and the second electrode group, a cell for performing a sustain discharge is selected. When performing discharge,
The potential difference between the third electrode group and the second electrode group changes during the address period. Further, when performing a discharge for selecting a cell to be subjected to the sustain discharge, the potential difference between the third electrode group and the second electrode group is increased during the address period. Or the voltage applied to the third electrode group takes two or more values during the address period, or the voltage applied to the third electrode group The applied voltage was increased gradually during the address period.

【0019】また、本発明は、上記プラズマディスプレ
イパネルの駆動方法において、維持放電を行なわせるセ
ルを選択する放電を行なう際に、第2の電極群に印加さ
れる電圧がアドレス期間において変化するようにする
か、第2の電極群に印加される電圧値がアドレス期間に
おいて二つ以上の値をとるようにするか、または、第2
の電極群に印加される電圧がアドレス期間において徐々
に低下するようにした。
Further, according to the present invention, in the above-described method for driving a plasma display panel, the voltage applied to the second electrode group changes during the address period when a discharge for selecting a cell for performing the sustain discharge is performed. Or the voltage value applied to the second electrode group takes two or more values in the address period, or
The voltage applied to the electrode group was gradually decreased during the address period.

【0020】本発明は、プラズマディスプレイパネルの
駆動方法において、維持放電を行なわせるセルを選択す
る放電を行なう両電極間の電位差を、セル毎に異ならせ
るようにするか、維持放電を行なわせるセルを選択する
放電を行なう両電極間の電位差が、アドレス期間におい
て変化するようにした。
According to the present invention, in a method of driving a plasma display panel, a potential difference between two electrodes for performing a discharge for selecting a cell for performing a sustain discharge is made different for each cell, or a cell for performing a sustain discharge is provided. The potential difference between the two electrodes for performing the discharge for selecting is changed during the address period.

【0021】さらに、本発明は、前面ガラス基板には維
持放電用の第1の電極群と該電極群に平行に配した維持
放電用および維持放電セル選択用の第2の電極群を、背
面ガラス基板には前記第1の電極群および前記第2の電
極群と交差する方向に維持放電セル選択用の第3の電極
群を有するプラズマディスプレイパネルの駆動装置にお
いて、維持放電を行なわせるセルを選択する放電を行な
う際に、第3の電極群に印加される電圧を、アドレス期
間において変化させる手段を設けるか、維持放電を行な
わせるセルを選択する放電を行なう際に、第3の電極群
に印加されるアドレスパルスを出力するドライバの電源
電圧をアドレス期間において変化させる電圧変調回路を
具備させた。また、維持放電を行なわせるセルを選択す
る放電を行なう際に、第3の電極群に印加されるアドレ
スパルスを出力するドライバをアドレス期間において電
圧変調回路でフローティング駆動させるようにした。
Further, according to the present invention, a first electrode group for sustain discharge and a second electrode group for sustain discharge and selecting a sustain discharge cell arranged in parallel with the electrode group are provided on the front glass substrate. In a driving apparatus for a plasma display panel having a third electrode group for selecting a sustain discharge cell in a direction intersecting the first electrode group and the second electrode group on a glass substrate, a cell for performing a sustain discharge is provided. When performing a selective discharge, means for changing the voltage applied to the third electrode group during the address period is provided, or when performing a discharge for selecting a cell for performing the sustain discharge, the third electrode group is changed. And a voltage modulation circuit that changes a power supply voltage of a driver that outputs an address pulse applied to the driver during an address period. In addition, when performing a discharge for selecting a cell to be subjected to the sustain discharge, a driver that outputs an address pulse applied to the third electrode group is floating-driven by the voltage modulation circuit in the address period.

【0022】また、本発明は、前面ガラス基板には維持
放電用の第1の電極群と該電極群に平行に配した維持放
電用および維持放電セル選択用の第2の電極群を、背面
ガラス基板には前記第1の電極群および前記第2の電極
群と交差する方向に維持放電セル選択用の第3の電極群
を有するプラズマディスプレイパネルの駆動装置におい
て、維持放電を行なわせるセルを選択する放電を行なう
際に、第2の電極群に印加される電圧を、アドレス期間
において変化させる手段を設けるか、維持放電を行なわ
せるセルを選択する放電を行なう際に、第2の電極群に
印加されるスキャンパルスを出力するドライバの電源電
圧をアドレス期間において変化させる電圧変調回路を具
備するか、維持放電を行なわせるセルを選択する放電を
行なう際に、第2の電極群に印加されるスキャンパルス
を出力するドライバをアドレス期間において電圧変調回
路でフローティング駆動させるようにした。
Further, according to the present invention, a first electrode group for sustain discharge and a second electrode group for sustain discharge and selecting a sustain discharge cell arranged in parallel with the electrode group are provided on the front glass substrate. In a driving apparatus for a plasma display panel having a third electrode group for selecting a sustain discharge cell in a direction intersecting the first electrode group and the second electrode group on a glass substrate, a cell for performing a sustain discharge is provided. When performing a selective discharge, means for changing the voltage applied to the second electrode group during the address period is provided, or when performing a discharge for selecting a cell for which a sustain discharge is to be performed, the second electrode group is required. A voltage modulation circuit for changing a power supply voltage of a driver that outputs a scan pulse applied to the address period during an address period, or performing a discharge for selecting a cell for performing a sustain discharge. And so as to float driven by a voltage modulation circuit in the driver address period for outputting a scan pulse applied to the electrode group.

【0023】[0023]

【発明の実施の形態】本発明の実施の形態について順に
説明する。図1に本発明の第1の実施の形態を示す。図
1は、本発明を実現する駆動方法のアドレス期間部分の
第1の実施形態を示したものである。横軸は時間を示
し、縦軸は上から順に、(a)はX電極5の印加電圧波
形を、(b)はY電極6のY1電極の印加電圧波形を、
(c)はY電極6のY2電極の印加電圧波形を、(d)
はY電極6のYm電極の印加電圧波形を示している。
(e)および(f)はアドレス電極11に印加する電圧
波形を表わしている。なお、例として(e)は垂直方向
の全セルが選択される場合を、(f)は垂直方向の最初
のセルと最後のセルが選択される場合を示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in order. FIG. 1 shows a first embodiment of the present invention. FIG. 1 shows a first embodiment of an address period portion of a driving method for realizing the present invention. The horizontal axis indicates time, and the vertical axis indicates, from the top, (a) the applied voltage waveform of the X electrode 5, (b) the applied voltage waveform of the Y1 electrode of the Y electrode 6,
(C) shows the voltage waveform applied to the Y2 electrode of the Y electrode 6, (d)
Indicates the waveform of the voltage applied to the Ym electrode of the Y electrode 6.
(E) and (f) show the voltage waveform applied to the address electrode 11. Note that, as an example, (e) shows a case where all cells in the vertical direction are selected, and (f) shows a case where the first cell and the last cell in the vertical direction are selected.

【0024】この実施の形態では、図1(e)に示すよ
うに、アドレス期間中にアドレス電極11に印加する電
圧を、初期値Va minから最終値Va maxまで直線的に上
昇させている。この電圧の時間的変化量を補正電圧とし
てv(t)とする。アドレス期間開始時刻をt=0、終
了時刻をt=Toとすると、最終値Va maxは、 Va max=Va min+v(To) となる。
In this embodiment, as shown in FIG. 1E, the voltage applied to the address electrode 11 during the address period is linearly increased from an initial value Va min to a final value Va max. The amount of temporal change of this voltage is set to v (t) as a correction voltage. Assuming that the address period start time is t = 0 and the end time is t = To, the final value Va max is Va max = Vamin + v (To).

【0025】上記のようにアドレス期間開始時刻からの
経過時間に応じて補正電圧v(t)をさらに印加するこ
とによって、アドレス放電がアドレス期間の遅い時期に
行われるセルでも、アドレス電極11上に蓄積した電荷
で打ち消された電圧分を補正することができ、安定した
アドレス放電を行なうことができる。図1(f)に示す
ように、垂直方向のすべてのセルが選択されず、アドレ
スパルスAPmが印加されない場合でも、図1(e)の
電圧変化は維持される。
As described above, by further applying the correction voltage v (t) in accordance with the elapsed time from the start time of the address period, even if the cell in which the address discharge is performed late in the address period, the cell remains on the address electrode 11. The voltage canceled by the accumulated charge can be corrected, and stable address discharge can be performed. As shown in FIG. 1F, even if all the cells in the vertical direction are not selected and the address pulse APm is not applied, the voltage change of FIG. 1E is maintained.

【0026】図7に第2の実施の形態を示す。この実施
の形態では、アドレス期間中のアドレス電極11に、初
期値Va minから最終値Va maxまで指数的に電圧が上昇
する補正電圧v(t)を加算した電圧を印加するように
した。これによっても、同様な効果を得ることができ
る。
FIG. 7 shows a second embodiment. In this embodiment, a voltage obtained by adding a correction voltage v (t) that increases exponentially from the initial value Va min to the final value Va max is applied to the address electrode 11 during the address period. With this, a similar effect can be obtained.

【0027】図8に本発明の第3の実施の形態を示す。
図8は、アドレス期間中のアドレス電極11の印加電圧
を、初期値Va minから最終値Va maxまで階段状にk段
階(k≧2、kは整数)で電圧が上昇する補正電圧v
(t)を加算して印加する例である。これによっても、
同様な効果が得られる。
FIG. 8 shows a third embodiment of the present invention.
FIG. 8 shows a correction voltage v in which the voltage applied to the address electrode 11 during the address period increases stepwise in k steps (k ≧ 2, k is an integer) from an initial value Va min to a final value Va max.
This is an example in which (t) is added and applied. This also
Similar effects can be obtained.

【0028】また、本発明の第4の実施の形態として、
図9に示すように、同一アドレス期間中に、水平ライン
を1ラインおきに奇数ラインのみアドレス放電を行なっ
ていき、次に偶数ラインのみをアドレス放電を行なって
いく駆動方式の場合、第3の実施の形態においてk=2
に相当する方法がある。
Further, as a fourth embodiment of the present invention,
As shown in FIG. 9, during the same address period, address driving is performed only on odd-numbered lines every other horizontal line, and then the address discharging is performed only on even-numbered lines. In the embodiment, k = 2
There is a method equivalent to

【0029】また前記第1〜4の実施の形態では、時間
的に隣接するアドレスパルスAPmに時間的隙間が無い
場合を例としているが、これに限定されること無く、時
間的隙間がある場合でも、その効果は有効である。
In the first to fourth embodiments, the case where there is no time gap between the address pulses APm temporally adjacent to each other is described as an example. However, the present invention is not limited to this. But the effect is effective.

【0030】さらに、前記第1〜4の実施の形態を実現
するには、図10に示すようにアドレスドライバ20の
電源に補正電圧v(t)を出力する電圧変調回路21を
接続すればよい。
Further, to realize the first to fourth embodiments, a voltage modulation circuit 21 for outputting a correction voltage v (t) may be connected to the power supply of the address driver 20 as shown in FIG. .

【0031】また、図11に示すように、定電圧電源回
路22とアドレスドライバ20と電圧変調回路21を直
列に接続することによって、アドレスドライバ20を該
電圧変調回路21によってフローティングし、電源には
Va minを出力する定電圧電源回路20を接続すること
で、前記第1〜4の実施の形態と同様な効果を得ること
ができる。このとき、例として、第1実施の形態の図1
(e)および(f)に相当するアドレス電極の駆動波形
は、それぞれ図12(a)(b)に示すようになる。
As shown in FIG. 11, by connecting a constant voltage power supply circuit 22, an address driver 20 and a voltage modulation circuit 21 in series, the address driver 20 is floated by the voltage modulation circuit 21 and the power supply is By connecting the constant voltage power supply circuit 20 that outputs Va min, the same effect as in the first to fourth embodiments can be obtained. At this time, as an example, FIG. 1 of the first embodiment is used.
The drive waveforms of the address electrodes corresponding to (e) and (f) are as shown in FIGS.

【0032】図13に、本発明の第5の実施の形態を示
す。ここでは、アドレス期間においてY電極6のスキャ
ンパルスの印加電圧Vyscを補正電圧−v(t)で徐々
に低下させていき、結果的にアドレス放電を生じさせる
アドレス電極11とY電極6間の電位差を増大させてい
る。この実施の形態においても、同様な効果が得られ
る。
FIG. 13 shows a fifth embodiment of the present invention. Here, in the address period, the applied voltage Vysc of the scan pulse of the Y electrode 6 is gradually decreased by the correction voltage −v (t), and as a result, the potential difference between the address electrode 11 and the Y electrode 6 that causes the address discharge. Is increasing. In this embodiment, the same effect can be obtained.

【0033】また、第5の実施の形態を実現する手段
を、図14に示す。この実施の形態では、定電圧電源回
路22とスキャンドライバ23と電圧変調回路を21直
列に接続することによって、スキャンドライバ23を該
電圧変調回路21によってフローティングし、電源には
Vscを出力する定電圧電源回路20を接続して、図13
に示す出力を得ている。
FIG. 14 shows a means for realizing the fifth embodiment. In this embodiment, the constant voltage power supply circuit 22, the scan driver 23, and the voltage modulation circuit 21 are connected in series, so that the scan driver 23 is floated by the voltage modulation circuit 21 and the power supply outputs a constant voltage Vsc. When the power supply circuit 20 is connected, FIG.
The output shown in is obtained.

【0034】[0034]

【発明の効果】以上説明したように、本発明によれば、
アドレス期間2中にアドレス電極11とY電極6間の電
位差を徐々に増大させることにより、アドレス期間の比
較的遅い時期にアドレス放電を行なうセルにおいても、
アドレス放電を確実に十分な強度で行なうことができ、
高精細化によるセルの微細化およびパネル内の総セル数
が増加しても、パネル全体で確実な動作を実現すること
ができる。
As described above, according to the present invention,
By gradually increasing the potential difference between the address electrode 11 and the Y electrode 6 during the address period 2, even in a cell that performs an address discharge at a relatively late time in the address period,
Address discharge can be reliably performed with sufficient intensity,
Even if the cells are miniaturized due to the high definition and the total number of cells in the panel is increased, a reliable operation can be realized in the entire panel.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明を実現する駆動方法のアドレス期間部分
の第1実施の形態を示す電圧波形図。
FIG. 1 is a voltage waveform diagram showing a first embodiment of an address period portion of a driving method for realizing the present invention.

【図2】AC型プラズマディスプレイパネルの構造の一
部を示す分解斜視図。
FIG. 2 is an exploded perspective view showing a part of the structure of the AC type plasma display panel.

【図3】AC型プラズマディスプレイパネルにおける各
電極の位置関係を表わす簡易構造図。
FIG. 3 is a simplified structural diagram showing a positional relationship of each electrode in an AC type plasma display panel.

【図4】従来の駆動方法におけるフィールド内の構成を
表わす駆動シーケンス図。
FIG. 4 is a driving sequence diagram showing a configuration in a field in a conventional driving method.

【図5】従来の駆動方法のにおけるある1サブフィール
ド内の駆動波形の構成を表わす駆動シーケンス図。
FIG. 5 is a drive sequence diagram showing a configuration of a drive waveform in one subfield in a conventional drive method.

【図6】従来の駆動方法における駆動波形のアドレス期
間部分を示す図。
FIG. 6 is a diagram showing an address period portion of a driving waveform in a conventional driving method.

【図7】本発明の第2の実施の形態を示すアドレス電極
印加電圧波形のアドレス期間部分の電圧波形図。
FIG. 7 is a voltage waveform chart of an address period portion of an address electrode applied voltage waveform according to the second embodiment of the present invention.

【図8】本発明の第3の実施の形態を示すアドレス電極
印加電圧波形のアドレス期間部分の電圧波形図。
FIG. 8 is a voltage waveform diagram of an address period portion of an address electrode applied voltage waveform according to a third embodiment of the present invention.

【図9】本発明の第4の実施の形態を示すアドレス電極
印加電圧波形のアドレス期間部分の電圧波形図。
FIG. 9 is a voltage waveform diagram of an address period portion of an address electrode applied voltage waveform according to a fourth embodiment of the present invention.

【図10】本発明の第1〜4の実施の形態を実現する駆
動装置の実施の形態を示すブロック図。
FIG. 10 is a block diagram showing an embodiment of a driving device for realizing the first to fourth embodiments of the present invention.

【図11】本発明の第1〜4の実施の形態を実現する駆
動装置の一実施の形態を示すブロック図。
FIG. 11 is a block diagram showing an embodiment of a driving device for realizing the first to fourth embodiments of the present invention.

【図12】本発明の第1の実施の形態を示すアドレス電
極印加電圧波形のアドレス期間部分の電圧波形図。
FIG. 12 is a voltage waveform diagram of an address period portion of an address electrode applied voltage waveform according to the first embodiment of the present invention.

【図13】本発明の第5の実施の形態を示すアドレス電
極印加電圧波形のアドレス期間部分の電圧波形図。
FIG. 13 is a voltage waveform diagram of an address period portion of an address electrode applied voltage waveform according to a fifth embodiment of the present invention.

【図14】本発明の第5の実施の形態を実現する駆動装
置の一実施の形態を示すブロック図。
FIG. 14 is a block diagram showing an embodiment of a driving device for realizing a fifth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 リセット期間 2 アドレス期間 3 維持放電期間 4 前面ガラス基板 5 X電極 5a X透明電極 5b Xバス電極 6 Y電極 6a Y透明電極 6b Yバス電極 7 保護膜 8a 前面板側誘電体層 8b 背面板側誘電体層 9 隔壁 10R、10G、10B 螢光体 11 アドレス電極 12 背面ガラス基板 13 放電空間 14 ブランク 15 フィールド 20 アドレスドライバ 21 電圧変調回路 22 定電圧電源回路 23 スキャンドライバ SFn サブフィールド SPm スキャンパルス APm アドレスパルス Reference Signs List 1 reset period 2 address period 3 sustain discharge period 4 front glass substrate 5 X electrode 5a X transparent electrode 5b X bus electrode 6 Y electrode 6a Y transparent electrode 6b Y bus electrode 7 Protective film 8a Front plate side dielectric layer 8b Back plate side Dielectric layer 9 Partition 10R, 10G, 10B Phosphor 11 Address electrode 12 Back glass substrate 13 Discharge space 14 Blank 15 Field 20 Address driver 21 Voltage modulator 22 Constant voltage power supply circuit 23 Scan driver SFn Subfield SPm Scan pulse APm Address pulse

───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐々木 孝 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所家電・情報メディア事業 本部内 (72)発明者 佐野 勇司 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所家電・情報メディア事業 本部内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takashi Sasaki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref.Hitachi, Ltd.Household Appliances & Information Media Business Unit (72) Inventor Yuji Sano Yoshida, Yoshida, Totsuka-ku, Yokohama, Kanagawa Prefecture No. 292, Hitachi, Ltd. Home Appliances and Information Media Division

Claims (16)

【特許請求の範囲】[Claims] 【請求項1】 前面ガラス基板には維持放電用の第1の
電極群と該電極群に平行に配した維持放電用および維持
放電セル選択用の第2の電極群を、背面ガラス基板には
前記第1の電極群および前記第2の電極群と交差する方
向に維持放電セル選択用の第3の電極群を有するプラズ
マディスプレイパネルの駆動方法において、 維持放電を行なわせるセルを選択する放電を行なう際
の、第3の電極群と第2の電極群の電位差が、アドレス
期間において変化することを特徴とするプラズマディス
プレイパネルの駆動方法。
A front glass substrate is provided with a first electrode group for sustain discharge and a second electrode group for sustain discharge and selecting a sustain discharge cell arranged in parallel to the electrode group, and a rear glass substrate. In a method of driving a plasma display panel having a third electrode group for selecting a sustain discharge cell in a direction intersecting with the first electrode group and the second electrode group, a discharge for selecting a cell for performing a sustain discharge is performed. A driving method of a plasma display panel, wherein a potential difference between a third electrode group and a second electrode group changes during an address period.
【請求項2】 前面ガラス基板には維持放電用の第1の
電極群と該電極群に平行に配した維持放電用および維持
放電セル選択用の第2の電極群を、背面ガラス基板には
前記第1の電極群および前記第2の電極群と交差する方
向に維持放電セル選択用の第3の電極群を有するプラズ
マディスプレイパネルの駆動方法において、 維持放電を行なわせるセルを選択する放電を行なう際
の、第3の電極群と第2の電極群の電位差が、アドレス
期間において増大していくことを特徴とするプラズマデ
ィスプレイパネルの駆動方法。
2. A front glass substrate is provided with a first electrode group for sustain discharge and a second electrode group for maintaining discharge and selecting a sustain discharge cell arranged in parallel with the electrode group. In a method of driving a plasma display panel having a third electrode group for selecting a sustain discharge cell in a direction intersecting with the first electrode group and the second electrode group, a discharge for selecting a cell for performing a sustain discharge is performed. A driving method of a plasma display panel, wherein a potential difference between a third electrode group and a second electrode group during the operation is increased in an address period.
【請求項3】 前面ガラス基板には維持放電用の第1の
電極群と該電極群に平行に配した維持放電用および維持
放電セル選択用の第2の電極群を、背面ガラス基板には
前記第1の電極群および前記第2の電極群と交差する方
向に維持放電セル選択用の第3の電極群を有するプラズ
マディスプレイパネルの駆動方法において、 維持放電を行なわせるセルを選択する放電を行なう際
に、第3の電極群に印加される電圧が、アドレス期間に
おいて変化することを特徴とするプラズマディスプレイ
パネルの駆動方法。
3. A front glass substrate is provided with a first electrode group for sustain discharge and a second electrode group for sustain discharge and selecting a sustain discharge cell arranged in parallel with the electrode group, and a back glass substrate is provided with a first electrode group for sustain discharge. In a method of driving a plasma display panel having a third electrode group for selecting a sustain discharge cell in a direction intersecting with the first electrode group and the second electrode group, a discharge for selecting a cell for performing a sustain discharge is performed. A method for driving a plasma display panel, wherein a voltage applied to a third electrode group changes during an address period.
【請求項4】 前面ガラス基板には維持放電用の第1の
電極群と該電極群に平行に配した維持放電用および維持
放電セル選択用の第2の電極群を、背面ガラス基板には
前記第1の電極群および前記第2の電極群と交差する方
向に維持放電セル選択用の第3の電極群を有するプラズ
マディスプレイパネルの駆動方法において、 維持放電を行なわせるセルを選択する放電を行なう際
に、第3の電極群に印加される電圧値が、アドレス期間
において二つ以上の値をとることを特徴とするプラズマ
ディスプレイパネルの駆動方法。
4. A front glass substrate is provided with a first electrode group for sustain discharge and a second electrode group for sustain discharge and selecting a sustain discharge cell arranged in parallel with the electrode group, and a rear glass substrate is provided with a second electrode group for sustain discharge selection. In a method of driving a plasma display panel having a third electrode group for selecting a sustain discharge cell in a direction intersecting with the first electrode group and the second electrode group, a discharge for selecting a cell for performing a sustain discharge is performed. A driving method of a plasma display panel, wherein a voltage value applied to the third electrode group takes two or more values in an address period when performing the operation.
【請求項5】 前面ガラス基板には維持放電用の第1の
電極群と該電極群に平行に配した維持放電用および維持
放電セル選択用の第2の電極群を、背面ガラス基板には
前記第1の電極群および前記第2の電極群と交差する方
向に維持放電セル選択用の第3の電極群を有するプラズ
マディスプレイパネルの駆動方法において、 維持放電を行なわせるセルを選択する放電を行なう際
に、第3の電極群に印加される電圧が、アドレス期間に
おいて徐々に上昇することを特徴とするプラズマディス
プレイパネルの駆動方法。
5. A front glass substrate is provided with a first electrode group for sustain discharge and a second electrode group for sustain discharge and selecting sustain discharge cells arranged in parallel to the electrode group, and a back glass substrate. In a method of driving a plasma display panel having a third electrode group for selecting a sustain discharge cell in a direction intersecting with the first electrode group and the second electrode group, a discharge for selecting a cell for performing a sustain discharge is performed. A driving method for driving the plasma display panel, wherein a voltage applied to the third electrode group is gradually increased during the address period.
【請求項6】 前面ガラス基板には維持放電用の第1の
電極群と該電極群に平行に配した維持放電用および維持
放電セル選択用の第2の電極群を、背面ガラス基板には
前記第1の電極群および前記第2の電極群と交差する方
向に維持放電セル選択用の第3の電極群を有するプラズ
マディスプレイパネルの駆動方法において、 維持放電を行なわせるセルを選択する放電を行なう際
に、第2の電極群に印加される電圧が、アドレス期間に
おいて変化することを特徴とするプラズマディスプレイ
パネルの駆動方法。
6. A front glass substrate is provided with a first electrode group for sustain discharge and a second electrode group for sustain discharge and selecting a sustain discharge cell arranged in parallel to the electrode group, and a back glass substrate is provided with a first electrode group for sustain discharge. In a method of driving a plasma display panel having a third electrode group for selecting a sustain discharge cell in a direction intersecting with the first electrode group and the second electrode group, a discharge for selecting a cell for performing a sustain discharge is performed. A method for driving a plasma display panel, wherein a voltage applied to a second electrode group changes during an address period.
【請求項7】 前面ガラス基板には維持放電用の第1の
電極群と該電極群に平行に配した維持放電用および維持
放電セル選択用の第2の電極群を、背面ガラス基板には
前記第1の電極群および前記第2の電極群と交差する方
向に維持放電セル選択用の第3の電極群を有するプラズ
マディスプレイパネルの駆動方法において、 維持放電を行なわせるセルを選択する放電を行なう際
に、第2の電極群に印加される電圧値が、アドレス期間
において二つ以上の値をとることを特徴とするプラズマ
ディスプレイパネルの駆動方法。
7. A front glass substrate is provided with a first electrode group for sustain discharge and a second electrode group for sustain discharge and selecting a sustain discharge cell arranged in parallel to the electrode group, and a back glass substrate is provided with a second electrode group for sustain discharge selection. In a method of driving a plasma display panel having a third electrode group for selecting a sustain discharge cell in a direction intersecting with the first electrode group and the second electrode group, a discharge for selecting a cell for performing a sustain discharge is performed. A driving method of a plasma display panel, wherein a voltage value applied to the second electrode group takes two or more values during an address period.
【請求項8】 前面ガラス基板には維持放電用の第1の
電極群と該電極群に平行に配した維持放電用および維持
放電セル選択用の第2の電極群を、背面ガラス基板には
前記第1の電極群および前記第2の電極群と交差する方
向に維持放電セル選択用の第3の電極群を有するプラズ
マディスプレイパネルの駆動方法において、 維持放電を行なわせるセルを選択する放電を行なう際
に、第2の電極群に印加される電圧が、アドレス期間に
おいて徐々に低下することを特徴とするプラズマディス
プレイパネルの駆動方法。
8. A front glass substrate is provided with a first electrode group for sustain discharge and a second electrode group for sustain discharge and selecting a sustain discharge cell arranged in parallel to the electrode group, and a rear glass substrate is provided with a second electrode group for sustain discharge selection. In a method of driving a plasma display panel having a third electrode group for selecting a sustain discharge cell in a direction intersecting with the first electrode group and the second electrode group, a discharge for selecting a cell for performing a sustain discharge is performed. A driving method of the plasma display panel, wherein a voltage applied to the second electrode group is gradually reduced during the address period.
【請求項9】 プラズマディスプレイパネルの駆動方法
において、維持放電を行なわせるセルを選択する放電を
行なう両電極間の電位差が、セル毎に異なることを特徴
とするプラズマディスプレイパネルの駆動方法。
9. A method of driving a plasma display panel, wherein a potential difference between two electrodes for performing a discharge for selecting a cell for performing a sustain discharge is different for each cell.
【請求項10】 プラズマディスプレイパネルの駆動方
法において、維持放電を行なわせるセルを選択する放電
を行なう両電極間の電位差が、アドレス期間において変
化することを特徴とするプラズマディスプレイパネルの
駆動方法。
10. A driving method of a plasma display panel, wherein a potential difference between two electrodes performing a discharge for selecting a cell for performing a sustain discharge changes in an address period.
【請求項11】 前面ガラス基板には維持放電用の第1
の電極群と該電極群に平行に配した維持放電用および維
持放電セル選択用の第2の電極群を、背面ガラス基板に
は前記第1の電極群および前記第2の電極群と交差する
方向に維持放電セル選択用の第3の電極群を有するプラ
ズマディスプレイパネルの駆動装置において、 維持放電を行なわせるセルを選択する放電を行なう際
に、第3の電極群に印加される電圧を、アドレス期間に
おいて変化させる手段を設けたことを特徴とするプラズ
マディスプレイパネルの駆動装置。
11. A first glass for sustaining discharge is provided on a front glass substrate.
And a second electrode group for sustain discharge and selecting a sustain discharge cell arranged in parallel with the electrode group, and the rear glass substrate intersects the first electrode group and the second electrode group. In a plasma display panel driving apparatus having a third electrode group for selecting a sustain discharge cell in the direction, a voltage applied to the third electrode group when performing a discharge for selecting a cell for performing a sustain discharge is determined by: A driving device for a plasma display panel, comprising a means for changing during an address period.
【請求項12】 前面ガラス基板には維持放電用の第1
の電極群と該電極群に平行に配した維持放電用および維
持放電セル選択用の第2の電極群を、背面ガラス基板に
は前記第1の電極群および前記第2の電極群と交差する
方向に維持放電セル選択用の第3の電極群を有するプラ
ズマディスプレイパネルの駆動装置において、 維持放電を行なわせるセルを選択する放電を行なう際
に、第3の電極群に印加されるアドレスパルスを出力す
るドライバの電源電圧をアドレス期間において変化させ
る電圧変調回路を具備することを特徴とするプラズマデ
ィスプレイパネルの駆動装置。
12. A first glass for a sustain discharge is provided on a front glass substrate.
And a second electrode group for sustain discharge and selecting a sustain discharge cell arranged in parallel with the electrode group, and the rear glass substrate intersects the first electrode group and the second electrode group. In a driving device for a plasma display panel having a third electrode group for selecting a sustain discharge cell in the direction, an address pulse applied to the third electrode group at the time of performing a discharge for selecting a cell for performing a sustain discharge is generated. A driving apparatus for a plasma display panel, comprising a voltage modulation circuit for changing a power supply voltage of a driver to output during an address period.
【請求項13】 前面ガラス基板には維持放電用の第1
の電極群と該電極群に平行に配した維持放電用および維
持放電セル選択用の第2の電極群を、背面ガラス基板に
は前記第1の電極群および前記第2の電極群と交差する
方向に維持放電セル選択用の第3の電極群を有するプラ
ズマディスプレイパネルの駆動装置において、 維持放電を行なわせるセルを選択する放電を行なう際
に、第3の電極群に印加されるアドレスパルスを出力す
るドライバをアドレス期間において電圧変調回路でフロ
ーティング駆動させることを特徴とするプラズマディス
プレイパネルの駆動装置。
13. A first glass for sustaining discharge is provided on a front glass substrate.
And a second electrode group for sustain discharge and selecting a sustain discharge cell arranged in parallel with the electrode group, and the rear glass substrate intersects the first electrode group and the second electrode group. In a driving device for a plasma display panel having a third electrode group for selecting a sustain discharge cell in the direction, an address pulse applied to the third electrode group at the time of performing a discharge for selecting a cell for performing a sustain discharge is generated. A driving apparatus for a plasma display panel, wherein an output driver is floating-driven by a voltage modulation circuit in an address period.
【請求項14】 前面ガラス基板には維持放電用の第1
の電極群と該電極群に平行に配した維持放電用および維
持放電セル選択用の第2の電極群を、背面ガラス基板に
は前記第1の電極群および前記第2の電極群と交差する
方向に維持放電セル選択用の第3の電極群を有するプラ
ズマディスプレイパネルの駆動装置において、 維持放電を行なわせるセルを選択する放電を行なう際
に、第2の電極群に印加される電圧を、アドレス期間に
おいて変化させる手段を設けたことを特徴とするプラズ
マディスプレイパネルの駆動装置。
14. A first glass for sustaining discharge on a front glass substrate.
And a second electrode group for sustain discharge and selecting a sustain discharge cell arranged in parallel with the electrode group, and the rear glass substrate intersects the first electrode group and the second electrode group. In a plasma display panel driving apparatus having a third electrode group for selecting a sustain discharge cell in a direction, a voltage applied to the second electrode group when performing a discharge for selecting a cell for performing a sustain discharge is determined by: A driving device for a plasma display panel, comprising a means for changing during an address period.
【請求項15】 前面ガラス基板には維持放電用の第1
の電極群と該電極群に平行に配した維持放電用および維
持放電セル選択用の第2の電極群を、背面ガラス基板に
は前記第1の電極群および前記第2の電極群と交差する
方向に維持放電セル選択用の第3の電極群を有するプラ
ズマディスプレイパネルの駆動装置において、 維持放電を行なわせるセルを選択する放電を行なう際
に、第2の電極群に印加されるスキャンパルスを出力す
るドライバの電源電圧をアドレス期間において変化させ
る電圧変調回路を具備することを特徴とするプラズマデ
ィスプレイパネルの駆動装置。
15. A first glass for sustaining discharge on a front glass substrate.
And a second electrode group for sustain discharge and selecting a sustain discharge cell arranged in parallel with the electrode group, and the rear glass substrate intersects the first electrode group and the second electrode group. In a driving apparatus for a plasma display panel having a third group of electrodes for selecting a sustain discharge cell in the direction, a scan pulse applied to the second group of electrodes is generated when performing a discharge for selecting a cell for performing a sustain discharge. A driving apparatus for a plasma display panel, comprising a voltage modulation circuit for changing a power supply voltage of a driver to output during an address period.
【請求項16】 前面ガラス基板には維持放電用の第1
の電極群と該電極群に平行に配した維持放電用および維
持放電セル選択用の第2の電極群を、背面ガラス基板に
は前記第1の電極群および前記第2の電極群と交差する
方向に維持放電セル選択用の第3の電極群を有するプラ
ズマディスプレイパネルの駆動装置において、 維持放電を行なわせるセルを選択する放電を行なう際
に、第2の電極群に印加されるスキャンパルスを出力す
るドライバをアドレス期間において電圧変調回路でフロ
ーティング駆動させることを特徴とするプラズマディス
プレイパネルの駆動装置。
16. A first glass for sustain discharge is provided on a front glass substrate.
And a second electrode group for sustain discharge and selecting a sustain discharge cell arranged in parallel with the electrode group, and the rear glass substrate intersects the first electrode group and the second electrode group. In a driving apparatus for a plasma display panel having a third group of electrodes for selecting a sustain discharge cell in the direction, a scan pulse applied to the second group of electrodes is generated when performing a discharge for selecting a cell for performing a sustain discharge. A driving apparatus for a plasma display panel, wherein an output driver is floating-driven by a voltage modulation circuit in an address period.
JP9221530A 1997-08-18 1997-08-18 Method and device for driving plasma display panel Pending JPH1165516A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9221530A JPH1165516A (en) 1997-08-18 1997-08-18 Method and device for driving plasma display panel

Publications (1)

Publication Number Publication Date
JPH1165516A true JPH1165516A (en) 1999-03-09

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