WO2011000201A1

WO2011000201A1 - Y driving circuit

Info

Publication number: WO2011000201A1
Application number: PCT/CN2009/076369
Authority: WO
Inventors: 霍伟
Original assignee: 四川虹欧显示器件有限公司
Priority date: 2009-06-30
Filing date: 2009-12-31
Publication date: 2011-01-06

Abstract

A Y driving circuit for driving plasma display includes a negative descent ramp scanning voltage generating circuit, which is set between the terminals Yout and YG of the Y driving circuit. During an addressing period, the negative descent ramp scanning voltage generating circuit generates a negative descent ramp scanning voltage (VYg=-(Vy+ΔVy)) on the basis of the negative voltage -Vy. The negative descent ramp scanning voltage applied to the Y electrodes descends as the addressing period extends.

Description

TECHNICAL FIELD The present invention relates to a cymbal drive circuit. BACKGROUND OF THE INVENTION Color AC plasma (AC-PDP) is developed based on the basic principle of gas discharge, and the display is realized by ultraviolet light emitted by a gas discharge to excite phosphor light. At present, the three-electrode surface discharge type AC-PDP is the most competitive type of PDP. For this type of AC-PDP, the addressing and display separation (ADS) technology is used to realize gray scale display. The field is divided into 8 or 10 or 12 subfields that are illuminated successively. Each subfield consists of a preparation period, an address period, and a sustain period. 256 levels of gray scale display can be realized by appropriate subfield combinations. The three electrodes of the three-electrode surface discharge type AC-PDP are orthogonally distributed on the front and rear substrates, and the discharge is performed between the two substrates. The front substrate is horizontally distributed with a sustain electrode (X electrode) and a scan electrode (Y electrode), and an address electrode (A electrode) is vertically disposed on the rear substrate. The X electrode and the Y electrode are parallel to each other and orthogonal to the A electrode. Figure 1 shows the driving waveform of a subfield in the ADS driving technology, which is divided into a preparation period, an addressing period, and a sustain period as shown in Fig. 1. In the preparation period, the three electrodes cooperate to erase the wall left by the previous subfield. The charge causes all display units of the full screen to reach a consistent initial state; during the address period, the driving circuit scans and addresses each line in an odd-even, top-down order, and writes image encoded data at the A electrode. All the cells to be displayed in the subfield accumulate a proper wall charge; during the sustain period, the X electrode and the Y electrode are alternately added with a sustain voltage, so that a cell which accumulates wall charges during the address period generates a discharge, thereby realizing image display. At the beginning of the preparation period, the voltage applied to the three electrodes is 0V, but the last sustain pulse at the end of the previous or previous subfield sustain period is applied to the X electrode, and the X electrode is accumulated after the sustain discharge. Negative wall charge accumulates positive wall charges on the Y electrode. Therefore, a wide positive ramp voltage (Vsetup « 350V ) that is much larger than the ignition voltage is applied to the Y electrode to cause discharge between the X and Y electrodes. Positive wall charges and negative wall charges are accumulated on the latter two electrodes, followed by a wide negative ramp voltage (VY « 170V;) on the Y electrode, and a positive step voltage (Vb) on the X electrode. « 150V ), let the X and Y electrodes slow down between '1' and reach the ignition voltage, discharge, neutralize X and Y The positive wall charge and the negative wall charge on the electrode finally bring the state of all the cells in the full screen to a consistent extinguished state, and the subsequent address period can be accurately addressed to each unit. The negative scan voltage generating circuit of the conventional Y driving circuit is as shown in FIG. 3, and the negative scanning voltage is generated by connecting the power switch tube Qrampdn to -Vy. The circuit structure is shown in the dotted line 4ϋ of Figure 3. The power switch Qrampdn is connected to -Vy and the other end is connected to the YG end of the scan chip (reference voltage terminal). During the address period, Qrampdn is turned on, and -Vy is applied to YG. At the end, the negative scan voltage is always -Vy for the entire address period, and the waveform is shown in Figure 1.

A major drawback of the ADS method is that the addressing takes too long, and as the resolution of the display increases, the required addressing time is longer. Longer addressing times mean that the time actually used to maintain the display becomes shorter. This is disadvantageous for improving the brightness of the display. In order to eliminate the pseudo contour problem existing in the plasma display using the ADS method, a method of increasing the display subfield can be generally used, but increasing the number of subfields also means a large increase in the address time, which also greatly reduces the sustain time. How to reduce the addressing time has become an important issue in PDP drivers, especially in high-resolution applications. Therefore, the present application proposes a Y driving circuit which can reduce the addressing time, that is, replace the circuit in the dotted line block of FIG. 2 with the circuit structure of FIG. SUMMARY OF THE INVENTION It is an object of the present invention to provide a gamma driving circuit to reduce addressing time, increase maintenance time, improve display brightness, improve picture quality, and reduce false contours. In order to achieve these and other advantages of the present invention, the present invention provides a Y driving circuit comprising: an address period negative falling ramp scanning voltage generating circuit disposed between the Yout and YG terminals of the Y driving circuit During the addressing period, the circuit generates a negative scan voltage at the YG terminal that changes to 4 以 in the form of a falling ramp to reduce the addressing time. Preferably, the Y driving circuit comprises a -A VY generating circuit floating in YG and a capacitor, two power switching tubes, and a diode; a positive terminal of the capacitor and a YG connection, a negative terminal and a diode anode connection, a diode cathode and - A VY generation circuit output connection, the negative terminal of the capacitor is connected to the emitter of a power switch tube, the drain of the power switch tube is connected to YG; the other switch tube is connected between Yout and YG, wherein the emitter and the Yout Connection, drain and YG connections. Preferably, the voltage stored on the capacitor is ΔVY, ΔVY is adjustable within a range of 5-20V, and the two power switches are interlocked. The driving circuit of the present application mainly sets a negative falling ramp wave scan between Yout and YG. The voltage generating circuit, the other parts are unchanged, and the negative falling ramp scanning voltage generating circuit is as shown in FIG. Generated by the switching power supply circuit -AVy, -AVy is connected to Yout through a diode D1 and capacitor CAVy. Yout is connected to the reference voltage terminal YG through a switch QpasslH. The negative terminal of CAVy is connected to the YG terminal through the switch QpasslL, and the positive terminal is connected to the Yout. At the beginning, Yout=0, so the voltage difference on CAVy is AVy. During the address period, the scan chip operates in the scan state, Qrampdn is turned on, Yout is pulled to -Vy, QscanL in Figure 3 is turned off, QscanH is turned on, and the voltage obtained at Yp is (Vsc-Vy;); QpasslH is turned off, QpasslL 4 is turned on, YG is pulled to - (Vy+AVy), thereby generating a negative falling ramp scanning voltage. Finally, a negative scanning pulse in the form of a falling ramp is obtained on the Y electrode according to the scan data. Since the negative scanning voltage is getting lower and lower, the larger the effective voltage (Va-VYg) applied to the display unit gas, effectively compensates for the address discharge delay caused by the decrease in the spatial ion concentration, so that shorter addressing can be selected. Time, increase useful hold time, improve display brightness, improve picture quality and reduce false contours. The present application uses a negative falling ramp scan voltage generating circuit which is disposed between the conventional Yout and YG. During the addressing period, the circuit structure generates a negative falling ramp scan on the basis of the negative voltage -VY. The voltage, applied to the reference voltage terminal YG of the scanning chip, can reduce the addressing time and increase the sustain time, which is advantageous for improving display brightness, improving image quality, and reducing false contours. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are set to illustrate,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, In the drawings: FIG. 1 is a driving waveform of a subfield on the X, Y, and 电极 electrodes of the prior art; FIG. 2 is a driving waveform of a subfield on the X, Y, and 电极 electrodes of the present invention; 3 is a prior art Y-driven negative scan voltage generating circuit; and FIG. 4 is a Y-driven negative falling ramp voltage generating circuit of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the accompanying drawings in conjunction with the embodiments. Referring to FIG. 2, it is a driving waveform of a subfield on the driving circuit X, Y, and 电极 three electrodes. Label 12345678910 is a phase of driving waveforms in a subfield, where 1234 is the preparation period, 567 is the addressing period, and the next few stages are the sustain period. Referring to Figures 3 and 4, Figure 4 is replaced with the portion of the dashed box of Figure 3, and the other circuit configurations are unchanged. At the beginning, that is, phase 1 in Figure 2, the voltage on Y is 0, when jt匕, Yout switches to YG, power switch QsusL turns on, YG connects to GND, and Y output voltage is 0V; In 2, the other switches are closed. The Y output of the scanning chip in Figure 3 is directly connected to the YP terminal through the chip control signal. The voltage amplitude is Vsc (about 110V), and the capacitor is connected between YP and YG, so the voltage of the two The difference is always Vsc; in phase 3, the switch Qsetup in Figure 3 is open, the other switches are off, and the Y output is exponentially ramped up to Vsetup (Vsetup=Vsc+Vs). The value of Vsetup is about 350V, slowly rising. The purpose is to neutralize most of the wall charges without a strong discharge, without a strong background light; in stage 4, the power switch QsusL of Figure 3 is turned on, the other switches are turned off, and the Y output is connected to GND, the output voltage is 0V; In phase 5, the switching transistor Qrampdn of Figure 4 is turned on, and the other switches are turned off, so that the YG voltage will be -Vy, so the Y output is ramped down to -Vy in an exponential manner, and the purpose of the ramp down is also In order not to happen On the basis of strong discharge, most of the wall charges are neutralized without strong background light; in the sixth stage, as shown in Figure 3, QscanL is turned off, and the Y output is connected to Vsc by scanning the chip control signal. At this time, the output is floating on -Vy, that is, the output is -Vy+Vsc. During the entire addressing period, the voltage on the unit that is not addressed is -Vy+Vsc, as shown in Figure 2. In phase 7, QpasslH is turned off, QpasslL is turned on, and the negative falling ramp circuit generates a negative falling ramp voltage (-(Vy+^Vy)), which is applied to the YG terminal of the scan chip, which is addressed by the scan data. The row Y drive circuit where the unit is located outputs a negative pulse in the form of a falling ramp wave; the next transition to the sustain period, in the eighth phase, the switch QsusL of Fig. 3 is opened, the other switches are closed, and the Y output is connected. To GND, make the output voltage 0V; the 9th stage is to maintain the rising edge of the pulse, and maintain the pulse amplitude as Vs. At this time, the energy recovery circuit will work. First, the switching transistors QerH, QpassL and QpasslH in Figure 3 are turned on, and the capacitor is turned on. Stored on Cer The charge inductors Ler and QpassL, QpasslH and the scan chip are transferred to the Y electrode. This part of the charge causes the voltage on the Y electrode to be about 80% of Vs. Next, the switch QsusH is turned on, and the other switches are turned off, which will maintain the rising edge of the pulse. The amplitude is pulled to Vs; the next 10th phase is to maintain the falling edge of the pulse, and the sustain voltage needs to be pulled to the 0 potential. In order to save energy, the charge is stored in the storage capacitor through the switching transistor QerL, and then passed through the switching transistor. QsusL pulls the output voltage amplitude to 0 potential, then repeats the rising and falling operations, completes the entire maintenance period, and then enters the driving process of the next subfield. Repeats the 10 processes similar to the previous one to complete the Y driving of all subfields. At the same time, with the X drive and the A drive, an image is displayed. Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device, or they may be separately fabricated into individual integrated circuit modules, or they may be Multiple modules or steps are made into a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software. The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the scope of the present invention are intended to be included within the scope of the present invention.

Claims

Claims A Y drive circuit, characterized in that it comprises:

The address period negative falling ramp scan voltage generating circuit is disposed between the Yout and YG terminals of the Y driving circuit. During the addressing period, the circuit generates a negative scanning voltage at the YG terminal that changes in the form of a falling ramp. A Y driving circuit according to claim 1, comprising: -Δ Vy generating circuit floating in YG and a capacitor, two power switching tubes, and a diode; a positive terminal of the capacitor and a YG connection, a negative terminal and Diode anode connection, diode cathode and -△ Vy generation circuit output connection, the negative terminal of the capacitor is connected with the emitter of a power switch tube, the drain of the power switch tube is connected with YG; the other switch tube is connected to Yout and YG Between, where the emitter is connected to the Yout, the drain is connected to the YG. The Y driving circuit according to claim 2, wherein the voltage stored in the capacitor is A Vy, ^ Vy is adjustable within a range of 5-20 V, and the two power switching tubes are interlocked.