CN102142225A - Addressing drive circuit of plasma display - Google Patents
Addressing drive circuit of plasma display Download PDFInfo
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- CN102142225A CN102142225A CN2011101199841A CN201110119984A CN102142225A CN 102142225 A CN102142225 A CN 102142225A CN 2011101199841 A CN2011101199841 A CN 2011101199841A CN 201110119984 A CN201110119984 A CN 201110119984A CN 102142225 A CN102142225 A CN 102142225A
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Abstract
The invention provides an addressing drive circuit of a plasma display. Besides a data drive chip, the circuit also comprises a positive addressing voltage generating circuit, wherein the positive addressing voltage generating circuit is located between the positive addressing voltage end Va and the VPP (Voltage Peak-Peak) end of the data drive chip and is used for generating more than one positive addressing voltage changing in the form of oblique rising waves at the VPP end during the addressing period. According to the technical scheme provided by the invention, the addressing time can be shortened, and the maintenance time can be prolonged.
Description
Technical field
The present invention relates to the plasma display field, in particular to a kind of addressing driving circuit of plasma display.
Background technology
Chromatic alternating-current plasma (AC-PDP) is to develop according to the ultimate principle of gas discharge, realizes showing by the ultraviolet excitation light-emitting phosphor that gas discharge sends.At present, three-electrode surface discharge type AC-PDP is the most competitive a kind of PDP type, adopt addressing and display separation (ADS) technology to realize what gray scale showed mostly for this AC-PDP, be about to a TV Field and be divided into successively luminous 8 or 10 or 12 son fields, each son field is formed by preparatory stage, address period and the phase of keeping, and just can realize 256 grades gray scale demonstration by the combination of suitable son.
Three electrode quadrature shapes of three-electrode surface discharge type AC-PDP are distributed on the front-back baseboard, and discharge is then carried out between two substrates.The prebasal plate horizontal distribution and is kept electrode (X electrode) and scan electrode (Y electrode), and addressing electrode (A electrode) is vertically distributing on metacoxal plate.X electrode and Y electrode are parallel to each other, and with A electrode quadrature.
Fig. 1 is the synoptic diagram of drive waveforms of son in the ADS Driving technique in the correlation technique.As shown in Figure 1, be divided into preparatory stage, address period and keep the phase.In the preparatory stage, three electrodes cooperatively interact, and wipe the wall electric charge that a son field is left over, and make full frame all display units reach consistent original state; In address period, driving circuit scans addressing to each row according to elder generation's strange back idol, top-down order, and writes image coded data at the A electrode, and the unit that all will be shown in this child field has accumulated suitable wall electric charge; In the phase of keeping, X electrode and Y electrode alternately add keeps voltage, makes the unit generation discharge that has accumulated the wall electric charge in address period, thereby realizes the demonstration of image.
Preparatory stage is when beginning, institute's making alive all is 0V on three electrodes, but, last when finishing of last or the last son field phase of keeping be added on the X electrode because keeping pulse, keep discharge back negative wall electric charge of accumulation on the X electrode, on the Y electrode, accumulated positive wall electric charge, therefore, on the Y electrode, add wide positive ramp voltage (Vsetup ≈ 350V) earlier much larger than firing voltage, make between X and Y electrode and discharge, discharge and accumulated positive wall electric charge and negative wall electric charge on latter two electrode respectively, on the Y electrode, add a wide negative ramp voltage (VY ≈ 170V) subsequently, on the X electrode, add a positive plateau voltage (Vb ≈ 150V), make between X and the Y electrode and slowly reach firing voltage, discharge, neutralize wall electric charge positive on X and the Y electrode and negative wall electric charge, make the state of full frame all unit reach the consistent state that extinguishes at last, address period subsequently just can be addressed to each unit accurately.Tradition A driving circuit as shown in Figure 2, positive addressing voltage Va produces by Switching Power Supply, Va directly and the Vpp of data driving chip hold and be connected, GND is connected with low pressure end, the positive addressing voltage perseverance of whole address period is Va, waveform is as shown in Figure 1.
It is exactly the overlong time that addressing takies that there is a major defect in the ADS method, and along with the raising of monitor resolution, the needed addressing time is just longer, and addressing time lengthening shortens with regard to meaning the time that really is used to keep demonstration, and this is disadvantageous for the brightness that improves display.In order to eliminate the false contouring problem that exists when plasma display adopts the ADS method, generally can adopt increases the method that shows the son field, but increases the increase greatly that sub-number of fields also means the addressing time, so also can reduce greatly to hold time.How reducing the addressing time has become the major issue that PDP faces in driving, and it is even more important particularly just to seem in high-resolution occasion.
Summary of the invention
At problem such as the addressing holding time that exists in the ADS technology in the correlation technique is long, the invention provides a kind of addressing driving circuit of plasma display, one of to address the above problem at least.
According to the present invention, provide a kind of addressing driving circuit.
Addressing driving circuit according to the present invention is except comprising: data driving chip, also comprise: positive addressing voltage produces circuit, between the VPP of positive addressing voltage end Va and data driving chip end, be used in address period, producing a positive addressing voltage that changes with rising ramp waveform formula at the Vpp end.
Above-mentioned positive addressing voltage produces circuit and comprises: Δ Va generative circuit, capacitor, first power switch pipe, second switch power tube and first diode, wherein, the positive pole of capacitor is connected with the negative electrode of first diode, and the negative pole of capacitor is connected with positive addressing voltage end Va; The anode of first diode is connected with Δ Va generative circuit, and the positive pole of capacitor is connected with the drain electrode of first power switch pipe, and the source electrode of first power switch pipe is connected with the Vpp end; The source electrode of second power switch pipe is connected with Va, and the drain electrode of second power switch pipe is connected with the source electrode of first power switch pipe.
Above-mentioned first power switch pipe is operated under the harmonic wave mode.
Above-mentioned addressing driving circuit also comprises: second diode and resistance, wherein, one end of the negative electrode of second diode and resistance also is connected to the source electrode that positive addressing voltage produces first power switch pipe in the circuit, and the anode of second diode and the other end of resistance and the VPP that is connected to data driving chip hold.
The voltage Δ Va that above-mentioned Δ Va generative circuit generates meets the following conditions: 5V≤Δ Va≤20V.
The voltage at above-mentioned capacitor two ends is Δ Va, wherein, and 5V≤Δ Va≤20V.
Above-mentioned first power switch pipe and the second power switch pipe interlocking.
Above-mentioned first power switch pipe and second power switch pipe be following one of at least: power field effect transistor MOSFET, insulated gate bipolar transistor IGBT.
By the present invention, in address period, positive addressing voltage produces circuit and produces a positive addressing voltage that changes with rising ramp waveform formula at the Vpp end, has solved problems such as the addressing holding time that exists in the ADS technology in the correlation technique is long, and then can reduce the addressing time, increase is held time.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the synoptic diagram of drive waveforms of son in the ADS Driving technique in the correlation technique;
Fig. 2 is the circuit theory diagrams of addressing driving circuit in the correlation technique;
Fig. 3 is the structural representation according to the addressing driving circuit of the embodiment of the invention;
Fig. 4 is the circuit theory diagrams of addressing driving circuit according to the preferred embodiment of the invention;
Fig. 5 is the drive waveforms of a certain son on X, Y, A three electrodes according to the preferred embodiment of the invention.
Embodiment
Hereinafter will describe the present invention with reference to the accompanying drawings and in conjunction with the embodiments in detail.Need to prove that under the situation of not conflicting, embodiment and the feature among the embodiment among the application can make up mutually.
Fig. 3 is the structural representation according to the addressing driving circuit of the embodiment of the invention.As shown in Figure 3, this addressing driving circuit is except comprising: data driving chip 1, also comprise: positive addressing voltage produces circuit 2, between the VPP of positive addressing voltage end Va and data driving chip end, be used in address period, producing a positive addressing voltage that changes with rising ramp waveform formula at the Vpp end.
Preferably, above-mentioned positive addressing voltage produces circuit and comprises: the Δ Va generative circuit, capacitor, first power switch pipe, second switch power tube and first diode that float on Va, wherein, the positive pole of capacitor is connected with the negative electrode of first diode, and the negative pole of capacitor is connected with positive addressing voltage end Va; The anode of first diode is connected with Δ Va generative circuit, and the positive pole of capacitor is connected with the drain electrode of first power switch pipe, and the source electrode of first power switch pipe is connected with the Vpp end; The source electrode of second power switch pipe is connected with Va, and the drain electrode of second power switch pipe is connected with the source electrode of first power switch pipe.
Wherein, above-mentioned first power switch pipe can be operated under the harmonic wave mode.In preferred implementation process, connect harmonic circuit by grid with first power switch pipe, first power switch pipe is operated under the harmonic wave mode.
Preferably, as shown in Figure 4, above-mentioned addressing driving circuit also comprises: second diode D2 and the resistance R, wherein, one end of the negative electrode of second diode and resistance also is connected to the source electrode that positive addressing voltage produces first power switch pipe in the circuit, and the anode of second diode and the other end of resistance and the VPP that is connected to data driving chip hold.
The circuit that above-mentioned second diode and resistance constitute, effectively current limliting prevents the VPP overshoot, prevents that data driving chip from burning out, and has played the effect of protected data chip for driving.
Preferably, the voltage Δ Va of Δ Va generative circuit generation meets the following conditions: 5V≤Δ Va≤20V.
Preferably, the voltage at above-mentioned capacitor two ends is Δ Va, wherein, and 5V≤Δ Va≤20V.
A large amount of experimental studies prove, when address period makes addressing voltage on the A electrode change 5V-20V, can make total addressing time decreased 30%, effectively increase and hold time, and help improving display brightness, improve image quality and reduce false contouring.
Wherein, in specific implementation process, first power switch pipe and the second power switch pipe interlocking.Promptly when first power switch pipe was opened, second power switch pipe opened and closed; When second power switch pipe was opened, first power switch pipe opened and closed.
In preferred implementation process, first power switch pipe and second power switch pipe can adopt but be not limited to following one of at least: power field effect transistor (MOSFET), igbt (IGBT).
Above-mentioned addressing driving circuit (also can be called the A driving circuit) mainly is a positive addressing voltage to be set produce circuit between Va and Vpp, as shown in Figure 4, by Δ Va generative circuit (for example, switching power circuit) produces Δ Va, Δ Va is relative Va, be connected to Va by a diode D1 (being equivalent to above-mentioned first diode) and capacitor C Δ Va (being equivalent to above-mentioned capacitor), Va is connected to Vaout by a switch Qpass (being equivalent to above-mentioned second power switch pipe), the negative pole of C Δ Va is connected to Va, positive pole is connected to the switch Qramp drain electrode end of (being equivalent to above-mentioned first power switch pipe), the source terminal of Qramp is connected to Vaout, incipient stage, switch Qpass opens among Fig. 4, Qramp closes, Vaout=Va, the Vpp end is pulled to Va, in address period, Qrampdn opens among Fig. 4, Qpass closes, the Vpp end is pulled to Va+ Δ Va, thereby produce the oblique wave addressing voltage that just rising, at last, according to address data obtain rising on the A electrode positive addressing pulse of oblique wave variation, because positive addressing voltage is more and more higher, the effective voltage (Vaw+Vy) that is applied on the display unit gas is big more, effectively having remedied the address discharge that is reduced to cause by the space ion concentration postpones, thereby can select the shorter addressing time, increase useful holding time, improve display brightness, improve image quality and reduce false contouring.
Further describe above-mentioned preferred implementation below in conjunction with Fig. 4 and Fig. 5.
Fig. 5 is the drive waveforms of a certain son on X, Y, A three electrodes according to the preferred embodiment of the invention; As shown in Figure 5,10. 9. 8. 7. 6. 5. 4. 3. 2. 1. number in the figure be each stage of an a son interior drive waveforms.Wherein, 5. 4. 3. 2. 1. be the preparatory stage, and 6. 7. the stage is an address period, 8. 9. 10. is the phase of keeping.
As shown in Figure 4, one son field at first, it is 1. 2. 3. 4. 5. stage preparatory stage among Fig. 5, Qramp (being above-mentioned first power switch pipe) closes, Qpass (being above-mentioned second power switch pipe) opens, the Vpp end is pulled to Va, and the data scanning chip is exported 0V by control signal, so the voltage on the A electrode is 0V; In 6. 7. address period stage, the switching tube Qramp of Fig. 4 opens, Qpass closes, make Vout voltage will be Va+ Δ Va, therefore realize that the Vpp terminal voltage rises to Va+ Δ Va with the slope form, the A driving circuit of the row at the place, unit that is addressed to by address data can be exported to the positive pulse of a rising oblique wave of these row A electrode form, and concrete waveform as shown in Figure 5; Keeping in stage phase, as shown in Figure 4, Qramp closes, Qpass opens this moment, and Vpp is pulled to Va, and the data scanning chip is exported 0V by control signal, so the voltage on the A electrode is 0V, in whole address period, the voltage on the unit that is not addressed to is 0, after enter the next son field the driving process, repeat 10 processes that similar front was said, the Y that finishes all son fields drives, and cooperates X to drive simultaneously and the A driving, finishes the demonstration of a field picture.
It should be noted that; it only is a preferred embodiment of the present invention that positive addressing voltage shown in Fig. 4 produces circuit; certainly; positive addressing voltage produces circuit and also has multiple equal mode of texturing and be equal to substitute mode, and the positive addressing voltage that can be in address period produces a positive addressing voltage that changes with rising ramp waveform formula at the Vpp end produces circuit all within protection domain of the present invention.
In sum, by the foregoing description provided by the invention, adopt a kind of positive addressing voltage to produce circuit, be arranged between traditional Va and the Vpp, in address period, this circuit produces the oblique wave addressing voltage that just rising on the basis of negative pressure Va, be applied to the Vpp end of data chip, can reduce the addressing time, increase is held time, and helps improving display brightness, improves image quality and reduces false contouring.
Obviously, those skilled in the art should be understood that, above-mentioned each module of the present invention or each step can realize with the general calculation device, they can concentrate on the single calculation element, perhaps be distributed on the network that a plurality of calculation element forms, alternatively, they can be realized with the executable program code of calculation element, carry out by calculation element thereby they can be stored in the memory storage, perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. the addressing driving circuit of a plasma display, comprising: data driving chip is characterized in that described addressing driving circuit also comprises:
Positive addressing voltage produces circuit, between the VPP of positive addressing voltage end Va and described data driving chip end, is used for producing a positive addressing voltage that changes with rising ramp waveform formula at described Vpp end in address period.
2. addressing driving circuit according to claim 1, it is characterized in that, described positive addressing voltage produces circuit and comprises: Δ Va generative circuit, capacitor, first power switch pipe, second switch power tube and first diode, wherein, the positive pole of described capacitor is connected with the negative electrode of described first diode, and the negative pole of described capacitor is connected with described positive addressing voltage end Va; The anode of described first diode is connected with described Δ Va generative circuit, and the positive pole of described capacitor is connected with the drain electrode of described first power switch pipe, and the source electrode of described first power switch pipe is connected with described Vpp end; The source electrode of described second power switch pipe is connected with Va, and the drain electrode of described second power switch pipe is connected with the source electrode of described first power switch pipe.
3. addressing driving circuit according to claim 2 is characterized in that, described first power switch pipe is operated under the harmonic wave mode.
4. addressing driving circuit according to claim 2, it is characterized in that, the addressing driving circuit also comprises: second diode and resistance, wherein, one end of the negative electrode of described second diode and described resistance also is connected to the source electrode that described positive addressing voltage produces first power switch pipe described in the circuit, and the anode of described second diode and the other end of described resistance and the VPP that is connected to described data driving chip hold.
5. according to each described addressing driving circuit in the claim 2 to 4, it is characterized in that the voltage Δ Va that described Δ Va generative circuit generates meets the following conditions: 5V≤Δ Va≤20V.
6. according to each described addressing driving circuit in the claim 2 to 4, it is characterized in that the voltage at described capacitor two ends is Δ Va, wherein, 5V≤Δ Va≤20V.
7. according to each described addressing driving circuit in the claim 2 to 4, it is characterized in that described first power switch pipe and the described second power switch pipe interlocking.
8. according to each described addressing driving circuit in the claim 2 to 4, it is characterized in that, described first power switch pipe and described second power switch pipe be following one of at least: power field effect transistor MOSFET, insulated gate bipolar transistor IGBT.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011101199841A CN102142225A (en) | 2010-09-30 | 2011-05-10 | Addressing drive circuit of plasma display |
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| CN201010507316 | 2010-09-30 | ||
| CN201010507316.1 | 2010-09-30 | ||
| CN2011101199841A CN102142225A (en) | 2010-09-30 | 2011-05-10 | Addressing drive circuit of plasma display |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1622151A (en) * | 2004-12-20 | 2005-06-01 | 彩虹集团电子股份有限公司 | Drive method for three-electrode surface discharge type plasma display |
| CN1753064A (en) * | 2004-09-23 | 2006-03-29 | 三星Sdi株式会社 | Method and apparatus of driving plasma display panel |
| CN101763811A (en) * | 2008-12-29 | 2010-06-30 | 四川虹欧显示器件有限公司 | Scanning-addressing voltage control circuit of plasma display and drive method thereof |
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2011
- 2011-05-10 CN CN2011101199841A patent/CN102142225A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1753064A (en) * | 2004-09-23 | 2006-03-29 | 三星Sdi株式会社 | Method and apparatus of driving plasma display panel |
| CN1622151A (en) * | 2004-12-20 | 2005-06-01 | 彩虹集团电子股份有限公司 | Drive method for three-electrode surface discharge type plasma display |
| CN101763811A (en) * | 2008-12-29 | 2010-06-30 | 四川虹欧显示器件有限公司 | Scanning-addressing voltage control circuit of plasma display and drive method thereof |
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Application publication date: 20110803 |