KR100649718B1 - Plasma Display and Driving Method thereof - Google Patents

Abstract

The present invention relates to a plasma display device and a driving method thereof for reducing afterimages.

The plasma display device alternately supplies sustain pulses to a scan electrode and a sustain electrode, and then at least one of a positive voltage and a negative voltage to an address electrode following the last sustain pulse supplied to one of the scan electrode and the sustain electrode. A drive part which supplies either is provided.

Description

Plasma display and driving method             

1 is a plan view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a perspective view showing in detail the structure of the discharge cell shown in FIG.

3 is a diagram illustrating a conventional frame including eight subfields in a method of driving a conventional plasma display panel.

4 is a waveform diagram illustrating a driving waveform for driving a conventional plasma display device.

5 is a diagram illustrating a test pattern of an afterimage experiment.

6 is a waveform diagram illustrating a method of driving a plasma display device according to a first embodiment of the present invention.

7 is a waveform diagram illustrating a method of driving a plasma display device according to a second embodiment of the present invention.

8 is a diagram showing an erase discharge for erasing charge on a lower plate.

9 is a waveform diagram illustrating a method of driving a plasma display device according to a third embodiment of the present invention.

10 is a block diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

101: timing controller 102: data driver

103: scan driver 104: sustain driver

105: driving voltage generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device and a driving method thereof, and more particularly to a plasma display device and a driving method thereof for reducing afterimages.

The plasma display panel (hereinafter referred to as "PDP") displays an image by emitting phosphors by ultraviolet rays generated during discharge of He + Xe, Ne + Xe, He + Xe + Xe gases. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP lowers the voltage required for discharge by using wall charges accumulated on the surface during discharge, and has advantages of low voltage driving and long life because it protects the electrodes from sputtering caused by the discharge.

1 and 2, the three-electrode AC surface discharge type PDP includes scan electrodes Y1 to Yn and sustain electrodes Z formed on the upper substrate 10, and addresses formed on the lower substrate 18. Electrodes X1 to Xm are provided.

The discharge cells 1 of the PDP are formed at the intersections of the scan electrodes Y1 to Yn, the sustain electrodes Z and the address electrodes X1 to Xm.

Each of the scan electrodes Y1 to Yn and the sustain electrode Z includes a transparent electrode 12 and a metal bus electrode 11 having a line width smaller than that of the transparent electrode 12 and formed at one edge of the transparent electrode. The transparent electrode 12 is typically formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrode 11 is formed of a metal on the transparent electrode 12 to reduce the voltage drop caused by the transparent electrode 12 having a high resistance. The upper dielectric layer 13 and the passivation layer 14 are stacked on the upper substrate 10 on which the scan electrodes Y1 to Yn and the sustain electrode Z are formed. On the upper dielectric layer 13, wall charges generated during plasma discharge are accumulated. The passivation layer 14 protects the electrodes Y1 to Yn and Z and the upper dielectric layer 13 from sputtering generated during plasma discharge and increases the emission efficiency of secondary electrons. As the protective film 14, magnesium oxide (MgO) is usually used.

The address electrodes X1 to Xm are formed on the lower substrate 18 in a direction crossing the scan electrodes Y1 to Yn and the sustain electrode Z. The lower dielectric layer 17 and the partition wall 15 are formed on the lower substrate 18. The phosphor layer 16 is formed on the surfaces of the lower dielectric layer 17 and the partition wall 15. The partition wall 15 is formed in parallel with the address electrodes X1 to Xm to physically distinguish the discharge cells, and prevents ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 16 is excited and emitted by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue.

An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne for discharging is injected into the discharge space of the discharge cell provided between the upper and lower substrates 10 and 18 and the partition wall 15.

The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. When the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. Each subfield SF1 to SF8 is divided into a reset period for initializing discharge cells, an address period for selecting discharge cells, and a sustain period for implementing gray levels according to the number of discharges. The reset period and the address period of each subfield SF1 to SF8 are the same for each subfield, while the sustain period and the number of discharges thereof are 2 ⁿ in each subfield (where n = 0,1,2,3,4). , 5,6,7).

4 shows a driving waveform of the PDP supplied to two subfields WSF1 and WSF2 in the selective writing method.

Referring to FIG. 4, the rising ramp waveform Ramp-up is simultaneously supplied to all the scan electrodes Y in the setup period SU of the reset period RST. At the same time, 0 [V] is supplied to the sustain electrode Z and the address electrode X. The rising ramp waveform Ramp-up causes a setup discharge with weak discharge between the scan electrode Y and the address electrode X and between the scan electrode Y and the sustain electrode Z in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y.

In the set-down period SD of the reset period, a falling ramp waveform Ramp-dn at which the voltage starts to drop from approximately the sustain voltage and drops to the base voltage GND or 0 [V] is simultaneously supplied to the scan electrodes Y. . While the falling ramp waveform Ramp-dn is supplied to the scan electrodes Y, the sustain electrode Z is supplied with a positive sustain voltage Vs, and 0 [V] is supplied to the address electrode X. do. When the falling ramp waveform Ramp-dn is supplied in this way, a set-down discharge occurs with a weak discharge between the scan electrode Y and the sustain electrode Z and between the scan electrode Y and the address electrode X. This set-down discharge eliminates unnecessary wall charges unnecessary for the address discharge among the wall charges formed during the setup discharge. Looking at the wall charge change in the reset period RST, there is almost no change in the wall charge on the address electrode X, and the negative (-) wall charges on the scan electrode Y formed during the setup discharge are partially caused by the setdown discharge. Is reduced. On the other hand, positive wall charges are formed on the sustain electrode Z during setup discharge, but negative wall charges are accumulated on the self as much as the decrease of the negative wall charges of the scan electrode Y during the set-down discharge. .

In the address period ADDR, the negative scan pulse SP is sequentially supplied to the scan electrodes Y, and at the same time, the positive data pulse DP is applied to the address electrodes X in synchronization with the scan pulse SP. Supplied. As the voltage difference between the scan pulse SP and the data pulse DP and the wall voltage generated during the reset period are added, an address discharge is generated in the on-cell to which the data pulse DP is supplied. In the on-cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is supplied. During this address period, the positive pole DC voltage Zdc is supplied to the sustain electrode Z.

In the sustain period SUT, the sustain pulse SUS is alternately supplied to the scan electrodes Y and the sustain electrodes Z. FIG. On-cells selected by the address discharge have a sustain discharge, that is, a display discharge, between the scan electrode Y and the sustain electrode Z whenever the sustain pulse SUS is supplied as the wall voltage and the sustain pulse SUS in the cell are added. Is generated. After the sustain discharge is completed, an erase ramp waveform (ramp-ers) is supplied to the sustain electrode (Z) to erase the wall charge remaining in the cells where the sustain discharge has occurred.

However, a conventional plasma display device may erase residual charges in a cell with an erase ramp waveform after the sustain discharge is completed, but may cause a problem that residual charges remain on the lower plate. This is because the erasure discharge caused by the erase ramp waveforms is caused by the surface discharge between the scan electrode Y and the sustain electrode Z, so that the charge on the upper plate, that is, the scan electrode Y and the sustain electrode Z, This is because the charges are satisfactorily erased, but the charges on the lower plate cannot be satisfactorily erased. This residual charge on the lower plate causes an erroneous discharge in the off-cell and causes an afterimage.

For example, for the afterimage experiment, the central local display area 50 is displayed in full white on the PDP of the specimen as shown in FIG. 5, and the other display areas are displayed in black. Then, when the discharge of the central local display region 50 is stopped, the local display region 50 is displayed when the local display region 50 is to be displayed in black by erasing the electric charge in the cell with the erase ramp waveform. After 50 hours, the image remains cloudy. In addition, the residual charge on the lower plate is excessively accumulated when the sustain discharge occurs due to overdischarge, and as described above, it causes an erroneous discharge and an afterimage to deteriorate the image quality and to reduce the driving voltage margin as well as to deteriorate the phosphor and cause a decrease in the lifetime.

Accordingly, an object of the present invention is to provide a plasma display device and a driving method thereof in which an afterimage is erased to reduce an afterimage.

In order to achieve the above object, a plasma display device according to the present invention alternately supplies sustain pulses to a scan electrode and a sustain electrode, and then an address electrode subsequent to the last sustain pulse supplied to any one of the scan electrode and the sustain electrode. And a driver for supplying at least one of a positive voltage and a negative voltage.

The driver supplies a narrow erase pulse of a positive voltage to the address electrode subsequent to the sustain pulse.

The driving unit continuously supplies the narrow erase pulse of the negative voltage and the narrow erase pulse of the positive voltage to the address electrode after the sustain pulse.

The driver supplies an erase ramp waveform in which a voltage gradually increases to at least one of the scan electrode and the sustain electrode before supplying at least one of a positive voltage and a negative voltage to the address electrode.

The pulse width of each of the narrow erase pulses is between 0.1 μs and 1 μs.

The positive voltage is a voltage between 20V and 80V, and the negative voltage is a voltage between -20V and -80V.

The plasma display device according to the present invention supplies a sustain pulse alternately to the scan electrode and the sustain electrode, and then supplies a positive voltage to the address electrode following the last sustain pulse supplied to any one of the scan electrode and the sustain electrode. At the same time, the driving unit for supplying a negative voltage to the scan electrode.

The driver supplies the narrow erase pulse of the positive voltage to the address electrode and the narrow erase pulse of the negative voltage to the scan electrode.

A driving method of a plasma display device according to the present invention includes the steps of supplying sustain pulses alternately to a scan electrode and a sustain electrode; And supplying at least one of a positive voltage and a negative voltage to an address electrode following the last sustain pulse supplied to one of the scan electrode and the sustain electrode.

A driving method of a plasma display device according to the present invention includes the steps of supplying sustain pulses alternately to a scan electrode and a sustain electrode; And supplying a negative voltage to the scan electrode at the same time as supplying a positive voltage to the address electrode subsequent to the last sustain pulse supplied to one of the scan electrode and the sustain electrode.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, with reference to Figures 6 to 10 attached to an embodiment of the present invention will be described in detail.

6 and 7, in the method of driving the plasma display device according to the present invention, the positive voltage Vx is supplied to the address electrodes X between the sustain period SUTT and the reset period RST. An erase discharge is caused between the electrodes X and the scan electrodes Y.

Since the reset period RST, the address period ADDR, and the sustain period SSUS are substantially the same as the driving waveforms of FIG. 2, detailed description thereof will be omitted.

The charges are accumulated on the bottom plate by the address discharge and the sustain discharge. The charges are accumulated on the bottom plate by the address discharge and the sustain discharge. Discharge cells that do not have an address discharge accumulate on the lower surface of the wall charge distribution immediately after the reset period, that is, on the lower plate, and discharge cells selected by the address discharge accumulate on the lower plate every sustain discharge. In order to erase the charges on the lower plate, the erase ramp waveforms (ramp-ers) are supplied to the sustain electrode Z, and then the positive voltage Vx in the form of narrow pulses on the address electrodes X as shown in FIG. Is supplied. The pulse width of the narrow pulse is approximately 0.1 μs to 1 μs, and the positive voltage Vx is a voltage between the base voltage and the data voltage Vd, for example, a voltage between 20V and 80V. As a result of the narrow pulse of the positive voltage Vx, an erase discharge occurs between the address electrodes X and the scan electrodes Y as shown in FIG. 8, and the remaining charges on the lower plate are erased.

In addition, as shown in FIG. 7, the negative electrode voltage (-Vx) and the positive voltage Vx may be continuously supplied to the address electrodes X in the form of narrow pulses. The pulse width of each of the three pulse pulses is approximately 0.1 μs to 1 μs, and the negative voltage (-Vx) is a voltage between -20 V and -80 V. By these narrow pulses, regardless of the polarity of the charge remaining on the lower plate in the cell, erase discharge occurs between the address electrodes X and the scan electrodes Y in each cell as shown in FIG. 8 on the lower plate. Accumulated charges are erased. In other words, in discharge cells in which negative charges are accumulated on the lower plate, erase discharge occurs when the negative voltage (-Vx) is supplied to the address electrodes X, while positive charges are accumulated on the lower plate. In the discharge cells, erase discharge occurs when the positive voltage Vx is supplied to the address electrodes X. FIG.

9 is a waveform diagram illustrating a method of driving a plasma display device according to another exemplary embodiment of the present invention.

Referring to FIG. 9, the driving method of the plasma display device according to the present invention supplies the positive voltage Vx to the address electrodes X between the sustain period SUT and the reset period RST, and simultaneously scan electrodes. A negative voltage (-Vy) is supplied to (Y) to cause an erase discharge between the address electrodes X and the scan electrodes Y.

Since the reset period RST, the address period ADDR, and the sustain period SSUS are substantially the same as the driving waveforms of FIG. 2, detailed description thereof will be omitted.

The charges are accumulated on the bottom plate by the address discharge and the sustain discharge. In order to erase the charges on the lower plate, the erase ramp waveforms are supplied to the sustain electrode Z, and then the address electrodes X are supplied with a positive voltage Vx in the form of narrow pulses. At the same time, the negative electrodes (-Vy) are supplied to the sustain electrodes Y in the form of narrow pulses. The pulse width of each of the pulse pulses is approximately 1 μs, the positive voltage Vx is a voltage between the base voltage and the data voltage Vd, and the negative voltage (-Vy) is between -20V and -80V.

On the other hand, the narrow erase pulses for erasing the charge on the lower plate may be replaced by rising ramp waveforms or falling ramp waveforms.

10 shows a plasma display device according to an embodiment of the present invention.

Referring to FIG. 10, a driving apparatus of a PDP according to the present invention includes a data driver 102 for supplying data to address electrodes X1 to Xm and a scan electrode Y1 to Yn of the PDP. A scan driver 103, a sustain driver 104 for driving the sustain electrodes Z serving as a common electrode, a timing controller 101 for controlling the drivers 102, 103, 104, and each driver ( A driving voltage generator 105 is provided for supplying driving voltages necessary for the 102, 113, and 114.

The data driver 102 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like, and then data mapped to each subfield is supplied by the subfield mapping circuit. The data driver 102 samples and latches data in response to the timing control signal CTRX from the timing controller 101, and then supplies the data to the address electrodes X1 to Xm during the address period ADDR. Done. 6, 7, and 9, the data driver 102 supplies the narrow erase pulse and the ramp waveform for erasing the charge on the lower plate to the address electrodes X before the reset period RST.

The scan driver 103 supplies a narrow erase pulse and a ramp waveform to erase the charge on the lower plate under the control of the timing controller 101 to the scan electrodes Y before the reset period RST, as shown in FIG. The rising ramp waveform Ramp-up and the falling ramp waveform Ramp-dn are supplied to the scan electrodes Y during the period RST. In addition, the scan driver 103 sequentially supplies the scan pulse SP to the scan electrodes Y1 to Yn during the address period ADDR. The scan driver 103 supplies the sustain pulse SUS shown in FIG. 6 to the scan electrodes Y1 to Yn under the control of the timing controller 101.

The sustain driver 104 alternately operates with the scan driver 103 under the control of the timing controller 101 to supply the sustain pulse SUS to the sustain electrodes Z. FIG.

The timing controller 101 receives a vertical / horizontal synchronization signal and a clock signal, generates timing control signals CTRX, CTRY, and CTRZ required for each driver, and transmits the timing control signals CTRX, CTRY, and CTRZ to the corresponding driver 102. , Respectively, to control the driving units 102, 103, 104. The data control signal CTRX includes a sampling clock for latching data, a latch control signal, a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element. The scan control signal CTRY includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the scan driver 103. The sustain control signal CTRZ includes a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element in the sustain driver 104.

The driving voltage generator 105 generates a sustain voltage Vs, a data voltage Vd, a scan voltage Vscan, and voltages Vx, -Vx, and -Vy for erasing charges on the lower plate, and generate the voltages. It supplies to each drive part 102,103,104.

As described above, the plasma display device and the driving method thereof according to the present invention can reduce the afterimage caused by the charge on the lower plate by applying a voltage to erase the charge accumulated on the lower plate to the address electrode. .

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (20)

A plasma display device having a scan electrode and a sustain electrode formed on an upper plate, an address electrode formed on a lower plate, and discharge cells formed at intersections of the electrodes, which are time-divided and driven into a plurality of subfields during one frame period. After supplying sustain pulses alternately to the scan electrode and the sustain electrode, residual charge in the cell is applied to at least one of the scan electrode and the sustain electrode following the last sustain pulse supplied to any one of the scan electrode and the sustain electrode. And a driver for supplying a positive voltage and a negative voltage to the address electrode after supplying an erase waveform for erasing the light. The method of claim 1, The driving unit, And a narrow erase pulse of a positive voltage is supplied to the address electrode after the sustain pulse. The method of claim 1, The driving unit, And a narrow erase pulse of a negative voltage and a narrow erase pulse of a positive voltage are successively supplied to the address electrode after the sustain pulse. The method of claim 1, The driving unit, And an erasing ramp waveform in which a voltage gradually increases to at least one of the scan electrode and the sustain electrode before supplying at least one of a positive voltage and a negative voltage to the address electrode. . The method of claim 2 or 3, And the pulse width of each of the narrow erase pulses is between 0.1 μs and 1 μs. The method according to any one of claims 1 to 4, The positive voltage is a voltage between 20V and 80V, And the negative voltage is a voltage between -20V and -80V. delete delete delete delete A method of time-divisionally driving a plasma display device having a scan electrode and a sustain electrode formed on an upper plate, an address electrode formed on a lower plate, and discharge cells formed at intersections of the electrodes into a plurality of subfields in one frame period. In Alternately supplying sustain pulses to the scan electrodes and the sustain electrodes; After the last sustain pulse supplied to any one of the scan electrode and the sustain electrode, an erase waveform for erasing residual charge in the cell is supplied to at least one of the scan electrode and the sustain electrode, and then a positive polarity is supplied to the address electrode. And supplying the voltage and the negative voltage. The method of claim 11, Supplying at least one of a positive voltage and a negative voltage to the address electrode, And a narrow erase pulse of a positive voltage is supplied to the address electrode after the sustain pulse. The method of claim 11, Supplying at least one of a positive voltage and a negative voltage to the address electrode, And a narrow erase pulse of a negative voltage and a narrow erase pulse of a positive voltage are successively supplied to the address electrode after the sustain pulse. The method of claim 11, Supplying at least one of a positive voltage and a negative voltage to the address electrode, And an erasing ramp waveform in which a voltage gradually increases to at least one of the scan electrode and the sustain electrode before supplying at least one of a positive voltage and a negative voltage to the address electrode. Driving method. The method according to claim 12 or 13, And the pulse width of each of the narrow erase pulses is between 0.1 μs and 1 μs. The method according to any one of claims 11 to 14, The positive voltage is a voltage between 20V and 80V, And said negative voltage is a voltage between -20V and -80V. delete delete delete delete

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