KR100499098B1 - Method and apparatus for driving plasma display panel - Google Patents

Abstract

The present invention relates to a method and apparatus for driving a plasma display panel which stabilizes initialization and improves contrast characteristics.

The method and apparatus for driving the plasma display panel initialize cells by supplying a first initialization waveform including a period in which a voltage rises and a period in which the voltage falls to a first electrode and a second electrode in an mth subfield, and n In the first subfield, the cells are initialized by supplying a second initialization waveform including a section in which the voltage falls to the first electrode and the second electrode without a section in which the voltage rises.

Description

TECHNICAL AND APPARATUS FOR DRIVING PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method and apparatus for driving a plasma display panel which stabilizes initialization and improves contrast characteristics.

Plasma Display Panel (hereinafter referred to as "PDP") is an ultraviolet light generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne, etc. discharges to display an image by emitting phosphors. do. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a conventional three-electrode AC surface discharge type PDP has an address orthogonal to the scan electrodes Y1 to Yn and the sustain electrode Z, and the scan electrodes Y1 to Yn and the sustain electrode Z. Electrodes X1 to Xm are provided.

Cells 1 for displaying any one of red, green and blue are formed at the intersections of the scan electrodes Y1 to Yn, the sustain electrode Z and the address electrodes X1 to Xm. The scan electrodes Y1 to Yn and the sustain electrode Z are formed on an upper substrate (not shown). On the upper substrate, a dielectric layer and an MgO protective layer (not shown) are stacked. The address electrodes X1 to Xm are formed on the lower substrate (not shown). On the lower substrate, partition walls are formed to prevent optical and electrical interference between horizontally adjacent cells. Phosphors are excited on the lower substrate and the partition walls to be excited by vacuum ultraviolet rays and emit visible light. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is injected into the discharge space between the upper substrate and the lower substrate.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into a reset period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray scale according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into a reset period, an address period, and a sustain period. The reset period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

3 shows driving waveforms of a PDP supplied to two subfields.

Referring to FIG. 3, the PDP is driven by dividing into a reset period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the reset period, the rising ramp waveform Ramp-up is simultaneously supplied to all the scan electrodes Y in the setup period SU. At the same time, 0 [V] is supplied to the sustain electrode Z and the address electrode X. Dark discharge with little light generated between the scan electrode (Y) and the address electrode (X) and between the scan electrode (Y) and the sustain electrode (Z) in the cells of the full screen by the rising ramp waveform (Ramp-up) Dark discharge occurs. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y.

In the set-down period SD, after the rising ramp waveform Ramp-up is supplied, it starts to fall at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up, and thus the base voltage GND or the negative polarity is specified. The falling ramp waveform Ramp-dn falling to the voltage level is simultaneously supplied to the scan electrodes Y. At the same time, the positive sustain voltage Vs is supplied to the sustain electrode Z, and 0 [V] is supplied to the address electrode X. When the falling ramp waveform Ramp-dn is supplied in this way, dark discharge is generated in which light is hardly generated between the scan electrode Y and the sustain electrode Z. Further, no discharge occurs between the scan electrode Y and the address electrode Z in the falling section of the falling ramp waveform Ramp-dn, and dark discharge occurs at the lower limit of the falling ramp waveform Ramp-dn. The discharge occurring in the set down period SD eliminates unnecessary wall charges unnecessary for the address discharge among the wall charges generated in the setup period SU. Looking at the wall charge change in the setup period SU and the setdown period SD, there is almost no wall charge change on the address electrode X, and the negative wall charge of the scan electrode Y decreases. On the other hand, the wall charge of the sustain electrode Z was positive in the set-up period SU, but the negative wall charge accumulated on itself as much as the decrease in the negative wall charge of the scan electrode Y was set-up period. At (SD), its polarity is reversed to negative polarity.

In the address period, the negative scan pulse scan is sequentially supplied to the scan electrodes Y, and the positive data pulse data is supplied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the reset period are added, an address discharge is generated in the cell to which the data pulse data is supplied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is supplied. During this address period, the positive pole DC voltage Zdc is supplied to the sustain electrode Z.

In the sustain period, sustain pulses sus are alternately supplied to the scan electrodes Y and the sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is supplied with the wall voltage and the sustain pulse sus added in the cell. Is generated.

After the sustain discharge is completed, an erase ramp waveform (ramp-ers) having a small pulse width and a low voltage level is supplied to the sustain electrode Z to erase wall charge remaining in the cells of the full screen.

However, in the conventional PDP, a discharge occurs between the scan electrode Y and the sustain electrode Z and a discharge occurs between the scan electrode Y and the address electrode X during the reset period. There is a problem that becomes unstable depending on the state of the wall charge or the composition of the discharge gas. In addition, the conventional PDP has a high black luminance level at a contrast ratio due to visible light emitted at the time of initializing discharge. Furthermore, the conventional PDP mainly discharges between the scan electrode (Y) and the sustain electrode (Z) by using a ramp waveform in which the voltage gradually rises, as shown in FIG. Wall charges accumulate only near the opposite sides between (Y) and the sustain electrode (Z), which not only increases the address driving voltage (scan voltage and / or data voltage), but also results in a bad address driving margin and a relatively low address discharge delay. There is a problem that the longer the address period. If the address period becomes longer, the sustain period decreases relatively, resulting in a decrease in luminance and inability to cope with an increase in resolution and subfields cannot be added to reduce deterioration factors such as pseudo contour noise that may appear in a video.

Accordingly, an object of the present invention is to provide a method and apparatus for driving a PDP, which stabilizes initialization and improves contrast characteristics.

In order to achieve the above object, the driving method of the PDP according to the embodiment of the present invention is a period in which the voltage rises to the first electrode and the second electrode in the m-th (where m is any positive integer) and the A first step of initializing cells by supplying a first initialization waveform including a period in which a voltage falls; In the n-th sub-field, n is a positive integer different from m, the second initialization waveform is provided to the first electrode and the second electrode including a period in which the voltage falls without a section in which the voltage increases. And a second step of initializing the cells.

Each of the first and second steps includes an address period for supplying a data voltage to a third electrode and supplying a scan voltage to at least one of the first and second electrodes to select the cells; And a sustain period for displaying by alternately supplying sustain voltages to the first electrodes and the second electrodes.

The first initialization waveform includes a rising ramp waveform supplied to the first and second electrodes at the same time; And a falling ramp waveform which is simultaneously supplied to the first and second electrodes after the rising ramp waveform.

A falling ramp waveform of the first initialization waveform supplied to the first electrode is lowered to a negative voltage; The falling ramp waveform of the first initialization waveform supplied to the second electrode is characterized in that the voltage is lowered to a voltage higher than the negative voltage.

The falling ramp waveform supplied to the second electrode is characterized in that the voltage is lowered to the ground voltage GND or 0 [V].

The second initialization waveform may include: a holding period for supplying a predetermined positive DC voltage to the first and second electrodes; And a falling ramp waveform that is simultaneously supplied to the first and second electrodes after the holding section.

The DC voltage supplied to the first electrode and the DC voltage supplied to the second electrode may be generated at a predetermined time difference.

The DC voltage is characterized in that the sustain voltage.

A falling ramp waveform of the second initialization waveform supplied to the first electrode has a voltage lowered to a negative voltage; The falling ramp waveform of the second initialization waveform supplied to the second electrode is characterized in that the voltage is lowered to a voltage higher than the negative voltage.

The PDP is time-division driven into at least one selective write subfield and at least one selective erase subfield during one frame period.

The m th subfield and the n th subfield are applied to the selective write subfield.

An apparatus for driving a PDP according to an embodiment of the present invention initializes the cells by supplying a first initialization waveform including a period in which a voltage increases and a period in which the voltage falls to a first electrode and a second electrode in an mth subfield. A first initialization circuit; and a second initialization circuit configured to initialize the cells by supplying a second initialization waveform including a period in which the voltage falls to the first electrode and the second electrode in the nth subfield without a section in which the voltage rises.

An apparatus for driving a PDP according to an embodiment of the present invention includes an address circuit for selecting the cells by supplying a data voltage to a third electrode and a scan voltage to at least one of the first and second electrodes; And a sustain circuit for displaying by alternately supplying a sustain voltage to the first electrodes and the second electrodes.

The first initialization circuit supplies a ramp ramp waveform to the first and second electrodes at the same time after the ramp ramp waveform is supplied to the first and second electrodes at the same time.

The second initialization circuit may supply a ramp ramp waveform to the first and second electrodes simultaneously after supplying a predetermined positive DC voltage to the first and second electrodes.

The second initialization circuit may generate the DC voltage supplied to the first electrode and the DC voltage supplied to the second electrode with a predetermined time difference.

The second initialization circuit may generate the DC voltage as the sustain voltage.

The second initialization circuit lowers the voltage of the falling ramp waveform supplied to the first electrode to a negative voltage; The voltage of the falling ramp waveform supplied to the second electrode is lowered to a voltage higher than the negative voltage.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 10.

Referring to FIG. 5, in the driving method of the PDP according to the first embodiment of the present invention, the rising ramp waveforms Ruy1 and Ruz1 and the falling ramp waveform Rdy1 in the m-th (where m is any positive integer) subfields. , Rdz is supplied to the scan electrodes (Y) and the sustain electrodes (Z) to initialize the PDP, and the DC voltage (Vry, Vrz) and the drop in the nth (where n is a positive integer different from m) The ramp waveforms Rdy2 and Rdz2 are supplied to the scan electrodes Y and the sustain electrodes Z to initialize the PDP.

During the reset period of the m-th subfield, first, the rising ramp waveforms Ruy1 and Ruz1 that rise at a predetermined slope from the sustain voltage Vs to the setup voltage Vsetup are first applied to the scan electrodes Y and the sustain electrodes Z. FIG. Supplied at the same time. At this time, the address electrode X maintains 0 [V] or the ground voltage GND. When the rising ramp waveforms Ruy2 and Ruz are simultaneously supplied to the scan electrodes Y and the sustain electrodes Z, the scan electrodes Y and the address electrodes X are formed in the first initialized cells. Write dark discharge occurs simultaneously between the sustain electrodes Z and the address electrodes X. FIG. As a result, as shown in FIG. 6, negative wall charges are accumulated on each of the bar scan electrodes Y and the sustain electrodes Z, and positive wall charges are accumulated on the address electrodes X. Referring to FIG.

Following the rising ramp waveforms Ruy1 and Ruz1, the falling ramp waveform Rdy1, which falls from the sustain voltage Vs to the negative voltage V1, is supplied to the scan electrodes Y while the sustain electrodes Z are supplied. A falling ramp waveform Rdz1 that falls from approximately sustain voltage Vs to 0 [V] or ground voltage GND is supplied. Here, the negative voltage V1 may be set to the scan voltage Vscan. At this time, the address electrode X maintains 0 [V] or the ground voltage GND. The falling ramp waveforms Rdy1 and Rdz1 generate an erase dark discharge between the scan electrode Y and the address electrode X and between the sustain electrode Z and the address electrode X. As a result of this set-down discharge, unnecessary wall charges unnecessary for address discharge are erased. And uniform wall charges remain in all the cells.

In general, the red, green, and blue subpixels have a variation in the firing voltage according to the characteristics of the phosphor material. When the falling ramp waveform Rdy1 supplied to the scan electrodes Y falls to the negative voltage, the discharge start condition can be made uniform regardless of the variation of the discharge start voltage appearing in the red, green, and blue subpixels. Therefore, the erase dark discharge generated by the falling ramp waveforms Rdy1 and Rdz1 makes the discharge conditions within all cells uniform, thereby increasing the driving margin.

By this initialization, since there is almost no potential difference between the scan electrodes (Y) and the sustain electrodes (Z) and the wall charges formed on the electrodes (Y, Z) are almost the same, the PDP is maintained at a high temperature of 50 ° C. or higher. Even if it is used, no false discharge caused by the wall charge fluctuation before the address discharge is started will occur.

Comparing the PDP of the present invention and the conventional PDP in the wall charge distribution after the reset period, the conventional PDP has a rising ramp waveform applied only to the scan electrodes Y as shown in FIG. 3 so that the scan electrodes Y and the sustain electrodes As a result of the surface discharge occurring between the holes Z, wall charges are accumulated only at the side portions of the scan electrodes Y and the sustain electrodes Z where the electric field is concentrated, as shown in FIG. 4. In contrast, in the PDP of the present invention, the rising ramp waveforms Ruy1 and Ruz1 are simultaneously applied to the scan electrodes Y and the sustain electrodes Z so that a potential difference between the scan electrodes Y and the sustain electrodes Z is applied. Since almost no, opposite discharge occurs between the scan electrodes (Y) and the address electrodes (X) and between the sustain electrodes (Z) and the address electrodes (X), so that the scan electrodes (Y) and the sustain electrodes are almost the same. Wall charges accumulate in the entire area on (Z). For this reason, the PDP of the present invention sufficiently accumulates negative wall charges on the scan electrodes Y, and sufficiently accumulates positive wall charges on the address electrodes X, thereby providing the scan voltage Vscan and data necessary for address discharge. The voltage Vd can be lowered and the delay of address discharge can be reduced.

During the address period of the m-th subfield, positive bias voltages Vscan-com and Vz-com are supplied to the scan electrodes Y and the sustain electrodes Z. FIG. This bias voltage may be set identically or differently. For example, when the bias voltage Vz-com supplied to the sustain electrodes Z is set to be higher than the bias voltage Vscan-com supplied to the scan electrodes Z, the sustain voltage Z is further applied to the sustain electrodes Z during the address period. Large amounts of negative wall charges can accumulate. When a large amount of negative wall charges are accumulated on the sustain electrodes Z, the first sustain pulse su is supplied between the sustain electrodes Z and the scan electrodes Y when the first sustain pulse su is supplied to the sustain electrodes Z. Since the voltage difference becomes larger, discharge is easy and stable, and thus the sustain driving margin is increased. Scan pulses falling from the bias voltage Vscan-com to the scan voltage Vscan are sequentially supplied to the scan electrodes Y, and the data pulses of the data voltage Vd are synchronized with the scan pulses. Is supplied to the address battles X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the reset period are added, an address discharge is generated in the cell to which the data pulse data is supplied. In the cells selected by the address discharge, wall charges are accumulated so that a discharge can occur when the sustain voltage Vs is supplied.

In the sustain period of the m-th subfield, the sustain pulse su is alternately supplied to the scan electrodes Y and the sustain electrodes Z. FIG. In the cells selected by the address discharge, a sustain voltage is generated between the scan electrode Y and the sustain electrode Z every time the sustain pulse sus is supplied while the wall voltage and the sustain pulse sus are added to the cells. Here, the first generated sustain pulse (sus) is set to a wide pulse width so that the initial sustain discharge is stable. After the last sustain pulse (sus) is supplied to the sustain electrodes (Z) and the sustain discharge is finished, the erase ramp waveform (not shown) is supplied to at least one of the scan electrodes (Y) and the sustain electrodes (Z). . Here, the erase ramp waveform serves to erase the wall charges generated by the sustain discharge. The erase ramp waveform may be supplied to either the scan electrode Z or the sustain electrode Z, or may be omitted.

For example, the present invention is a patent application No. 10-2000-0012669, Patent Application No. 10-2000-0053214, Patent Application No. 10-2001-0003003, Patent Application No. 10-2001-0006492 filed by the applicant of the present application Korean Patent Application No. 10-2002-0082512, Patent Application No. 10-2002-0082513, Patent Application No. 10-2002-0082576, and the like, are applied to the so-called 'SWSE (Selective Witing and Selective Erasure) method'. Can be. In this case, each of the m th subfield and the n th subfield may be applied to an optional write subfield that selects an on cell during an address period in the SWSE scheme. In this way, the erase ramp waveform is omitted in the last subfield of the selective writing subfield in the mth subfield or the nth subfield in the SWSE method.

In the nth subfield, after the positive DC voltage Vry is supplied to the scan electrodes Y during the t1 period of the reset period, the positive DC voltage Vrz is supplied to the sustain electrodes Z. The DC voltages Vry and Vrz may be selected as the sustain voltage Vs. At this time, the address electrode X maintains 0 [V] or the ground voltage GND. During the t1 period, write dark discharge occurs between the scan electrodes Y and the sustain electrodes Z as shown in FIG. 7, and write dark discharge occurs between the scan electrodes Y and the address electrodes X at the same time. . As a result of this setup discharge, negative wall charges are accumulated on the scan electrodes Y and positive wall charges are accumulated on the sustain electrodes Z and the address electrodes X as shown in FIG. 7. Subsequently, after the positive voltages Vry and Vrz are maintained for a predetermined time for the period t2, the falling ramp waveform Rdy2 falling from the approximately sustain voltage Vs to the negative voltage V1 is applied to the scan electrodes Y. At the same time, the sustain electrode Z is supplied with a falling ramp waveform Rdz2 that falls from approximately sustain voltage Vs to 0 [V] or ground voltage GND. At this time, the address electrode X maintains 0 [V] or the ground voltage GND. The falling ramp waveforms Rdy2 and Rdz2 generate an erase dark discharge between the scan electrode Y and the address electrode X and between the sustain electrode Z and the address electrode X. As a result of this set-down discharge, unnecessary wall charges unnecessary for address discharge are erased. And uniform wall charges remain in all the cells.

Looking at the wall charge distribution immediately after the reset period in the nth subfield, negative wall charges remain on the scan electrodes Y and positive wall charges remain on the address electrodes X. FIG. As a result of the erase dark discharge in the form of the opposite discharge between the sustain electrodes Z and the address electrodes X, the wall charges on the sustain electrodes Z are reversed to the negative wall charges.

Thus, the write dark discharge of the reset period in the nth subfield occurs with a low positive DC voltage (Vry, Vrz). As a result, the discharge does not occur significantly during the write dark discharge during the reset period, and the amount of visible light emission is reduced, thereby improving the contrast characteristic.

Since the operation of the address period and the reset period of the nth subfield is substantially the same as the mth subfield, a detailed description thereof will be omitted.

The m th subfield may be selected as at least one subfield disposed initially among the subfields arranged within one frame period, and the n th subfield may select the m th subfield among the subfields arranged within one frame period. At least one subfield may be selected. In addition, the m th subfield and the n th subfield may be alternately or periodically arranged.

8 shows a method of driving a PDP according to a second embodiment of the present invention.

Referring to FIG. 8, in the driving method of the PDP according to the second embodiment of the present invention, the scan electrodes Y are supplied after the DC voltage Vrz is supplied to the sustain electrodes Z during the reset period of the n-th subfield. Supply DC voltage (Vry) to.

A waveform substantially the same as the driving waveform shown in FIG. 5 is supplied to the electrodes X, Y, and Z in the m th subfield.

During the t1 period of the reset period in the nth subfield, the positive DC voltage Vrz is first supplied to the sustain electrodes Z, and then the positive DC voltage Vry is supplied to the scan electrodes Y. At this time, the address electrode X maintains 0 [V] or the ground voltage GND. During the t1 period, a write dark discharge occurs between the scan electrodes Y and the sustain electrodes Z as shown in FIG. 9, and a write dark discharge occurs between the scan electrodes Y and the address electrodes X at the same time. . As a result of this setup discharge, negative wall charges are accumulated on the sustain electrodes Y and negative wall charges are accumulated on the scan electrodes Y and the address electrodes X as shown in FIG. 9. . Subsequently, after the positive voltages Vry and Vrz are maintained for a predetermined time for the period t2, the falling ramp waveform Rdy2 falling from the approximately sustain voltage Vs to the negative voltage V1 is applied to the scan electrodes Y. At the same time, the sustain electrode Z is supplied with a falling ramp waveform Rdz2 that falls from approximately sustain voltage Vs to 0 [V] or ground voltage GND. At this time, the address electrode X maintains 0 [V] or the ground voltage GND. The falling ramp waveforms Rdy2 and Rdz2 generate an erase dark discharge between the scan electrode Y and the address electrode X and between the sustain electrode Z and the address electrode X. As a result of this set-down discharge, unnecessary wall charges unnecessary for address discharge are erased. And uniform wall charges remain in all the cells.

Looking at the wall charge distribution immediately after the reset period in the nth subfield, negative wall charges remain on the sustain electrodes Z and positive wall charges remain on the address electrodes X. FIG. As a result of the erase dark discharge in the form of the opposite discharge between the scan electrodes Y and the address electrodes X, wall charges on the scan electrodes Y are reversed to negative wall charges as shown in FIG. 9.

Thus, the write dark discharge of the reset period in the nth subfield occurs with a low positive DC voltage (Vry, Vrz). As a result, the discharge does not occur significantly during the write dark discharge during the reset period, and the amount of visible light emission is reduced, thereby improving the contrast characteristic.

Since the operation of the address period and the reset period of the nth subfield is substantially the same as the mth subfield, a detailed description thereof will be omitted.

10 shows an apparatus for driving a PDP according to an embodiment of the present invention.

Referring to FIG. 10, a driving apparatus of a PDP according to an embodiment of the present invention uses a data driver 102 for supplying data to address electrodes X1 to Xm of the PDP, and scan electrodes Y1 to Yn. A scan driver 103 for driving, a sustain driver 104 for driving the sustain electrode Z serving as a common electrode, a timing controller 101 for controlling the respective driving units 102, 103, 104, and each A driving voltage generator 105 is provided to supply driving voltages necessary for the driving units 102, 103, and 104.

The data driver 102 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like, and then data mapped to each subfield is supplied by the subfield mapping circuit. The data driver 102 samples and latches data in response to the timing control signal CTRX from the timing controller 101, and then supplies the data to the address electrodes X1 to Xm.

The scan driver 103 supplies the initialization waveforms Ruy1, Rdy1, Ruy2, and Rdy2 shown in FIGS. 5 and 8 to the scan electrodes Y1 to Yn during the reset period under the control of the timing controller 101. The scan driver 103 sequentially supplies the scan pulses to the scan electrodes Y1 to Yn during the address period, and the sustain pulses to the scan electrodes Y1 to Yn during the sustain period.

The sustain driver 104 supplies the initialization waveforms Ruz1, Rdz1, Ruz2, and Rdz2 shown in FIGS. 5 and 8 to the sustain electrodes Z during the reset period under the control of the timing controller 101. In addition, the sustain driver 104 supplies the bias voltage Vz-com to the sustain electrodes Z during the address period, and alternately operates the scan driver 103 during the sustain period to generate the sustain pulses Z. Will be supplied to

The timing controller 101 receives a vertical / horizontal synchronization signal and generates timing control signals CTRX, CTRY, and CTRZ required for each driver, and transmits the timing control signals CTRX, CTRY, and CTRZ to the corresponding driving units 102, 103, and the like. Each drive unit 102, 103, 104 is controlled by supplying the same to the 104. The data control signal CTRX includes a sampling clock for latching data, a latch control signal, a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element. The scan control signal CTRY includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the scan driver 103. The sustain control signal CTRZ includes a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element in the sustain driver 104.

The driving voltage generator 105 includes a setup voltage Vsetup, an address bias voltage Vscan-com and Vz-com, a scan voltage Vscan, a sustain voltage Vs, a setdown voltage V1, and a data voltage Vd. Etc. These driving voltages may vary depending on the composition of the discharge gas or the structure of the discharge cell.

As described above, the method and apparatus for driving a PDP according to the present invention reduce the gap voltage between the scan electrode and the sustain electrode by simultaneously applying a voltage having substantially the same waveform to the scan electrode and the sustain electrode. Initialization discharge is generated between the address electrodes and between the sustain electrode and the address electrode, and the rising ramp waveform for the setup discharge is omitted according to the subfield, and the initializing discharge is performed only with the falling ramp waveform. Accordingly, the method and apparatus for driving a PDP according to the present invention can improve contrast characteristics by stabilizing initialization and reducing visible light generated during initialization discharge. Furthermore, the method and apparatus for driving a PDP according to the present invention not only lowers the driving voltage required for the address discharge by accumulating the wall charges on the scan electrodes in the initialization discharge but also reduces the address period by minimizing the delay of the address discharge. As a result, high-speed driving of the PDP is possible, so that high resolution can be effectively coped with and display quality can be improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram illustrating a frame configuration of an 8-bit default code for implementing 256 gray levels.

3 is a waveform diagram showing driving waveforms for driving a conventional plasma display panel.

4 is a view schematically showing wall charges formed at the time of initialization through surface discharge of a scan electrode and a sustain electrode in a conventional plasma display panel.

5 is a waveform diagram illustrating a method of driving a plasma display panel according to a first embodiment of the present invention.

FIG. 6 is a view schematically showing a change in the wall charge distribution during the initial discharge of the m-th subfield shown in FIG. 4.

FIG. 7 is a view schematically showing a change in the wall charge distribution during the initial discharge of the n-th subfield shown in FIG. 4.

8 is a waveform diagram illustrating a method of driving a plasma display panel according to a second embodiment of the present invention.

FIG. 9 is a view schematically showing a change in the wall charge distribution during the initial discharge of the n-th subfield shown in FIG. 8.

10 is a block diagram illustrating an apparatus for driving a plasma display panel according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

101: timing controller 102: data driver

103: scan driver 104: sustain driver

105: driving voltage generator

Claims (19)

A plasma display panel including an upper plate on which a plurality of electrode pairs including first and second electrodes are formed, and a lower plate on which a plurality of third electrodes intersect the plurality of electrode pairs are formed, and cells are formed at the intersections of the electrodes. In the method for In the m th (where m is any positive integer), the cells are supplied by supplying a first initialization waveform including a period in which a voltage increases and a period in which the voltage falls to the first electrode and the second electrode. Initializing; In the n-th sub-field, n is a positive integer different from m, the second initialization waveform is provided to the first electrode and the second electrode including a period in which the voltage falls without a section in which the voltage increases. And a second step of initializing the cells. The method of claim 1, Each of the first step and the second step, An address period for supplying a data voltage to the third electrode and supplying a scan voltage to at least one of the first and second electrodes to select the cells; And a sustain period in which a display is performed by alternately supplying a sustain voltage to the first electrodes and the second electrodes. The method of claim 1, The first initialization waveform, Rising ramp waveforms simultaneously supplied to the first and second electrodes; And a falling ramp waveform supplied to the first and second electrodes simultaneously after the rising ramp waveform. The method of claim 3, wherein The falling ramp waveform supplied to the first electrode is lowered to a negative voltage; And the falling ramp waveform supplied to the second electrode is lowered to a voltage higher than the negative voltage. The method of claim 3, wherein The falling ramp waveform supplied to the second electrode has a voltage lowered to a ground voltage (GND) or 0 [V]. The method of claim 2, The second initialization waveform, A holding section for supplying a predetermined positive DC voltage to the first and second electrodes; And a falling ramp waveform supplied to the first and second electrodes at the same time after the holding section. The method of claim 6, And the DC voltage supplied to the first electrode and the DC voltage supplied to the second electrode are generated at a predetermined time difference. The method of claim 6, And the DC voltage is the sustain voltage. The method of claim 6, The falling ramp waveform supplied to the first electrode is lowered to a negative voltage; And the falling ramp waveform supplied to the second electrode is lowered to a voltage higher than the negative voltage. The method of claim 1, The plasma display panel is time-division driven into at least one selective write subfield and at least one selective erase subfield for one frame period, And the m th subfield and the n th subfield are applied to the selective write subfield. A plasma display panel including an upper plate on which a plurality of electrode pairs including first and second electrodes are formed, and a lower plate on which a plurality of third electrodes intersect the plurality of electrode pairs are formed, and cells are formed at the intersections of the electrodes. In the device for In the m th (where m is any positive integer), the cells are supplied by supplying a first initialization waveform including a period in which a voltage increases and a period in which the voltage falls to the first electrode and the second electrode. A first initialization circuit for initializing; In the n-th sub-field, n is a positive integer different from m, the second initialization waveform is provided to the first electrode and the second electrode including a period in which the voltage falls without a section in which the voltage increases. And a second initialization circuit for initializing the cells. The method of claim 11, An address circuit for supplying a data voltage to the third electrode and supplying a scan voltage to at least one of the first and second electrodes to select the cells; And a sustain circuit for supplying a sustain voltage alternately to the first electrodes and the second electrodes to perform display. The method of claim 11, The first initialization circuit, And supplying the ramp ramp waveform to the first and second electrodes at the same time and then supplying the ramp ramp waveform to the first and second electrodes at the same time. The method of claim 13, The falling ramp waveform supplied to the first electrode is lowered to a negative voltage; The falling ramp waveform supplied to the second electrode has a voltage lowered to a voltage higher than the negative voltage. The method of claim 13, The falling ramp waveform supplied to the second electrode has a voltage lowered to a ground voltage (GND) or 0 [V]. The method of claim 12, The second initialization circuit, And supplying a ramp ramp waveform to the first and second electrodes simultaneously after supplying a predetermined positive DC voltage to the first and second electrodes. The method of claim 16, The second initialization circuit, And driving the DC voltage supplied to the first electrode and the DC voltage supplied to the second electrode at a predetermined time difference. The method of claim 16, The second initialization circuit, And the DC voltage is generated as the sustain voltage. The method of claim 16, The second initialization circuit, Lowering the voltage of the falling ramp waveform supplied to the first electrode to a negative voltage; And a voltage of the falling ramp waveform supplied to the second electrode is lowered to a voltage higher than the negative voltage.