KR100726652B1 - Method and apparatus for driving plasma display panel - Google Patents

Abstract

The present invention relates to a method and apparatus for driving a plasma display panel which can minimize the deterioration of contrast characteristics.

In an apparatus for driving a plasma display panel by time-dividing one frame period into a plurality of subfields, the plasma display driving apparatus according to the present invention supplies only a falling ramp waveform during a reset period of some subfields among the plurality of subfields. It characterized in that it comprises a scan voltage driver to be.

The method and apparatus for driving a plasma display according to the present invention can minimize the deterioration in contrast characteristics by eliminating the setup period during the reset period of some subfields, and initialize all the cells by supplying the negative ramp wave sustain pulse at the end of the sustain period. It becomes possible.

Description

TECHNICAL AND APPARATUS FOR DRIVING PLASMA DISPLAY PANEL}

1 is a plan view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram illustrating a subfield pattern of an 8-bit default code for implementing 256 gray levels.

3 is a waveform diagram showing a drive waveform of a conventional PDP.

4 is a block diagram schematically illustrating an apparatus for driving a plasma display panel according to an exemplary embodiment of the present invention.

5 is a waveform diagram illustrating a driving waveform of a PDP according to an exemplary embodiment of the present invention.

6 illustrates a subfield pattern of the plasma display panel according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

31: timing controller 32: data driver

33: scan driver 34: sustain driver

35: drive voltage generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method and apparatus for driving a plasma display panel capable of minimizing a decrease in contrast characteristics.

Plasma Display Panel (hereinafter referred to as "PDP") is used to excite and emit phosphors by using ultraviolet rays generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is discharged. Will be displayed. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a conventional three-electrode AC surface discharge type PDP has an address orthogonal to the scan electrodes Y1 to Yn and the sustain electrode Z, and the scan electrodes Y1 to Yn and the sustain electrode Z. Electrodes X1 to Xm.

Cells 1 for displaying any one of red, green and blue are formed at the intersections of the scan electrodes Y1 to Yn, the sustain electrode Z and the address electrodes X1 to Xm. The scan electrodes Y1 to Yn and the sustain electrode Z are formed on an upper substrate (not shown). On the upper substrate, a dielectric layer and an MgO protective layer (not shown) are stacked. The address electrodes X1 to Xm are formed on the lower substrate (not shown). On the lower substrate, partition walls are formed to prevent optical and electrical interference between horizontally adjacent cells. Phosphors are excited on the lower substrate and the partition walls to be excited by vacuum ultraviolet rays and emit visible light. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is injected into the discharge space between the upper substrate and the lower substrate.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into a reset period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray scale according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

3 shows driving waveforms of a PDP supplied to two subfields.

Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initial stage of the reset period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y, and 0 [V] is applied to the sustain electrode Z and the address electrode X. A write arm in which light is hardly generated between the scan electrode Y and the address electrode X and between the scan electrode Y and the sustain electrode Z in the cells of the full screen by the rising ramp waveform Ramp-up. Dark discharge or setup discharge occurs. Due to the setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y.

At the end of the reset period, the falling ramp waveform Ramp-dn, which starts to fall from approximately the sustain voltage Vs, is simultaneously applied to the scan electrodes Y. At the same time, a positive sustain voltage Vs is applied to the sustain electrode Z, and 0 [V] is applied to the address electrode X. When the falling ramp waveform Ramp-dn is applied in this manner, an erase dark discharge or a set-down discharge with little light is generated between the scan electrode Y and the sustain electrode Z. This set-down discharge eliminates unnecessary wall charges unnecessary for address discharge.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is applied.

The sustain electrode Z is supplied with a positive DC voltage Zdc during the set down period and the address period so as to reduce the voltage difference with the scan electrode Y so as to prevent mis-discharge with the scan electrode Y.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. This will happen.

In the conventional PDP having such a structure, discharge occurs as the setup and set-down waveforms are supplied during the reset period, and light is generated during the reset period. There is a problem that the contrast is greatly degraded by the discharge generated during this reset period.

Accordingly, an object of the present invention is to provide a method and apparatus for driving a PDP that can minimize the deterioration of contrast characteristics.

In order to achieve the above object, a plasma display driving apparatus according to the present invention is a device for driving a plasma display panel by time-dividing one frame period into a plurality of subfields, the reset of some of the subfields among the plurality of subfields. It includes a scan voltage driver to supply only the falling ramp waveform during the period.

The falling ramp waveform is characterized in that the ramp waveform falling from the base voltage to the scan voltage.

The apparatus for driving a plasma display panel according to the present invention includes a plasma display panel which is divided and driven into a plurality of subfields divided into a reset period for initializing a cell, an address period for addressing a cell, and a sustain period for sustaining a discharge. An apparatus for driving, comprising: a data driver for supplying data to address electrodes; A scan driver for driving scan electrodes; And a sustain driver for driving the sustain electrode as a common electrode, wherein the scan driver includes a first rising ramp waveform having a predetermined slope during the reset period, a second rising ramp waveform having a smaller magnitude than the first rising ramp waveform, and a first rising ramp waveform. And a first falling ramp waveform falling from the second rising ramp waveform to the negative scan voltage supplied to the scan electrode and a second falling ramp waveform falling from the base voltage to the scan voltage.

A timing controller for controlling the respective driving units; And a driving voltage generator configured to supply driving voltages to the driving units, wherein the driving voltage generator generates the first and second rising ramp waveforms and the first and second falling ramp waveforms. .

A plasma display panel driving method according to the present invention includes a plasma display panel which is divided and driven into a plurality of subfields divided into a reset period for initializing a cell, an address period for addressing a cell, and a sustain period for sustaining a discharge. The driving method includes supplying only a falling ramp waveform falling from a base voltage to a negative scan voltage supplied to a scan electrode during at least one reset period of the subfields.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 6.

Referring to FIG. 4, a driving apparatus of a PDP according to an embodiment of the present invention may include a data driver 32 for supplying data to address electrodes X1 to Xm of the PDP, and scan electrodes Y1 to Yn. A scan driver 33 for driving, a sustain driver 34 for driving the sustain electrode Z serving as a common electrode, a timing controller 31 for controlling each driver 32, 33, 34, and each And a driving voltage generator 35 for supplying driving voltages to the driving units 32, 33, and 34.

The data driver 32 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like, and then data mapped to a subfield pattern preset by the subfield mapping circuit is supplied. The data driver 32 samples and latches data under the control of the timing controller 31, and then supplies the data to the address electrodes X1 to Xm.

The scan driver 33 supplies the set-up and first falling ramp waveforms Ramp-dn1 in the subfield in which both the setup and the set-down periods exist during the reset period under the control of the timing controller 31, while the reset period In the subfield in which no setup period exists, the second falling ramp waveform Ramp-dn2 is continuously supplied to the scan electrodes Y1 to Yn to initialize the full screen, and then the address is selected to select the scan line. During the period, scan pulses of negative polarity are sequentially supplied to the scan electrodes Y1 to Yn. Here, the first falling ramp waveform Ramp-dn1 and the second falling ramp waveform Ramp-dn2 may be the same waveforms or waveforms having different slopes.

The sustain driver 34 supplies the positive DC voltage during the reset period under the control of the timing controller 41. In addition, the sustain driver 34 supplies a positive DC bias voltage to the sustain electrode Z during the address period, and then alternately operates the scan driver 33 during the sustain period to supply the sustain pulses to the sustain electrode Z. do.

The timing controller 31 receives the vertical / horizontal synchronization signal and generates timing control signals CTRX, CTRY, and CTRZ required for each of the driving units 32, 33, and 34, and outputs the timing control signals CTRX, CTRY, and CTRZ. Each of the driving units 32, 33, 34 is controlled by supplying the driving units 32, 33, 34. The timing control signal CTRX supplied to the data driver 32 includes a sampling clock for latching data, a latch control signal, a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element. The timing control signal CTRY applied from the timing controller 31 to the scan driver 33 includes a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element in the scan driver 33. The timing control signal CTRZ applied from the timing controller 31 to the sustain driver 34 includes a switch control signal for controlling the energy recovery circuit and the on / off time of the driving switch element in the sustain driver 34. .

The driving voltage generator 35 may include the first and second setup voltages Vsetup1 and Vsetup2 supplied with the upper limit voltage of the rising ramp waveform and the scan bias voltage Vscan-com supplied to the scan electrode Y during the address period. , The first set-down voltage Vsetdown1 having the first falling ramp waveform Ramp-dn1 that starts to fall from approximately the sustain voltage Vs and then drops the scan voltage Vscan, and the scan voltage Vscan at 0 [V]. The second set-down voltage Vsetdown2 having the second falling ramp waveform Ramp-dn2 descending to, the scan voltage Vscan set to the voltage of the scan pulse, the sustain voltage Vs of the sustain pulse, and the data voltage Vd. ) And so on. Here, the first setdown voltage Vsetdown1 and the second setdown voltage Vsetdown2 may be selected from 0 to 100 [V]. The first setup voltage Vsetup1 is a typical setup voltage of about 250 to 270 [V]. The second setup voltage Vsetup2 has a voltage corresponding to 10-30% of the first setup voltage. The scan bias voltage Vscan-com is set to a positive voltage lower than the sustain voltage Vs. The scan voltage Vscan can be selected within -70 to -100 [V]. The sustain voltage Vs can be selected within 180 to 200 [V]. The data voltage Vd can be selected between approximately 50 and 80 [V].

Meanwhile, the voltage condition is not limited to the above, but may vary depending on a discharge characteristic or a model of the PDP.

5 and 6 illustrate driving waveforms of a PDP according to an embodiment of the present invention.

5 and 6, the PDP according to the embodiment of the present invention is driven by maintaining an address period for selecting a cell and a discharge period for initializing all cells at the second half while maintaining the discharge of the selected cell.

As for the reset period, the i th (where i is any positive integer) subfield SFi, the j th subfield SFj, and the k th subfield d SFk (where k, j and i are different from each other). Will be explained by dividing by a positive integer). The i th subfield SFi, the j th subfield SFj, and the k th subfield SFk are arranged in one frame period.

In the i-th subfield SFi, the rising ramp waveform Ramp-up1 rising to the first setup voltage Vsetup1 is applied to all the scan electrodes Y at the beginning of the reset period. At the same time, 0 [V] is applied to the sustain electrode Z and the address electrode X. The rising ramp waveform Ramp-up1 stabilizes the setup discharge by increasing the voltage difference between the scan electrode Y and the sustain electrode Z, and the voltage difference between the scan electrode Y and the address electrode X. As a result, a sufficient amount of negative wall charges are accumulated between the scan electrodes (Y) to increase the address driving margin, thereby reducing the bright spot discharge.

In the j-th subfield SFj, the rising ramp waveform Ramp-up2 is applied to all the scan electrodes Y up to the second setup voltage Vsetup2 lower than the first setup voltage Vsetup1 at the beginning of the reset period. do. At the same time, 0 [V] is applied to the sustain electrode Z and the address electrode X. This rising ramp waveform (Ramp-up2) weakens the setup discharge, thereby minimizing light emission and improving the contrast characteristic.

In the kth subfield SFk, there is no initial setup period of the reset period.

In the i-th subfield SFi and the j-th subfield SFj, the first falling ramp waveform Ramp-dn1 begins to fall from the sustain voltage Vs to the scan voltage Vscan at the end of the reset period. It is applied to these scan electrodes (Y). At the same time, the sustain voltage Vs is applied to the sustain electrode Z, and 0 [V] is applied to the address electrode X. In this way, when the first falling ramp waveform Ramp-dn1 is applied, an erase dark discharge or a set-down discharge with little light is generated between the scan electrode Y and the sustain electrode Z. This set down discharge eliminates unnecessary excessive wall charges in the address discharge.

In the k-th subfield SFk, an erase arm that generates little light as the second falling ramp waveform Ranp-dn2 falling from 0 [V] to the scan voltage Vscan is supplied in the set-down period during the reset period. Discharge or set-down discharge occurs.

The address period and the sustain period are driven the same in the i-th subfield SFi, the j-th subfield SFj and the k-th subfield SFk, and are substantially the same as those of FIG. 3 described above. It will be omitted.

On the other hand, it is preferable that the i-th subfield SFi in which the setup voltage is set high is selected as at least one or more subfields arranged at the beginning of the frame period.

In the PDP driving method according to the embodiment of the present invention having the structure as described above, at least one k-th subfield SFk is present in one frame, thereby eliminating the setup period during the reset period, thereby suppressing the discharge generated during the reset period as a whole. By minimizing light emission, the contrast can be maximized. Here, the i-th subfield SFi and the j-th subfield SFj may be disposed in one or more frames in order to maintain wall charges.

As described above, the method and apparatus for driving a PDP according to the present invention can minimize the deterioration of the contrast characteristic by eliminating the setup period during the reset period of some subfields, and supply the negative ramp wave sustain pulse at the end of the sustain period. All cells can be initialized. In addition, the PDP driving method and apparatus according to the present invention can save time by being eliminated in the setup period compared to the conventional.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (5)

An apparatus for driving a plasma display panel by time-dividing one frame period into a plurality of subfields, And a scan voltage driver for supplying only a falling ramp waveform during a reset period of some of the subfields among the plurality of subfields. The method of claim 1, The down ramp waveform is A drive device for a plasma display panel, characterized in that the ramp waveform falls from the base voltage to the scan voltage. An apparatus for driving a plasma display panel which is divided and driven into a plurality of subfields divided into a reset period for initializing a cell, an address period for addressing a cell, and a sustain period for sustaining discharge. A data driver for supplying data to the address electrodes; A scan driver for driving scan electrodes; And A sustain driver for driving a sustain electrode which is a common electrode, The scan driver includes a first rising ramp waveform having a predetermined slope during the reset period, a second rising ramp waveform having a smaller magnitude than the first rising ramp waveform, and a portion supplied to the scan electrode from the first and second rising ramp waveforms. And a first falling ramp waveform falling to the polarity scan voltage and a second falling ramp waveform falling from the base voltage to the scan voltage. The method of claim 3, wherein A timing controller for controlling the respective driving units; And a driving voltage generator for supplying a driving voltage to each of the driving units. The driving voltage generator And driving the first and second rising ramp waveforms and the first and second falling ramp waveforms. A method of driving a plasma display panel which is divided and driven into a plurality of subfields divided into a reset period for initializing a cell, an address period for addressing a cell, and a sustain period for sustaining a discharge. And supplying only a falling ramp waveform falling from a base voltage to a negative scan voltage supplied to a scan electrode during at least one reset period of the subfields.

Images