KR100421672B1 - Driving Method for scanning of Plasma Display Panel - Google Patents

Abstract

The present invention relates to a scan driving method of a plasma display panel which can increase the contrast ratio and reduce the data driving voltage.

A scan driving method of a plasma display panel according to the present invention includes a plurality of subfields in one field, and a scan driving method of a plasma display panel including a first sustain electrode, a second sustain electrode, and an address electrode for generating a discharge. A first subfield including a reset discharge by a ramp pulse, and one or more second subfields to perform a reset discharge by a ramp-up pulse having a voltage smaller than a ramp pulse of the first subfield. .

According to the present invention, the scan driving method of the plasma display panel is driven to increase the wall voltage of a cell which has been turned on by performing a reset discharge applying a ramp-up pulse after the sustain discharge, thereby enabling data low voltage driving without reducing the contrast. .

Description

Scanning driving method of plasma display panel {Driving Method for scanning of Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel, and more particularly, to a scan driving method of a plasma display panel capable of increasing contrast ratio and lowering data driving voltage.

Plasma Display Panel (hereinafter referred to as "PDP") displays an image including text or graphics by emitting phosphors by 147 nm ultraviolet rays generated during discharge of He + Xe or Ne + Xe inert mixed gas. . Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

1 is a perspective view showing a conventional AC surface discharge PDP.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode 12Y and a sustain electrode 12Z formed on an upper substrate 10, and an address electrode formed on a lower substrate 18. 20X).

The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode 12Y and the sustain electrode 12Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan electrode 12Y and the sustain electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

These discharge cells are arranged in a matrix form as shown in FIG. In FIG. 2, the discharge cells 11 are provided at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn. The scan electrode lines Y1 to Ym are sequentially driven, and the sustain electrode lines Z1 to Zm are commonly driven. The address electrode lines X1 to Xn are driven by being divided into odd-numbered lines and even-numbered lines.

The three-electrode AC surface discharge type PDP 30 is driven by being divided into a plurality of subfields, and gray scale display is performed by emitting light a number of times proportional to the weight of video data in each subfield period. For example, when an image is displayed in 256 gray scales using 8-bit video data, one frame display period (for example, 1/60 second = about 16.7 msec) in each discharge cell 11 is shown in FIG. As shown, the data is divided into eight subfields SF1 to SF8. Each subfield SF1 to SF8 is further divided into a reset period, an address period and a sustain period, and 1: 2: 4: 8:... The weight is given at the ratio of 128. Here, the reset period is a period for initializing the discharge cells, the address period is a period during which selective address discharge occurs according to the logic value of the video data, and the sustain period is such that discharge is maintained in the discharge cells in which the address discharge has occurred. It is a period. The reset period and the address period are equally allocated to each subfield period.

4 is a driving waveform diagram of a plasma display panel according to the related art, in which only one lamp reset waveform is used per frame.

Referring to FIG. 4, the ramp reset waveform RP1 of the first subfield SF1 performs a reset per frame. The reset waveform RP2 of the second subfield SF2 differs from that of the first subfield SF1. That is, the reset waveform RP2 after the second subfield SF2 resets the discharge through the reference reset voltage Vs without the ramp-up waveform and reduces the wall charge through the ramp-down waveform.

First, the reset waveform RP1 of the first subfield SF1 receives wall charges from the scan / sustain electrode Y and the common sustain electrode Z of all panels by the ramp-up waveform of the set-up period. Stack over a certain amount. Thereafter, the wall charges are subtracted to some extent by the ramp-down waveform of the set-down period so that a constant wall charge is accumulated on the entire panel as shown in FIG. 5. That is, since the ramp-down waveform of the first subfield SF1 has an effect of accumulating (+) wall charges not only on the scan / sustain electrode Y and the common sustain electrode Z but also on the address electrode X, the data voltage Can be driven at a voltage as low as the wall charge.

The wall charge change after the second subfield SF2 is described by dividing the cell turned on and the cell not turned on in the previous subfield. First, in a cell that is not turned on in the previous subfield, positive ions accumulated on the address electrode X are maintained as they are by the ramp-up waveform as shown in FIG. However, in the cell turned on in the previous subfield, a lot of positive ions accumulated in the data voltage are lost due to many sustain pulses as shown in FIG. The cells can be divided into cells that are turned on and cells that are not turned on. Then, before the address period of the subfield, the wall charges accumulated on the electrodes in the two cells must be matched to the same conditions before the new subfield driving starts again.

Therefore, a method of lowering the positive wall charges accumulated on the address electrodes X of the cells that are not turned on to the wall charges of the cells that were turned on was used. This operation is accomplished by a ramp-down pulse that drops to the negative voltage. In other words, in the conventional method in which the ramp waveform is used in every subfield, the panel condition is generally initialized by using a high lamp pulse regardless of the cells that are turned on and the cells that are not turned on after the sustain discharge, but the method of FIG. Instead of using a lamp pulse, high contrast characteristics are obtained by using a driving method that equalizes the states of on and off cells.

However, after the second subfield SF2, since the positive wall voltage accumulated on the address electrode is lowered, the data voltage is increased.

Referring to FIG. 7, in the method of driving a three-electrode AC surface discharge type PDP, one frame includes subfields SF1 to SF6 of selective writing and subfields SF7 to SF12 of selective erasing. The first subfield SF1 is divided into a reset period for turning off the full screen, an optional write address period for turning on the selected discharge cells, a sustain period for sustaining discharge for the discharge cell selected by the address discharge, and an erasing period for canceling the sustain discharge. . Each of the second to fifth subfields SF2 to SF5 is divided into an optional write address period, a sustain period, and an erase period. The sixth subfield SF6 is divided into an optional write address period and a sustain period. In the first to sixth subfields SF1 to SF6, the selective write address period and the erase period are the same for each subfield, while the sustain period is 2n in each subfield (n = 0, 1, 2, 3, 4). Is increased by 5). The seventh to twelfth subfields SF7 to SF12 sustain sustain discharge of discharge cells other than the discharge cells selected by the address discharge and the selective erase address period for turning off the selected discharge cells without the entire surface-writing period. Divided into periods. In the seventh to twelfth subfields SF7 to SF12, not only the selective erasure address period but also the sustain period are set equally. The sustain period of the seventh to twelfth subfields SF7 to SF12 is set to a luminance relative ratio of 25 to have the same luminance relative ratio as that of the sixth subfield SF6.

Each of the seventh to twelfth subfields SF7 to SF12 driven by the selective erasing method must have the previous subfield turned on to turn off unnecessary discharge cells whenever the subfields are consecutive. For example, in order for the seventh subfield SF7 to be turned on, the sixth subfield SF6 driven by the selective write method, which is the previous subfield, must be turned on. After the sixth subfield SF6 is turned on, the unnecessary discharge cells are turned off in the seventh to twelfth subfields SF7 to SF12. To this end, the cells turned on in the sixth subfield WSF, which is the last selective write subfield WSF, must be turned on by the sustain discharge in order for the selective erase subfield ESF to be used. Therefore, the seventh subfield SF7 does not need a separate writing discharge for the selective erase address. In addition, the eighth to twelfth subfields SF8 to SF12 also selectively turn off cells that are turned on in the previous subfield without front lighting.

FIG. 8 is a waveform diagram illustrating a PDP driving waveform shown in FIG. 7.

Referring to FIG. 8, in the reset period or the setup period of the first selective write subfield SW1, the reset waveform of the ramp-down waveform is followed by the reset pulse RP of the ramp-up waveform in the scan / sustain electrode lines Y. -RP) are supplied sequentially. The reset waveform (-RP) of this ramp down falls to the scan reference voltage (Vw) of negative polarity (-). In addition, the scan sustain voltage DCSC having a positive polarity is supplied to the common sustain electrode lines Z.

In the address period of the selective write subfield SW1, the scan / sustain electrode lines Y and the address electrode lines X are respectively supplied while the positive scan DC voltage DCSC is supplied to the common sustain electrode lines Z. The negative write (-SWSP) and the positive write (+) selective write data pulses (SWDP) are supplied to be synchronized with each other. The sustain pulses SUSPy and SUSPz alternate with the scan / sustain electrode lines Y and the common sustain electrode lines Z so that sustain discharge occurs for the cells turned on by the address discharge in the selective write subfield SW. Supplied by. At the end of the second selective write subfield SW2, the erase pulse EP is supplied to the scan / sustain electrode lines Y for the sustain discharge to be erased.

The reset period of the selective erase subfield SE is omitted. In the address period of the selective erasing subfield SE, a negative selective erasing scan pulse (-SESP) and a positive selective erasing for turning off a cell in each of the scan / sustain electrode lines Y and the address electrode lines X are performed. The data pulses SEDP are supplied to be synchronized with each other. The selective erase scan pulse (-SESP) drops to the selective erase scan voltage (-Ve) higher than the scan reference voltage (-Vw). Sustain pulses SUSPy and SUSPz alternate between scan / sustain electrode lines Y and common sustain electrode lines Z so that sustain discharge occurs for cells that are not turned off by address discharge in the selective erase subfield SE. Supplied as In the case where the next subfield is the selective erasure field SE, a sustain pulse SUSPy having a relatively large pulse width is supplied to the scan / sustain electrode lines Y at the end of the current selective erasure subfield SE. . In the last selective erase subfield in which the next subfield is the selective write subfield SW, the erase pulse EP and the ramp signal RAMP are applied to the scan / sustain electrode lines Y and the common sustain electrode lines Z. It erases the sustain discharge of the supplied and turned on cells.

As described above, in the driving waveform for driving the PDP, since the positive wall voltage accumulated on the address electrode X decreases after the second subfield SF2, the data driving voltage increases.

Accordingly, an object of the present invention is to provide a scan driving method of a plasma display panel having a low data driving voltage by dividing a cell which is turned on and a cell which is not turned on in a previous subfield, and accumulating a lower wall charge again.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 2 is a layout view of electrodes of the plasma display panel shown in FIG. 1. FIG.

3 is a frame configuration diagram according to a conventional subfield driving method.

FIG. 4 is a drive waveform diagram for driving the plasma display panel shown in FIG. 1 for one frame. FIG.

FIG. 5 is a diagram illustrating a wall charge generation form in the first subfield period of FIG. 3. FIG.

FIG. 6 illustrates a form of wall charge generation after the first subfield period of FIG. 3. FIG.

7 is a frame diagram according to another subfield driving method.

FIG. 8 is a drive waveform diagram for driving the plasma display panel shown in FIG. 7 for one frame; FIG.

9 is a driving waveform diagram for driving during one frame of the plasma display panel according to the first embodiment of the present invention;

FIG. 10 is a view showing a wall charge generation form after a first subfield period in the driving waveform diagram shown in FIG. 9; FIG.

FIG. 11 illustrates driving waveforms of a PDP according to a second embodiment of the present invention; FIG.

12 illustrates a driving waveform of a PDP according to a third embodiment of the present invention.

FIG. 13 is a view showing driving waveforms of a PDP according to a fourth embodiment of the present invention; FIG.

14 illustrates driving waveforms of a PDP according to a fifth embodiment of the present invention;

15 illustrates a driving circuit of a PDP for driving embodiments of the present invention.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 11: discharge cell

12Y, 42 scan electrode 12Z, 44 sustain electrode

14 upper dielectric layer 16 protective film

18: lower substrate 20X: address electrode

22: lower dielectric layer 24: partition wall

26 phosphor 30 PDP

40: scan driver 42: sustain pulse generator circuit

In order to achieve the above objects, a scan driving method of a plasma display panel according to the present invention includes a plurality of subfields in one field and a plasma display having a first sustain electrode, a second sustain electrode and an address electrode for generating a discharge. A method of driving a scan of a panel, the method comprising: a first subfield including a reset discharge by a ramp pulse and at least one second discharge reset by a ramp-up pulse having a voltage smaller than a ramp pulse of the first subfield And subfields.

At this time, the second subfields performing the reset discharge by the ramp-up pulse cause negative wall charges to accumulate on the first sustain electrode, and positive wall charges to accumulate on the second sustain electrode and the address electrode. Characterized in that it comprises a step.

According to another exemplary embodiment of the present invention, a scan driving method of a plasma display panel includes at least one or more optional write subfields representing low gray levels by turning on selected discharge cells and maintaining discharge of the turned on cells, and a last one of the selective write subfields. 12. A scan driving method of a plasma display panel including at least one selective erasing subfield representing high gray levels by turning off cells turned on in a write subfield, wherein the selective write subfields include a reset discharge by a ramp pulse. And one or more second subfields for performing a reset discharge by a ramp-up pulse having a voltage smaller than a ramp pulse of the first subfield.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 9 to 15.

FIG. 9 is a diagram illustrating a drive waveform of another PDP according to the first embodiment of the present invention, and FIGS. 10A and 10B are views illustrating a wall charge generation form by the drive waveform shown in FIG. 9.

9, 10A, and 10B, the first reset waveform RP1 in the first subfield SF1 is the same as the conventional case, but the second reset waveform RP2 after the second subfield SF2 is the same as the conventional case. ) Forms a negative wall charge by applying a ramp-up waveform to the scan / sustain electrode (Y). A relatively positive wall voltage is formed on the common sustain electrode Z and the address electrode X, respectively.

In the address period, the scan pulse SP is supplied to the scan / sustain electrode Y and the data pulse DP is supplied to the address electrode X, thereby causing address discharge. The wall charge formed by this address discharge is maintained for the period during which the other discharge cells are addressed.

The triggering pulse TP is supplied to the scan / sustain electrode Y at the beginning of the sustain period to start the sustain discharge in the discharge cells 11 in which wall charges are sufficiently formed in the address period. Subsequently, sustain pulses SUSPz and SUSPy are alternately supplied to the common sustain electrode Z and the scan / sustain electrode Y to maintain sustain discharge during the sustain period.

Referring to the states of the cells that are not turned on and the cells turned on in FIGS. 10A and 10B, first, wall charges are already applied to the scan / sustain electrode Y, the common sustain electrode Z, and the address electrode X in the cells that are not turned on in FIG. 10A. There is little wall charge due to a slight ramp-up waveform because it is sufficiently stacked. Of course, this does not mean that there is absolutely no change in the wall charge, but in a cell that is not turned on, the condition of applying a reset pulse with no change is preceded. In the cell turned on in the previous subfield of FIG. 10B, the positive charge of the address electrode X is lost due to many sustain pulses SUSPy and SUSPz, and the scan / sustain electrode Y and the common sustain electrode ( The wall charges are also lost by the erasing pulse EP even between Z). Therefore, the ramp-up waveform of the scan / sustain electrode Y causes the negative wall charges to be accumulated on the scan / sustain electrode Y and the positive wall charges to the address electrode X. In addition to lowering the voltage, the sustain voltages of the scan / sustain electrode Y and the common sustain electrode Z can be lowered.

11 is a view illustrating a driving waveform of a PDP according to a second embodiment of the present invention.

Referring to FIG. 11, the driving waveform in the present invention does not apply an excessively high voltage to the ramp-up reset pulse RP2 of the scan / sustain electrode Y after the second subfield SF2. This is because if the ramp-up reset pulse RP2 is too high, it can excessively amplify the wall charge remaining in the cell that was not turned on.

Thus, in the reset period after the second subfield SF2, the first reset voltage Vr1 having the magnitude of the negative scan voltage −Vsc applied to the address period of the first subfield SF1 is set as a reference voltage in FIG. 9. The reset pulse RP2 is applied to the second reset voltage Vr2 of the magnitude equal to the second reset waveform at.

Therefore, the ramp-up reset pulse RP2 crossing the ground level also has a driving effect because the ramp-up reset pulse RP2, as described above, only acts to compensate for the wall charges lost in the lit cell. do.

Subsequently, in the address period, the scan pulse SP is supplied to the scan / sustain electrode Y and the data pulse DP is supplied to the address electrode X, thereby causing address discharge. The wall charge formed by this address discharge is maintained for the period during which the other discharge cells are addressed.

The triggering pulse TP is supplied to the scan / sustain electrode Y at the beginning of the sustain period to start the sustain discharge in the discharge cells 11 in which wall charges are sufficiently formed in the address period. Subsequently, sustain pulses SUSPz and SUSPy are alternately supplied to the common sustain electrode Z and the scan / sustain electrode Y to maintain sustain discharge during the sustain period.

12 illustrates a driving waveform of the PDP according to the third embodiment of the present invention.

Referring to FIG. 12, in the driving waveform according to the present invention, since the voltage is applied to the scan / sustain electrode Y in the direction of increasing the lowered wall voltage again, a negative scan voltage (−) is applied to the address period of each subfield. Scan driving is performed by applying a positive scan voltage Vsc without applying Vsc).

In the reset waveform after the second subfield SF2, the first reset voltage Vr1 matches the negative scan voltage (−Vsc), and the second reset voltage Vr2 matches the positive scan voltage Vsc. do. However, the magnitudes of the first and second reset voltages Vr1 and Vr2 do not necessarily have to match the scan voltage Vsc. Since the reset pulse RP2 after the second subfield SF2 is a waveform that exists independently before the address period, the reset pulse RP2 is a value determined as a bias level at which address discharge can occur best in each system.

FIG. 13 is a view showing a drive waveform of another PDP according to the fourth embodiment of the present invention. FIG.

Referring to FIG. 13, the driving waveform according to the present invention does not fall to the base voltage in the reset pulse RP of the first subfield SF1 as shown in the dotted circle. Keep it. At this time, the predetermined voltage is about 10 to 20V. This reduces the amount of positive wall charges lost at the address electrode X by the ramp-down reset pulse RPd, thereby obtaining a lower data driving voltage.

Subsequently, in the address period of each subfield, scan driving is performed by applying a positive scan voltage Vsc as shown in FIG.

At this time, in the reset waveform after the second subfield SF2, the first reset voltage Vr1 matches the negative scan voltage (−Vsc), and the second reset voltage Vr2 is equal to the positive scan voltage Vsc. Matches. However, the magnitudes of the first and second reset voltages Vr1 and Vr2 do not necessarily have to match the scan voltage Vsc.

14 illustrates a driving waveform of a PDP according to a fifth embodiment of the present invention.

Referring to FIG. 14, during the reset period of the first selective write subfield SW1, the ramp-down reset pulse RP is sequentially supplied to the scan / sustain electrode lines Y after the ramp-up reset pulse RP. do. This ramp-down reset pulse (-RP) drops to 0V. In addition, the scan sustain voltage DCSC having a positive polarity is supplied to the common sustain electrode lines Z.

In the address period of the selective write subfield SW1, each of the scan / sustain electrode lines Y and the address electrode lines X while the positive scan DC voltage DCSC is supplied to the common sustain electrode lines Z. The negative selective write scan pulse (-SWSP) and the positive selective write data pulse (SWDP) are supplied to be synchronized with each other. The sustain pulses SUSPy and SUSPz alternate with the scan / sustain electrode lines Y and the common sustain electrode lines Z so that sustain discharge occurs for the cell turned on by the address discharge of the selective write subfield SW1. Is supplied.

The reset waveform of the reset period of the second selective write subfield SW2 causes negative wall charges to accumulate in the scan / sustain electrode lines Y. A relatively positive wall voltage is accumulated on the common sustain electrode Z and the address electrode lines X. As a result, the ramp-up reset pulse RP2 of the scan / sustain electrode lines Y accumulates negative wall charges on the scan / sustain electrode line Y, and relatively the (+) walls of the address electrode lines X. By accumulating electric charges, not only the data driving voltage can be lowered later but also the sustain voltages of the scan / sustain electrode Y and the common sustain electrode Z can be lowered. At the end of the second selective write subfield SW2, the erase pulse EP is supplied to the scan / sustain electrode lines Y for the sustain discharge to be erased.

The reset period of the selective erase subfield SE is omitted. In the address period of the selective erase subfield SE, a negative selective erase scan pulse (-SESP) and a positive selective erase to turn off a cell in each of the scan / sustain electrode lines Y and the address electrode lines X, respectively. The data pulses SEDP are supplied to be synchronized with each other. The selective erase scan pulse (-SESP) drops to the selective erase scan voltage (-Ve) higher than the scan reference voltage (-Vw). Sustain pulses SUSPy and SUSPz alternate between scan / sustain electrode lines Y and common sustain electrode lines Z so that sustain discharge occurs for cells that are not turned off by the address discharge in the selective erase subfield SE. Supplied as In the case where the next subfield is the selective erasure field SE, a sustain pulse SUSPy having a relatively large pulse width is supplied to the scan / sustain electrode lines Y at the end of the current selective erasure subfield SE. . The erase pulse and the ramp signal are supplied to the scan / sustain electrode lines Y and the common sustain electrode lines Z in the last selective erase subfield SE in which the next subfield is the selective write subfield SW. Clear the sustain discharge of the cells.

15 is a diagram illustrating a driving circuit of a PDP for driving embodiments of the present invention.

Referring to FIG. 15, a driving circuit according to the present invention includes first and second switches S1 and S2 connected in series between a setup voltage source Vsetup and a sustain pulse generating circuit 42, and first and second electrodes. A capacitor Cs connected in parallel with the switches S1 and S2, a node Q between the first switch S1 and the second switch S2, and a scan connected between the node Q and the panel A third switch S3 connected between the drive unit 40 and the node Q and the ground voltage source GND and having a lamp switch function, and a lamp switch function connected between the node Q and the reset voltage source Vr. It has a fourth switch (S4) having a.

The first switch S1 is a switch for supplying a ramp-up pulse waveform, and the second switch S2 is supplied with a ramp-up pulse waveform and at the same time a basic base voltage Vs is supplied from the sustain pulse generator circuit 42. To be supplied. The third switch S3 generates a ramp-down pulse waveform of the first subfield SF1. As a result, the first, second and third switches S1, S2, and S3 are driven only in the first subfield SF1 in each subfield.

In order to generate the ramp-up pulse after the second subfield SF2 of the present invention, only the fourth switch S4 is added and driven to reset discharge in the reset period. In addition, according to the system state, the ramp-up pulse after the second subfield SF2 may be generated by using only the ramp-up pulse by the first switch S1 without the sustain bias voltage Vs.

As described above, in the driving method of the PDP according to the present invention, the low-voltage driving without increasing the contrast is possible by driving to increase the wall voltage of the cell which is turned on by performing a reset discharge applying a ramp-up pulse after the sustain discharge. do.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

1. A scan driving method of a plasma display panel including a plurality of subfields in one field and including a first sustain electrode, a second sustain electrode, and an address electrode for generating a discharge. A first subfield including a reset discharge by a ramp pulse, And one or more second subfields for reset discharge by a ramp-up pulse having a voltage smaller than the ramp pulse of the first subfield. The method of claim 1, Accumulating negative wall charges on the first sustain electrode in the second subfields performing the reset discharge by the ramp-up pulse; And accumulating positive wall charges on the second sustain electrode and the address electrode. The method of claim 2, Applying a positive ramp-up pulse to the first sustain electrode; And applying 0V to the second sustain electrode and the address electrode while a pulse is applied to the first sustain electrode. The method of claim 2, Applying a ramp-up pulse rising to the first sustain electrode based on a negative scan reference voltage; And applying 0V to the second sustain electrode and the address electrode while a pulse is applied to the first sustain electrode. The method of claim 4, wherein Applying a scanning pulse of OV to the first sustain electrode; And applying a data pulse to the address electrode at the same time as the application of the scan pulse so that a counter discharge occurs in the address period of the plurality of subfields. The method of claim 5, wherein And decreasing a ramp down pulse of the ramp pulses of the first subfield to a predetermined voltage. The method of claim 6, The predetermined voltage is 10 to 20V, the scan driving method of the plasma display panel. By turning on the selected discharge cells and maintaining the discharge of the turned on cells, at least one or more optional write subfields representing low gradations and the cells turned on in the last selective write subfield among the selective write subfields are turned off. A scan driving method of a plasma display panel including at least one selective erasing subfield to be expressed, The selective write subfields may include a first subfield including a reset discharge by a ramp pulse; And one or more second subfields for reset discharge by a ramp-up pulse having a voltage smaller than the ramp pulse of the first subfield. The method of claim 8, Accumulating negative wall charges on the first sustain electrode in the second subfields performing the reset discharge by the ramp-up pulse; And accumulating positive wall charges on the second sustain electrode and the address electrode. The method of claim 9, Applying a positive ramp-up pulse to the first sustain electrode; And applying 0V to the second sustain electrode and the address electrode while a pulse is applied to the first sustain electrode.