KR100486911B1 - Method and apparatus for driving plasma display panel - Google Patents

Abstract

The present invention relates to a method and apparatus for driving a plasma display panel which enables an off-cell to be stably operated and enables low voltage driving.

The method and apparatus for driving the plasma display panel select on-cells to be turned on by applying a data voltage to a first electrode and applying a scan voltage to a second electrode, and then pre-clearing the same type to the second electrode and the third electrode. A signal is supplied to erase charges remaining in the off cells other than the on cells, and a sustain voltage is alternately applied to the second and third electrodes to discharge the on cells, thereby displaying an image.

Description

TECHNICAL AND APPARATUS FOR DRIVING PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method and an apparatus for driving a plasma display panel which enables an off-cell to be stably operated and enables low voltage driving.

Plasma Display Panel (hereinafter referred to as "PDP") is used to excite and emit phosphors by using ultraviolet rays generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is discharged. Will be displayed. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a conventional three-electrode AC surface discharge type PDP has an address orthogonal to the scan electrodes Y1 to Yn and the sustain electrode Z, and the scan electrodes Y1 to Yn and the sustain electrode Z. Electrodes X1 to Xm are provided.

Cells 1 for displaying any one of red, green and blue are formed at the intersections of the scan electrodes Y1 to Yn, the sustain electrode Z and the address electrodes X1 to Xm. The scan electrodes Y1 to Yn and the sustain electrode Z are formed on an upper substrate (not shown). On the upper substrate, a dielectric layer and an MgO protective layer (not shown) are stacked. The address electrodes X1 to Xm are formed on the lower substrate (not shown). On the lower substrate, partition walls are formed to prevent optical and electrical interference between horizontally adjacent cells. Phosphors are excited on the lower substrate and the partition walls to be excited by vacuum ultraviolet rays and emit visible light. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is injected into the discharge space between the upper substrate and the lower substrate.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period (reset period) for initializing the full screen, an address period for selecting a scan line and selecting a cell from the selected scan line, and a sustain period for implementing gray scale according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

3 illustrates a driving waveform of a driving signal supplied to the PDP shown in FIG. 1.

Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period (reset period), the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y in the setup period SU. At the same time, 0 [V] is applied to the sustain electrode Z and the address electrode X. Dark discharge with little light generated between the scan electrode (Y) and the address electrode (X) and between the scan electrode (Y) and the sustain electrode (Z) in the cells of the full screen by the rising ramp waveform (Ramp-up) Dark discharge occurs. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. Here, the wall charge amount of negative polarity (-) accumulated on the scan electrode (Y) is equal to the total amount of wall charges of positive polarity (+) stacked on the address electrode (X) and the sustain electrode (Z).

In the set-down period SD, after the rising ramp waveform Ramp-up is supplied, it starts to fall at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up, and thus the base voltage GND or the negative polarity is specified. A falling ramp waveform Ramp-down falling to the voltage level is simultaneously applied to the scan electrodes Y. At the same time, a positive sustain voltage Vs is applied to the sustain electrode Z which is a common electrode, and 0 [V] is applied to the address electrode X. When the ramp ramp is applied in this manner, dark discharge occurs in which light is hardly generated between the scan electrode Y and the sustain electrode Z. Further, no discharge occurs between the scan electrode Y and the address electrode Z in the section in which the falling ramp waveform falls, and dark discharge occurs at the lower limit of the falling ramp waveform. The discharge occurring in the set down period SD eliminates unnecessary excessive wall charges generated in the address discharge generated in the setup period SU. Looking at the wall charge change in the setup period SU and the setdown period SD, there is almost no wall charge change on the address electrode X, and the negative wall charge of the scan electrode Y decreases. On the other hand, the wall charge of the sustain electrode Z was positive in the set-up period SU, but the negative wall charge accumulated on itself as much as the decrease in the negative wall charge of the scan electrode Y was set-up period. At (SD), its polarity is reversed to negative polarity.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage due to the wall charge generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse data is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is applied.

On the other hand, the sustain electrode Z is supplied with a positive DC voltage (Vz-com) to reduce the voltage difference between the scan electrode (Y) during the set-down period and the address period so as to prevent erroneous discharge from the scan electrode (Y). .

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. This will happen.

After the sustain discharge is completed, ramp-ers having a small pulse width and a low voltage level are supplied to the sustain electrode Z to be turned on in the cells turned on by the sustain discharge (hereinafter referred to as "on cell"). The remaining wall charges are eliminated.

However, in the conventional PDP, since the wall charge remaining from the initialization period in the non-selected cell (hereinafter referred to as an "off cell") where no address discharge has occurred is maintained for the sustain period, the sustain pulse is caused by the residual wall charge. When (sus) is applied, the off-cell can be discharged while the wall voltage in the off-cell and the sustain voltage (Vs) of the sustain pulse (sus) are added. Such misdischarges degrade the display quality of the image, and in severe cases, the image cannot be displayed.

Conventional PDP is reduced on the scan electrode (Y) by the discharge of the set-down period (SD) and the residual amount of remaining wall charges is small, the voltage level of the voltage (Vd, Vscan) supplied from the outside during the address discharge is high only none. In addition, the conventional PDP has a small wall charge on the sustain electrode Z which is accumulated during the discharge of the set-down period SD, so that the voltage of the sustain pulse su supplied from the outside during the sustain period, that is, the sustain voltage Vs, becomes high. There is no choice but to. Furthermore, in the conventional PDP, since the wall charge in the cell is reduced and the operation conditions are changed in a high temperature environment, there is a problem in that incorrect discharge occurs frequently during address discharge.

Accordingly, an object of the present invention is to provide a method and apparatus for driving a PDP, which enables the off-cell to operate stably and to enable low voltage driving.

In order to achieve the above object, the driving method of the PDP according to the embodiment of the present invention is a PDP having a first electrode, a second electrode and a third electrode, applying a data voltage to the first electrode and the second electrode Selecting on cells to be turned on by applying a scan voltage to the same; and supplying a pre-clear signal of the same type to the second electrode and the third electrode to erase charges remaining in the off cells other than the on cells. And displaying an image by applying a sustain voltage to the second and third electrodes alternately to cause discharge of the on cells. The pre-clear signal has a linear voltage level change. The pre-clear signal has a voltage level that varies in stages. The voltage of the pre-clear signal starts to fall from a predetermined reference voltage and falls to a voltage between 0V and the scan voltage. The voltage of the pre-clear signal drops to a voltage lower than the scan voltage. The driving method of the PDP further includes the step of initializing the cells by supplying at least one of the second and third electrodes an initialization signal of which voltage level increases during an initialization period before selecting the cell. The initialization signal is simultaneously supplied to the second and third electrodes. The driving method of the PDP further includes supplying a post-erasing signal to at least one of the second and third electrodes after displaying the image to erase the charge remaining in the on cells. The driving method of the PDP further includes supplying a positive voltage to the first electrode while the pre-clear signal and the sustain voltage are supplied to the second and third electrodes. The driving device of the PDP includes a cell selection driver which selects on cells to be turned on by applying a data voltage to the first electrode and a scan voltage to the second electrode, and the same shape as that of the second electrode and the third electrode. A pre-erasing driver for erasing charge remaining in the off-cells other than the on-cells by supplying a pre-clearing signal of the cell, and a sustain voltage is alternately applied to the second and third electrodes to cause discharge to the on-cells. A display driver for displaying an image. The driving device of the PDP further includes an initialization driver for initializing the cells by supplying an initialization signal of increasing voltage level to at least one of the second and third electrodes in the initialization period before selecting the cell. The driving apparatus of the PDP further includes a post-erasing driving unit for supplying a post-erasing signal to at least one of the second and third electrodes to erase the charge remaining in the on cells after displaying the image. Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 11.

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Referring to FIG. 4, a driving apparatus of a PDP according to an embodiment of the present invention uses a data driver 42 for supplying data to address electrodes X1 to Xm of the PDP, and scan electrodes Y1 to Yn. A scan driver 43 for driving, a sustain driver 44 for driving the sustain electrode Z serving as a common electrode, a timing controller 41 for controlling the drivers 42, 43, 44, and each A driving voltage generator 45 is provided to supply driving voltages to the driving units 42, 43, and 44.

The data driver 42 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like, and then data mapped to each subfield is supplied by the subfield mapping circuit. The data driver 42 samples and latches data in response to the timing control signal CTRX supplied from the timing controller 41, and then supplies the data to the address electrodes X1 to Xm.

On the other hand, the data driver 42 has a positive data voltage Vd or other positive electrode during the pre-erasing period during which the pre-clear signal is generated from the scan driver 43 and the sustain driver 44 during the sustain period or during the sustain period. The voltage of the castle may be supplied to the address electrodes X1 to Xm.

The scan driver 43 simultaneously supplies a waveform for initializing the full screen to the scan electrodes Y1 to Yn under the control of the timing controller 41, and then scans the scan pulse in the address period to select the scan line. To Y1 to Yn sequentially. In addition, the scan driver 43 scans the pre-erase signal for erasing the wall charge unnecessarily remaining in the off-cell in which the address discharge has not occurred after the address period ends. Then, the sustain pulses are simultaneously supplied to the scan electrodes Y1 to Ym so that the on-cell can be sustained (or displayed) discharged during the sustain period. After the sustain period is over, the scan driver 43 simultaneously supplies a post-erase signal to the scan electrodes Y1 to Yn for erasing wall charges in the on-cell generated by the sustain discharge. do.

The sustain driver 44 supplies a pre-clear signal to the sustain electrode Z for erasing unnecessary wall charges remaining in the off-cell after the address period ends under the control of the timing controller 41, and then during the sustain period. Alternately with the scan driver 43, the sustain pulses are supplied to the sustain electrodes Z.

The timing controller 41 receives the vertical / horizontal synchronization signal and generates timing control signals CTRX, CTRY, and CTRZ required for each driver, and transmits the timing control signals CTRX, CTRY, and CTRZ to the corresponding driving units 42, 43, By supplying to 44, each drive part 42,43,44 is controlled. The timing control signal CTRX supplied to the data driver 42 includes a sampling clock SMPCLK for sampling data, a latch control signal, a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element. Included. The timing control signal CTRY applied from the timing controller 41 to the scan driver 43 includes a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element in the scan driver 43. The timing control signal CTRZ applied from the timing controller 41 to the sustain driver 44 includes a switch control signal for controlling the energy recovery circuit in the sustain driver 44 and the on / off time of the driving switch element. .

The driving voltage generator 45 includes a positive setup voltage Vset-up, a positive scan common voltage Vscan-com applied as a common voltage during an address period, and a negative scan voltage Vscan for selecting a scan line. ), A positive sustain voltage Vs and a pre-erase voltage Vpre-erase are generated, and the voltages are supplied to the scan driver 43. In the case where the setup waveform and the setdown waveform are continuously generated from the scan driver 43, the drive voltage generator 45 may include a setdown voltage Vset− selected from one of 0 [V], a base voltage GND, and a negative voltage. down) may be supplied to the scan driver 43. The setup voltage Vset-up is set higher than the sustain voltage Vs. The scan common voltage Vscan-com is selected between approximately 80 and 130 [V], and the scan voltage Vscan is selected within -70 to -100 [V]. The sustain voltage Vs is selected within 180 to 200 [V]. The pre-erase voltage Vpre-erase is a potential difference between the scan electrodes Y1 to Yn and the sustain electrode Z to which the pre-erase voltage Vpre-erase is applied, and the address electrodes X1 to Xm opposite thereto. Since the pre-erasing discharge occurs when the discharge start voltage is more than a probable degree, it depends on the level of the voltage supplied to the address electrodes X1 to Xm during the pre-clearing signal supply period. Therefore, the pre-erasing voltage Vpre-erase is positively applied to the address electrodes X1 to Xm during the period in which the pre-erasing signal is supplied. The higher the voltage level is, the lower the voltage level is. The voltage applied to Xm) is selected between 0 [V] and the setdown voltage (Vset-down).

In addition, the driving voltage generator 45 generates a positive data voltage Vd, supplies the voltage Vd to the data driver 42, and sets a common voltage equal to the scan common voltage Vscan-com. (Vz-com) is supplied to the sustain drive unit 44. The data voltage Vd is selected from 50 to 80 [V].

On the other hand, it is preferable that the initialization waveform generated at the same time in each of the scan driver 43 and the sustain driver 44 is composed only of the positive ramp ramp waveform. The rising ramp waveform at this time accumulates a sufficient amount of negative wall charges on the scan electrodes Y1 to Yn and the sustain electrode Z. In this case, initializing the PDP only by the setup discharge reduces the time required for the initialization and also forms a sufficient negative wall charge on the scan electrode (Y), so that the external driving voltage (Vscan, Vd) required for the address is low. Since the negative wall charges formed on the high scan electrodes Y and the sustain electrodes Z are maintained until the end of the address period, the voltage required for the sustain discharge is lowered.

5 illustrates waveforms of driving signals generated from the driving unit illustrated in FIG. 4. In Fig. 5, the waveform of the signal generated in the initialization period is omitted.

Referring to FIG. 5, the driving method of the PDP according to the first embodiment of the present invention includes an initialization period (or reset period) for initializing a full screen, an address period for selecting a cell, and an unnecessary wall of an offcell. The driving is divided into a pre-erasing period for erasing charge and a sustaining period for sustaining the discharge of the selected cell.

In the initialization period (reset period), a setup waveform and a set-down waveform as shown in FIG. 3 may be supplied, and a full cell can be initialized using various types of waveforms such as a square voltage pulse of a large voltage. In addition, during the initialization period, the cell of the full screen can be initialized only by the setup pulse applied to the scan electrodes Y1 to Yn and the sustain electrode Z at the same time. Detailed description thereof will be provided later.

The address period begins as the positive scan common voltage Vscan-com and the common voltage Vz-com are simultaneously applied to the scan electrodes Y and the sustain electrode Z. FIG. Since the same voltages Vscan-com and Vz-com are simultaneously applied to the scan electrode Y and the sustain electrode Z at the beginning of the address period, there is no potential difference between the scan electrode Y and the sustain electrode Z. The scan pulses falling to the scan voltage Vscan by the scan driver 43 during the address period are sequentially applied to the scan electrodes Y, and at the same time, the data pulses Vd are synchronized in synchronization with the scan pulses. When the data pulse data rising up to the address electrodes X is applied, the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added to the data pulse data. An address discharge is generated in the cell to be applied. In the on-cells selected by the address discharge, wall charges such that discharge can occur when the sustain voltage Vs is applied are formed.

In the pre-erasing period, the positive DC voltage Vx-com, which rises to the data voltage Vd and is maintained until the sustain period, is supplied to the address electrode X, and the pre-erase lamp signal Pre-ers is supplied with the scan electrode ( Y) and the sustain electrode Z are simultaneously supplied. The pre-erase lamp signal Pre-ers is generated for a period of approximately 20 [µs], and the voltage level of the pre-erase lamp signal Pre-ers is shown to fall below the scan voltage Vscan in FIG. The voltage difference between the two electrodes to generate a voltage is determined by the voltage on the address electrode X because the voltage on the scan electrode Y and the sustain electrode Z with respect to the voltage on the address electrode X is determined as the counter discharge start voltage. This may vary. By this pre-erase lamp signal Pre-ers, dark discharge with little light is generated between the address electrode X and the scan electrode Y and between the address electrode X and the sustain electrode Z. . This dark discharge erases the wall charge remaining from the initialization period in the off-cells. As a result, the off-cells are connected between the electrodes X, Y, and Z even when the sustain pulse is supplied because the wall voltage thereof is zero or close when the sustain pulse is supplied during the sustain period. Since the voltage of is maintained below the discharge start voltage, it is not mis-discharged. On the other hand, since the on-cells are charged with the negative charge on the address electrode X and the positive charge on the scan electrode Y, the pre-erase lamp signal Pre-ers falling to the negative voltage receives the scan electrode Y. ) And the sustain electrode Z are not discharged (cleared discharge) because the voltage between the electrodes (X, Y, Z) is kept below the discharge start voltage.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. This will happen.

After the sustain discharge is completed, the post-erase lamp signal post-ers rising up to the sustain voltage Vs is supplied to the scan electrode Y. By this post-erase lamp signal (post-ers), erasure discharge occurs in the on cells generated by the sustain discharge, and as a result, wall charges in the on cells are erased. In addition to the ramp waveform form as shown in FIG. 5, the post-erased signal may also use a square wave signal having a pulse width smaller than 2 [µs] and maintaining the sustain voltage Vs.

6 is a waveform diagram illustrating a method of driving a PDP according to a second embodiment of the present invention.

Referring to FIG. 6, in the driving method of the PDP according to the second embodiment of the present invention, an initialization period (or a reset period) for initializing a full screen in one frame, an address period for selecting a cell, and an unnecessary wall of an off cell The driving is divided into a pre-erasing period for erasing charge and a sustaining period for sustaining discharge of a selected cell, and the pre-erasing signal is generated in a multi-step form in which the voltage level is changed step by step.

In the initialization period (reset period), an initialization waveform (not shown) in the form of a ramp or a square wave is generated and the initialization waveform is supplied to the scan electrodes Y1 to Yn and / or the sustain electrode Z. This initialization waveform causes dark discharge between the electrodes X, Y, and Z in the cells of the full screen. Due to the dark discharge generated during the initialization period, wall charges necessary for the address discharge are accumulated in the cells of the full screen.

The address period begins as the positive scan common voltage Vscan-com and the common voltage Vz-com are simultaneously applied to the scan electrodes Y and the sustain electrode Z. FIG. Since the same voltages Vscan-com and Vz-com are simultaneously applied to the scan electrode Y and the sustain electrode Z at the beginning of the address period, there is no potential difference between the scan electrode Y and the sustain electrode Z. The scan pulses falling to the scan voltage Vscan by the scan driver 43 during the address period are sequentially applied to the scan electrodes Y, and at the same time, the data pulses Vd are synchronized in synchronization with the scan pulses. When the data pulse data rising up to the address electrodes X is applied, the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added to the data pulse data. An address discharge is generated in the cell to be applied. In the on-cells selected by the address discharge, wall charges such that discharge can occur when the sustain voltage Vs is applied are formed.

In the pre-erasing period, the positive DC voltage Vx-com, which rises to the data voltage Vd and is maintained until the sustain period, is supplied to the address electrode X, and the pre-erasing signal 3Pre which the voltage gradually decreases in three steps is performed. -ers are simultaneously supplied to the scan electrode (Y) and the sustain electrode (Z). The pre-erase signal 3Pre-ers is generated for a period of approximately 20 [µs], and the voltage level of the pre-erase signal Pre-ers is a voltage difference between the two electrodes for generating an erase discharge. Since the voltage on the scan electrode (Y) and the sustain electrode (Z) with respect to is determined as the counter discharge start voltage, the voltage level may vary according to the voltage on the address electrode (X). The pre-clearing signal 3Pre-ers generates dark discharge in which light is hardly generated between the address electrode X and the scan electrode Y and between the address electrode X and the sustain electrode Z. This dark discharge erases the wall charge remaining from the initialization period in the off-cells. As a result, the off-cells are connected between the electrodes X, Y, and Z even when the sustain pulse is supplied because the wall voltage thereof is zero or close when the sustain pulse is supplied during the sustain period. Since the voltage of is maintained below the discharge start voltage, it is not mis-discharged. On the other hand, since the on-cells are charged with the negative charge on the address electrode X and the positive charge on the scan electrode Y, the pre-erase signal 3Pre-ers falling to the negative voltage is the scan electrode Y. When the voltage is applied to the sustain electrode Z, the voltage between the electrodes X, Y, and Z is kept below the discharge start voltage, so that the discharge (erasure discharge) is not performed.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. This will happen.

After the sustain discharge is completed, the post-erase lamp signal post-ers rising up to the sustain voltage Vs is supplied to the scan electrode Y. By this post-erase lamp signal (post-ers), erasure discharge occurs in the on cells generated by the sustain discharge, and as a result, wall charges in the on cells are erased. In addition to the ramp waveform, the post-erasing signal may also use a square wave signal having a pulse width of less than 2 [µs] and maintaining a sustain voltage Vs.

7 is a waveform diagram illustrating a method of driving a PDP according to a third embodiment of the present invention.

Referring to FIG. 7, in the driving method of the PDP according to the third embodiment of the present invention, an initialization period (or a reset period) for initializing a full screen in one frame, an address period for selecting a cell, and wall charges unnecessary for sustain The driving waveform is divided into a pre-erasing period for erasing and a sustaining period for maintaining the discharge of the selected cell, and the initializing waveform is composed of only the setup waveform and the setup waveform is simultaneously supplied to the scan electrode Y and the sustain electrode Z. do.

In the initialization period, a rising ramp waveform rising at a predetermined slope from the common scan voltage Vscan-com to the setup voltage Vsetup is applied to all the scan electrodes Y and the sustain electrodes Z at the same time. At the same time, 0 [V] is applied to the address electrode X. As a result of the rising ramp waveform applied to the scan electrodes Y and the sustain electrodes Z at the same time, dark discharge with little light is generated in the cells of the full screen. As a result, the scan electrodes Y and the sustain electrodes are generated. The negative (-) wall charges are accumulated on each of the (Z), and the positive (+) wall charges are accumulated on the address electrode (X). Since the same voltage is simultaneously applied to the scan electrode (Y) and the sustain electrode (Z), the potential difference according to the wall voltage between the scan electrode (Y) and the address electrode (X) and between the sustain electrode (Z) and the address electrode (X). The potential difference according to the wall voltage of is equal to the counter discharge start voltage between the scan electrode Y and the address electrode X required for the address discharge. On the other hand, there is no potential difference between the scan electrode Y and the sustain electrode Z. The wall voltage according to the wall charge in each of the scan electrode Y and the sustain electrode Z has the same value as the dark discharge occurs due to the rising ramp waveform even if the initial state of the setup period, that is, the initial condition is different.

The address period starts as the positive scan common voltage Vscan-com is simultaneously applied to the scan electrodes Y and the common voltage Vz-com is simultaneously applied to the sustain electrodes Z. Since the same voltages Vscan-com and Vz-com are simultaneously applied to the scan electrode Y and the sustain electrode Z at the beginning of the address period, there is no potential difference between the scan electrode Y and the sustain electrode Z. Subsequently, a scan pulse falling to the negative scan voltage Vscan is sequentially applied to the scan electrodes Y, and a data pulse rising to the positive data voltage Vd in synchronization with the scan pulse scan. (data) is applied to the address electrodes (X). As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the on-cells selected by the address discharge, wall charges such that discharge can occur when the sustain voltage Vs is applied are formed.

Meanwhile, before the address discharge is started, there is no potential difference between the scan electrode Y and the sustain electrode Z, and the wall charge values formed on each of the two electrodes Y and Z are kept the same. For this reason, even if the PDP according to the present invention is used in a high temperature environment of 50 ° C. or higher, mis-discharge caused by wall charge fluctuation can be prevented before address discharge starts in a high temperature environment.

In the pre-erasing period, the positive DC voltage Vx-com, which rises to the data voltage Vd and is maintained until the sustain period, is supplied to the address electrode X, and the pre-erase lamp signal Pre-ers is supplied with the scan electrode ( Y) and the sustain electrode Z are simultaneously supplied. The pre-erase lamp signal (Pre-ers) is generated for a period of approximately 20 [µs], and the voltage level of the pre-erase lamp signal (Pre-ers) is the voltage difference between the two electrodes for generating an erase discharge address electrode (X). Since the voltage on the scan electrode (Y) and the sustain electrode (Z) with respect to the voltage of the phase is determined as the counter discharge start voltage, the voltage level may vary according to the voltage on the address electrode (X). Dark discharge is generated between the address electrode X and the scan electrode Y and between the address electrode X and the sustain electrode Z by the pre-erase lamp signal Pre-ers. This dark discharge erases the wall charge remaining from the initialization period in the off-cells. As a result, the off-cells have the electrodes X, Y, and Z even when the sustain pulse sus is supplied because the wall voltage therein is zero or close when the sustain pulse sus is supplied during the sustain period. Since the voltage between them is kept below the discharge start voltage, it is not mis-discharged. On the other hand, since the on-cells are charged with the negative charge on the address electrode X and the positive charge on the scan electrode Y, the pre-erase lamp signal Pre-ers falling to the negative voltage receives the scan electrode Y. ) And the sustain electrode Z are not discharged (cleared discharge) because the voltage between the electrodes (X, Y, Z) is kept below the discharge start voltage.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. On-cells selected by the address discharge have a sustain voltage generated between the scan electrode Y and the sustain electrode Z every time the sustain pulse sus is applied as the wall voltage and the sustain pulse sus in the cell are added.

After the sustain discharge is completed, the post-erase lamp signal post-ers rising up to the sustain voltage Vs is supplied to the scan electrode Y. By this post-erase lamp signal (post-ers), erasure discharge occurs in the on cells generated by the sustain discharge, and as a result, wall charges in the on cells are erased. In addition to the ramp waveform, the post-erasing signal may also use a square wave signal having a pulse width of less than 2 [µs] and maintaining a sustain voltage Vs.

In the method and apparatus for driving a PDP according to the third embodiment of the present invention, since the PDP is initialized only by the setup discharge by omitting the conventional set down period, the initialization time can be reduced. In addition, since the PDP driving method and apparatus according to the third embodiment of the present invention form a sufficient amount of negative wall charges on the scan electrode Y, the external driving voltages Vscan and Vd required for the address are greatly reduced. Can be. Furthermore, in the PDP driving method and apparatus according to the third embodiment of the present invention, since the negative wall charges formed on the scan electrode (Y) and the sustain electrode (Z) are maintained until the end of the address period, an external device required for sustain discharge is required. The driving voltage Vs can be lowered.

On the other hand, the PDP proposed through Japanese Patent Application Laid-Open No. 2001-135238 has a discharge gas encapsulated in the PDP as Ne-Xe10% and 46 kPa, which makes the density of the Xe component higher than before. The driving voltage is higher than that of the low density Xe panel, but the luminance can be further increased. Applying the third embodiment of the present invention to such a high density Xe panel, it is possible to lower the driving voltage of the high voltage level required by increasing the Xe component in the discharge gas, which is applied to the high density Xe panel to satisfy high brightness and low voltage driving at the same time. It becomes possible.

8 is a waveform diagram illustrating a method of driving a PDP according to a fourth embodiment of the present invention.

Referring to FIG. 8, in the driving method of the PDP according to the fourth embodiment of the present invention, the initialization waveform supplied in the initialization period is composed of only the setup waveform and the setup waveform is simultaneously applied to the scan electrode Y and the sustain electrode Z. The pre-clearing signal is generated in a multi-step form in which the voltage level is gradually changed in the pre-erasing period.

In the initialization period, a rising ramp waveform rising at a predetermined slope from the common scan voltage Vscan-com to the setup voltage Vsetup is applied to all the scan electrodes Y and the sustain electrodes Z at the same time. At the same time, 0 [V] is applied to the address electrode X. As a result of the rising ramp waveform applied to the scan electrodes Y and the sustain electrodes Z at the same time, dark discharge with little light is generated in the cells of the full screen. As a result, the scan electrodes Y and the sustain electrodes are generated. The negative (-) wall charges are accumulated on each of the (Z), and the positive (+) wall charges are accumulated on the address electrode (X). Since the same voltage is simultaneously applied to the scan electrode (Y) and the sustain electrode (Z), the potential difference according to the wall voltage between the scan electrode (Y) and the address electrode (X) and between the sustain electrode (Z) and the address electrode (X). The potential difference according to the wall voltage of is equal to the counter discharge start voltage between the scan electrode Y and the address electrode X required for the address discharge. On the other hand, there is no potential difference between the scan electrode Y and the sustain electrode Z. The wall voltage according to the wall charge in each of the scan electrode Y and the sustain electrode Z has the same value as the dark discharge occurs due to the rising ramp waveform even if the initial state of the setup period, that is, the initial condition is different.

The address period starts as the positive scan common voltage Vscan-com is simultaneously applied to the scan electrodes Y and the common voltage Vz-com is simultaneously applied to the sustain electrodes Z. Since the same voltages Vscan-com and Vz-com are simultaneously applied to the scan electrode Y and the sustain electrode Z at the beginning of the address period, there is no potential difference between the scan electrode Y and the sustain electrode Z. Subsequently, a scan pulse falling to the negative scan voltage Vscan is sequentially applied to the scan electrodes Y, and a data pulse rising to the positive data voltage Vd in synchronization with the scan pulse scan. (data) is applied to the address electrodes (X). As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the on-cells selected by the address discharge, wall charges such that discharge can occur when the sustain voltage Vs is applied are formed.

On the other hand, in the PDP according to the fourth embodiment of the present invention, since the wall charge values formed on each of the scan electrodes Y and the sustain electrodes Y and Z remain the same, no false discharge occurs even in a high temperature environment of 50 ° C. or higher.

In the pre-erasing period, the positive DC voltage Vx-com, which rises to the data voltage Vd and is maintained until the sustain period, is supplied to the address electrode X, and the pre-erasing signal 3Pre which the voltage gradually decreases in three steps is performed. -ers are simultaneously supplied to the scan electrode (Y) and the sustain electrode (Z). The pre-clearing signal 3Pre-ers generates dark discharge in which light is hardly generated between the address electrode X and the scan electrode Y and between the address electrode X and the sustain electrode Z. This dark discharge erases the wall charge remaining from the initialization period in the off-cells. As a result, the off-cells are connected between the electrodes X, Y, and Z even when the sustain pulse is supplied because the wall voltage thereof is zero or close when the sustain pulse is supplied during the sustain period. Since the voltage of is maintained below the discharge start voltage, it is not mis-discharged. On the other hand, since the on-cells are charged with the negative charge on the address electrode X and the positive charge on the scan electrode Y, the pre-erase signal 3Pre-ers falling to the negative voltage is the scan electrode Y. When the voltage is applied to the sustain electrode Z, the voltage between the electrodes X, Y, and Z is kept below the discharge start voltage, so that the discharge (erasure discharge) is not performed.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. On-cells selected by the address discharge have a sustain voltage generated between the scan electrode Y and the sustain electrode Z every time the sustain pulse sus is applied as the wall voltage and the sustain pulse sus in the cell are added.

After the sustain discharge is completed, the post-erase lamp signal post-ers rising up to the sustain voltage Vs is supplied to the scan electrode Y. By this post-erase lamp signal (post-ers), erasure discharge occurs in the on cells generated by the sustain discharge, and as a result, wall charges in the on cells are erased. In addition to the ramp waveform, the post-erasing signal may also use a square wave signal having a pulse width of less than 2 [µs] and maintaining a sustain voltage Vs.

The method and apparatus for driving a PDP according to the fourth embodiment of the present invention can reduce the time required for initialization since the PDP is initialized only by the setup discharge by omitting the conventional set down period. In addition, since the PDP driving method and apparatus according to the third embodiment of the present invention form a sufficient amount of negative wall charges on the scan electrode Y, the external driving voltages Vscan and Vd required for the address are greatly reduced. Can be. Furthermore, in the PDP driving method and apparatus according to the third embodiment of the present invention, since the negative wall charges formed on the scan electrode (Y) and the sustain electrode (Z) are maintained until the end of the address period, an external device required for sustain discharge is required. The driving voltage Vs can be lowered.

The driving method and apparatus of the PDP according to the fourth embodiment of the present invention can reduce the driving voltage at a high voltage level required by increasing the Xe component in the discharge gas when applied to the high density Xe panel. It can be applied to satisfy high brightness and low voltage driving at the same time.

Although the initialization waveforms according to the third and fourth embodiments of the present invention illustrate that the voltage level is linearly increased in the rising period, it may be increased in the form of an exponential function, that is, a gentle curve as shown in FIGS. 9 and 10. And it may be increased in the form of a sine wave (sine wave) as shown in Figure 11 using a resonant circuit.

As described above, the method and apparatus for driving a PDP according to the present invention set a pre-erasing period between an address period and a sustain period and simultaneously pre-erasing the scan electrode Y and the sustain electrode Z within the pre-erasing period. By applying a signal, the off-cell can be stably operated by erasing wall charges in the off-cells remaining after the initialization period. In addition, the method and apparatus for driving a PDP according to the present invention allow low voltage driving by accumulating a sufficient amount of wall charges on the scan electrode Y and the sustain electrode Z during the initialization period, and before the address discharge starts. By maintaining the voltage difference between the scan electrode (Y) and the sustain electrode (Z) at 0 [V], it is possible to prevent erroneous discharge generated in a high temperature environment. Furthermore, the method and apparatus for driving a PDP according to the present invention are suitable for high density Xe panels because they can not only increase the luminance but also can operate at low voltage when applied to the high density Xe panels.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. For example, a person skilled in the art will use the embodiment to mix the pre-clear signal in which the voltage level changes linearly with the pre-clear signal in which the voltage level changes in a multi-step form, and supply the scan electrode Y and the sustain electrode Z to each other. It may be possible to erase the wall charge remaining in the cells. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram illustrating a frame configuration of an 8-bit default code for implementing 256 gray levels.

FIG. 3 is a waveform diagram illustrating a driving signal for driving the plasma display panel shown in FIG. 1.

4 is a block diagram schematically illustrating an apparatus for driving a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 5 is a waveform diagram illustrating driving signals of the plasma display panel according to the first exemplary embodiment of the present invention generated from each driving unit of FIG. 4.

FIG. 6 is a waveform diagram illustrating driving signals of the plasma display panel according to the second exemplary embodiment of the present invention generated from each driving unit of FIG. 4.

FIG. 7 is a waveform diagram illustrating driving signals of the plasma display panel according to the third exemplary embodiment of the present invention generated from each driving unit of FIG. 4.

FIG. 8 is a waveform diagram illustrating driving signals of the plasma display panel according to the fourth exemplary embodiment of the present invention generated from each driving unit of FIG. 4.

FIG. 9 is a waveform diagram illustrating driving signals of a plasma display panel according to a fifth exemplary embodiment of the present invention generated from each driving unit of FIG. 4.

FIG. 10 is a waveform diagram illustrating driving signals of a plasma display panel according to a sixth exemplary embodiment of the present invention generated from each driving unit of FIG. 4.

FIG. 11 is a waveform diagram illustrating driving signals of a plasma display panel according to a seventh exemplary embodiment of the present invention generated from each driving unit of FIG. 4.

<Description of Symbols for Main Parts of Drawings>

41: timing controller 42: data driver

43: scan driver 44: sustain driver

45: drive voltage generator

Claims (22)

In the driving method of a plasma display panel having a first electrode, a second electrode and a third electrode, Selecting on cells to be turned on by applying a data voltage to the first electrode and applying a scan voltage to the second electrode; Supplying a pre-clear signal of the same type to the second electrode and the third electrode to erase charges remaining in the off cells other than the on cells; And displaying an image by applying a sustain voltage to the second and third electrodes alternately to cause discharge of the on-cells. The method of claim 1, And the voltage level of the pre-clear signal changes linearly. The method of claim 1, And the voltage level of the pre-clear signal is changed in stages. delete The method of claim 1, And the voltage of the pre-clear signal starts to decrease from a predetermined reference voltage and drops to a voltage between 0V and the scan voltage. The method of claim 1, And the voltage of the pre-erase signal falls to a voltage lower than the scan voltage. The method of claim 1, And driving the plasma display panel by supplying an initialization signal of increasing voltage level to at least one of the second and third electrodes in the initialization period before selecting the cell. Way. The method of claim 7, wherein And the initialization signal is simultaneously supplied to the second and third electrodes. delete The method of claim 1, Driving a plasma display panel after supplying a post-erasing signal to at least one of the second and third electrodes after displaying the image to erase charges remaining in the on cells. Way. In the driving apparatus of the plasma display panel having a first electrode, a second electrode and a third electrode, A cell selection driver for selecting on cells to be turned on by applying a data voltage to the first electrode and a scan voltage to the second electrode; A pre-clearing driver supplying a pre-clearing signal of the same type to the second electrode and the third electrode to erase charge remaining in the off-cells other than the on-cells; And a display driver for displaying an image by applying a sustain voltage to the second and third electrodes alternately to generate discharge to the on cells. The method of claim 11, And the pre-erase signal is linearly changed in voltage level. The method of claim 11, And the voltage level of the pre-clear signal is changed in stages. delete The method of claim 11, And the voltage of the pre-erase signal starts to decrease from a predetermined reference voltage and drops to a voltage between 0 [V] and the scan voltage. The method of claim 11, And the voltage of the pre-erase signal drops to a voltage lower than the negative scan voltage. The method of claim 11, And an initialization driver configured to supply an initialization signal of increasing voltage level to at least one of the second and third electrodes in the initialization period before selecting the cell to initialize the cells. Drive system. The method of claim 17, And the initialization signal is simultaneously supplied to the second and third electrodes. delete The method of claim 11, And a post erasing driver for supplying a post erasing signal to at least one of the second and third electrodes after the image is displayed, thereby erasing charge remaining in the on cells. Drive system. The method of claim 1, And supplying a positive voltage to the first electrode while the pre-clear signal and the sustain voltage are supplied to the second and third electrodes. The method of claim 11, And a driving unit to supply a positive voltage to the first electrode while the pre-clear signal and the sustain voltage are supplied to the second and third electrodes.